CHAPTER

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REMIND

 Inside a CPU
 Abstraction layer

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What will you learn?

 How programs are translated into the machine language

 How hardware executes a program
 How CPU process an instruction
 Measuring execution time
 Uniprocessor vs Multiprocessor

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Instruction

 The sequence bit that contains the request that the

processor must make.
 An instruction consists of 2 part:
Opcode: the operation ALU must take
Operand: objects affected by the action contained in the code

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Instruction Set Architecture (ISA)
 The format and behavior of a machine-level program is
defined by the instruction set architecture
 Different computers have different instruction sets but
with many aspects in common
 Commonly ISA:
• MIPS: used in embedded • IA-16: 16-bits processor (Intel 8086, 80186, 80286)
system • IA-32: 32-bits processor (Intel 80368 – i386, 80486
• ARM: A64, A32, T32 – i486, Pentium II, Pentium III …)
• Power-PC • IA-64: 64-bits processor (Intel x86-64 - Pentium D…)

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ISA design: CISC & RISC
 Complete Instruction Set Computer (CISC): includes
many instructions, from simple to complex
 Reduced Instruction Set Computer (RISC): consists of
only simple instructions
 Which one is better?

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Discussion

What is it? What is it?

High-level Assembly Machine
language Compiler language Assembler Laguage

temp = v[k]; lw $t0, 0($2) 0000 1001 1100 0110

v[k] = v[k+1]; lw $t1, 4($2) 1111 0101
v[k+1] = temp; sw $t1, 0($2) …..
sw $t0, 4($2)

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Assembly Language
 A symbolic representation of machine code, clearer than
in machine code
 Each assembly instruction represents exactly one
machine instruction
 Ex: Save the value 5 decimal in the register $4
Machine language: 00110100 0000100 00000000 00000101
Assembly: ori $4, $0, 5
opcode dest reg src reg
immediate
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Assembly Language
 Since each processor has its own register structure and
instruction set when setting the assembly, it must be
clear which processor is set, or the family of the
processor.
 Ex:
 Assembly for MIPS
 Assembly for the line of Intel 8086 processors

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Compiler

 A program that translates high-level language statements into

assembly language statements
 Belong to:
 The system hardware architecture below which it is running
 The high-level language which it compiles
 Ex:
Compiler for C <> Compiler cho Java
Compiler for “C on Windows” <> “C on Linux”

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Assembler
 A program that translates a symbolic version of instructions
into the machine code
 A single processor (1 set of definitions) can have multiple
assemblers from different vendors running on different
operating systems.
 Ex: list of assembler for x86 architecture
A86, GAS, TASM, MASM, NASM
 The Assembly program depends on the assembler it
uses

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Discussions
 Who will compile the compiler? (It’s also a program)
 Assembler
 How the hardware execute a program?
 Loader & Linker

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fit@hcmus Linker
 A systems program that combines independently
assembled machine language programs (object file) and
resolves all undefined labels into an executable file.

Loader
 A systems program that places an object program in
main memory so that it is ready to execute.

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Create executable file

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A translation
hierarchy for C

Chap2, A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface,5th 15
ed, 2014 Figure 2.21
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A translation hierarchy for Java

Chap2, A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface,5th ed, 16
2014 Figure 2.23
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Realistic
Model

• Compiler and assembler can be skipped in the certain cases

• In fact, there are several compilers that can create executables on a variety
of underlying architecture platforms (cross-platform compiler)
• Ex: Compiler for Java, Cygwin, Code::Block Studio

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Instruction processing

Fetch next Execute

Start Halt
Instruction Instruction

Instruction Cycle: consists of 2 phases

• Fetch cycle: Transfer data from memory to registers
• Execute cycle: Decode the instruction and execute the requirements of it

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Fetch cycle
• PC (Program Counter)
 Store the next instruction’s address
• MAR (Memory Address Register)
 Store the address of a location in memory
(output to address bus)
• MBR (Memory Buffer Register)
 A word of data to be written to
memory or the word most recently read
(output to data bus)
• IR (Instruction Register)
 Contain the most recently fetched
instruction

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Fetch cycle
• The control unit move the instruction
which has address in PC regs to IR
Default update PC reg:
PC += size of the fetched instruction
• The fetched instruction is loaded into an
IR, where the opcode and operand are
analyzed
• Data are exchanged with memory using
the MAR and MBR

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Example Chương trình CPU PC 00010011 R1

x=x+y
IR 00010000 01000000 00000001
…
CPU
RAM
…
00010000 01000000 00000001 Địa chỉ Lệnh (Instruction)

ALU
00001100 01000010 00000001
00010000 00000001 01000000
00010000 x  R1
…
00010011 R1+y  R1
x 00010110 R1  x
y ….
… 01000000 ….
01000010 ….
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Execute cycle

Chap3, William Stalling, Computer Organization and Architecture, 8th ed,

2014 Figure 3.6
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 Measuring execution time
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Elapsed time
• Total response time, including all aspects: processing,
i/o, idle time, OS overhead
CPU time
• Time spent processing a given task
• Comprise user CPU time and system CPU time
• Different program are affected differently by CPU and
system performance
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 Clock Cycles
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Instead of reporting execution time in seconds, we often use

cycles. In modern computers hardware events progress cycle
by cycle: in other words, each event, e.g., multiplication,
addition, etc., is a sequence of cycles
seconds cycles seconds
= 
program program cycle
cycle time = time between ticks = seconds per cycle
clock rate (frequency) = cycles per second (1 Hz. =
1 cycle/sec, 1 MHz. = 106 cycles/sec)

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CPU Time
𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 𝐶𝑃𝑈 𝑐𝑙𝑜𝑐𝑘 𝑐𝑦𝑐𝑙𝑒𝑠 𝑠𝑒𝑐𝑜𝑛𝑑𝑠
CPU time = × ×
𝑃𝑟𝑜𝑔𝑟𝑎𝑚 𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛 𝐶𝑃𝑈 𝑐𝑙𝑜𝑐𝑘 𝑐𝑦𝑐𝑙𝑒𝑠

Performance depends on:

• Algorithm
• Programming language
• Compiler
• ISA
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fit@hcmus Uniprocessor vs Multiprocessor

Constrained by: Multicore microprocessors (>1 processor/

Power chip)
Requires explicitly parallel programming
Instruction-level parallelism
• Compare with instruction level
Memory latency parallelism
o Hardware executes multiple
instructions at once
o Hidden from the programmer
• Hard to do
o Programming for performance
o Load balancing
o Optimizing communication and
synchronization

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