AOZ8105

Ultra-Low Capacitance TVS Diode Array

General Description Features

The AOZ8105 is a transient voltage suppressor array ● ESD protection for high-speed data lines:
designed to protect high speed data lines such as HDMI – IEC 61000-4-2, level 4 (ESD) immunity test
and Gigabit Ethernet from damaging ESD events. – ±30kV (air discharge) and ±24kV (contact discharge)
This device incorporates eight surge rated, low capaci- – IEC 61000-4-5 (Lightning) 3A (8/20µs)
tance steering diodes and a TVS in a single package. – Human Body Model (HBM) ±24kV
During transient conditions, the steering diodes direct the ● Array of surge rated diodes with internal TVS diode
transient to either the positive side of the power supply ● Small package saves board space
line or to ground.
● Protects four I/O lines
The AOZ8105 provides a typical line to line capacitance ● Low capacitance between I/O lines: 0.35pF
of 0.35pF and low insertion loss up to 3GHz providing ● Low clamping voltage
greater signal integrity making it ideally suited for HDMI
● Low operating voltage: 5.0V
1.3 applications, such as Digital TVs, DVD players,
set-top boxes and mobile computing devices.
Applications
The AOZ8105 comes in RoHS compliant, tiny SOT-23-6 ● HDMI ports
package and is rated -40°C to +85°C junction tempera-
● Monitors and flat panel displays
ture range.
● Set-top box
● USB 2.0 power and data line protection
● Video graphics cards
● Digital Video Interface (DVI)
● 10/100/1000 Ethernet
● Notebook computers

Typical Application
Vcc

I/O1
I/O2
I/O3
I/O4
Figure 1. HDMI Ports

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 AOZ8105

Ordering Information
Part Number Ambient Temperature Range Package Environmental
AOZ8105CI -40°C to +85°C SOT-23-6 Green Product

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.

Pin Configuration

CH1 1 6 CH4

VN 2 5 VP

CH2 3 4 CH3

SOT23-6
(Top View)

Absolute Maximum Ratings

Exceeding the Absolute Maximum ratings may damage the device.

Parameter Rating
Storage Temperature (TS) -65°C to +150°C
(1)
ESD Rating per IEC61000-4-2, contact ±24kV
(1)
ESD Rating per IEC61000-4-2, air ±30kV
(2)
ESD Rating per Human Body Model ±24kV
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ.

Maximum Operating Ratings

Parameter Rating
Junction Temperature (TJ) -40°C to +125°C

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 AOZ8105

Electrical Characteristics
TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.

Symbol Parameter Conditions Min. Typ. Max. Units

(3)
VRWM Reverse Working Voltage Between VP and VN 5.5 V
(4)
VBR Reverse Breakdown Voltage IT = 1mA, between VP and VN 6.6 V
IR Reverse Leakage Current VRWM = 5V, between VP and VN 1 µA
VF Diode Forward Voltage IF = 15mA 0.70 0.85 1 V
(5)
VCL Channel Clamp Voltage IPP = 1A, tp = 100ns, any I/O pin to Ground
Positive Transients 12 V
Negative Transient -1.4 V
Channel Clamp Voltage IPP = 5A, tp = 100ns, any I/O pin to Ground(5)
Positive Transients 16.5 V
Negative Transient -2.8 V
Cj Channel Input Capacitance VR = 0V, f = 1MHz, between I/O pins(6) 0.35 pF
VR = 0V, f = 1MHz, any I/O pin to Ground(6) 0.80 0.9 pF
VP = 5.0V, VR = 2.5V, f = 1MHz, any I/O pins 0.43 0.5 pF
to Ground
ΔCj Channel Input Capacitance VR = 0V, f = 1MHz, between I/O pins 0.03 pF
Matching

Notes:
3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
4. VBR is measured at the pulse test current IT.
5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.
6. Measure performed with no external capacitor on VP .

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 AOZ8105

Typical Operating Characteristics

Clamping Voltage vs. Peak Pulse Current Forward Voltage vs. Forward Current
(tperiod = 100ns, tr = 1ns) (tperiod = 100ns, tr = 1ns)
18 5
16
Clamping Voltage, VCL (V)

14 4

Forward Voltage (V)

12
3
10
8
2
6
4 1
2
0 0
0 1 2 3 4 5 0 1 2 3 4 5
Peak Pulse Current, Ipp (A) Forward Current (A)

Typical Variation of CIN vs. VR

(f = 1MHz, T = 25°C )
1.2
Normalized Input Capacitance

1.0

0.8

0.6

0.4

0.2

0.0
0 1 2 3 4 5
Forward Current (A)

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 AOZ8105

Application Information
The AOZ8105 TVS is designed to protect four high VGA Ports
speed data lines from ESD and transient over-voltage by
With VGA ports back-drive current is a concern for
clamping them to a fixed voltage. When the voltages on
system instability, start ups and power loss. The
the protected lines exceed the limit, the internal steering
back-drive current occurs when two systems are
diode are forward bias will conduct the harmful transient
connected through a cable and one system is OFF and
away from the sensitive circuitry. As system frequency
another system is ON. In this case the system that is ON
increases, printed circuit board layout becomes more
is the monitor. The monitor can inject current into the
complex. A successful high speed board must integrate
system that is turned OFF via the cable. To inhibit the
the device and traces while avoiding signal transmission
back-drive current from happening, an integrated diode is
problems associated with HDMI data speed.
designed into the AOZ8105 to prevent current from going
into the system that is turned OFF. Figure 2 shows the
schematics where the back-drive current is flowing in a
system that is turned OFF.

Mother Board Video Monitor

VGA 5V+
System VGA
6 5 4 5V 5V

BAV 70

1 2 3 Cable 100kΩ
100Ω
DDCA_SDA Scaler
DDCA_SDA

Figure 2.

ESD Protection

Sync VGA 5V Blue

6 5 4
Video Scaler
15 Pin DSUB
Connector
Red Red
Green Green
Blue Blue
Sync 1 2 3 Sync
SCL Red SCL
Green
SDA SDA
VSync VSync
CLK VGA 5V SDA
HSync HSync
Dig Gnd 6 5 4
Red Gnd
Blue Gnd
Green Gnd

1 2 3
VSYNC HSYNC

Figure 3. ESD design for VGA Ports in which two AOZ8105 are used.

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 AOZ8105

PCB Layout Example for VGA Port possible traces. A short trace length equates to low
Figure 4 shows an example for a VGA port with two impedance, which ensures that the surge energy will be
AOZ8105 being used. Place the AOZ8105 device as dissipated by the AOZ8105 device. Long signal traces
close to the connector as possible. Use ground plane will act as antennas to receive energy from fields that are
wherever to ensure maximum performance of the device. produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize inter-
connecting line lengths by placing devices with the most
interconnect as close together as possible. The protec-
tion circuits should shunt the surge voltage to either the
reference or chassis ground. Shunting the surge voltage
directly to the IC’s signal ground can cause ground
bounce. The clamping performance of TVS diodes on a
single ground PCB can be improved by minimizing the
impedance with relatively short and wide ground traces.
The PCB layout and IC package parasitic inductances
can cause significant overshoot to the TVS’s clamping
voltage. The inductance of the PCB can be reduced by
using short trace lengths and multiple layers with sepa-
rate ground and power planes. One effective method to
minimize loop problems is to incorporate a ground plane
in the PCB design.

The AOZ8105 ultra-low capacitance TVS is designed to

protect four high speed data transmission lines from
transient over-voltages by clamping them to a fixed refer-
ence. The low inductance and construction minimizes
voltage overshoot during high current surges. When the
voltage on the protected line exceeds the reference
voltage the internal steering diodes are forward biased,
conducting the transient current away from the sensitive
circuitry. The AOZ8105 is designed for the ease of PCB
layout by allowing the traces to run underneath the
device. The pinout of the AOZ8105 is design to simply
drop onto the IO lines of a High Definition Multimedia
Interface (HDMI) design without having to divert the
signal lines that may add more parasitic inductance.

Figure 4. It is crucial that the layout is successful for a HDMI

design PCB board. Some of the problems associated
High Speed HDMI PCB Layout Guidelines with high speed design are matching impedance of the
traces and to minimize the crosstalk between parallel
Printed circuit board layout is the key to achieving the
traces. This application note is to provide you as much
highest level of surge immunity on power and data lines.
information to successfully design a high speed PCB
The location of the protection devices on the PCB is the
using Alpha & Omega devices.
simplest and most important design rule to follow. The
AOZ8105 devices should be located as close as possible The HDMI video signals are transmitted on a very high
to the noise source. The placement of the AOZ8105 speed pair of traces and any amount of capacitance,
devices should be used on all data and power lines that inductance or even bends in a trace can cause the
enter or exit the PCB at the I/O connector. In most impedance of a differential pair to drop as much as 40Ω.
systems, surge pulses occur on data and power lines This is not desirable because HDMI ports must maintain
that enter the PCB through the I/O connector. Placing the a 100Ω ±15% on each of the four pairs of its differential
AOZ8105 devices as close as possible to the noise lines per HDMI Compliance Test Specifications. The
source ensures that a surge voltage will be clamped HDMI CTS specifies that the impedance on the differen-
before the pulse can be coupled into adjacent PCB tial pair of a receiver must be measured using a Time
traces. In addition, the PCB should use the shortest Domain Reflectometry method with a pulse rise time of

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 AOZ8105

≤200pS. The TDR measurements of the PCB traces Typical value of W = 12.6 mil, h = 10mils, D = 10mils,
allows to locate and model discontinuities cause by the t = 1.4mils and εr = 4.0 with the equation below for a
geometrical features of a bend and by the frequency- microstrip impedance yields:
dependant losses of the trace itself. These fast edge
87 5.98 × h
rates can contribute to noise and crosstalk, depending on Zo = -------------------------- = ln ⎛ ----------------------⎞
the traces and PCB dielectric construction material. ε r + 1.41 ⎝ 0.8W + t⎠ (3)

Material selection is another aspect that determines good Zo = 61.73Ω

characteristic impedance in the lines. Different material
will give you different results. The dielectric material will By solving for Zo you can calculate the differential
have the dielectric constant (εr). Where Q1, Q2 = impedance with the equation below.
charges, r = distance between charges (m), F = force(N),
D
ε = permittivity of dielectric (F/m). ⎛ – 0.96 ----⎞
h
Zdiff = 2 × Zo ⎜ 1 – 0.48e ⎟ (4)
Q1 Q2 ⎝ ⎠
F = --------------- (1) Zdiff = 100.77
2
4πεr
Adjust the trace width, height, distance between the
Each PCB substrate has a different relative dielectric traces and FR4 thickness to obtain the desired 100Ω
constant. The dielectric constant is the permittivity of a differential impedance. The general rule of thumb is to
relative that of empty space. Where εr = dielectric route the traces as short as possible, use differential
constant, ε = permittivity, and εo = permittivity of empty routing strategies whenever feasible and match the
space. length and bends to each of the differential traces.
ε
ε r = ----- (2) The graphs below show the differential impedance with
εo
varying trace width without the package part on it. Each
of the graphs and board layout represent changing trace
The dielectric constant affects the impedance of a trans- width from 100Ω to 160Ω in increment of 20Ω.
mission line and can propagate faster in materials that
have a lower εr . The frequency in your design will
depend on the material being used. With equation 1 you
can determine the type of material to use. If higher fre-
quency is required other board material maybe consid-
ered. GETEK is another material that can be used in high
speed boards. They have a typical εr between 3.6 to 4.0.
The most common type of dielectric material used for
PCB is FR-4. Typical dielectric constant for FR-4 is
between 4.0 to 4.5. Most PCB manufacture will be able to
give you the exact value of the FR-4 dielectric constant.
Once you determined the dielectric constant of the board
material you can start to calculate the impedance of each
trace. Below are the formulas for a microstrip layout. This Figure 6. 100Ω Differential Impedance
impedance is dependant on the width of the microstrip Max 103Ω, Min 97Ω
(W) the thickness (t) of the trace and the height (h) of the
FR4 material, and (D) trace edge to edge spacing.

W D W t
Trace

εr Dielectric Material H
Ground

Figure 5.

Figure 7. 120Ω Differential Impedance

Max 110Ω, Min 102Ω

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 AOZ8105

Zo = 61Ω Zo = 61Ω
Z1 C(TVS)

Figure 11.

Z1
K = ------ (5)
Z2
Figure 8. 140Ω Differential Impedance
Max 102Ω, Min 92Ω Z 0 C TVS K
X = ⎛ ---------------------⎞ ⎛ ----------------⎞ (6)
⎝ τ ⎠⎝ 2 ⎠
K –1

Z0 is the normal 61Ω differential impedance on the trace.

Z1 is the need impedance to compensate for the added

C(TVS)

K is defined as the unloaded impedance of the adjusted

trace.

X is the length of the trace needed for the compensation.

Figure 9. 160Ω Differential Impedance
Max 123Ω, Min 109Ω τ is the propagation delay time required for a signal to
travel from one point to another. This value should be
140 less than 200pS.
Differentail Impedance (Ω)

120
Max. From the above method the designer should layout the
100 boards with a 50Ω common mode trace. The result
80
Min.
should give you approximately 100Ω differential imped-
ance. Z1 is the impedance that you choose in order to
60
compensate the TVS capacitance. Based on Z1 value,
40 we can get the length of the segment from the above
20 equations. With the value of Z1 = 98Ω, Zo = 61Ω,
C(TVS) = 0.7 and τ = 180. The X(mils) equates to
0
50 55 60 65 70 75 80 250 mils.
Common Mode Impedance (Ω)
Page 9 has a series of graph that represent changing
Figure 10. Differential Impedance width and length of the trace from 100Ω to 160Ω in
increment of 20Ω with a package solder onto the board.
By adding a TVS onto the traces it can have a large As you can observe from the graphs, a small incremental
effect on the impedance of the line. This addition of a capacitance that is added to the differential lines can
capacitance added to a 100Ω differential transmission significantly decrease the differential impedance. Thus
line without any compensation may decrease the violated the HDMI specification of 100Ω±15%.
impedance as much as 20Ω or more. Below is a formula
to calculate the length for the compensation of C(TVS).

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 AOZ8105

Figure 12. 100Ω Differential Impedance with Package on it Figure 14. 140Ω Differential Impedance with Package on it
Max. 97Ω, Min. 80Ω Max. 102Ω, Min. 92Ω

Figure 13. 120Ω Differential Impedance with Package on it Figure 15. 160Ω Differential Impedance with Package on it
Max. 99Ω, Min. 86Ω Max. 101Ω, Min. 95Ω

From Figure 15 we are able to get the best result from

using all of the equation above. With the value of
Z1 = 98Ω, Z0 = 61Ω, C(TVS) = 0.7, τ = 180. The X(mils)
equates to 250 mils to give the best compensated
differential impedance on the traces for the added capac-
itance from the AOZ8105.

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 AOZ8105

Conclusion
This application section discusses ESD protection while
maintaining the differential impedance of a HMDI sink
device. Since the TVS add capacitance we must design
the board to meet the HDMI requirements. This applica-
100Ω tion note is a guideline to calculate and layout the PCB.
Differential Different board manufacture and process will fluctuate
and will cause the final board to vary slightly. You must
carefully plan out a successful high speed HDMI PCB.
Factor such as PCB stack up, ground bounce, crosstalk
and signal reflection can interfere with a signal. The
layout, trace routing, board materials and impedance
calculation discussed in this application note can help
160Ω 250 mils you design a more effective PCB.
Differential Total Distance

Figure 16. Recommended Layout for SOT-23 Package

Table 1. AOZ8105 SOT-23-6 Evaluation Board

Specifications
Number of layers 4
Copper Trace Thickness 1.4 mils
Dielectric Constant εr 4
Overall Board Thickness 62 mils
Dielectric thickness between top and ground layer 10 mils

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 AOZ8105

Package Dimensions, SOT23-6L

Gauge Plane Seating Plane

D
0.25mm
e1 c

E E1

θ1
e b

A A2
.010mm

A1

Dimensions in millimeters Dimensions in inches

Symbols Min. Nom. Max. Symbols Min. Nom. Max.
RECOMMENDED LAND PATTERN
A 0.90 — 1.25 A 0.035 — 0.049
A1 0.00 — 0.15 A1 0.00 — 0.006
A2 0.80 1.10 1.20 A2 0.031 0.043 0.047
b 0.30 0.40 0.50 b 0.012 0.016 0.020
2.40
c 0.08 0.13 0.20 c 0.003 0.005 0.008
0.80 D 2.70 2.90 3.10 D 0.106 0.114 0.122
E 2.50 2.80 3.10 E 0.098 0.110 0.122
0.95 E1 1.50 1.60 1.70 E1 0.059 0.063 0.067
0.63
e 0.95 BSC e 0.037 BSC
UNIT: mm e1 1.90 BSC e1 0.075 BSC
L 0.30 — 0.60 L 0.012 — 0.024
θ1 0° — 8° θ1 0° — 8°

Notes:
1. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each.
2. Dimension “L” is measured in gauge plane.
3. Tolerance ±0.100mm (4 mil) unless otherwise specified.
4. Followed from JEDEC MO-178C & MO-193C.
6. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.

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 AOZ8105

Tape and Reel Dimensions, SOT23-6L

Tape
P1
T D1 P2

E1

E2
E
B0

K0 A0 D0 P0
Unit: mm Feeding Direction

Package A0 B0 K0 D0 D1 E E1 E2 P0 P1 P2 T
SOT-23 3.15 3.20 1.40 1.00 1.50 8.00 1.75 3.50 4.00 4.00 2.00 0.25
(8mm) ±0.10 ±0.10 ±0.10 Min. ±0.10 ±0.30 ±0.10 ±0.05 ±0.10 ±0.10 ±0.05 ±0.05

Reel
W1

S
G

N
M K
V

R
H
Unit: mm

Tape Size Reel Size M N W W1 H K S G R V

8mm ø180 ø180.00 ø60.50 9.00 11.40 ø13.00 10.60 2.00 ø9.00 5.00 18.00
±0.50 ±0.30 ±1.00 +0.50 / -0.20 ±0.50

Leader/Trailer and Orientation

Trailer Tape Components Tape Leader Tape

(300mm min., 75 Empty Pockets) Orientation in Pocket (500mm min., 125 Empty Pockets)

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 AOZ8105

Part Marking

AOZ8105CI
(SOT-23)

LT
AP 0 4 Assembly
Lot Code

Part Number Code Week & Year Code

Option & Assembly Location Code

This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.

LIFE SUPPORT POLICY

ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

As used herein:

1. Life support devices or systems are devices or 2. A critical component in any component of a life
systems which, (a) are intended for surgical implant into support, device, or system whose failure to perform can
the body or (b) support or sustain life, and (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in a significant injury of
the user.

Rev. 1.6 January 2010 www.aosmd.com Page 13 of 13

SOT23-6L Carrier Tape Material: Plastic