LM 4889
LM 4889
LM 4889
1FEATURES DESCRIPTION
23 • Available in Space-Saving VSSOP, SOIC, The LM4889 is an audio power amplifier primarily
WSON, and DSBGA Packages designed for demanding applications in mobile
phones and other portable communication device
• Ultra Low Current Shutdown Mode (3.3 to 2.6V applications. It is capable of delivering 1 watt of
- 0.01µA) continuous average power to an 8Ω BTL load with
• Can Drive Capacitive Loads up to 500 pF less than 2% distortion (THD+N) from a 5VDC power
• Improved Pop & Click Circuitry Eliminates supply.
Noises During Turn-On and Turn-Off Boomer™ audio power amplifiers were designed
Transitions specifically to provide high quality output power with a
• 2.2 - 5.5V Operation minimal amount of external components. The
LM4889 does not require output coupling capacitors
• No Output Coupling Capacitors, Snubber or bootstrap capacitors, and therefore is ideally suited
Networks or Bootstrap Capacitors Required for mobile phone and other low voltage applications
• Unity-Gain Stable where minimal power consumption is a primary
• External Gain Configuration Capability requirement.
The LM4889 features a low-power consumption
APPLICATIONS shutdown mode, which is achieved by driving the
• Mobile Phones shutdown pin with a logic low. Additionally, the
LM4889 features an internal thermal shutdown
• PDAs protection mechanism.
• Portable Electronic Devices
The LM4889 contains advanced pop & click circuitry
to eliminate noise which would otherwise occur during
KEY SPECIFICATIONS turn-on and turn-off transitions.
• Improved PSRR at 217Hz, 5 - 3.3V 75dB The LM4889 is unity-gain stable and can be
• Power Output at 5.0V & 2% THD 1.0W(typ.) configured by external gain-setting resistors.
• Power Output at 3.3V & 1% THD 400mW(typ.)
• Shutdown Current at 3.3 & 2.6V 0.01µA(typ.)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 Boomer is a trademark of Texas Instruments.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM4889
SNAS157H – APRIL 2002 – REVISED MAY 2013 www.ti.com
Typical Application
Connection Diagram
Figure 2. Small Outline (SOIC) Package - Top View Figure 3. Mini Small Outline (VSSOP) Package –
See Package Number D Top View
See Package Number DGK
Figure 4. 8-Bump DSBGA - Top View Figure 5. WSON Package - Top View
See Package Number YZR0008 See Package Number NGZ
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever
is lower. For the LM4889, see power derating currents for additional information.
(4) Human body model, 100 pF discharged through a 1.5 kΩ resistor.
(5) Machine Model, 220 pF–240 pF discharged through all pins.
(6) All bumps have the same thermal resistance and contribute equally when used to lower thermal resistance. The LM4889ITL demo board
(views featured in the Application Information section) has two inner layers, one for VDD and one for GND. The planes each measure
600mils x 600mils (15.24mm x 15.24mm) and aid in spreading heat due to power dissipation within the IC.
Operating Ratings
Temperature Range TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ 85°C
Supply Voltage 2.2V ≤ VDD ≤ 5.5V
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test or statistical analysis.
(6) For DSBGA only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a
maximum of 2µA.
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM4889
LM4889
SNAS157H – APRIL 2002 – REVISED MAY 2013 www.ti.com
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test or statistical analysis.
(6) For DSBGA only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a
maximum of 2µA.
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test or statistical analysis.
(6) For DSBGA only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a
maximum of 2µA.
4 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
(Figure 1)
Figure 6. Figure 7.
Figure 8. Figure 9.
Power Supply Rejection Ratio (PSRR) at VDD = 5V Power Supply Rejection Ratio (PSRR) at VDD = 5V
Figure 14. Input terminated with 10Ω R Figure 15. Input Floating
Power Supply Rejection Ratio (PSRR) at VDD = 2.6V Power Supply Rejection Ratio (PSRR) at VDD = 3.3V
Figure 16. Input terminated with 10Ω R Figure 17. Input terminated with 10Ω R
Power Dissipation vs
Output Power vs Output Power
Load Resistance VDD = 2.6V
Power Derating Curves - 8 bump µSMD Power Derating Curves - 10 Pin LD pkg
(PDMAX = 670mW) (PDMAX = 670mW)
Application Information
POWER DISSIPATION
Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or
single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an
increase in internal power dissipation. Since the LM4889 has two operational amplifiers in one package, the
maximum internal power dissipation is 4 times that of a single-ended amplifier. The maximum power dissipation
for a given application can be derived from the power dissipation graphs or from Equation 2.
PDMAX = 4*(VDD)2/(2π2RL) (2)
It is critical that the maximum junction temperature TJMAX of 150°C is not exceeded. TJMAX can be determined
from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the
thermal resistance of the application can be reduced from a free air value of 150°C/W, resulting in higher PDMAX.
Additional copper foil can be added to any of the leads connected to the LM4889. It is especially effective when
connected to VDD, GND, and the output pins. Refer to the application information on the LM4889 reference design
board for an example of good heat sinking. If TJMAX still exceeds 150°C, then additional changes must be made.
These changes can include reduced supply voltage, higher load impedance, or reduced ambient temperature.
Internal power dissipation is a function of output power. Refer to the Typical Performance Characteristics curves
for power dissipation information for different output powers and output loading.
SHUTDOWN FUNCTION
In order to reduce power consumption while not in use, the LM4889 contains a shutdown pin to externally turn off
the amplifier's bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the
shutdown pin. By switching the shutdown pin to ground, the LM4889 supply current draw will be minimized in idle
mode. While the device will be disabled with shutdown pin voltages less than 0.5VDC, the idle current may be
greater than the typical value of 0.1µA. (Idle current is measured with the shutdown pin grounded).
In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry to
provide a quick, smooth transition into shutdown. Another solution is to use a single-pole, single-throw switch in
conjunction with an external pull-up resistor. When the switch is closed, the shutdown pin is connected to ground
and disables the amplifier. If the switch is open, then the external pull-up resistor will enable the LM4889. This
scheme ensures that the shutdown pin will not float thus preventing unwanted state changes.
The LM4889 is unity-gain stable and requires no external components besides gain-setting resistors, an input
coupling capacitor, and proper supply bypassing in the typical application. However, if a closed-loop differential
gain of greater than 10 is required, a feedback capacitor (C4) may be needed as shown in Figure 30 to
bandwidth limit the amplifier. This feedback capacitor creates a low pass filter that eliminates possible high
frequency oscillations. Care should be taken when calculating the -3dB frequency in that an incorrect
combination of R3 and C4 will cause rolloff before 20kHz. A typical combination of feedback resistor and
capacitor that will not produce audio band high frequency rolloff is R3 = 20kΩ and C4 = 25pf. These components
result in a -3dB point of approximately 320kHz.
REFERENCE DESIGN BOARD AND PCB LAYOUT GUIDELINES - VSSOP & SOIC BOARDS
REVISION HISTORY
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LM4889MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 GA2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TUBE
Pack Materials-Page 3
PACKAGE OUTLINE
DGK0008A SCALE 4.000
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
C
5.05
TYP
A 4.75
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1
2X
3.1
1.95
2.9
NOTE 3
4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4
0.23
0.13
SEE DETAIL A
0.25
GAGE PLANE
1.1 MAX
0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20
TYPICAL
4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
8X (1.4) (R0.05) TYP
8X (0.45) 1 8
SYMM
6X (0.65)
5
4
SEE DETAILS
(4.4)
4214862/A 04/2023
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
8X (0.45) 1 8
SYMM
6X (0.65)
5
4
(4.4)
4214862/A 04/2023
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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