CS212 Counters Timers and DMM

College of Information and Communication Technologies
Department of Computer Science and Engineering
CS212 : Measurement and

Instrumentation Engineering II
Counters & Timers
UDSM, 12.05.2021 CS212: Counters and Timers Page 2

Counters… Introduction
Counters are important element in digital

electronics used not only for counting but
also for measuring frequency and time ;
increment memory addresses.
Counters are specially designed
synchronous sequential circuits, in which ,
the state of the counter is equal to the
count held in the circuit by the flip flops.
Counters calculate or note down the
number that how many times an event
occurred.
Design on Counters
Counters are designed by grouping of flip flops and

applying a single clock signal to them.
Counters are those, which have the group of storage
elements like flip flops to hold the count.

Principle of Operation
Counters are the crucial hardware components in a

digital circuit, and are defined as the circuit which is
used to count the number of pulses. Counters are
well known to us as “Timers”.
Counters have modes. The ‘mod’ of the counter
represents the number of states of the cycles
through it, before setting the counter to its initial
state.
For example, a binary mod 8 counter has 8
countable states. They are from 000 to 111. So
the mod 8 counter counts from 0 to 7. This
means, in general a mod N counter can contain
n number of flip flops, where 2n = N.
Need of Counters
Counting means incrementing or decrementing the

values of an operator, with respect to its previous state
value. So to perform the mathematical operation we use
no devices other than counters. We cannot perform this
action (counting) with any other logic devices rather than
counters.
Types of counters
There are two types of counters available for digital circuits,

they are
1. Synchronous (parallel) counters
2. Asynchronous (ripple) counters

Types of Counters
Asynchronous (ripple) counters allow some flip-

flop outputs to be used as a source of clock for
other flip-flops (FF). No common clock.
Synchronous (parallel) counters apply the same
clock to all flip-flops (FF).

Asynchronous (Ripple) Counters
 Asynchronous counters: the flip-flops do not change

states at exactly the same time as they do not have a
common clock pulse.
 Also known as ripple counters, as the input clock pulse
“ripples” through the counter – cumulative delay is a
drawback.
 n flip-flops  a MOD (modulus) 2n counter. (Note: A
MOD-x counter cycles through x states.)
 Output of the last flip-flop (MSB) divides the input clock
frequency by the MOD number of the counter, hence a
counter is also a frequency divider.

Asynchronous (Ripple) Counters…
 Example: 2-bit ripple binary counter.

 Output of one flip-flop is connected to the clock input of
the next more-significant flip-flop.
HIGH
J Q0 J Q1
CLK C C
Q0
K K
FF0 FF1
CLK 1 2 3 4
Q0 Timing diagram
00  01  10  11  00 ...
Q0 0 1 0 1 0
Q1 0 0 1 1 0

Example: 3-bit ripple binary counter.

HIGH
J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2
CLK 1 2 3 4 5 6 7 8
Q0 0 1 0 1 0 1 0 1 0
Q1 0 0 1 1 0 0 1 1 0
Q2 0 0 0 0 1 1 1 1 0
Recycles back to 0

 Propagation delays in an asynchronous (ripple-clocked)

binary counter.
 If the accumulated delay is greater than the clock pulse,
some counter states may be misrepresented!
CLK 1 2 3 4
Q0
Q1
Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)

 Example: 4-bit ripple binary counter (negative-edge triggered).
HIGH
Q0 Q1 Q2 Q3
J J J J
CLK C C C C
K K K K
FF0 FF1 FF2 FF3
CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q0
Q1
Q2
Q3

Asyn. Counters with MOD no. < 2n
 States may be skipped resulting in a truncated

sequence.
 Technique: force counter to recycle before going through
all of the states in the binary sequence.
 Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q
CLR
K Q
CLR
K Q
CLR
K
are 1
(HIGH). B
C

 Example (cont’d):
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C
MOD-6 counter
1 2 3 4 5 6 7 8 9 10 11 12
Clock
A produced by
clearing (a MOD-8
B
binary counter)
C when count of six
NAND 1 (110) occurs.
Output 0

Example (cont’d): Counting sequence of circuit (in CBA

order).
1 2 3 4 5 6 7 8 9 10 11 12
Clock
A
B
C
NAND 1
Output 0
111 000
Temporary 001
state
Counter is a MOD-6
110 010 counter.
101 011
100

Question
 Exercise: How to construct an asynchronous MOD-5

counter? MOD-7 counter? MOD-12 counter?
 Question: The following is a MOD-? counter?
F E D C B A
Q J Q J Q J Q J Q J Q J
Q K Q K Q K Q K Q K Q K
CLR CLR CLR CLR CLR CLR
C
D
E All J = K = 1.
F

 Decade counters (or BCD counters) are counters with

10 states (modulus-10) in their sequence. They are
commonly used in daily life (e.g.: utility meters,
odometers, etc.).
 Design an asynchronous decade counter.
(A.C)'
HIGH
D C B A
J Q J Q J Q J Q
CLK C C C C
K K K K
CLR CLR CLR CLR

Types of Recorder
(according to Points)
 Asynchronous decade/BCD counter (cont’d).
HIGH D C B A
J Q J Q J Q J Q (A.C)'
CLK C C C C
K K K K
CLR CLR CLR CLR
1 2 3 4 5 6 7 8 9 10 11
Clock
D
C
B
A
NAND
output
Asynchronous Down Counters
 So far we are dealing with up counters. Down counters,

on the other hand, count downward from a maximum
value to zero, and repeat.
 Example: A 3-bit binary (MOD-23) down counter.
1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C up counter
Q' K Q' K Q'
K
1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C down counter
Q' K Q' K Q'
K

Asynchronous Down Counters
 Example: A 3-bit binary (MOD-8) down counter.

000
001 111
1
Q0 Q1 Q2
J Q J Q J Q 010 110
CLK C C C
Q' K Q' K Q'
K
011 101
100
CLK 1 2 3 4 5 6 7 8
Q0 0 1 0 1 0 1 0 1 0
Q1 0 1 1 0 0 1 1 0 0
Q2 0 1 1 1 1 0 0 0 0

Cascading Asynchronous Counters
 Larger asynchronous (ripple) counter can be constructed

by cascading smaller ripple counters.
 Connect last-stage output of one counter to the clock input
of next counter so as to achieve higher-modulus
operation.
 Example: A modulus-32 ripple counter constructed from a
modulus-4 counter and a modulus-8 counter.
Q0 Q1 Q2 Q3 Q4
J Q J Q J Q J Q J Q
CLK C C C C C
Q' K Q' Q' K Q' K Q'
K K
Modulus-4 counter Modulus-8 counter

Cascading Asynchronous Counters…
Example: A 6-bit binary counter (counts from 0 to 63)

constructed from two 3-bit counters.
A0 A1 A2 A3 A4 A5
Count 3-bit 3-bit

binary counter binary counter
pulse
A5 A4 A3 A2 A1 A0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 : : :
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
: : : : : :

Synchronous (Parallel) Counters

Preamble
 In the previous Asynchronous (ripple) binary counter discussion,

we saw that the output of one counter stage is connected directly to
the clock input of the next counter stage and so on along the chain.
The result of this is that the Asynchronous counter suffers from
what is known as “Propagation Delay” in which the timing signal is
delayed a fraction through each flip-flop.
 However, with the Synchronous (Parallel) Counter, the external

clock signal is connected to the clock input of EVERY individual flip-
flop within the counter so that all of the flip-flops are clocked
together simultaneously (in parallel) at the same time giving a fixed
time relationship. In other words, changes in the output occur in
“synchronisation” with the clock signal.
The result of this synchronisation is that all the individual output
bits changing state at exactly the same time in response to the
common clock signal with no ripple effect and therefore, no
propagation delay.
Triggering A Synchronous Counter
 Synchronous Counters use edge-triggered flip-flops that change

states on either the “positive-edge” (rising edge) or the “negative-
edge” (falling edge) of the clock pulse on the control input resulting
in one single count when the clock input changes state.
 Generally, synchronous counters count on the rising-edge which is
the low to high transition of the clock signal and asynchronous
(ripple) counters count on the falling-edge which is the high to low
transition of the clock signal.

Triggering A Synchronous Counter…
 It may seem unusual that ripple counters use the falling-

edge of the clock cycle to change state, but this makes it
easier to link counters together because the most
significant bit (MSB) of one counter can drive the clock
input of the next.
This works because the next bit must change state when
the previous bit changes from high to low – the point at
which a carry must occur to the next bit. Synchronous
counters usually have a carry-out and a carry-in pin for
linking counters together without introducing any
propagation delays.

Synchronous (Parallel) Counters
 Synchronous (parallel) counters: the flip-flops are

clocked at the same time by a common clock pulse.
 Synchronous counters can be design using the
sequential logic design process.
 Example: 2-bit synchronous binary counter (using T flip-
flops, or JK flip-flops with identical J,K inputs).
Present Next Flip-flop

state state inputs
00 01
A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
11 10 0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

Synchronous (Parallel) Counters…
 Example: 2-bit synchronous binary counter (using T flip-flops, or

JK flip-flops with identical J,K inputs).

state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA1 = A0
0 0 0 1 0 1 TA0 = 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1
A0 J A1
J Q Q
C C
Q' K Q'
K
CLK

 Example: 3-bit synchronous binary counter (using T flip-

flops, or JK flip-flops with identical J, K inputs).
state state inputs
A2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A1 A1 A1
1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1
A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1
Example: 3-bit synchronous binary counter (cont’d).

TA2 = A1.A0 TA1 = A0 TA0 = 1
A2 A1 A0
Q Q Q
J K J K J K
CP
1

 Note that in a binary counter, the nth bit (shown

underlined) is always complemented whenever
011…11  100…00
or 111…11  000…00
 Hence, Xn is complemented whenever
Xn-1Xn-2 ... X1X0 = 11…11.
 As a result, if T flip-flops are used, then
TXn = Xn-1 . Xn-2 . ... . X1 . X0

 Example: 4-bit synchronous binary counter.

TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1
1 A1.A0 A2.A1.A0
A0 J A1 J A2 J A3
J Q Q Q Q
C C C C
Q' K Q' K Q' K Q'
K
CLK

Up/Down Synchronous Counters
Binary 4-bit Synchronous Up Counter
It can be seen above, that the external clock pulses (pulses to be counted) are
fed directly to each of the J-K flip-flops in the counter chain and that both the J
and K inputs are all tied together in toggle mode, but only in the first flip-flop,
flip-flop FFA (LSB) are they connected HIGH, logic “1” allowing the flip-flop to
toggle on every clock pulse. Then the synchronous counter follows a
predetermined sequence of states in response to the common clock signal,
advancing one state for each pulse.
Up/Down Synchronous Counters…
Binary 4-bit Synchronous Up Counter
The J and K inputs of flip-flop FFB are connected directly to the output QA of
flip-flop FFA, but the J and K inputs of flip-flops FFC and FFD are driven from
separate AND gates which are also supplied with signals from the input and
output of the previous stage.
 These additional AND gates generate the required logic for the JK inputs of
the next stage.

4-bit Synchronous Counter Waveform Timing Diagram
Because this 4-bit synchronous counter counts sequentially on every clock pulse
the resulting outputs count upwards from 0 ( 0000 ) to 15 ( 1111 ). Therefore, this
type of counter is also known as a 4-bit Synchronous Up Counter.

Binary 4-bit Synchronous Down Counter
A 4-bit Synchronous Down Counter can be constructed by connecting the

AND gates to the Q output of the flip-flops as shown to produce a waveform
timing diagram the reverse of the above. Here the counter starts with all of its
outputs HIGH ( 1111 ) and it counts down on the application of each clock
pulse to zero, ( 0000 ) before repeating again.

Decade counter or BCD counter
Synchronous counters are formed by connecting flip-

flops together and any number of flip-flops can be
connected or “cascaded” together to form a “divide-by-n”
binary counter, the modulo’s or “MOD” number still
applies as it does for Asynchronous counters so a
Decade counter or BCD counter with counts from 0 to
2n-1 can be built along with truncated sequences.
What is needed is to increase the MOD count of an up
or down synchronous counter by increasing an additional
flip-flop or AND gate across it.

 Example: Synchronous decade/BCD counter.
Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1 T0 = 1
2 0 0 1 0 T1 = Q3'.Q0
3 0 0 1 1 T2 = Q1.Q0
4 0 1 0 0
5 0 1 0 1 T3 = Q2.Q1.Q0 + Q3.Q0
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 (recycle) 0 0 0 0

 Example: Synchronous decade/BCD counter (cont’d).
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0
Q0
1 T T Q1 T Q2 T Q3
Q Q Q Q
C C C C
Q' Q' Q' Q'
CLK

Serial Synchronous Counter Asynchronous Counter

No.
1. In synchronous counter, all flip flops are In asynchronous counter, different flip
triggered with same clock simultaneously flops are triggered with different clock, not
simultaneously.
2. Synchronous Counter is faster than Asynchronous Counter is slower than
asynchronous counter in operation. synchronous counter in operation.
3. Synchronous Counter does not produce Asynchronous Counter produces decoding
any decoding errors. error.
4. Synchronous Counter is also called Parallel Asynchronous Counter is also called Serial
Counter. Counter.
5. Synchronous Counter designing as well Asynchronous Counter designing as well as
implementation are complex due to implementation is very easy.
increasing the number of states.
6. Synchronous Counter will operate in any Asynchronous Counter will operate only in
desired count sequence fixed count sequence (UP/DOWN).
7. Synchronous Counter examples are: Ring Asynchronous Counter examples are:
counter, Johnson counter. Ripple UP counter, Ripple DOWN counter.
8. In synchronous counter, propagation In asynchronous counter, there is high
delay is less. propagation delay.

Examples of Synchronous and
Asynchronous
74HC192
Pin Package
Asynchronous
Synchronous Counter
Counter
Surface Mount Package

Digital Multimeter (DMM)
Portable Analog
Multimeter
Hand-held
DMM
Bench top
UDSM, 12.05.2021
DMM CS212: Counters and Timers Page 42
Digital Voltmeter (DVM)

Comparison of Digital and Analogue Meter

Analogue to Digital Conversion

Analogue to Digital Conversion…

Ramp-type Digital Voltmeter

Comparator

Ramp-type Digital Voltmeter

Staircase Ramp Digital Voltmeter

Successive Approximation Digital
Voltmeter

Digital Ramp Vs Successive Approximation
Digital Ramp Method Successive Approximation Method

Dual-slope Digital Voltmeter

Dual-slope Digital Voltmeter…

Exercises

Exercises…

Typical Specification of DMM

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College of Information and Communication Technologies

Department of Computer Science and Engineering

CS212 : Measurement and

Counters & Timers

UDSM, 12.05.2021 CS212: Counters and Timers Page 2

Counters are important element in digital

Counters are designed by grouping of flip flops and

UDSM, 12.05.2021 CS212: Counters and Timers Page 4

Counters are the crucial hardware components in a

Counting means incrementing or decrementing the

There are two types of counters available for digital circuits,

UDSM, 12.05.2021 CS212: Counters and Timers Page 6

Asynchronous (ripple) counters allow some flip-

UDSM, 12.05.2021 CS212: Counters and Timers Page 7

 Asynchronous counters: the flip-flops do not change

UDSM, 12.05.2021 CS212: Counters and Timers Page 8

 Example: 2-bit ripple binary counter.

UDSM, 12.05.2021 CS212: Counters and Timers Page 9

Example: 3-bit ripple binary counter.

UDSM, 12.05.2021 CS212: Counters and Timers Page 10

 Propagation delays in an asynchronous (ripple-clocked)

UDSM, 12.05.2021 CS212: Counters and Timers Page 11

 Example: 4-bit ripple binary counter (negative-edge triggered).

UDSM, 12.05.2021 CS212: Counters and Timers Page 12

 States may be skipped resulting in a truncated

UDSM, 12.05.2021 CS212: Counters and Timers Page 13

UDSM, 12.05.2021 CS212: Counters and Timers Page 14

Example (cont’d): Counting sequence of circuit (in CBA

UDSM, 12.05.2021 CS212: Counters and Timers Page 15

 Exercise: How to construct an asynchronous MOD-5

UDSM, 12.05.2021 CS212: Counters and Timers Page 16

 Decade counters (or BCD counters) are counters with

UDSM, 12.05.2021 CS212: Counters and Timers Page 17

 Asynchronous decade/BCD counter (cont’d).

 So far we are dealing with up counters. Down counters,

UDSM, 12.05.2021 CS212: Counters and Timers Page 19

 Example: A 3-bit binary (MOD-8) down counter.

UDSM, 12.05.2021 CS212: Counters and Timers Page 20

 Larger asynchronous (ripple) counter can be constructed

Modulus-4 counter Modulus-8 counter

UDSM, 12.05.2021 CS212: Counters and Timers Page 21

Example: A 6-bit binary counter (counts from 0 to 63)

Count 3-bit 3-bit

UDSM, 12.05.2021 CS212: Counters and Timers Page 22

Synchronous (Parallel) Counters

UDSM, 12.05.2021 CS212: Counters and Timers Page 23

 In the previous Asynchronous (ripple) binary counter discussion,

 However, with the Synchronous (Parallel) Counter, the external

 Synchronous Counters use edge-triggered flip-flops that change

UDSM, 12.05.2021 CS212: Counters and Timers Page 25

 It may seem unusual that ripple counters use the falling-

UDSM, 12.05.2021 CS212: Counters and Timers Page 26

 Synchronous (parallel) counters: the flip-flops are

Present Next Flip-flop

UDSM, 12.05.2021 CS212: Counters and Timers Page 27

 Example: 2-bit synchronous binary counter (using T flip-flops, or

Present Next Flip-flop

UDSM, 12.05.2021 CS212: Counters and Timers Page 28

 Example: 3-bit synchronous binary counter (using T flip-