Introduction To Power Electronic

1
Introduction to Power Electronic

Converters
Power electronic converters are a family of electrical circuits which convert
electrical energy from one level of voltage/current/frequency to another using
semiconductor-based electronic switches. The essential characteristic of these
types of circuits is that the switches are operated only in one of two states -
either fully ON or fully OFF - unlike other types of electrical circuits where the
control elements are operated in a (near) linear active region. As the power
electronics industry has developed, various families of power electronic con-
verters have evolved, often linked by power level, switching devices, and topo-
logical origins. The process of switching the electronic devices in a power
electronic converter from one state to another is called modulation, and the
development of optimum strategies to implement this process has been the
subject of intensive international research efforts for at least 30 years. Each
family of power converters has preferred modulation strategies associated with
it that aim to optimize the circuit operation for the target criteria most appropri-
ate for that family. Parameters such as switching frequency, distortion, losses,
harmonic generation, and speed of response are typical of the issues which
must be considered when developing modulation strategies for a particular
family of converters.
Figure 1.1 presents a categorization of power electronic converters into
families according to their type of electrical conversion. Of these families, con-
verters that change energy to or from alternating current (AC) form involve
much more complex processes than those that solely involve direct current
(DC). The purpose of this book is to explore the converter modulation issue in
detail as it relates to high power DC/AC (inverting) and AC/DC (rectifying)
converters, with particular emphasis on the process of open-loop pulse width
modulation (PWM) applied to these types of converters. This chapter presents
the fundamentals of inverter structures, block-switching voltage control, and
space vector concepts, as a foundation for the material to follow.
2 Introduction to Power Electronic Converters
.____Ac_._vi._11__.I ~
AC/DC Rectifier
~ DC/DC
Converter
AC/AC Converter DC Link ___. I DC,Vdcl I ~ ... I DC, vdc2 I
(Matrix Converter) Converter
l DC/~tifier
~A_c._v2_.fi~I /
Figure 1.1 Families of solid state power converters categorized

according to their conversion function.
1.1 Basic Converter Topologies
1.1.1 Switch Constraints

The transistor switch used for solid state power conversion is very nearly
approximated by a resistance which either approaches zero or infinity depend-
ing upon whether the switch is closed or opened. However, regardless of where
the switch is placed in the circuit, Kirchoff's voltage and current laws must, of
course, always be obeyed. Translated to practical terms, these laws give rise to
the two basic tenets of switch behavior:
The switch cannot be placed in the same branch with a current source
(i.e., an inductance) or else the voltage across the inductor (and conse-
quently across the switch) will become infinite when the switch turns
off. As a corollary to this statement it can be argued that at least one of
the elements in branches connected via a node to the branch containing
the switch must be non-inductive for the same reason.
Basic Converter Topologies
• The switch cannot be placed in parallel with a voltage source (i.e., a true
source or a capacitance) or else the current in the switch will become
infinite when the switch turns on. As a corollary it can be stated that if
more than one branch forms a loop containing the switch branch then at
least one of these branch elements must not be a voltage source.
If the purpose of the switch is to aid in the process of transferring energy
from the source to the load, then the switch must be connected in some manner
so as to select between two input energy sources or sinks (including the possi-
bility of a zero energy source). This requirement results in the presence of two
branches delivering energy to one output (through a third branch). The pres-
ence of three branches in the interposing circuit implies a connecting node
between these branches.
One of the three branches can contain an inductance (an equivalent current
source frequently resulting from an inductive load or source), but the other
branches connected to the same node must not be inductive or else the first
basic tenet will be violated. The only other alternatives for the two remaining
branches are a capacitance or a resistance. However, when the capacitor is con-
nected between the output or input voltage source and the load, it violates the
second tenet. The only choice left is a resistance.
The possibility of a finite resistance can be discarded as a practical matter
since the circuit to be developed must be as highly efficient as possible, so that
the only possibility is a resistor having either zero or infinite resistance, i.e., a
second switch. This switch can only be turned on when the first switch is
turned off, or vice versa, in order to not violate Kirchoff 's current law. For the
most common case of unidirectional current flow, a unidirectional switch
which inhibits current flow in one direction can be used, and this necessary
complementary action is conveniently achieved by a simple diode, since the
demand of the inductance placed in the other branch will assure the required
behavior. Alternatively, of course, the necessary complementary switching
action can be achieved by a second unidirectional switch. The resulting cir-
cuits, shown in Figure 1.2, can be considered to be the basic switching cells of
power electronics. The switches having arrows in (b) and (c) denote unidirec-
tional current flow devices.
When the circuit is connected such that the current source (inductance) is
connected to the load and the diode to the source, one realizes what is termed a
step-down chopper. If the terminals associated with input and output are
Introduction to Power Electronic Converters
/ / /
(a) (b) / ^ (c)
Figure 1.2 Basic commutation cells of power electronic converters using

(a) bidirectional switches and (b) and (c) unidirectional switches.
reversed, a step-up chopper is produced. Energy is passed from the voltage

source to the current "source" (i.e., the load) in the case of the step-down con-
verter, and from the current source to the voltage "source" (load) in the case of
the step-up converter.
Since the source voltage sums to the voltage across the switch plus the
diode and since the load is connected across the diode only, the voltage is the
quantity that is stepped down in the case of the step-down chopper. Because of
the circulating current path provided by the diode, the current is consequently
stepped up. On the other hand the sum of the switch plus diode voltage is equal
to the output voltage in the case of the step-up chopper so that the voltage is
increased in this instance. The input current is diverted from the output by the
switch in this arrangement so that the current is stepped down.
Connecting the current source to both the input and output produces the up-
down chopper configuration. In this case the switch must be connected to the
input to control the flow of energy into/out of the current source. Since the
average value of voltage across the inductor must equal zero, the average volt-
age across the switch must equal the input voltage while the average voltage
across the diode equals the output voltage. Ratios of input to output voltages
greater than or less than unity (and consequently current ratios less or greater
than unity) can be arranged by spending more or less than half the available
time over a switching cycle with the switch closed. These three basic DC/DC
converter configurations are shown in Figure 1.3.
1.1.2 Bidirectional Chopper

In cases where power flow must occur in either direction a combination of a
step-down and a step-up chopper with reversed polarity can be used as shown
Basic Converter Topologies
+ + + +
+ +
Vin Vout Vin Vou,
(a) (b) (c)
Figure 1.3 The three basic DC/DC converters implemented with a

basic switching cell (a) step-down chopper, (b) step-up
chopper, and (c) up-down chopper.
in Figure 1.4. The combination of the two functions effectively places the
diodes in inverse parallel with switches, a combination which is pervasive in
power electronic circuits. When passing power from left to right, the step-
down chopper transistor is operated to control power flow while the step-up
chopper transistor operates for power flow from right to left in Figure 1.4. The
two switches need never be (and obviously should never be) closed at the same
instant.
1.1.3 Single-Phase Full-Bridge (H-Bridge) Inverter

Consider now the basic switching cell used for DC/AC power conversion. In
Figure 1.4 it is clear that current can flow bidirectionally in the current source/
sink of the up-down chopper. If this component of the circuit is now considered
as an AC current source load and the circuit is simply tipped on its side, the
half-bridge DC/AC inverter is realized as shown in Figure 1.5. Note that in this
case the input voltage is normally center-tapped into two equal DC voltages,
Vdc\ = ^dci = Vdc-> xxv orc * er t 0 produce a symmetrical AC voltage wave-
form. The total voltage across the DC input bus is then 2Vdc. The parallel
combination of the unidirectional switch and inverse conducting diode forms
+ +
ViH *out
Figure 1.4 Bidirectional chopper using one up-chopper and one down-
chopper.
+
VdcX Load D
i T
i
+
D2 T
2
Vdcl *ctc
Figure 1.5 Half-bridge single-phase inverter.
the first type of practical inverter switch. The switch combination permits uni-
directional current flow but requires only one polarity of voltage blocking abil-
ity and hence is suitable, in this case, for operating from a DC voltage source.
It is important to note that in many inverter circuits the center-tap point of
the DC voltage shown in Figure 1.5 will not be provided. However, this point
is still commonly used either as an actual ground point or else, in more elabo-
rate inverters, as the reference point for the definition of multiple DC link volt-
ages. Hence in this book, the total DC link voltage is considered as always
consisting of a number of DC levels, and with conventional inverters that can
only switch between two levels it will always be defined as 2 Vdc.
The structure of a single-phase full-bridge inverter (also known as a H -
bridge inverter) is shown in Figure 1.6. This inverter consists of two single-
phase leg inverters of the same type as Figure 1.5 and is generally preferred
over other arrangements in higher power ratings. Note that as discussed above,
the DC link voltage is again defined as 2 Vdc. With this arrangement, the max-
imum output voltage for this inverter is now twice that of the half-bridge
inverter since the entire DC voltage can be impressed across the load, rather
than only one-half as is the case for the half-bridge. This implies that for the
same power rating the output current and the switch currents are one-half of
those for a half-bridge inverter. At higher power levels this is a distinct advan-
tage since it requires less paralleling of devices. Also, higher voltage is pre-
ferred since the cost of wiring is typically reduced as well as the losses in many
types of loads because of the reduced current flow.
In general, the converter configurations of Figures 1.5 and 1.6 are capable
of bidirectional power flow. In the case where power is exclusively or prima-
rily intended to flow from DC to AC the circuits are designated as inverters,
while the same circuits are designated rectifiers if the reverse is true. In cases
Voltage Source/Stiff Inverters
+
T
l D
l
Load
°3' T
3
V
bi<s=2Vdc
T
T
2 D2 *ac D
4 4
Figure 1.6 Single-phase full-bridge (H-bridge) inverter
where the DC supplies are derived from a source such as a battery, the inverter
is designated as a voltage source inverter (VSI). If the DC is formed by a tem-
porary DC supply such as a capacitor (being recharged ultimately, perhaps,
from a separate source of energy), the inverter is designated as a voltage stiff
inverter to indicate that the link voltage tends to resist sudden changes but can
alter its value substantially under heavy load changes. The same distinction can
also be made for the rectifier designations.
1.2 Voltage Source/Stiff Inverters
1.2.1 Two-Phase Inverter Structure

Inverters having additional phases can be readily realized by simply adding
multiple numbers of half-bridge (Figure 1.5) and full-bridge inverter legs (Fig-
ure 1.6). A simplified diagram of a two-phase half-bridge inverter is shown in
Figure 1.7(a). While the currents in the two phases can be controlled at will,
the most desirable approach would be to control the two currents so that they
are phase shifted by 90° with respect to each other (two-phase set) thereby
producing a constant amplitude rotating field for an AC machine. However,
note that the sum of the two currents must flow in the line connected to the
center point of the DC supplies. If the currents in the two phases can be
approximated by equal amplitude sine waves, then
'neutral = /sin<Dof+ / s i n ( © 0 / + | )
72/sinfa)o/+2 (i.i)
+
Dl Tl D3 T
3
Vdc
(a) +
D2 T2 D4 T4
Vdc
Dl Tl D
3 T3 D5" T5 D7 T7
2Vdc=Vbus
(b) T
D2 T2 D4 4 D6 T6 D8 T
8
Figure 1.7 Two-phase (a) half-bridge and (b) full-bridge inverters.
Since a relatively large AC current must flow in the midpoint connection, this
inverter configuration is not commonly used. As an alternative, the midpoint
current could be set to zero if the currents in the two phases were made equal
and opposite. However, this type of operation differs little from the single-
phase bridge of Figure 1.6 except that the neutral point of the load can be con-
sidered as being grounded (i.e., referred to the DC supply midpoint). As a
result this inverter topology is also not frequently used.
The full-bridge inverter of Figure 1.7(b) does not require the DC midpoint
connection. However, eight switches must be used which, in most cases, makes
this possibility economically unattractive.
1.2.2 Three-Phase Inverter Structure

The half-bridge arrangement can clearly be extended to any number of phases.
Figure 1.8 shows the three-phase arrangement. In this case, operation of an AC
motor requires that the three currents are a balanced three-phase set, i.e., equal
amplitude currents with equal 120° phase displacement between them. How-
ever it is easily shown that the sum of the three currents is zero, so that the con-
nection back to the midpoint of the DC supply is not required. The
Connection not
p necessary
Vdc Di Ti D3 T3 D5 T5
a
b
+z s
c
D4 T4 D6 T6 D2 T2
Vdc
n
Figure 1.8 Three-phase bridge-type voltage source inverter.
simplification afforded by this property of three-phase currents makes the

three-phase bridge-type inverter the de facto standard for power conversion.
However while the connection from point s (neutral of the star-connected sta-
tionaiy load to the midpoint z {zero or reference point of the DC supply) need
not be physically present, it remains useful to retain the midpoint z as the refer-
ence (ground) for all voltages. Also note that p and n are used in this text to
denote the positive and negative bus voltages respectively, with respect to the
midpoint z.
1.2.3 Voltage and Current Waveforms in Square-Wave

Mode
The basic operation of the three-phase voltage inverter in its simplest form can
be understood by considering the inverter as being made up of six mechanical
switches. While it is possible to energize the load by having only two switches
closed in sequence at one time (resulting in the possibility of one phase current
being zero at instances in a switching cycle), it is now accepted that it is prefer-
able to have one switch in each phase leg closed at any instant. This ensures
that all phases will conduct current under any power factor condition. If two
switches of each phase leg are turned on for a half cycle each in nonoverlap-
ping fashion, this produces the voltage waveforms of Figure 1.9 at the output
terminals a, b, and c, referred to the negative DC bus n. The numbers on the
top part of the figure indicate which switches of Figure 1.8 are closed. The
sequence is in the order 123, 234, 345, 456, 561, 612, and back to 123.
561 612 123 234 345 456
v
an
2Vdc
n In
v
bn
2Vdc
2TI/3 5TI/3
v
cn
2Vdc
JT/3 4TX/3
Figure 1.9 The six possible connections of a simple three-phase

voltage stiff inverter. The three waveforms show voltages
from the three-phase leg outputs to the negative DC bus
voltage.
The line-to-line (/-/) voltage vab then has the quasi-square waveform
shown in Figure 1.10. As will be shown shortly, the line-to-line voltage con-
tains a root-mean-square (RMS) fundamental component of
1, //, rms •= 1.56Fdc (1.2)
Thus, a standard 460 V, 60 Hz induction motor would require 590 V at the DC

terminals of the motor to operate the motor at its rated voltage and speed. For
this reason a 600 V DC bus (i.e., Vdc = 300 V ) is quite standard in the United
States for inverter drives.
Although motors function as an active rather than a passive load, the effec-
tive impedances of each phase are still balanced. That is, insofar as voltage
drops are concerned, active as well as passive three-phase loads may be repre-
sented by the three equivalent impedances [and electromotive forces (EMFs)]
shown in Figure 1.10 for the six possible connections. Note that each individ-
ual phase leg is alternately switched from the positive DC rail to the negative
DC rail and that it is alternately in series with the remaining two phases con-
561 612 123 234 345 456
v 2Vdc
ab n 5TT/3
2TT/3 271
v
bc TT/3 Wdc 5TT/3
2n/3 4TT/3
v
ca TI/3 71
2*W
4TI/3 2TT
4/3 Vdc
v
as wvdc
v
bs
v
cs
Figure 1.10 The three line-to-line and line-to-neutral load voltages

created by the six possible switch connection arrangements of
a six-step voltage stiff inverter.
nected in parallel, or it is in parallel with one of the other two phases and in
series with the third. Hence the voltage drop across each phase load is always
one-third or two-thirds of the DC bus voltage, with the polarity of the voltage
drop across the phase being determined by whether it is connected to the posi-
tive or negative DC rail.
A plot of the line and phase voltages for a typical motor load is included in
Figure 1.10. The presence of six "steps" in the load line-to-neutral voltage
waveforms vas, vbs, and vcs, is one reason this type of inverter is called a six-
step inverter, although the term six-step in reality pertains to the method of
voltage/frequency control rather than the inverter configuration itself.
A Fourier analysis of these waveforms indicates a simple square-wave type
of geometric progression of the harmonics. When written as an explicit time
function, the Fourier expansion for the time-varying a phase to negative DC
bus voltage n can be readily determined to be
v
™(0 = ^ c J g + sino3^+^sin3co^ + |sin5o3or4-isin7o3or+--.] (1.3)
The b and c phase to negative DC bus voltages can be found by replacing co0/
with (a> o f-27i/3) and (oo0f + 2TC/3), respectively, in Eq. (1.3).
The vab line-to-line voltage is found by subtracting vbn from van to give
vfl*(0=^c^[sin((V^
(1.4)
Similar relationships can be readily found for the vbc and vca voltages, phase
shifted by -27i/3 and + 2TC/3, respectively. Note that harmonics of the order
of multiples of three are absent from the line-to-line voltage, since these triplen
harmonics cancel between the phase legs.
In terms of RMS values, each harmonic of the line-to-neutral voltages has
the value of
and, for the line-to-line voltages,

2^6 \
VnSUrms= Vdc^ n Z n where/I = 6*± 1, *= 1,2,3,... (1.6)
Because of its utility as a reference value for pulse width modulation in
later chapters, it is useful to write the fundamental component of the line-to-
neutral voltage in terms of its peak value referred to half the DC link voltage,
in which case
Voltage Source/Stiff Inverters 13
\Jn,pk = lVdc=V] (1.7)
This value is, of course, the fundamental component of a square wave of

amplitude Vdc. It should be noted also that since the use of peak rather than
RMS quantities will predominate in this book, quantities in capital letters will
denote only DC or peak AC quantities. Hence, for simplicity Vx in Eq. (1.7)
has the same meaning as Vlln k. When the quantity is intended to be root-
mean-square, the subscript rms will always be appended. For example, the
term VXjnrms designates the RMS fundamental value of the line-to-neutral
voltage.
Assuming an R-L-EMF load, the current as well as voltage waveforms are

sketched for both wye and delta connections in Figure 1.11 (a). Note that when
the inverter current flows in opposite polarity to the voltage, the current is car-
ried by the feedback diode (in a step-up chopper mechanism) in much the same
manner as for the single-phase inverter. The transfer of current from main to
auxiliary switches is illustrated by the conduction pattern of Figure 1.11 and
can be used to determine the DC side inverter current waveform Idc. For exam-
ple, from the moment that T 3 is turned off to the instant that D 2 turns on, the
input current is equal to the current in T 1? that is, ia. This interval lasts one-
sixth of a period or 60°. During the next 60°, switch T 6 returns current to the
v
as 'a
Idc
o.o
0.0
0 0
0 0.006 0.012 0.018 0.024 0.03 °006 °012 °°18 0 0 2 4 0 0 3
/(sec) /(sec)
(a) (b)
Figure 1.11 Current flow in three-phase voltage stiff inverter: (a) phase
voltage and current waveform, wye-connected load, and (b)
DC link current.
DC link. In effect, the link current is equal to -ic. Continuing through all six
60° intervals generates the DC link current shown in Figure 1.1 l(b). For the
case shown, Idc is both positive and negative so that a certain amount of energy
transfers out of and into the DC supplies. If the load current is considered to be
sinusoidal, it can be shown that Idc is always positive only when the fundamen-
tal power factor is greater than 0.55. However, in any case, the source supplies
the average component of the link current while a current with frequency six
times the fundamental frequency component circulates in and out of the DC
capacitor. The sizing of the capacitor to accommodate these harmonics, regard-
less of the modulation algorithm, is a major consideration in inverter design.
1.3 Switching Function Representation of

Three-Phase Converters
The basic three-phase inverter circuit operation shown in Figures 1.9 and 1.10
can be condensed to equation form by defining logic-type switching functions
which express the closure of the switches [1, 2] 1 . For example, let
ml9 m2, ..., m6 take on the value "+1" when switches T l5 T2, ...,T6 are closed
and the value "zero" when opened. The voltages from the three-phase legs to
the DC center point can then be expressed as
v
az= Vdc{mx-mA)
^z=^c(m3-m6) (1.8)
V
cz= V
dc(m5~m2)
Considering now the constraints imposed by the circuit it is apparent that

both the top and bottom switches of a given phase cannot be closed at the same
time. Furthermore, from current continuity considerations in each phase leg
m j + m4 = 1
/w3 + #w 6 = 1 (1.9)
=
m5 + m2 1
References referred to throughout this text are given at the end of each chapter. A more
exhaustive set of references are located in the Bibliography.
Switching Function Representation of Three-Phase Converters 15
Substituting Eq. (1.9) into Eq. (1.8) gives
v«=^c(2wi-l)
vbz=Vdc(2m3-l) (1.10)
vCz=rrfc(2«5-i)
Since the quantities in the parentheses of Eq. (1.10) take on the values ±1,
it is useful to define new variables ma, mb, rnc, such that ma = 2mx - 1, etc.
Hence, more compactly,
V V
az = dcma
vhz=Vdcmb (1.11)
V = V
cz dcmc
The current in the DC link can be expressed as

ma + 1 mb + 1 mc + 1
l = l +z +Z C
dc a 2 ^ 2 ' 2 ( 1<12 )
However, since
ia + h + ic = 0
Equation (1.12) reduces to
he = 2^^ma+ibmb +i m
c c) (L13>
The line-to-line AC voltages are
V
ab = Vaz-Vbz= V
dc(ma~mb)
V
bc = Vbz-Vcz= V
ddmb~mc) (U4>
v
ca = v
cz-vaz=Vdc(mc-ma)
If the load is star connected, the load line-to-neutral (phase) voltages can be
expressed as
v —v — v
as az sz
v, = Vt — v (1.15)
v
bs bz vsz v J
v —v — v
cs cz sz
For most practical cases, the phase impedances in all three legs of the star
load are the same. Hence, in general,
V
as = Z(P)'a
vbs = Z{p)ih (1.16)
v
cs = Z(P)'c
where the operator p = d/dt and the impedance Z(p) is an arbitrary function
of p (which is the same in each phase). The phase voltages can now be solved
by adding together the three parts of Eq. (1.16), to produce
V
as + Vbs + Vcs = Vaz + Vbz + V
cz^Vsz
= Z(p)(ia + ib + ic) = 0 (1.17)
Thus
V
sz = ^Vaz +V
bz + Vcz)
= \vdc{ma + mb + mc) (1.18)
The phase voltages can now be expressed as
v = !v _IV,- - v (I 19)
v
as 3 vaz ybz 3 l cz \L-iy)
so that, from Eq. (1.8),
(L20)
v« = ^c(K-S-K)
Similarly
V
bs = Vdc\^mb-\ma-\mc) (1-21)
"cs = Vdc{^nc-\ma-\m^ (1-22)
Finally, the power flow through the inverter is given by

Pdc = 2 Vdcldc = Vdc(iama + ibmb + icmc) (1.23)
Equations (1.20) to (1.22) are convenient for use in defining switching func-
tions representing the converter's behavior in different frames of reference [2].
Output Voltage Control 17
1.4 Output Voltage Control

A power electronic inverter is essentially a device for creating a variable AC
frequency output from a DC input. The frequency of the output voltage or cur-
rent is readily established by simply switching for equal time periods to the
positive and the negative DC bus and appropriately adjusting the half-cycle
period. However, the variable frequency ability is nearly always accompanied
by a corresponding need to adjust the amplitude of the fundamental component
of the output waveform as the frequency changes, i.e., voltage control. This
section introduces the concept of voltage control, a central theme of this book.
1.4.1 Volts/Hertz Criterion

In applications involving AC motors, the load can be characterized as being
essentially inductive. Since the time rate of change of flux linkages X in an
inductive load is equal to the applied voltage, then
I
X = J v dt (1.24)
If one is only concerned with the fundamental component, then, if a phase volt-
age is of the form v = Vx cosco 0 /\ the corresponding flux linkage is
Xx = — sinco^ (1.25)
suggesting that the fundamental component of voltage must be varied in pro-

portion to the frequency if the amplitude of the flux in the inductive load is to
remain sensibly constant.
1.4.2 Phase Shift Modulation for Single-Phase Inverter

The method by which voltage adjustment is accomplished in a solid state
power converter is the heart of the issue of modulation. Much more detail will
be developed concerning modulation techniques in later chapters. However, a
very simple introductory example of modulation can be obtained by taking a
single-phase inverter as shown in Figure 1.12(a) and operating each phase leg
with a 50% duty cycle but with a phase delay of n - a between the two phase
legs. Typical waveforms for this inverting operation (DC-to-AC power conver-
sion) in what can be termed phase shift voltage control or phase shift modula-
p
T|. T3.
D| D3
a< b
(a) 2Vdc
T2, T4
D2 D4
n
v
+ ab -
v
an
\2Vdc
a t
v
bn 180°
2Vdc
(b) 180°-a t
180°
v
ab
2Vdc
a t
180°-a
Figure 1.12 Full-bridge, single-phase inverter control by phase shift

cancellation: (a) power circuit and (b) voltage waveforms.
tion are shown in Figure 1.12(b). Clearly, as the phase delay angle a changes,
the RMS magnitude of the line-to-line output voltage changes.
The switched output voltage of this inverter can be represented as the sum
of a series of harmonic components (a Fourier series in fact). The magnitude of
each harmonic can be conveniently evaluated using the quantity
P = 9 0 ° - a / 2 where a is as shown in Figure 1.12. Conventional Fourier
analysis gives, for each harmonic n, a peak harmonic magnitude of
71/2
Vab(n) = l \ 2VdccosnQdQ (1.26)

-7T/2
Output Voltage Control 19
P
= Vdc- [ cosnQdQ
-P
O
= Vd—sin/?p
= Vdc— cos — where n is odd (1.27)
Figure 1.13 shows the variation of the fundamental frequency and har-
monic components as a function of the overlap angle a. The components are
normalized with respect to 2 Vdc.
1.4.3 Voltage Control with a Double Bridge

While voltage control is not possible with a conventional six-step inverter
without adjusting the DC link voltage, some measure of voltage control is pos-
1,4
—•—1
1.2 <^-- -
\ 1
1.0
\
0.8
In. \
2Fdc 0.6
—?^ ^— \
0.4
^ ^<
0.2
\
0° 20° 40° 60° 80° 100° 120° 140° 160° 180°
a
Figure 1.13 First five odd (nonzero) harmonic components of single-
phase inverter with phase shift control as a function of
phase shift angle a normalized with respect to 2Vdc
sible with a double bridge as shown in Figure 1.14. Note that this type of
bridge is essentially three single-phase bridges so that voltage control can
again be accomplished by phase shifting in much the same manner as the over-
lap method described by Figure 1.12. To avoid short circuits the three-phase
load must either be separated into three electrically isolated single-phase loads
or a transformer must be used to provide electrical isolation. Figure 1.14 shows
the output phase voltages of this inverter.
Recall also that when the phase output voltages are coupled through a
transformer into a three-phase voltage set with a common neutral, harmonics
of multiples of three are eliminated in the line-to-line output voltages by virtue
of the 120° phase shift between the quasi square waves of each phase.
(a) ™dc C
n
a b c
a b' c'
v
\a
aa'
Wdc 71
2TT
V
bb'
(b) 2*V 57T/3
2rc/3
v
cc'
71/3 2VdA
4TU/3
Figure 1.14 Double three-phase bridge arrangement: (a) basic circuit

and (b) voltage waveforms.
Current Source/Stiff Inverters 21
1.5 Current Source/Stiff Inverters

Up to this point the focus has been on the most popular class of power convert-
ers, i.e., those operating with a voltage source or with a stiff capacitor on the
DC side of the converter. However, another class of inverters evolve from the
dual concept of a current source or stiff inductor on the DC side. These con-
verters can be developed from essentially the same starting point using the
basic commutation cells of Figure 1.2, except that the diode is replaced with a
second switch in order to have complete control over the direction of the
inductor current. Figure 1.15 briefly depicts the evolution of the three-phase
current source/stiff inverter. In Figure 1.15(a) the current source commutation
cell is shown, and in Figure 1.15(b) the inductor is chosen as the source so that
the switch branches become loads. Since the switch branches are connected in
series with the load, these loads must clearly be noninductive so as to not pro-
duced infinite voltage spikes across the switches. In order to create AC cur-
rents in the load two such commutation cells are used - one to produce positive
current and the other to produce negative current in the load as shown in Figure
1.15(c). A single-phase bridge is produced by recognizing that no current need
flow in the center point connection between the two current sources if they
produce the same amplitude of current, as shown in Figure 1.15(d). Finally, a
third phase is added in the same manner to produce a three-phase current
source inverter, Figure 1.15(e). This evolution realizes the second practical
switch combination suitable for DC current sources, a bidirectional voltage
blocking, unidirectional current conducting switch. At the present time, such a
switch is typically realized by a series-connected transistor and diode arrange-
ment, as shown in Figure 1.15(f).
The basic switching strategy for this converter can again be summarized
using switching functions. If mx, m2, ..., m6 are defined as +1 when switches
Tj, T 2 , ...,T6 are closed and zero when they are open, then to ensure current
continuity in the DC side inductor, it is evident from current continuity consid-
erations and Figure 1.15 that
mx +rn3 + m5 = 1 (1.28)
and
m2 + m4 + m6 = 1 (1.29)
+
Vdc
+
2Vdc
+
{
Vdc
(a) (b)
(c)
T T T
l 3 5,
Vdc
2î
Vdc T T T
4 6, 2,
(d) (e) (f)
Figure 1.15 Evolution of three-phase current source/stiff inverter from

basic commutation cell.
The load currents can also be defined as
h = ldc(m3-m6) (L3°)
The line voltages can then be expressed in terms of the switching functions as
V 2V
ab = dc(mlm6-m4m3)
v = 2V
bc dc(m3m2-m6m5) (L31)
v
ca=:2Vdc(m5m4-m2ml)
where it is assumed that the voltage drop across the link inductor is negligible
for any reasonable size of inductor, since the current will then be very nearly
constant.
Current Source/Stiff Inverters 23
The phase voltages can be determined in much the same manner as for the
voltage link converter, i.e.,
v — v +v
an as sn
v —v +v
en cs sn
where n again represents the voltage at the negative bus of the DC link voltage
and s denotes the center point of the load. Adding together the voltages of Eq.
(1.32) gives
V
an + Vbn + Vcn = VQS + Vbs + Vcs + 3vsn
= 0 + 3vJlf (1.33)
from which
v
sn = ^van + v
bn + v
cr,)
= -{mx+mz + m5)Vdc
= \vdc (1.34)
Thus
(1.35)
V
cs = {m5-lJ2Vdc
A plot of the load current assuming a star- and wye-connected load is given
in Figure 1.16. If the load is inductive, it is apparent that the idealized current
waveforms of Figure 1.16 would produce infinite spikes of voltage. Hence,
strictly speaking, the harmonic content for this converter is infinite. In reality,
the slopes corresponding to the rapidly changing di/dt would not be infinite but
would change at a rate dominated by the capacitance of a commutating circuit.
For example, the autosequentially commutated inverter (ASCI) of Figure 1.17
is widely used for implementing a current source/stiff converter. Alternatively,
capacitive filters can be placed on AC output terminals to absorb the rapid
changes in current.
s-
8-
(a) - - 1 - (b)"
f
9-
?•
DDT
'0.0 0.8 1.6 2.4 3.2 4.0 '0.0 0.8 1.6 2.4 3.2 4.0
tx 10- tx 1(T2
Figure 1.16 Current source inverter waveforms: (a) line current for a
star-connected load and (b) phase current for a delta-
connected load assuming a DC link current of 100 A.
T T T
l 3. 5
+
Wdc
T
_ 4. s T
2,
Figure 1.17 Autosequentially commutated current source/stiff converter.
1.6 Concept of a Space Vector

The highly coupled nature of inverter loads such as induction and synchronous
machines has led to the use of artificial variables rather than actual (phase)
variables for the purpose of simulation as well as for visualization. The essence
of the nature of the transformation of variables that is utilized can be under-
Concept of a Space Vector 25
stood by reference to Figure 1.18, which shows three-dimensional orthogonal

axes labeled a, b, and c [3]. Consider, for instance, the stator currents of a
three-phase induction machine load which is, in general, made up of three
independent variables. These currents (phase variables) can be visualized as
being components of a single three-dimensional vector {space vector) existing
in a three-dimensional orthogonal space, i.e., the space defined by Figure 1.18.
The projection of this vector on the three axes of Figure 1.18 produces the
instantaneous values of the three stator currents.
In most practical cases as has been noted already, the sum of these three
currents adds up to zero since most three-phase loads do not have a neutral
return path. In this case, the stator current vector is constrained to exist only on
a plane defined by
ia + ib + ic = 0 (1.36)
The fact that Eq. (1.36) defines a particular plane is evident if it is recalled
from analytic geometry that the general definition of a plane is
ax+by + cz = d. This plane, the so-called d—q plane, is also illustrated in
Figure 1.18. Components of the current and voltage vector in the plane are
called the d—q components while the component in the axis normal to the plane
(in the event that the currents do not sum to zero) is called the zero component.
d—q plane
c axis
b axis
a'axis
a axis
q axis
Figure 1.18 Cartesian coordinate system for phase variables showing
location of the d—q plane and projection of phase variables
onto the plane.
When the phase voltages and phase flux linkages also sum to zero, as is the
case with most balanced three-phase loads (including even a salient pole syn-
chronous machine), this same perspective can be applied to these variables as
well. By convention it is assumed that the projection of the phase a axis on the
d-q plane forms the reference q axis for the case where the d-q axes are not
rotating. A second axis on the plane is defined as being orthogonal to the q axis
such that the cross product d x q yields a third axis, by necessity normal to the
d-q plane, that produces a third component of the vector having the conven-
tional definition of the zero sequence quantity. The components of the phase
current, phase voltage, or phase flux linkage vectors in the d-q-0 stationary
coordinate system in terms of the corresponding physical variables are
= (L37)
h J ° -T f *
/oj _L _L _L L/c-
[_V2 75 75
where / is a general variable used to denote the current variable i, voltage v,
flux linkage X or charge q. The superscript 5 on the d-q variable is used to
denote the case where the d-q axes are stationary and fixed in the d-q plane.
In the dominant case where the three-phase variables sum to zero (i.e., the
corresponding current, voltage, and flux linkage vectors are located on the d-q
plane and have no zero sequence component) this transformation reduces to
fA | 0 0 \f
Jq A/2 Ja
/•; = 0 j _ i /* o- 38 )
Ja U — ——
f 42 Jl fc
L J
[0 0 0_
where the last row is now clearly not necessary and often can be discarded.
Figure 1.19 shows the location of the various axes when projected onto the
d-q plane. Note that the projection of the a phase axis on the d-q plane is con-
sidered to be lined up with the q axis (the a phase axis corresponds to the mag-
netic axis of phase a in the case of an electrical machine). The other axis on the
b axis
0 axis
q axis
(normal to paper) a axis
daxis
c axis
Figure 1.19 Physical a-b-c and conceptual stationary frame d-q-Q axes
when viewed from an axis normal to the d-q plane.
plane is, by convention, located 90° clockwise with respect to the q axis. The
third axis (necessarily normal to the d-q plane) is chosen such that the
sequence d-q-0 forms a right-hand set.
Sometimes another notation, using symbols a,(3 (Clarke's components), is
used to denote these same variables. However, the third component, For-
tesque's zero sequence component, is normally not scaled by the same factor as
the two Clarke components, and this can cause some confusion. With the trans-
formation shown, when viewed from the zero sequence axis, the d axis is
located 90° clockwise with respect to the q axis. Unfortunately, these two axes
are sometimes interchanged so that the reader should exercise caution when
referring to the literature. When the d-q axes are fixed in predefined positions
in the d-q plane, they are said to define the stationary reference frame [2].
1.6.1 d-q-0 Components for Three-Phase Sine Wave

Source/Load
When balanced sinusoidal three-phase AC voltages are applied to a three-
phase load, typically, with respect to the supply midpoint z
vaz= K,sina>o/
vbz=Vlsm{(oot-^f) (L39)
v cz = K l S i n ( © 0 / + y
It can be recalled from Eqs. (1.15) and (1.16) that for a three-wire wye-con-
nected load with balanced impedances the load voltages can be expressed in
terms of the supply voltages as [2]
= V
Vaz as+Vsz = Z
(P)ia + V
sz
+
vbz = vbs vsz = Z(p)ib + vsz (1-40)
V = V
cz cs + Vsz = Z
(P)ic+Vsz
where, again, s is the load neutral point, p represents the time derivative opera-
tor p = d/(dt)9 and Z(p) denotes the impedance operator made up of an
arbitrary circuit configuration of resistors, inductors, and capacitors. If the cir-
cuit is at rest at t = 0, then summing the rows of Eq. (1.40) gives
*az + VbZ + Vcz = 2{p)(ia + ib + ic) + 3V,Z (1.41)

Since the three currents sum to zero and Z(p) is common to all three-phases,
the voltage between load neutral and inverter zero voltage points, for balanced
loads but arbitrary source voltages, is
"„= \(Vaz+Vbz + Vcz) (1.42)
In the special case of balanced source voltages [Eq. (1.39)] the right-hand side
of Eq. (1.42) is zero and the corresponding phase and source voltages are iden-
tical. From this result it can readily be determined that, in the d-q-0 coordinate
system,
v = J F i sino v
* /3r/ , (1.43)
The use of the subscript s used here to denote the load neutral point can be
remembered as the star point, c(s)enter point, or neutral point of the stationary
circuit. It should be apparent from the orthogonality of the d-q axes and the
sine/cosine relationships that the phase voltage vector traces out a circle on the
d-q plane with radius /- Vx where Vx is the amplitude of the phase voltage.
The vector rotates with an angular velocity equal to the angular frequency of
the source voltage (377 rad/s in the case of 60 Hz). The current and flux link-
age vectors, being a consequence of applying the voltage to a linear, balanced
load will also trace out circles on the d-q plane in the steady state.
The fact that the length of the rotating vector differs from the amplitude of
the sinusoidal variable has prompted researchers to introduce methods to "cor-
rect" this supposed deficiency. The difference in length essentially comes
about because the a-b-c axes are not in the plane of the d-q axes but have a
component in the third direction (0 axis) as evidenced by the third row of Eq.
(1.37). However, if the transformation of Eq. (1.37) is multiplied by 7 2 / 3 a
scale change is made in moving from a-b-c to d-q-0 variables which elimi-
nates this difference. The transformation becomes
2 _I _I
fs 3 3 3 [\."
Jqs Jas
rS = 0 —~= -L f (1.44)
hs
fas 73 73
/oj 72 72 72 ^cs-
3 3 3_
with the inverse relationship of
1
° 7=1 n
qs
1 A 1
f = J. _*£ -L , (1.45)
Jbs
2 2/2 fds
lf4 i 73 j _ [/o,
_2 T 72
Since the same scale change has been made for all three components, the zero
component uses somewhat unconventional scaling. More conventionally, For-
tesque's scaling for this component is
fos = \(fas+fbs+fcs) (!- 46 )

and is also widely used. When the projection of the vector on the zero sequence
axis is zero, Eq. (1.44) reduces to
Jqs Jas
/oj [.0 0 ojl/"-

or inversely as
1 0 0 r -
h, - r i ° fL o.48)
Note that Eq. (1.47) does not formally have an inverse, but a suitable equiva-
lent can be obtained by first inverting Eq. (1.44) and then setting the zero
sequence component to zero. This modified definition of the stationary frame
d-q-0 components will be used in the remainder of this book.
1.6.2 d-q-0 Components for Voltage Source Inverter

Operated in Square-Wave Mode
In general it is readily determined that there are only eight possible switch
combinations for a three-phase inverter, as shown in Figure 1.20. Two of these
states (SV0 and SV1) are a short circuit of the output while the remaining six
produce active voltages, as previously indicated in Figure 1.10. Figure 1.21
shows how the eight switch combinations can be represented as stationary vec-
tors in the d-q plane simply by repetitive application of Eq. (1.47). It is rela-
tively easy to determine the values of the six vectors in the d-q plane by
investigating each nonzero switch connection. For example, for vector SV3,
switch S3 is closed connecting phase b to the positive terminal, while switches
S4 and S2 are closed connecting phases a and c to the negative terminal.
Assuming a wye-connected load, the phase b voltage receives two-thirds of the
DC pole-to-pole voltage while the parallel connected phases a and c receive
one-third of this voltage. With due regard for polarity, the d-q voltages are,
from Eq. (1.44),
Figure 1.20 The eight possible phase leg switch combinations for a VSI.
s—x Im (-d) axis

svy SV2,
<v = %
S
1S3S5 SjS 3 S 5
^ ,
c c< <^1
SV4_ 5F,
S c Qc Re (a) axis
1S3S5 or/ \ 5
1^355 W /
s,s3s5
SV SV
5. 6,
3
a axis s1s3s5
Figure 1.21 Eight possible stationary vectors on the d-q plane for a VSI.
(1.49)
1 f 2 4 > 2
Vds =
7 ^ ~ 3 Fjc ~ 3 ^ =
~ 73 Vdc
The magnitude of this vector is
^ | = Hs + v l = j { l ^ 2 + {j=/d^)2 = tVdc d-50)

as is the case for all six of the nonzero vector locations. For convenience, the
projection of axes of the three-phase voltages can also be located on the d-q
plane since vectors SVX, SV3, and SV5 also result in a positive maximum
voltage on phases as, bs, and cs, respectively.
Note that the lower phase leg switches (S4, S6, S2) are represented as
"NOT" the upper phase leg switches (S 1? S 3 , S5) in Figure 1.21, reflecting the
fact that the upper or lower switch in each phase leg must always be turned on
to maintain current continuity through each phase leg for a voltage source
inverter.
In general, the inverter attempts to follow the circle defined by the bal-
anced set of voltages, Eqs. (1.39) and (1.43). However, since only nonzero
inverter states are possible, as illustrated by SVX, SV2 , SV3,..., SV6 in Figure
1.20, the vector representing the voltage applied to the load jumps abruptly by
60 electrical degrees in a continuous counterclockwise fashion, approximating
the circle by the points on a hexagon. While only crudely approximated in this
case, more accurate tracking of the target circle on the d-q plane can be accom-
plished by more sophisticated pulse width modulation techniques, as will be
considered later in this book. If a simple inductive load is assumed, Figure 1.22
shows a typical plot of the transient progression of the voltage vector and cur-
rent vector for a typical r-L load initially at rest (zero initial conditions) with-
out PWM. The voltage vector remains confined to the six points of a hexagon
while the current vector traces out a hexagon rotated by roughly 90 electrical
degrees.
Since any vector has spatial content (length and direction), it is frequently
convenient to abandon the matrix notation and to assign directional unit vec-
tors to identify the components of the vector in the three-dimensional space
defined by the d-q-0 coordinates. In this case, however, one is concerned
V-1000 -600 -200 200 600 1000 "20 -12 " 4 . 4 1? 20

V
(a) * (b) '*
1 1
0.0 0 8 1.6 2.4 3.2 -t.D D.O 0.8 1 6 2.1 2.Z 1.0
(c) 'xl0"~2 (d) tx 101-2

Figure 1.22 Locus of the (a) voltage and (b) current space vectors for
square-wave voltage source inverter assuming a balanced
r-L load and (c), (d) corresponding time domain
waveforms. Parameters: Vdc = 500 V, r = 2.0 Q, L = 0.1 mH.
almost entirely with rotation in the d-q plane as opposed to linear translation in
the three dimensional d-q-0 space. In such cases, rotation is most readily rep-
resented in complex polar form so the most convenient method of representing
the rotating vector is simply to convert the d-q plane to one which is complex,
whereupon, by definition,
Reft) =fqcs (1.51)

!«»&) = - / *
The "jumps" in the vector representing the inverter voltage can now be conve-
niently represented by defining the operator
- = eJW)=_\_+j£ (152)
where / = V~l • In terms of the vector a the axes of the three-phase voltages
-2
can be located by the vectors 1, a, and a , respectively.
Since the phase voltages have been assigned spatial attributes, it is now
possible to visualize the phase variables as space vectors in the complex plane.
In general, this vector is given by
fs=fqSs-JfdSs 0-53)
and, from Eq.( 1.47),
7 r .(Jcs Jbs) /! r/lx

fs =fas-j{—y=~J (L54>
The quantity -j can be written in terms of the operator a as
-j = j=(a2-~a) (1.55)
so that Eq. (1.54) becomes
i j
/* =fas +
i& -a)(fcs-fbs)
= fas + |(«V CS + ofbs) ~ \{a2fbs + afcs) (1.56)
Since the sum of the three components fas,fbs,fcs equals zero, this equation
can be written as
Z = fas + \Cafcs + afbs) - \ [a\-fas - / „ ) + a(-fas -fbs)]

which simplifies to
fs =
" \Vas
iyJas^ °fbs + °2fcs)
+uJbs (1-57)
Note the presence of the 2/3 factor, which is necessary to preserve the correct
amplitude when represented in phase variable coordinates.
The six nonzero switch combinations can also be considered to be station-
ary snapshots of a three-phase set of time-varying sinusoids with a phase volt-
age magnitude Vm as shown in Figure 1.23. The magnitude of each of the six
active vectors is determined by recognizing that the line voltage at each snap-
sr2) (sv3) (sv4) (sv5) (sr6) (srj
VJ2
-VJ1
-vm
0 TI/3 2TT/3 7i 4TT/3 5TT/3 2TT
Figure 1.23 VSI phasor angular positions in fundamental cycle for space
vector.
shot of voltage in Figure 1.23 is 1.5 Vm where Vm is the peak phase voltage, and
that this voltage is equal to the DC bus voltage 2V^C. That is,
r
m 3 dc (1.58)
1.6.3 Synchronously Rotating Reference Frame

The visualization of vector rotation on the d-q plane has also led to transfor-
mations which rotate with these vectors. For example, if axes are defined
which rotate with the stator voltage, one realizes the synchronous voltage ref-
erence frame. In general, it is not necessary to define rotating axes to rotate
synchronously with one particular vector but to simply define a general rotat-
ing transformation which transforms the phase variables to rotating axes on the
d-q plane, viz:
cos0 c o s l O - — I coslU + —I
/ A (6) = \ sinG s i n ( e - ^ ) sin(e + f ) fbs d-59)

_ J°s - 1 1 1 1 \-cs-
Ji Ji J2
For completeness, the zero component is also again included, together with
the scale change of ^ 2 / 3 . The angle 0 is the angular displacement of the vec-
tor on the d-q plane measured with respect to the projection of the as axis onto
this plane. Since the same scale change has been made for all three compo-
nents, the zero component again uses somewhat unconventional scaling. Alter-
natively, Fortesque's scaling for this component can also be selected, namely
fos = \(fas+fbs+fcs) C1-60)
and this is also widely used.

Note that the zero axis does not enter into the rotational transformation.
Hence, the zero axis can be considered as the axis about which the rotation
takes place, i.e., the axis of rotation. Because of the scaling, the power (and
subsequently the torque if the load is a motor) is different in d-q-0 components
than in a-b-c variables and a 3/2 multiplier must be added to the power as cal-
culated in the transformed system of equations since both current and voltage
variables have been scaled by A/2/3 .
In vector notation, Eq. (1.59) can be written as
fqM = TqM(Q)fabc (1.61)
where
cos8 cosl0-—J cos(9 + —J
W9> =
I sine s i n ( e - ^ ) sin(e + ^ ) (1-62)
The transformation Tqd0(Q) can, for convenience and for computational

advantage, be broken into two portions, one of which takes variables from
physical phase quantities to nonrotating d-q-0 variables (stationary reference
frame) while the other goes from nonrotating to rotating d-q-0 variables
(rotating reference frame). For this case one can write,
where
2 1 1
3 3 3
W°>= O^jl 0.64)

J2 J2 J2
.3 3 3_
and
cos0 -sin0 0
*(9) = sine cosG 0 (1-65)
0 0 1
Note that T d0(0) is obtained by simply setting 0 = 0 in Eq. (1.62). The
inverse transformation is
where
cos0 sin0 -—
V^r1 =
| ^ o ( 6 ) r = cos(o-f) sin(e-^) j=2 (1-67)
cos[0 + -Jsm[0 + T j -
1
° T
72
Vow1 = |v(°) r= 4 " ^ ^ (L68)
_1 J3 J_
2 2 72
cos 6 sin 6 0
T
* ( 0 ) - ' = R(Q) = - S i n 0 cos0 0 d-69)
0 0 1
Figure 1.24 shows the locus of the same voltage and current vector as Fig-
ure 1.22, but viewed in a synchronously rotating reference frame. Here, the
superscript e is used on the d-q variables to denote that they are rotating with
the electrical frequency. In this case the locus of the vector continually jumps
ahead by 60 electrical degrees at each switching instant. However, since the
vector subsequently remains stationary while the synchronous frame continues
to rotate, the locus of the vector slowly retreats backward and then jumps for-
ward, repeating the locus shown six times each cycle.
1.7 Three-Level Inverters

Another voltage source/stiff inverter configuration which is becoming increas-
ingly important for high power applications is the so-called neutral-point
clamped (NFC) inverter [4]. This inverter, shown in Figure 1.25, has a zero DC
voltage center point, which is switchable to the phase outputs, thereby creating
the possibility of switching each inverter phase leg to one of three voltage lev-
els. The major benefit of this configuration is that, while there are twice as
many switches as in the two-level inverter, each of the switches must block
only one-half of the DC link voltage (as is also the case for the six center-
tapped diodes). However, one problem, that does not occur with a two-level
inverter, is the need to ensure voltage balance across the two series-connected
capacitors making up the DC link. One solution is to simply connect each of
10 '
0 -
<
-10 -
-20 -
-30 -
-40 -
570 590 610 630 650 67C _2Q _12 _4 . e 12
V l
d d
Figure 1.24 Locus of phase voltage and line current in the
synchronously rotating reference frame for the same
parameters as Figure 1.22.
Three-Level Inverters 39
• J - i
I
JI-
Vdc
z
i
<
Ta2i
i i :J T - L i It Tc2î i
+
T
i i b3/ i k i
vdc
\1
T .
L i
u u «-
Figure 1.25 Three-level voltage source/stiff inverter.

the capacitors to its own isolated DC source (for example the output of a diode
bridge fed from a transformer secondary). The other method is to balance the
two capacitor voltages by feedback control. In this case the time that each
inverter leg dwells on the center point can be adjusted so as to regulate the
average current into the center point to be zero [5, 6].
In order to produce three levels, the switches are controlled such that only
two of the four switches in each phase leg are turned on at any time. For exam-
ple, when switches T a] and Ta2 are turned on, the positive DC link voltage is
applied to the phase a terminal, when Ta2 and T a3 are turned on, the center
point voltage (zero volts) is applied, while when Ta3 and Ta4 are turned on, the
negative DC link voltage appears at the terminal of phase a. Defining variables
m
\\-> mx2-> a n d mX3 (x = a> b, or c) as a logical one when switch combinations
(T x l -T x 2 ), (TX2-Tx3), (TX3-Tx4) are true, respectively, and zero otherwise, the
three terminal voltages can be written as
v
az=Vdc(ma\-ma3)
vbz=Vdc{rnbx-mb,) (1.70)
V V
cz= dc(mc\-mc3)
In a similar manner to previous work, the line-to-line and line-to-neutral

voltages (in the case of a star-connected load) are given by
v
ab = V
dc(mal-ma3-mb\+mbi)
v V
bc= dc(mb\-mb3-mcl+mc3) <L71)
v V
ca= dc(mc\-mc2-ma\+ma3>
and
v
as = \ Vd\ma\ ~ ma3 ~ \(mbl ~ mbi + mc\ ~ "rf)]
"7 r i ~i
V
cs = lVdc[mc\-mc3-\(ma\-ma3 + m
b\-mb3)\
The load neutral-to-inverter-midpoint voltage is, for this case,
1
'sz = * V m m
3 dc( a\- a3 + mb\-mb3 + mc\-mc3) (l'73>
The three DC link currents are

I = m
dc a\ia + m
b\ib + m
c\ic
l
dc = ma3ja + ^63'6 + mc^c ( L ? 4 )
I
dc = ma2ia + m
b2ib + m
c2ic
It is clear from the constraints of the circuit that
m
a\+ma2 + ma3 = 1
(L75)
and so forth, so that ljc from Eq. (1.74) can also be written as
!
dc = ~(ma\ + m
a3)ia-<mb\ + m
bîb<mc\ + m
Cz)
i
c (L76)
Examination of Eq. (1.72) identifies that the line-to-neutral voltage can take on
seven distinct values, namely ±4 ^ c / 3 , ±Vdc, ±2 Vdc/3 , and zero.
Figure 1.26 shows the switched phase leg, line-to-line and line-to-neutral
phase voltages for a three level NPC inverter, where the phase legs are
switched with a 30° zero voltage plateau between the +Vdc and the -Vdc steps
to achieve minimum total harmonic distortion (THD). It is obvious that the
switched waveforms of Figure 1.26 are significantly improved compared to
those of a square-wave, two-level converter shown in Figure 1.10.
The fundamental component of the load voltage can now be determined by
calculating the fundamental component of the voltage from one phase leg to
Three-Level Inverters 41
2V,dc
1
dc
n
6
(a)
-Vdc
0
1 1
1
-2V, dc
0 2TT/3 4TT/3 2TT 8TC/3 IOTT/3 4TT

(tit
2V,dc
"1
1
dc
(b) 0
V
\ ab 1
1
-vtdc
-iv,dc
0 2TT/3 4TC/3 2TT 8TC/3 IOTT/3 4TT
C0 o /
2Kdc
v
dc
r1
—1
-
y>as I
(c)
1
J L j
"i., r i,, r
- ^^/c
u
- 2 Kflt
2TC/3 4TC/3 2TC 8TT/3 IOTT/3 4TI

co o z
Figure 1.26 Switched (a) line-to-midpoint, (b) line-to-line and (b) line-to-
neutral voltages produced by three-level NPC inverter. Phase
leg zero voltage step width arranged for minimum THD.
the DC center point, which will be the same as the fundamental component
measured with respect to the load neutral. Hence
571/12
= hJlsin5jlVdc = 0.81Vdc (1.77)

This is not quite as large as the 0.90Vdc RMS voltage that is obtained from a
two-level inverter with the same overall DC link voltage of 2Vdc by dividing
the result of Eq. (1.7) by Jl to convert it to RMS. Of course, the same RMS
voltage could still be obtained if the midpoint voltage was never selected, but
this results in a higher harmonic content and more or less defeats the purpose
of having a three-level inverter.
The space vector approach, discussed in Section 1.6, can be utilized to ana-
lyze these types of converters as well. For example, when the possible phase
voltage switching states of the three-level inverter of Figure 1.25 are expressed
as space vectors, a double hexagon is obtained as shown in Figure 1.27.
1.8 Multilevel Inverter Topologies
1.8,1 Diode-Clamped Multilevel Inverter

It has been shown that the principle of diode-clamping to DC link voltages can
be extended to any number of voltage levels [7]. Figure 1.28 shows the circuit
implementation for four- and five-level inverters. Since the voltages across the
semiconductor switches are limited by conduction of the diodes connected to
the various DC levels, this class of multilevel inverters is termed diode-
clamped multilevel inverters. For the case of the four-level inverter, switches
T a l , T a2 , and T a3 are turned on simultaneously, then T a2 , T a3 , and T a4 and so
forth to produce the desired level. A possible total of 12 voltage vectors are
produced, being ±kVdc/3 , k = 1,...,6 where the k = 2 state does not appear in
the line-to-neutral voltage output. In the same manner, four switches are
always triggered to select a desired level in the five-level inverter, producing
19 voltage levels, ±kVdc/3 , k = 1,...,9 plus zero where the k = 1 and k = 3 lev-
els do not appear in the output line-to-neutral voltage. Since several intermedi-
ate levels are now created, the problem of ensuring voltage balance across each
Multilevel Inverter Topologies 43
b axis
(0,+,-)
(- + -) (+,+ - )
(0,+,0) N (0,0,-)
(-,+,0) ,(+,+,0) (+A-)
(-0-),
(0,-,-)
(-0,0) (+,+,+) ,(+,0,0) (+--)
(-+,+) (0,+,+) (0,0,0)
/• \
q and a axis
(-,o,+)
(-.-or (0-,0) (+-,0)
(0,0,+) (+.0.+)
(--+) (+-,+)
(0,-+)
c axis daxis
Figure 1.27 Hexagons of possible switching states for three-level DC

voltage source/stiff inverter.
of the series-connected capacitors becomes a challenging problem. The prob-

lem is most easily solved by feeding each DC link capacitor with an indepen-
dent DC supply but this sometimes adds undesirable cost to the system. When
supplied by a single DC supply, the issue has been shown to be solvable by the
use of appropriate control algorithms [8]. However, complete control of the
DC link voltages is lost when the output phase voltage reaches roughly 65% of
its maximum value, somewhat restricting the use of this circuit [9].
The switching operation of these converters and the current path for posi-
tive and negative current can further identified by considering the seven-level
diode-clamped inverter of Figure 1.29. The three DC voltages are labeled as
^/ci' Vdci-> Vdc3 t 0 distinguish them in the inverter output, although in most
cases VdcX = Vdcl = Vdc3. The phase leg switch states required to achieve
the seven output levels can be determined by connecting say phase leg b to the
negative DC bus by triggering all switches in the lower portion of its phase leg.
Then the phase leg a output voltage with respect to the negative DC rail, van,
can be identified for various switch combinations, as summarized in Table 1.1.
+
T.i
Vdc
+
T.I Ta2
Vdc
+
Ta2 Ta3
Vdc
+ Ta3 Ta4
v • a a
dc +
T
a4 \s
Vdc
+ Ta5 Ta6
Vdc
Ta6 + \ i
Vdc
(a) Ta8
(b)
Figure 1.28 (a) Four-level and (b) five-level diode-clamped inverter

implementations (one phase only shown).
Figures 1.30, 1.31, and 1.32, show the switched phase leg, line-to-line and
line-to-neutral phase voltages for a four-level, five-level, and a seven-level,
diode-clamped inverter, respectively. In this case the phase legs have been
switched between the voltage levels at the appropriate times to eliminate low-
order harmonics, as discussed in Section 10.3.1 and summarized in Table 10.1.
The progressive improvement in the quality of the switched waveform is obvi-
ous as the number of inverter voltage levels increases.
Regardless of the number of levels, the blocking voltage of the switches in
this type of topology is limited to Vdc, so that inverters operating at the
medium AC voltage range (2 to 13.2 kV) can be implemented with low cost,
high-performance Insulated Gate Bipolar Transistor (IGBT) switches. Unfortu-
nately the same is not true of the diodes connecting the various DC levels to
Tal2 Tbl2 Ten
T a ll Tbii Tcll
T
al0
T
bl0 Tcio
Ta9 Tb9 Tc9
Ta8 Tb8 T c8
Ta7 Tb7 TC7

Vdc\ i b
i C
z —
Vdcx
Ta6 Tb6 Tc6
Ta5 Tb5
Vdc2 Tb4
Ta3 Tb3 TC3

Tb2 Tc2
T.1 Tb,
n
Figure 1.29 A seven-level diode-clamped inverter.
Table 1.1 Switch States and Corresponding Current Path for Diode-Clamped
Converter Illustrating Seven Positive Levels for Phase Leg a Voltage
vaw Phase b Assumed Connected to the Negative DC Bus
Switch Phase Leg a Devices CuiTent Path with Current Path with
State Voltage van Turned on Ia Positive Ia Negative
1 T a itoT a 6 Ta6>Ta5>Ta4> TaeâSâ^

van = 0 T a 3 >T a 2 >T a l Ta3>Ta2>Tai
T a 6>T a5 >T a4 >

2 v
cm = Vdc3 T a 2 toT a 7 Da7>Ta7
T.3>Ta2>Da2
Ta6>Ta5>Ta4>
3 v
cm=Vdc3+Vdc2 T a 3 toT a 8 Da8>Ta8>Ta7
Ta3>Da3
v = V +V Ta6>Ta5>Ta4>
an dc3 dc2
4
+
T
a4 t 0 Ta9 Da9>Ta9>Ta8>Ta7
Vdc\ Da4
5 ân=Vdc3+Vdc2 T
DalO>TalO>Ta9>
a5 t 0 T al0 Tae>T.s>DaS
Ta8>Ta7
v
an = Vdc3 Dall>T.n>T a io>
6 T
a6toTall Ta6 > D a6
+ Wdc2+Vdc\) Ta^Tag^.7
v
7 an = 2(Vdc3 T a 7 toT a l 2 T"al2 > T a ll > T a l0 > Ta7>Ta8>Ta9>
+
Vdc2+Vdc\) T
a9 >T a8 >T a7 T
al0 > T a ll > T al2
—1 I
v
1
J az
(a) 0 L r
-Vdc
| ) \
-Wdc
2n/2 4JC/3 2TC 8TI/3 1OTC/3 4TI

C0 o /
„_
3P*
,1 I I
1 1
1
(b)
-V,
0
1 1
1, 1 I 1
-2^*
-T>Vdc
11
2TC/3 4TT/3 2TC 8TC/3 IOTT/3 4n
C0o/
Wdc
Vdc
(c) 0
-Vdc
~2Vdc
-wdc
27T/3 47T/3 2TC 8TI/3 IOTT/3 4TT
co o r
Figure 1.30 Switched (a) line-to-midpoint, (b) line-to-line and (b) line-
to-neutral voltages produced by four-level diode-clamped
inverter. Switching times defined in Table 10.1.
2Vdc
(a) 0
jvaz .r....
-2Vr dc 1 |
-AVtdc
0 2TU/3 4TE/3 2TT 8TE/3 IOTT/3 4TC

co0/
4K£/c
J
2F,Jc
(b) 0
1
r
-4Kdc i H
0 2TC/3 4TI/3 2TI 8H/3 IOTI/3 4T:
<v
2Vdc jn
v
J as \
(C) 0 J L
|
1
I,Tir rJI nr i r
-4^ e
2TC/3 4TT/3 2TI 8TI/3 IOTT/3 4TC
CO./
to-neutral voltages produced by five-level diode-clamped
6^c
1 j— 1
2Vdc
L haz \ I
(a) 0
\
i i
\
1 1
1
-*V<k
-(>vdc
2nB 4W3 2K 8TC/3 10JI/3 4it
co 0 /
Hl
6Vdc
Wdc 1
2Vdc / \
0
\
(b)
~2Vdc
~4Vdc i1 i - L
~6Vdc
Li 1
r ! 1
27T/3 4ir/3 2TT 8TT/3 IOTT/3 4TT
03 o r
6 V*
2Vdc
0 \ /
(c) 1 T
-Wdc
~6Vdc
2TI/3 47C/3 2TT 8TT/3 IOTT/3 4TT

co 0 /
to-neutral voltages produced by seven-level diode-clamped
the switches, some of which must be rated at (k ~ 2)Vdc where k is the number
of levels (k> 3 ). The voltage rating of the diodes therefore quickly becomes a
problem and levels greater than five are not considered as practical at the
present time. This problem can be overcome by simply connecting several
diodes in series, but the stress across the series-connected devices must then be
carefully managed. Also since the number of series-connected switches
increases with the number of levels, the switch conduction losses clearly
increase in the same proportion. Fortunately, the power rating also increases at
the same rate so the efficiency of the inverter remains roughly unaffected by
the number of series-connected switches.
1.8.2 Capacitor-Clamped Multilevel Inverter

The capacitor-clamped VSI proposed by Meynard and Foch is an alternative to
the diode-clamped VSI and shares many of the advantages of this topology
[10]. Figure 1.33 illustrates the capacitor-clamped VSI topology for a seven-
level system.
4vdc J^ 4 J: 3 Ji 2 jr
Figure 1.33 Topology of a five-level capacitor-clamped inverter.

The circuit operation of the capacitor-clamped topology is best explained

by considering the simple three-level single-phase version shown in Figure
1.34. To obtain an output voltage level of 2 Vdc, switches S1? S 2 , S 7 , and S 8 are
turned on. To obtain -2Vdc, switches S 3 , S 4 , S 5 , and S 6 are turned on. To
obtain Vdc9 S 1 -S 3 -S 7 -S 8 are turned on, and to obtain -Vdc, S3-S 4 -S 5 -S 7 are
turned on. If clamping capacitors Cj are maintained at voltage Vdc, the voltage
on these capacitors in series with the load will partially cancel the source volt-
age. To obtain the zero voltage level, the combinations of either S 1 -S3-S 5 -S 7
or S2-S 4 -S 6 -Sg can be turned on. The charge of C\ can be balanced by proper
management of the switch combinations.
This topology shares the advantages of all multilevel voltage source con-
verters (VSCs) listed above, as well as those of a diode-clamped system, in that
the required number of voltage levels can be obtained without the use of a
transformer. This assists in reducing the cost of the converter and again reduces
power loss. Unlike the diode-clamped structure where the series string of
capacitors share the same voltage, in the capacitor-clamped VSC the capacitors
within a phase leg are charged to different voltage levels. To synthesize the
phase voltage waveform the various switches within the phase leg are switched
ON to combine the various capacitor voltage levels with the constraint that no
capacitor is short circuited and current continuity with the DC link is main-
tained for each capacitor. This leads to a significant amount of redundancy in
c
\ + a a' C{ +
n
Figure 1.34 Three-level capacitor-clamped inverter, voltage on
capacitors Q regulated to Vdc.
the switching states that lead to the same phase voltage levels. A similar table
to Table 1.1 can be readily prepared for the capacitor-clamped circuit of Figure
1.33.
The capacitor-clamped (alternatively known as flying-capacitor) topology
has several disadvantages that have limited its use. The first of these is the con-
verter initialization. Before the capacitor-clamped VSC can be modulated, the
clamping capacitors must be set up with the required voltage levels. This com-
plicates the modulation process and hinders the performance of the converter
under ride-through conditions. The capacitor voltages must also be regulated
under normal operation in a similar fashion to the capacitor neutral points for a
diode-clamped VSC. However, due to the large degree of redundancy in the
phase voltage states, this regulation problem is generally combined with the
modulation strategy. Another problem concerns the rating of the capacitors that
form the clamping network. Since these have large fractions of the DC bus
voltage across them, the voltage rating of the capacitors must be large when
compared to the diode-clamped topology. It is this requirement and the initial-
ization problems of the capacitor-clamped VSC that have limited its continued
development.
1.8.3 Cascaded Voltage Source Multilevel Inverter

The third topological alternative for a multilevel inverter is to series-cascade
single-phase full-bridges to make up each phase leg of the main inverter, as
shown in Figure 1.35 for a seven-level system. Each full-bridge can switch
between +Vdc, 0, and -Vdc, so that, for the seven-level example shown in Fig-
ure 1.35, each phase leg as a whole can switch in steps of Vdc over the range
+3 Vdc to - 3 Vdc. Note also that the DC link voltage of each full-bridge has been
redefined to Vdc rather than 2 Vdc as was used in Section 1.1.3. This is the usual
convention for cascaded voltage source multilevel inverter systems. In general,
N series connected full-bridges can generate (2N + 1) switching levels per
phase leg.
For this topology, the DC link supply for each full-bridge converter ele-
ment must be provided separately, and this is typically achieved using diode
rectifiers fed from isolated secondary windings of a three-phase transformer. A
very simple approach is shown in Figure 1.36 using single-phase diode
bridges. Other types of input side converters can also be used such as three-
phase diode bridge rectifiers fed from a secondary star or delta connection. It
va Vb vc
Vdc Vdc Vdc
vdc vdc Vdc
Vdc Vdc Vdc:
v
s
Figure 1.35 Seven-level series-bridge cascaded inverter.
can be shown that with progressive phase shifting of the three-phase secondar-
ies by 60/(^-1) degrees where k is the number of levels, significant harmonic
cancellation can be achieved in the transformer input current.
The cascaded inverter topology has several advantages that have made it
attractive in power conditioning systems and medium to high power drive
applications [11, 12, 13]. The first advantage concerns the ease of regulation of
the DC buses described above, while the second advantage concerns the modu-
larity of control that can be achieved. Unlike the diode-clamped inverter and
the capacitor-clamped inverter where individual phase legs must be modulated
by a central controller, the full-bridge inverters of a cascaded structure can be
modulated independently of each other. Communication between the full-
bridge inverters is required in order to achieve the synchronization of reference
and carrier waveforms, but the controller can be distributed. This makes for a
simpler controller structure than for either of the two previously discussed
topologies. However, the cascaded inverter topology has not been applied par-
ticularly successfully at low power levels to date because of the need to pro-
vide separate isolated DC supplies for each full-bridge converter element.
Clearly, while the control logic to realize the switched state varies, the
same switched phase leg voltages can be accomplished by any of the three
Phase Voltage
i
+
c 1 ]
i ^
f :
Three-Phase +
Voltage i Ji
r 1 i
.^ -
V
+
s—i : L i
= Fw
•I3 r J- i
1 i
i
T \
V
Neutral
Figure 1.36 Isolated DC voltage supplies obtained from separate
transformer secondary windings for 7-level cascaded
multilevel inverter (one output phase only shown).
multilevel inverter topologies described here, provided, of course, they have

the same number of available voltage levels. Hence, one would anticipate that
the harmonic signature produced by the three circuits would be essentially the
same. This property will be shown to be the case later in Chapter 11. However,
in general the various switches of the phase leg of a multilevel converter are
not equally loaded. This presents some difficulties with a practical multilevel
inverter implementation, but it is possible at least for a cascaded inverter to
rotate its switching between the series-connected full-bridges and hence bal-
ance the average power flow through each bridge. This approach is presented
in Chapters 10 and 11.
One important difference between the three multilevel circuits, which will
not be addressed in this book, concerns the issue of capacitor voltage balanc-
ing. Since the capacitors of each individual single-phase inverter derive from a
different DC source, balancing is inherent. However, this is not the case for the
diode-clamped or capacitor-clamped inverters. In this case the inner capacitors,
such as those producing voltages Vdc2 and VdcX in Figure 1.29 will become
over or undercharged if the average current fed to the inner taps on the DC link
is not zero. Regulation of the link capacitor voltages has been resolved for
these inverters [14, 15], but the details will not be pursued in this text.
1.8.4 Hybrid Voltage Source Inverter

The hybrid VSC proposed by Manjrekar et al. is a cascaded structure that has
been modified such that the full-bridge inverters that comprise the phase leg of
a hybrid inverter have different magnitude DC buses [16]. Figure 1.37 shows
the structure of a seven-level hybrid inverter, in which it can be seen that each
phase leg is constructed from a high-voltage (HV) stage and a low-voltage
(LV) stage. In terms of operation, the hybrid converter uses the HV stage to
achieve the bulk power transfer and uses the LV stage as a means to improve
the spectral performance of the overall converter. Also note that the HV stage
is shown to be constructed using devices that have high-voltage blocking char-
acteristics but not necessarily fast switching characteristics [e.g., integrated
gate controlled thyristors (IGCTs)], while the LV stage is constructed using
devices that have fast switching characteristics but not necessarily high-volt-
age blocking characteristics (e.g., IGBTs). The major advantages of the hybrid
structure include the fact that it marries the best performance characteristics of
two different power electronic devices, and that it can achieve similar perfor-
v v v
a b c
2V^-£ 2ydc 2 Vdc
Vdc Vdc Vdc
v
s
Figure 1.37 Topology of a seven-level hybrid voltage source inverter.
Summary 55
mance to other multilevel VSCs with a reduced switch count (e.g., 24 switches
for a seven-level hybrid VSC as opposed to 36 for diode-clamped, cascaded,
and capacitor-clamped VSCs).
The hybrid system again requires the use of a transformer to produce the
isolated DC supplies for each full-bridge inverter, and the control of the con-
verter is more complex than the standard cascaded structure. However, the
control is still modular in that the LV stage and HV stage have their own refer-
ence waveforms, but the LV stage reference must be created from the HV ref-
erence. Another problem that must be addressed for the hybrid converter is that
the HV stage will supply more power than the load requires in the middle
ranges of the modulation index. Under these operating conditions the LV stage
will be required to operate in a rectification mode, which means that the DC
link must be capable of bidirectional power flow [16]. This necessitates the use
of a PWM rectifier on the front end of the LV stage and further complicates the
control of the hybrid converter system. However, the reduced switch count and
more effective use of the power electronic devices that comprise the hybrid
system make it a particularly attractive system at medium to high power levels.
1.9 Summary
This introductory chapter has presented the switching circuits and block modu-
lation concepts involved in the application of power electronic converters.
While block modulation is still used to produce a variable frequency AC sup-
ply in some applications, it has largely been supplanted by more sophisticated
modulation strategies such as pulse width modulation, which have the major
advantage of allowing simultaneous phase and amplitude control of the output
voltage. Some time has also been spent here introducing the concept of space
vectors, which have great utility in the analysis of the more complex inverter
switching processes that are presented later in this book.
References
[1] P.C. Krause and T.A. Lipo, "Analysis and simplified representation of a recti-
fier-inverter induction motor drive," IEEE Trans, on Power Apparatus and Sys-
tems, vol. PAS-88, no. 5, May 1969, pp. 55-66.
[2] D.W. Novotny and T.A. Lipo, Vector Control and Dynamics of AC Drives,
Oxford University Press, London, 1996.
[3] T.A. Lipo, "A Cartesian vector approach to reference frame theory of AC
machines," in Conf. Rec. International Conference on Electrical Machines
(ICEM), Lausanne, 1994, pp. 239-242.
[4] A. Nabae, I. Takahashi, and H. Akagi, "A new neutral-point-clamped PWM
inverter," IEEE Trans, on Indnstiy Applications, vol. IA-17, no. 5, Sept./Oct.
1981, pp. 518-523.
[5] M.C. Klabunde, Y. Zhao, and T.A. Lipo, "Current Control of a 3-Level Recti-
fier/Inverter Drive System," in Conf. Rec. IEEE Industry Applications Society
Annual Mtg., Denver, 1994, pp. 859-866.
[6] S. Ogasawara and H. Akagi, "Analysis of variation of neutral point potential in
neutral-point-clamped voltage source PWM inverters," in Conf. Rec. IEEE
Industry Applications Society Annual Mtg., Toronto, 1993, pp. 965-970.
[7] P. Bhagwat and V.R. Stefanovic, "Generalized structure of a multilevel PWM
inverter," IEEE Trans, on Industry Applications, vol. 19, no. 6, Nov./Dec. 1983,
pp. 1057-1069.
[8] G. Sinha and T.A. Lipo, "A four-level inverter based drive with a passive front
end," IEEE Trans, on Power Electronics, vol. 15, no. 2, March 2000, pp. 285-
294.
[9] M. Marchesoni and P. Tenca, "Theoretical and practical limits in multilevel npc
inverters with passive front ends," in Conf. Record European Power Electron-
ics Conf. (EPE\ Graz, 2001, in CD-ROM, 12pp.
[10] T.A. Meynard and H. Foch, "Multi-level conversion: high voltage choppers and
voltage-source inverters," in Conf Rec. IEEE Power Electronics Specialists
Conf. (PESQ, Toledo Spain, 1992, pp. 397-403.
[11] Y. Liang and CO. Nwankpa, "A new type of STATCOM based on cascading
voltage source inverters with phase-shifted unipolar SPWM," in Conf. Rec.
Industry Applications Society Annual Mtg., St. Louis, 1998, pp. 978-985.
[12] N.P. Schibli, T. Nguyen, and A.C. Rufer, "A three-phase multilevel converter
for high-power induction motors," IEEE Trans, on Power Electronics, vol. 13,
no. 5, Sept. 1998, pp. 987-985.
[13] R.H. Osman, "A medium voltage drive utilizing series-cell multilevel topology
for outstanding power quality," in Conf Rec. IEEE Industry Applications Soci-
ety Annual Mtg., Phoenix, 1999, pp. 2662-2669.
[14] X. Yuan, H. Stemmler, and I. Barbi, "Investigation on the clamping voltage
self-balancing of the three-level capacitor clamping inverter," in Conf Rec.
Power Electronics Specialists Conf (PESQ, Charleston, 1999, pp. 1059-1064.
[15] C. Keller, R. Jakob, and S. Salama, "Topology and balance control of medium
voltage multilevel drives," in Conf. Rec. European Power Electronics Conf
(EPE), Graz, 2001, in CD-ROM.
[16] M.D. Manjrekar, R. Lund, P. Steimer, and T.A. Lipo, "Hybrid multilevel power
conversion system: A competitive solution for high power applications," IEEE
Trans, on Industry Applications, vol. 36, no. 3, May/June 2000, pp. 834—841.

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1

Introduction to Power Electronic

Figure 1.1 Families of solid state power converters categorized

1.1 Basic Converter Topologies

1.1.1 Switch Constraints

(a) (b) / ^ (c)

Figure 1.2 Basic commutation cells of power electronic converters using

reversed, a step-up chopper is produced. Energy is passed from the voltage

1.1.2 Bidirectional Chopper

(a) (b) (c)

Figure 1.3 The three basic DC/DC converters implemented with a

1.1.3 Single-Phase Full-Bridge (H-Bridge) Inverter

Figure 1.5 Half-bridge single-phase inverter.

Figure 1.6 Single-phase full-bridge (H-bridge) inverter

1.2 Voltage Source/Stiff Inverters

1.2.1 Two-Phase Inverter Structure

Figure 1.7 Two-phase (a) half-bridge and (b) full-bridge inverters.

1.2.2 Three-Phase Inverter Structure

simplification afforded by this property of three-phase currents makes the

1.2.3 Voltage and Current Waveforms in Square-Wave

561 612 123 234 345 456

Figure 1.9 The six possible connections of a simple three-phase

1, //, rms •= 1.56Fdc (1.2)

Thus, a standard 460 V, 60 Hz induction motor would require 590 V at the DC

561 612 123 234 345 456

Figure 1.10 The three line-to-line and line-to-neutral load voltages

and, for the line-to-line voltages,

\Jn,pk = lVdc=V] (1.7)

This value is, of course, the fundamental component of a square wave of

Assuming an R-L-EMF load, the current as well as voltage waveforms are

1.3 Switching Function Representation of

Considering now the constraints imposed by the circuit it is apparent that

Substituting Eq. (1.9) into Eq. (1.8) gives

The current in the DC link can be expressed as

The line-to-line AC voltages are

= \vdc{ma + mb + mc) (1.18)

The phase voltages can now be expressed as

"cs = Vdc{^nc-\ma-\m^ (1-22)

Finally, the power flow through the inverter is given by

1.4 Output Voltage Control

1.4.1 Volts/Hertz Criterion

suggesting that the fundamental component of voltage must be varied in pro-

1.4.2 Phase Shift Modulation for Single-Phase Inverter

Figure 1.12 Full-bridge, single-phase inverter control by phase shift

Vab(n) = l \ 2VdccosnQdQ (1.26)

= Vdc— cos — where n is odd (1.27)

1.4.3 Voltage Control with a Double Bridge

Figure 1.14 Double three-phase bridge arrangement: (a) basic circuit

1.5 Current Source/Stiff Inverters

(d) (e) (f)

Figure 1.15 Evolution of three-phase current source/stiff inverter from

The load currents can also be defined as

Figure 1.17 Autosequentially commutated current source/stiff converter.

1.6 Concept of a Space Vector

stood by reference to Figure 1.18, which shows three-dimensional orthogonal

1.6.1 d-q-0 Components for Three-Phase Sine Wave

*az + VbZ + Vcz = 2{p)(ia + ib + ic) + 3V,Z (1.41)

"„= \(Vaz+Vbz + Vcz) (1.42)

with the inverse relationship of