counters using D flipflops. Now, let us discuss various counters using T flip-flops.

We know
that T flip-flop toggles the output either for every positive edge of clock signal or for negative edge of clock
signal.

An ‘N’ bit binary counter consists of ‘N’ T flip-flops. If the counter counts from 0 to 2𝑁 − 1, then it is called
as binary up counter. Similarly, if the counter counts down from 2𝑁 − 1 to 0, then it is called as
binary down counter.

There are two types of counters based on the flip-flops that are connected in synchronous or not.

 Asynchronous counters
 Synchronous counters

Asynchronous Counters
If the flip-flops do not receive the same clock signal, then that counter is called as Asynchronous counter.
The output of system clock is applied as clock signal only to first flip-flop. The remaining flip-flops receive
the clock signal from output of its previous stage flip-flop. Hence, the outputs of all flip-flops do not
change affect𝑎𝑓𝑓𝑒𝑐𝑡 at the same time.

Now, let us discuss the following two counters one by one.

 Asynchronous Binary up counter

 Asynchronous Binary down counter

Asynchronous Binary Up Counter

An ‘N’ bit Asynchronous binary up counter consists of ‘N’ T flip-flops. It counts from 0 to 2𝑁 − 1.
The block diagram of 3-bit Asynchronous binary up counter is shown in the following figure.

The 3-bit Asynchronous binary up counter contains three T flip-flops and the T-
input of all the flip-flops are connected to ‘1’. All these flip-flops are negative
edge triggered but the outputs change asynchronously. The clock signal is
directly applied to the first T flip-flop. So, the output of first T flip-
flop toggles for every negative edge of clock signal.
The output of first T flip-flop is applied as clock signal for second T flip-flop. So,
the output of second T flip-flop toggles for every negative edge of output of first
T flip-flop. Similarly, the output of third T flip-flop toggles for every negative
edge of output of second T flip-flop, since the output of second T flip-flop acts as
the clock signal for third T flip-flop.

Assume the initial status of T flip-flops from rightmost to leftmost

is Q2Q1Q0=000𝑄2𝑄1𝑄0=000. Here, Q2𝑄2 & Q0𝑄0 are MSB & LSB
respectively. We can understand the working of 3-bit asynchronous binary
counter from the following table.

No of negative edge of
Q2MSB𝑀𝑆𝐵 Q1 Q0LSB𝐿𝑆𝐵 Clock

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7

Here Q0𝑄0 toggled for every negative edge of clock signal. Q1𝑄1 toggled for
every Q0𝑄0 that goes from 1 to 0, otherwise remained in the previous state.
Similarly, Q2𝑄2 toggled for every Q1𝑄1 that goes from 1 to 0, otherwise
remained in the previous state.

The initial status of the T flip-flops in the absence of clock signal

is Q2Q1Q0=000𝑄2𝑄1𝑄0=000. This is incremented by one for every negative
edge of clock signal and reached to maximum value at 7th negative edge of clock
signal. This pattern repeats when further negative edges of clock signal are
applied.
Asynchronous Binary Down Counter
An ‘N’ bit Asynchronous binary down counter consists of ‘N’ T flip-flops. It counts from 2𝑁 − 1 to 0.
The block diagram of 3-bit Asynchronous binary down counter is shown in the following figure.

The block diagram of 3-bit Asynchronous binary down counter is similar to the block diagram of 3-bit
Asynchronous binary up counter. But, the only difference is that instead of connecting the normal outputs of
one stage flip-flop as clock signal for next stage flip-flop, connect the complemented outputs of one stage
flip-flop as clock signal for next stage flip-flop. Complemented output goes from 1 to 0 is same as the
normal output goes from 0 to 1.

Assume the initial status of T flip-flops from rightmost to leftmost is Q2Q1Q0=000𝑄2𝑄1𝑄0=000.

Here, Q2𝑄2 & Q0𝑄0 are MSB & LSB respectively. We can understand the working of 3-bit asynchronous
binary down counter from the following table.

Q2MSB𝑀𝑆𝐵 Q1 Q0LSB𝐿𝑆𝐵 No of negative edge of Clock

0 0 0 0

1 1 1 1

1 1 0 2

1 0 1 3

1 0 0 4

0 1 1 5

0 1 0 6

0 0 1 7

Here Q0𝑄0 toggled for every negative edge of clock signal. Q1𝑄1 toggled for
every Q0𝑄0 that goes from 0 to 1, otherwise remained in the previous state.
Similarly, Q2𝑄2 toggled for every Q1𝑄1 that goes from 0 to 1, otherwise
remained in the previous state.
The initial status of the T flip-flops in the absence of clock signal
is Q2Q1Q0=000𝑄2𝑄1𝑄0=000. This is decremented by one for every negative
edge of clock signal and reaches to the same value at 8th negative edge of clock
signal. This pattern repeats when further negative edges of clock signal are
applied.

Synchronous Counters
If all the flip-flops receive the same clock signal, then that counter is called
as Synchronous counter. Hence, the outputs of all flip-flops
change affect𝑎𝑓𝑓𝑒𝑐𝑡 at the same time.

Now, let us discuss the following two counters one by one.

 Synchronous Binary up counter

 Synchronous Binary down counter

Synchronous Binary Up Counter

An ‘N’ bit Synchronous binary up counter consists of ‘N’ T flip-flops. It counts

from 0 to 2𝑁 − 1. The block diagram of 3-bit Synchronous binary up counter is
shown in the following figure.

The 3-bit Synchronous binary up counter contains three T flip-flops & one 2-input AND gate. All these flip-
flops are negative edge triggered and the outputs of flip-flops change affect𝑎𝑓𝑓𝑒𝑐𝑡 synchronously. The T
inputs of first, second and third flip-flops are 1, Q0𝑄0 & Q1Q0𝑄1𝑄0 respectively.

The output of first T flip-flop toggles for every negative edge of clock signal. The output of second T flip-
flop toggles for every negative edge of clock signal if Q0𝑄0 is 1. The output of third T flip-flop toggles for
every negative edge of clock signal if both Q0𝑄0 & Q1𝑄1 are 1.

Synchronous Binary Down Counter

An ‘N’ bit Synchronous binary down counter consists of ‘N’ T flip-flops. It
counts from 2𝑁 − 1 to 0. The block diagram of 3-bit Synchronous binary down
counter is shown in the following figure.

The 3-bit Synchronous binary down counter contains three T flip-flops & one 2-
input AND gate. All these flip-flops are negative edge triggered and the outputs
of flip-flops change affect𝑎𝑓𝑓𝑒𝑐𝑡 synchronously. The T inputs of first, second
and third flip-flops are 1, Q0′𝑄0′ &' Q1′𝑄1′Q0′𝑄0′ respectively.

The output of first T flip-flop toggles for every negative edge of clock signal.
The output of second T flip-flop toggles for every negative edge of clock signal
if Q0′𝑄0′ is 1. The output of third T flip-flop toggles for every negative edge of
clock signal if both Q1′𝑄1′ & Q0′𝑄0′ are 1.

1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main
clock and the clock input of rest of the following flip flop is driven by output of previous
flip flops. We can understand it by following diagram-
It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock pulse
is encountered, Q1 is changing when rising edge of Q0 is encountered (because Q0 is like
clock pulse for second flip flop) and so on. In this way ripples are generated through
Q0,Q1,Q2,Q3 hence it is also called RIPPLE counter and serial counter. A ripple counter is
a cascaded arrangement of flip flops where the output of one flip flop drives the clock input of
the following flip flop

2. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives each
flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it
does not have cumulative delay because of same clock is given to each flip flop. It is also
called as parallel counter.
 Synchronous counter circuit

Timing diagram synchronous counter

From circuit diagram we see that Q0 bit gives response to each falling edge of clock while Q1
is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.

What is CMOS?
CMOS (complementary metal-oxide semiconductor) is a popular method of constructing
digital integrated circuits. Its low power consumption, good noise immunity, and
compatibility with a wide range of voltage levels distinguish it. Here's a more in-depth
description of CMOS technology:

 MOSFET Transistors: MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are used to

construct CMOS logic gates. MOSFETs have three terminals and are made up of a metal gate, an
insulating layer (oxide), and a semiconductor channel. NMOS (n-type MOSFET) and PMOS (p-type
MOSFET) transistors are used in CMOS.
 Complementary Pair: In CMOS, the use of both NMOS and PMOS transistors in each logic gate is
referred to as "complementary." Low-voltage logic levels (0 or ground) are handled by NMOS
transistors, whereas high-voltage logic levels (1 or power supply voltage) are handled by PMOS
transistors. This arrangement makes optimal use of power and decreases static power usage.
 CMOS Logic Gates: Combinations of NMOS and PMOS transistors are used to construct CMOS logic
gates. The CMOS inverter, NAND gate, NOR gate, and XOR gate are the most common CMOS gates.
These gates can be connected together in order to create more complicated digital circuits

Due to its low power consumption, good noise immunity, compatibility with various
voltage levels, and adaptability in circuit design, CMOS technology has become the
preferred choice for designing digital integrated circuits. It is used in a variety of
applications, including microprocessors

What is TTL?
TTL (transistor-transistor logic) is a widely used digital logic family in the design of
integrated circuits. It is well-known for its durability, fast performance, and compatibility
with a wide range of input and output devices. TTL technology is described below:

 Bipolar Transistors: Bipolar junction transistors (BJTs) are used to construct TTL logic gates. These
transistors have three terminals: a base, an emitter, and a collector. TTL gates make use of bipolar
transistors that are NPN (negative-positive-negative) or PNP (positive-negative-positive).
 Bipolar Transistor Operation: TTL transistors operate in the active region, where the transistor's base-
emitter junction is forward-biassed. The current flowing through the transistor's collector-emitter circuit
defines the output of a TTL gate.
 Voltage Levels: The voltage levels of the TTL logic levels are fixed. A low logic level (0) is normally
represented by a voltage near 0 volts, whereas a high logic level (1) is typically represented by a voltage
near the power supply voltage (typically 5 volts). TTL devices are not designed to function at different
voltage levels.
 Power Consumption: Even while idle, TTL circuits require a large amount of electricity. This is because
current is flowing through the transistors in the active zone. As a result, TTL is less energy-efficient than
CMOS.

Difference between CMOS and TTL

The following table highlights the major differences between CMOS and TTL:
 TTL CMOS Characteristics

Fixed voltage levels Wide range of voltage levels Voltage Levels

(typically 5V)

High Low Power

Consumption

Bipolar Junction Transistor MOSFET Technology

(BJT)

Low High Noise Immunity

Lower fan-out capability High fan-out capability Fan-Out

Capability

Fast propagation delays Slow propagation delays Speed

Typically operates at 5V Typically operates at 5V or Power Supply

3.3V

High-speed applications, Battery-operated devices, Applications

memory systems high-density ICs

What is CMOS?
CMOS is the shortened form for Complementary Metal Oxide Semiconductor and it is a technology for
fabricating the IC’s which are used in various applications. CMOS is the most
common MOSFET fabrication type, it uses the complementary and symmetrical pairs of the p-type and n-
type Metal Oxide Field effect transistors for performing the logic functions. The combination of PMOS and
NMOS transistor being utilized in a single package is shown below.

CMOS Working Technology

Various types of Integrated circuits are constructed using the CMOS technology like the
microprocessors, microcontrollers, memory chips and several other digital logic circuits. In
static analog circuits like the data converters, image sensors, and transceivers, this technology is used
widely. CMOS propagates both logics, high and low or the 0 and What is TTL?
TTL stands for Transistor-transistor Logic. It is a logic family made up of bipolar junction transistors
(BJTs). Here, both the functions (logic and amplifying) are performed by the transistors; therefore, it is
named as the Transistor-Transistor Logic. An ideal example of TTL logic IC would be Logic Gate ICs like
the 7400 NAND or the 7402 NOR Gate.

TTL ICs
TTL is the short form of transistor-transistor logic. TTL logic uses multiple transistors having multiple
emitters and multiple inputs. The types of the transistor-transistor logic are Standard transistor-transistor
logic, Fast transistor-transistor logic, Schottky transistor-transistor logic, High power transistor-transistor
logic, Low power transistor-transistor logic, and Advanced Schottky transistor-transistor logic.

TTL logic gates are made up of the Bipolar junction transistors and resistors. There are many variants of
TTL developed for various particular purposes like the radiation-hardened TTL packages for space
applications and Low power Schottky diodes that can provide an excellent combination of speed and lesser
power consumption.

What Is The Difference Between CMOS and TTL?

The advantage of the CMOS over the TTL chips is that the CMOS has a higher density of logic gates within
the same material. TTL chips consume more power as compared to the power consumed by the CMOS chips
even at rest. The power consumption of the CMOS depends on various factors and is variable. The clock
rate is one of the major factors for power consumption. Higher clock values will result in higher
power consumption. When making the comparisons, a single gate in CMOS chip would consume the 10nW
of power whereas an equivalent gate on the TTL chip will consume approximately 10mW power. The
difference is substantially high and this is why the CMOS chips are always preferred over the TTL chips.

When the design and fabrication are considered, no doubt that the CMOS chips are very delicate and it is
difficult to handle as these are highly susceptible to electrostatic discharge. A very minute amount of static
electricity could cause damage to the CMOS chips. Thus, people often unwillingly damage their chips only
by touching the terminals of the CMOS. Some basic differences between CMOS and TTL are explained
below:

1. CMOS components are generally more expensive when compared to the TTL components. But
on system-level, CMOS chips are less expensive as these are smaller in size as compared to the
TTL chips.
 2. There are propagation delays present in both. On average, the propagation delays of TTL are
usually 10nS whereas the propagation delays for the CMOS lies between 20 to 50 nS
3. CMOS has longer rise and fall times thus digital signals are simpler and less expensive with the
CMOS chips.
4. There is a substantial difference in the voltage level range for both. For TTL it is 4.75 V to 5.25
V while for CMOS it ranges between 0 to 1/3 VDD at a low level and 2/3VDD to VDD at high
levels.
5. CMOS technology is more economical and preferred more as compared to the TTL logic.
6. The current requirements of the CMOS are low and thus power consumption is limited.
Therefore, it is easier for the circuits to be designed with the best power management.
7. The electromagnetic disruptions CMOS components are more sensitive as compared to the
TTL components
8. CMOS has one other advantage over the TTL that it has allowed lower noise during the
transmission
9. The number of standard loads that could be connected to the output of the gate under the
normal operation that is the fan-out is 10 for TTL whereas it is 50 for the CMOS.
10. The number of standard inputs that can be connected to the gate is the fan in, which is
approximately 12-14 for the TTL and for the CMOS it is 10 only.
11. CMOS circuits have better noise immunity then the TTL circuits
12. The basic gates which are used in the construction of the TTL are the NAND gate whiles both
the NAND-NOR gates are used in the CMOS circuits.

CMOS TTL

CMOS stands for Complementary Metal Oxide TTL stands for Transistor-Transistor Logic. The
Semiconductor. name is derived from the use of two Bipolar
Junction Transistors or BJTs in the design of each
logic gate.

CMOS is another classification of ICs that uses TTL is a classification of integrated circuits.
field effect transistors in the design.

The primary advantage of CMOS chips to TTL The density of logic gates is less in TTL as
chips is in the greater density of logic gates compared to CMOS.
within the same material.

An equivalent single gate in a CMOS chip can A single gate on a TTL chip can consume around
consume around 10nW. 10mW of power.
 CMOS TTL

CMOS chips are a bit more delicate compared to TTL chips are lesser delicate and is not very
TTL chips when it comes to handling as it is suseptible to electrostatic discharge.
quite susceptible to electrostatic discharge.

There are CMOS chips that have TTL logic and TTL chips do not have CMOS logic.
are meant as replacements for TTL chips.

A single logic gate in a CMOS chip can consist of A logic gate in a TTL chip can consist of a
as little as two Field Effect Transistors. substantial number of parts as extra components
like resistors are needed.

CMOS circuits comsumes less power at rest. TTL circuits consumes more power compared to
CMOS circuits at rest.

What are Fan-in and Fan-Out?

Fan-in: Fan-in is a term that defines the maximum number of digital inputs
that a single logic gate can accept. Most transistor-transistor logic
( TTL )gates have one or two inputs, although some have more than two. A
typical logic gate has a fan-in of 1 or 2.

Fan-Out: Fan-out is a term that defines the maximum number of digital

inputs that the output of a single logic gate can feed. Most transistor-
transistor logic ( TTL) gates can feed up to 10 other digital gates or devices.
Thus, a typical TTL gate has a fan-out of 10.

In Software Engineering or Application Development, we use the term fan-

out to describe the number of requests to other services we need to make in
order to serve just one incoming request.
:Fan-out
Fan-out is defined as the maximum number of inputs of the same IC family that a gate can drive without falling outside the
specified output voltage limits. Higher the fan-out, the higher the current supplying capacity of a gate. For example, a fan-
out of 5 indicates that the gate can drive (supply current to) at the most 5 inputs of the same IC family. CMOS has the
.highest fan out. Standard TTL has the lowest fan out