CHAPTER 3

3. The Central Processing Unit

3.1 Computer Arithmetic
3.1.1 The Arithmetic and Logic unit (ALU)
The ALU is that part of the computer that actually performs arithmetic and logical operations on
data. All of the other elements of the computer system—control unit, registers, memory, I/O—
are there mainly to bring data into the ALU for it to process and then to take the results back out.
The following figure indicates, in general terms, how the ALU is interconnected with the rest of
the processor:

Operands for arithmetic and logic operations are presented to the ALU in registers, and the
results of an operation are stored in registers. These registers are temporary storage locations
within the processor that are connected by signal paths to the ALU. The ALU may also set flags
as the result of an operation. For example, an overflow flag is set to 1 if the result of a
computation exceeds the length of the register into which it is to be stored.
3.2 Instruction Set Architecture and Design
The Instruction Set Architecture (ISA) is the part of the processor that is visible to the
programmer or compiler writer. The ISA serves as the boundary between software and hardware.
ISA provides all information needed for someone that wants to write a program in machine
language (or translate from a high-level language to machine language). The following three key
components define any instruction set architecture :
a) The operations the processor can execute
b) Data access mode for use as operands in the operations defined
c) Representation of the operations in memory
3.2.1 Machine Instruction Characteristics
The operation of the processor is determined by the instructions it executes, referred to as
machine instructions or computer instructions. The collection of different instructions that the
processor can execute is referred to as the processor’s instruction set.
Elements of Machine Instruction
Each instruction must contain the information required by the processor for execution.

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These elements are as follows:
 Operation code: Specifies the operation to be performed (e.g., ADD, I/O) for the processor.
The operation is specified by a binary code, known as the operation code, or opcode. [Note that
the programmers use mnemonic symbols to represent the opcodes. ]
 Source operand reference: The operation may involve one or more source operands, that is,
these operands are inputs for the operation.
 Result operand reference: The operation may produce a result and this operand is the reference
about where the output is.
 Next instruction reference: This tells the processor where to fetch the next instruction after the
execution of the current instruction is complete.
[Note : The address of the next instruction to be fetched could be either a real address or a
virtual address, depending on the architecture. Generally, the distinction is transparent to the
instruction set architecture. In most cases, the next instruction to be fetched immediately follows
the current instruction. In those cases, there is no explicit reference to the next instruction. When
an explicit reference is needed, then the main memory or virtual memory address must be
supplied.] Source and result operands can be in one of four areas:
 Main or virtual memory: As with next instruction references, the main or virtual memory
address must be supplied.
 Processor register: With rare exceptions, a processor contains one or more registers that may
be referenced by machine instructions. If only one register exists, reference to it may be implicit.
If more than one register exists, then each register is assigned a unique name or number, and the
instruction must contain the number of the desired register.
 Immediate: The value of the operand is contained in a field in the instruction being executed.
 I/O device: The instruction must specify the I/O module and device for the operation.
3.2.2 Number of Addresses (Instruction Formats)
One of the traditional ways of describing processor architecture is in terms of the number of
addresses contained in each instruction. Arithmetic and logic instructions will require the most
operands. Virtually all arithmetic and logic operations are either unary (one source operand) or
binary (two source operands). Thus, we would need a maximum of two addresses to reference
source operands. The result of an operation must be stored, suggesting a third address, which
defines a destination operand. Finally, after completion of an instruction, the next instruction
must be fetched, and its address is needed. In most architectures, most instructions have one,
two, or three operand addresses, with the address of the next instruction being implicit
(obtained from the program counter).
Example: The following figures-(a), (b), and (c) illustrate typical three-, two-, and one-address
instructions that could be used to compute
Y = (A - B) / [C + (D * E)]

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With three addresses, each instruction specifies two sources operand locations and a destination
operand location. To not to alter the value of any of the operand locations, a temporary location,
T, is used to store some intermediate results. [Note that there are four instructions and that the
original expression had five operands.] Three-address instruction formats are not common
because they require a relatively long instruction format to hold the three address references.

With two-address instructions, and for binary operations, one address must do double duty as
both an operand and a result. Thus, the instruction SUB Y, B carries out the calculation Y - B and
stores the result in Y. The two-address format reduces the space requirement but also introduces
some awkwardness. To avoid altering the value of an operand, a MOVE instruction is used to
move one of the values to a result or temporary location before performing the operation.

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With one-address instructions, a second address must be implicit. This was common in earlier
machines, with the implied address being a processor register known as the Accumulator (AC).
The accumulator contains one of the operands and is used to store the result.
3.2.3 Instruction Sets (Instruction Types)
A computer should have a set of instructions that allows the user to formulate any data
processing task. Instructions can be classified into the following categories based on their
functionality:
 Data Transfer
 Arithmetic
 Logical
 Conversion
 Transfer of Control
 Input/Output
The following table summarizes the actions of processor for these
various types of operations:

Table: Actions of Processor for various types of operations for these categories of operations,
some common Instructions can be listed as in the following tables:

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3.2.4 Addressing Modes
Information involved in any operation performed by the CPU needs to be addressed. In computer
terminology, such information is called the operand. Therefore, any instruction issued by the
processor must carry at least two types of information. These are the operation to be performed,
encoded in what is called the op-code field, and the address information of the operand on which
the operation is to be performed, encoded in what is called the address field. Addressing modes
are the different ways in which the CPU generates the address of operands. In other words, they
provide access paths to memory locations and CPU registers.
Note : In this section, we use the following notation:
A = contents of an address field in the instruction
R = contents of an address field in the instruction that refers to a register
EA = actual (effective) address of the location containing the referenced operand
(X) = contents of memory location X or register X
ACC = Accumulator ; IR = Instruction Register
Some of the commonly used addressing modes are as follows :
(i) Immediate Addressing Mode
According to this addressing mode, the value of the operand is (immediately) available in the
instruction itself. In this addressing mode, data is the part of the instruction itself, and so there is
no need of address calculation. However, immediate addressing mode is used to hold source
operands only; cannot be used for storing results. The range of the operands is limited by the
number of bits available for encoding the operands in the instruction; for n bit fields, the range is
2(n-1) to +(2(n-1)-1). A diagrammatic illustration of instructions in this addressing
mode would appear as:

Ex: LOAD 123

From the figure above, it can be understood that the

immediate operand, 123, is loaded onto the accumulator. No address
calculation is required.
(ii) Direct Addressing Mode
It is a very simple form of addressing, in which the address field contains the effective address of
the operand: EA = A In this mode, the address of the operand is specified as a constant, and this
constant is coded as part of the instruction.

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Ex: LOAD [123]

As shown in the figure, the address of the operand is stored in the instruction. The operand is
then fetched from that memory address.
(iii) Indirect Addressing Mode
The address of the location where the address of the data is to be found is stored in the
instruction as the operand. Thus, the operand is the address of a memory location, which holds
the address of the operand. To fetch the operand in this addressing mode, two memory accesses
are required. Since memory accesses are slow, this is not efficient for frequent memory accesses.
The indirect addressing mode may be used to implement pointers.
Ex: LOAD [[123]]

As shown in the figure, the address of the memory location that holds the address of the data in
the memory is part of the instruction.
(iv) Register Direct Addressing Mode
In this addressing mode, the operand is contained in a CPU register, and the address of this
register is encoded in the instruction. As no memory access is needed, operand fetch is efficient.
However, there are only a limited number of CPU registers available, and this imposes a
limitation on the use of this addressing mode.
Ex: LOAD R2

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This load instruction specifies the address of the register and the operand is fetched from this
register. As is clear from the diagram, no memory access is involved in this addressing mode.
(v) Register Indirect Addressing Mode
In the register indirect mode, the address of memory location that contains the operand is in a
CPU register. The address of this CPU register is encoded in the instruction.
Ex: LOAD [R1]

The address of the register that contains the address of memory location holding the operand is
encoded in the instruction. There is one memory access involved.
(vi) Displacement Addressing Mode
The displacement-addressing mode is also called based or indexed addressing mode. Effective
memory address is calculated by adding a constant (which is usually a part of the instruction) to
the value in a CPU register. This addressing mode is useful for accessing arrays. The addressing
mode may be called ‘indexed’ in the situation when the constant refers to the first element of the
array (base) and the register contains the ‘index’. Similarly, ‘based’ refers to the situation when
the constant refers to the offset (displacement) of an array element with respect to the first
element. The address of the first element is stored in a register.
Ex: LOAD [R1 + 8]

In this example, R1 is the address of the register that holds a memory address, which is to be
used to calculate the effective address of the operand. The constant (8) is added to this address
held by the register and this effective address is used to retrieve the operand.
3.3 CPU Structure and Function
3.3.1 CPU Basics (Processor Organization)
A typical CPU has three major components:
1) Register Set – The register set differs from one computer architecture to another. It is usually
a combination of general purpose and special-purpose registers.
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General-purpose registers are used for any purpose, hence the name general purpose. Special-
purpose registers have specific functions within the CPU. For example, the program counter
(PC) is a special-purpose register that is used to hold the address of the instruction to be executed
next. Another example of special-purpose registers is the instruction register (IR), which is used
to hold the instruction that is currently executed.
2) Arithmetic and Logic Unit (ALU) – The ALU provides the circuitry needed to perform the
arithmetic, logical and shift operations demanded of the instruction set.
3) Control Unit (CU) – The control unit is the entity responsible for fetching the instruction to
be executed from the main memory and decoding and then executing it.
The following figure (Internal Structure) shows the main components of the CPU and their
interactions through the control paths :

Note: The Internal Processor Bus is needed to transfer data between the various registers and the
ALU because the ALU in fact operates only on data in the internal processor memory. The figure
also shows typical basic elements of the ALU.
Processor Operations:
A processor must perform the following general operations:
o Fetch instruction: The processor reads an instruction from memory (register, cache, main
memory).
o Interpret instruction: The instruction is decoded to determine what action is required.
o Fetch data: The execution of an instruction may require reading data from memory or an I/O
module.
o Process data: The execution of an instruction may require performing some arithmetic or
logical operation on data.
o Write data: The results of an execution may require writing data to memory or an I/O module.

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3.3.2 Register Organization
The processor requires a minimal amount of internal memory to store some data temporarily and
it must remember the location of the last instruction so that it can know where to get the next
instruction from. These internal memory locations where the data or instruction is temporarily
stored (during execution) are called Registers.
There are two types of registers in a processor:
(1) User-visible registers: Enable the machine - or assembly language programmer to minimize
main memory references by optimizing use of registers. We can characterize these in the
following categories:
a. General Purpose Registers – These are registers that can be assigned to a variety of functions
by the programmer. Sometimes, any general-purpose register can contain the operand for any
opcode. This provides true general-purpose register use. But in some cases, they may be
dedicated for floating-point and stack operations.
b. Data Registers – There registers may be used only to hold data and cannot be employed in the
calculation of an operand address.
c. Address Registers - Address registers may themselves be somewhat general purpose, or they
may be devoted to a particular addressing mode. They may be used as Segment pointers, Index
registers, or as a stack pointer.
d. Condition Code Registers (Flag Registers) - Condition codes are bits set by the processor
hardware as the result of operations. For example, an arithmetic operation may produce a
positive, negative, zero, or overflow result. In addition to the result itself being stored in a
register or memory, a condition code is also set. The code may subsequently be tested as part of a
conditional branch operation. Condition code bits are collected into one or more registers.
Usually, they form part of a control register.
(2) Control and status registers: There are a variety of processor registers that are employed to
control the operation of the processor. Most of these, on most machines, are not visible to
the user. Four registers are essential to instruction execution:
a. Program counter (PC): Contains the address of an instruction to be fetched.
b. Instruction register (IR): Contains the instruction most recently fetched.
c. Memory address register (MAR): Contains the address of a location in memory.
d. Memory buffer register (MBR): Contains a word of data to be written to memory or the word
most recently read.
Many processor designs include a register or set of registers, often known as the program status
word (PSW), that contain status information. The PSW typically contains condition codes
plus other status information. Common fields or flags include the following:
o Sign: Contains the sign bit of the result of the last arithmetic operation.
o Zero: Set when the result is 0.
o Carry: Set if an operation resulted in a carry (addition) into or borrow (subtraction) out of a
high-order bit. Used for multiword arithmetic operations.
o Equal: Set if a logical compare result is equality.

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o Overflow: Used to indicate arithmetic overflow.
o Interrupt Enable/Disable: Used to enable or disable interrupts.
o Supervisor: Indicates whether the processor is executing in supervisor or user mode. Certain
privileged instructions can be executed only in supervisor mode, and certain areas of memory
can be accessed only in supervisor mode.
3.4 RISC and CISC
Generally, computers can be classified as being RISC machines or CISC machines.
3.4.1 RISC (Reduced Instruction Set Computers)
The underlying idea in designing RISC machines is to reduce the number and complexity of
instructions. However, new RISC machines have some instructions that may be quite complex
and the number of instructions may also be large. The common features of RISC machines
are :
o One instruction per clock period
o Fixed size instructions (generally of 32 bits)
o CPU accesses memory only for Load and Store operations
o Simple and few addressing modes
o Less work per instruction
o Improved usage of delay slots
o Efficient usage of Pre-fetching and Speculative Execution Techniques
3.4.2 CISC (Complex Instruction Set Computers)
The CISC machines have resulted from the efforts of computer designers to efficiently utilize
memory and minimize execution time, yet add in more instruction formats and addressing
modes. The common attributes of CISC machines are:
o More work per instruction
o Wide variety of addressing modes
o Variable instruction lengths and execution times per instruction
o CISC machines attempt to reduce the “semantic gap” between machine-level instructions and
high-level language constructs
o Clock period is more
o Complex addressing modes delay operand fetch from memory
o Difficult to make efficient use of speedup techniques such as pipelining, pre-fetching, etc.

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