K32 L2B Microcontroller: NXP Semiconductors
K32 L2B Microcontroller: NXP Semiconductors
K32 L2B Microcontroller: NXP Semiconductors
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Operating Characteristics Timers
• Voltage range: 1.71 to 3.6 V • One 6-channel Timer/PWM module
• Flash write voltage range: 1.71 to 3.6 V • Two 2-channel Timer/PWM modules
• Temperature range: –40 to 105 °C • One low-power timer
• Periodic interrupt timer
Packages • Real time clock
• 64 LQFP 10mm x 10mm, 0.5 mm pitch, 1.6 mm
thickness
Security and Integrity
• 64 MAPBGA 5mm x 5mm, 0.5 mm pitch, 1.23 mm
• 80-bit unique identification number per chip
thickness
• Advanced flash security
• 48 QFN 7mm x 7mm, 0.5 mm pitch, 0.65 mm thickness
• 32 QFN 5mm x 5mm, 0.5 mm pitch, 0.65 mm thickness
Low Power
• Down to 54 μA/MHz in very low power run mode
• Down to 1.96 μA in VLLS3 mode (RAM + RTC
retained)
• Six flexible static modes
Related Resources
Type Description Resource
Selector The NXP Selector Guide is a web-based tool that features interactive Selector Guide
Guide application wizards and a dynamic product selector.
Reference The Reference Manual contains a comprehensive description of the K32L2B3xRM1
Manual structure and function (operation) of a device.
Data Sheet The Data Sheet includes electrical characteristics and signal This document.
connections.
Chip Errata The chip mask set Errata provides additional or corrective information for K32L2B_1N71K1
a particular device mask set.
Package Package dimensions are provided in package drawings. 64-LQFP: 98ASS23234W, 64-
drawing MAPBGA: 98ASA00420D, 32-
QFN: 98ASA00615D, 48-QFN:
98ASA00616D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
1 Ordering information
The following chips are available for ordering.
Table 1. Ordering information
Product Memory Package IO and ADC channel Serial
Interface
Part number Flash SRAM Pin Package GPIOs GPIOs ADC SLCD
(KB) (KB) count (INT/HD)1 channels
(SE/DP)
K32L2B31VLH0A 256 32 64 LQFP 50 31/6 16/2 Yes
K32L2B31VMP0A 256 32 64 MAPBGA 50 31/6 16/2 Yes
K32L2B31VFT0A 256 32 48 QFN 36 24/6 14/1 —
K32L2B31VFM0A 256 32 32 QFN 23 19/6 7/0 —
K32L2B21VLH0A 128 32 64 LQFP 50 31/6 16/2 Yes
K32L2B21VMP0A 128 32 64 MAPBGA 50 31/6 16/2 Yes
K32L2B21VFT0A 128 32 48 QFN 36 24/6 14/1 —
K32L2B21VFM0A 128 32 32 QFN 23 19/6 7/0 —
K32L2B11VLH0A 64 32 64 LQFP 50 31/6 16/2 Yes
K32L2B11VMP0A 64 32 64 MAPBGA 50 31/6 16/2 Yes
K32L2B11VFT0A 64 32 48 QFN 36 24/6 14/1 —
K32L2B11VFM0A 64 32 32 QFN 23 19/6 7/0 —
2 Overview
The following figure shows the system diagram of this device
GPIOA
GPIOB
Master Slave
Cortex M0+ GPIOC
GPIOD
GPIOE
IOPORT
Watchdog(COP)
MCG-Lite Register File(32 Bytes)
HIRC48M LLWU
OSC RCM
SMC
LIRC2M/8M
PMC
SLCD
The crossbar switch connects bus masters and slaves using a crossbar switch structure.
This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access
the same slave.
2.1.2 NVIC
The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority
levels for interrupts. In the NVIC, each source in the IPR registers contains two bits. It
also differs in number of interrupt sources and supports 32 interrupt vectors.
The Cortex-M family uses a number of methods to improve interrupt latency to up to 15
clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait and
VLPW modes.
2.1.3 AWIC
The asynchronous wake-up interrupt controller (AWIC) is used to detect asynchronous
wake-up events in Stop mode and signal to clock control logic to resume system
clocking. After clock restarts, the NVIC observes the pending interrupt and performs
the normal interrupt or event processing. The AWIC can be used to wake MCU core
from Stop and VLPS modes.
Wake-up sources are listed as below:
Table 2. AWIC stop wake-up sources
Wake-up source Description
Available system resets RESET pin when LPO is its clock source
Low-voltage detect Power management controller—functional in Stop mode
Low-voltage warning Power management controller—functional in Stop mode
Pin interrupts Port control module—any enabled pin interrupt is capable of waking the system
ADC The ADC is functional when using internal clock source or external crystal clock
CMP0 Interrupt in normal or trigger mode
I2Cx Address match wakeup
2.1.4 Memory
This device has the following features:
• 32 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait
states.
• The non-volatile memory is divided into two arrays
• Up to 256 KB of embedded program memory
• 16 KB ROM (built-in bootloader to support UART, I2C, USB, and SPI
interfaces)
The program flash memory contains a 16-byte flash configuration field that stores
default protection settings and security information. The page size of program
flash is 1 KB.
The protection setting can protect 32 regions of the program flash memory from
unintended erase or program operations.
The security circuitry prevents unauthorized access to RAM or flash contents
from debug port.
• System register file
This device contains a 32-byte register file that is powered in all power modes.
Also, it retains contents during low power modes and is reset only during a
power-on reset.
The CM0+ core adds support for a programmable Vector Table Offset Register
(VTOR) to relocate the exception vector table after reset. This device supports booting
from:
• internal flash
• ROM
The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows
the user to customize the operation of the MCU at boot time. The register contains
read-only bits that are loaded from the NVM's option byte in the flash configuration
field. Below is boot flow chart for this device.
POR or Reset
N
RCM[FORCEROM] =00
N
FOPT[BOOTPIN_OPT]=0
N
BOOTCFG0 pin=0
Y
FOPT[BOOTSRC N
_SEL]=10/11
The blank chip is default to boot from ROM and remaps the vector table to ROM base
address, otherwise, it remaps to flash address.
The system oscillator supports low frequency crystals (32 kHz to 40 kHz), high
frequency crystals (3 MHz to 32 MHz), and ceramic resonators (3 MHz to 32 MHz). An
external clock source, DC to 48 MHz, can be used as the system clock through the
EXTAL0 pin. The external oscillator also supports a low speed external clock (32.768
kHz) on the RTC_CLKIN pin for use with the RTC.
For more details on the clock operations and configurations, see Reference Manual.
The following figure is a high level block diagram of the clock generation.
HIRC48M MCGPCLK
LIRC
8MHz/ 8MHz MCGOUTCLK
2MHz FCRDIV OUTDIV1 CG Core/Platform/System clock
IRC 2MHz
IRCS
CLKS
OUTDIV4 CG Bus/Flash clock
System oscillator EREFS0
EXTAL0 OSCCLK
XTAL_CLK
CG OSCERCLK
OSC
XTAL0 logic OSC32KCLK
ERCLK32K
RTC_CKLIN
CG — Clock gate
In order to provide flexibility, many peripherals can select from multiple clock sources
for operation. This enables the peripheral to select a clock that will always be available
during operation in various operational modes.
The following table summarizes the clocks associated with each module.
Table 4. Module clocks
Module Bus interface clock Internal clocks I/O interface clocks
Core modules
2.1.7 Security
Security state can be enabled via programming flash configuration field (0x40e). After
enabling device security, the SWD port cannot access the memory resources of the
MCU, and ROM boot loader is also limited to access flash and not allowed to read out
flash information via ROM boot loader commands.
Access interface Secure state Unsecure operation
SWD port Cannot access memory source by SWD The debugger can write to the Flash
interface Mass Erase in Progress field of the
MDM-AP Control register to trigger a
mass erase (Erase All Blocks)
command
ROM boot loader Interface Limit access to the flash, cannot read Send “FlashEraseAllUnsecureh"
(UART/I2C/SPI/USB) out flash content command or attempt to unlock flash
security using the backdoor key
The PMC provides Run (Run), and Very Low Power Run (VLPR) configurations in
Arm’s Run operation mode. In these modes, the MCU core is active and can access all
peripherals. The difference between the modes is the maximum clock frequency of the
system and therefore the power consumption. The configuration that matches the
power versus performance requirements of the application can be selected.
The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in
Arm’s Sleep operation mode. In these modes, even though the MCU core is inactive,
all of the peripherals can be enabled and operate as programmed. The difference
between the modes is the maximum clock frequency of the system and therefore the
power consumption.
The PMC provides Stop (Stop), Very Low Power Stop (VLPS), Low Leakage Stop
(LLS), and Very Low Leakage Stop (VLLS) configurations in Arm’s Deep Sleep
operational mode. In these modes, the MCU core and most of the peripherals are
disabled. Depending on the requirements of the application, different portions of the
analog, logic, and memory can be retained or disabled to conserve power.
The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up
Interrupt Controller (AWIC), and the Low Leakage Wake-Up Controller (LLWU) are
used to wake up the MCU from low power states. The NVIC is used to wake up the
MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU
core from STOP and VLPS modes. The LLWU is used to wake up the MCU core
from LLS and VLLSx modes.
For additional information regarding operational modes, power management, the
NVIC, AWIC, or the LLWU, please refer to the Reference Manual.
The following table provides information about the state of the peripherals in the
various operational modes and the modules that can wake MCU from low power
modes.
Table 6. Peripherals states in different operational modes
Core mode Device mode Descriptions
Run mode Run In Run mode, all device modules are operational.
Very Low Power Run In VLPR mode, all device modules are operational at a reduced frequency
except the Low Voltage Detect (LVD) monitor, which is disabled.
Sleep mode Wait In Wait mode, all peripheral modules are operational. The MCU core is
placed into Sleep mode.
Very Low Power Wait In VLPW mode, all peripheral modules are operational at a reduced
frequency except the Low Voltage Detect (LVD) monitor, which is disabled.
The MCU core is placed into Sleep mode.
2.1.9 LLWU
The LLWU module is used to wake MCU from low leakage power mode (LLS and
VLLSx) and functional only on entry into a low-leakage power mode. After recovery
from LLS, the LLWU is immediately disabled. After recovery from VLLSx, the LLWU
continues to detect wake-up events until the user has acknowledged the wake-up event.
This device uses 8 external wakeup pin inputs and 4 internal modules as wakeup
sources to the LLWU module.
The following is internal peripheral and external pin inputs as wakeup sources to the
LLWU module.
2.1.11 COP
The COP monitors internal system operation and forces a reset in case of failure. It
can run from bus clock, LPO, 8/2 MHz internal oscillator or external crystal oscillator.
Optional window mode can detect deviations in program flow or system frequency.
The COP has the following features:
• Support multiple clock input, 1 kHz clock(LPO), bus clock, 8/2 MHz internal
reference clock, external crystal oscillator
• Can work in Stop/VLPS and Debug mode
• Configurable for short and long timeout values, the longest timeout is up to 262
seconds
• Support window mode
2.2.2 BME
The Bit Manipulation Engine (BME) provides hardware support for atomic read-
modify-write memory operations to the peripheral address space in Cortex-M0+ based
microcontrollers. It reduces up to 30% of the code size and up to 9% of the cycles for
bit-oriented operations to peripheral registers.
The BME supports unsigned bit field extract, load-and-set 1-bit, load-and-clear 1-bit,
bit field insert, logical AND/OR/XOR operations with byte, halfword or word-sized
data type.
2.2.4 TPM
This device contains three low power TPM modules (TPM). All TPM modules are
functional in Stop/VLPS mode if the clock source is enabled.
The TPM features include:
• TPM clock mode is selectable from external clock input, internal clock source,
external crystal input clock, MCGIRCLK clock or clocking from MCGFLLCLK
and MCGPLLCLK/2
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• TPM includes a 16-bit counter
• Includes 6 channels that can be configured for input capture, output compare,
edge-aligned PWM mode, or center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel or counter
overflow
• Support selectable trigger input to optionally reset or cause the counter to start or
stop incrementing
• Support the generation of hardware triggers when the counter overflows and per
channel
2.2.5 ADC
This device contains one ADC module. This ADC module supports hardware triggers
from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports
wakeup of MCU in low power mode when using internal clock source or external
crystal clock.
ADC module has the following features:
• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 17 single-ended external analog inputs
• Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16-
bit, 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Selectable clock source up to four
• Operation in low-power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the
clock
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within
range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function up to 32x
• Selectable voltage reference: external or alternate
• Self-calibration mode
2.2.6 VREF
The Voltage Reference (VREF) can supply an accurate voltage output (1.2V typically)
trimmed in 0.5 mV steps. It can be used in applications to provide a reference voltage
to external devices or used internally as a reference to analog peripherals such as the
ADC or CMP.
The VREF supports the following programmable buffer modes:
• Bandgap on only, used for stabilization and startup
• High power buffer mode
• Low-power buffer mode
• Buffer disabled
The VREF voltage output signal, bonded on VREFH for 48 QFN, 64 LQFP and 64
MAPBGA packages and on PTE30 for 32 QFN packages, can be used by both
internal and external peripherals in low and high power buffer mode. A 100 nF
capacitor must always be connected between this pin and VSSA if the VREF is used.
This capacitor must be as close to VREF_OUT pin as possible.
2.2.7 CMP
The device contains one high-speed comparator and two 8-input multiplexers for both
the inverting and non-inverting inputs of the comparator. Each CMP input channel
connects to both muxes.
The CMP includes one 6-bit DAC, which provides a selectable voltage reference for
various user application cases. Besides, the CMP also has several module-to-module
interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces.
The CMP has the following features:
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of
the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, digitally filtered
• External hysteresis can be used at the same time that the output filter is used for
internal functions
• Two software selectable performance levels: shorter propagation delay at the
expense of higher power and Low power with longer propagation delay
K32 L2B Microcontroller, Rev. 3, 09/2020 19
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Overview
2.2.8 DAC
The 12-bit Digital-to-Analog Converter (DAC) is a low-power, general-purpose DAC.
The output of the DAC can be placed on an external pin or set as one of the inputs to
the analog comparator, op-amps, or ADC.
The features of the DAC module include:
• On-chip programmable reference generator output. The voltage output range is
from 1⁄4096 Vin to Vin, and the step is 1⁄4096 Vin, where Vin is the input voltage.
• Vin can be selected from two reference sources.
• Static operation in Normal Stop mode.
• 2-word data buffer supported with multiple operation modes.
• DMA support.
2.2.9 RTC
The RTC is an always powered-on block that remains active in all low power modes.
The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an
external crystal using the oscillator or clock directly from RTC_CLKIN pin.
RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all
RTC registers.
The RTC module has the following features
• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and
3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt
2.2.10 PIT
The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It
has two independent channels and each channel has a 32-bit counter. Both channels
can be chained together to form a 64-bit counter.
Channel 0 can be used to periodically trigger DMA channel 0, and channel 1 can be
used to periodically trigger DMA channel 1. Either channel can be programmed as an
ADC trigger source, or TPM trigger source. Channel 0 can be programmed to trigger
DAC.
The PIT module has the following features:
• Each 32-bit timers is able to generate DMA trigger
• Each 32-bit timers is able to generate timeout interrupts
• Two timers can be cascaded to form a 64-bit timer
• Each timer can be programmed as ADC/TPM trigger source
• Timer 0 is able to trigger DAC
2.2.11 LPTMR
The low-power timer (LPTMR) can be configured to operate as a time counter with
optional prescaler, or as a pulse counter with optional glitch filter, across all power
modes, including the low-leakage modes. It can also continue operating through most
system reset events, allowing it to be used as a time of day counter.
The LPTMR module has the following features:
• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power
mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
2.2.12 UART
This device contains a basic universal asynchronous receiver/transmitter (UART)
module with DMA function supported. Generally, this module is used in RS-232,
RS-485, and other communications. It also supports LIN slave operation and
ISO7816.
2.2.13 LPUART
This product contains two Low-Power UART modules, both of their clock sources are
selectable from IRC48M, IRC8M/2M or external crystal clock, and can work in Stop
and VLPS modes. They also support 4x to 32x data oversampling rate to meet different
applications.
The LPUART module has the following features:
• Programmable baud rates (13-bit modulo divider) with configurable oversampling
ratio from 4x to 32x
• Transmit and receive baud rate can operate asynchronous to the bus clock and can
be configured independently of the bus clock frequency, support operation in Stop
mode
• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
22 K32 L2B Microcontroller, Rev. 3, 09/2020
NXP Semiconductors
Overview
2.2.14 SPI
This device contains two SPI modules. SPI modules support 8-bit and 16-bit modes.
FIFO function is available only on SPI1 module.
The SPI modules have the following features:
• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
• Support DMA
2.2.15 I2C
This device contains two I2C modules, which support up to 1 Mbits/s by dual buffer
features, and address match to wake MCU from the low power mode.
I2C modules support DMA transfer, and the interrupt condition can trigger DMA
request when DMA function is enabled.
The I2C modules have the following features:
• Support for system management bus (SMBus) specification, version 2
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Arbitration-lost interrupt with automatic mode switching from master to slave
K32 L2B Microcontroller, Rev. 3, 09/2020 23
NXP Semiconductors
Overview
2.2.16 USB
This device contains one USB module which implements a USB2.0 full-speed
compliant peripheral and interfaces to the on-chip USBFS transceiver. It implements
keep-alive feature to avoid re-enumerating when exiting from low power modes and
enables HIRC48M to allow crystal-less USB operation.
The USBFS has the following features:
• USB 1.1 and 2.0 compliant full-speed device controller
• 16 bidirectional end points
• DMA or FIFO data stream interfaces
• Low-power consumption
• HIRC48 with clock-recovery is supported to eliminate the 48 MHz crystal. It is
used for USB device-only implementation.
• USB keeps alive in low power mode down to VLPS and is able to wake MCU from
low power mode
2.2.17 FlexIO
The FlexIO is a highly configurable module providing a wide range of protocols
including, but not limited to UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform
generation. The module supports programmable baud rates independent of bus clock
frequency, with automatic start/stop bit generation.
The FlexIO module has the following features:
3 Memory map
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space. The following figure shows the system memory and
peripheral locations
0x4000_0000 Reserved
0x4000_8000 DMA controller
0x4000_F000 GPIO Controller (alias to 0x400F_F000)
0x4002_0000 Flash memory
0x0000_0000 0x4002_1000 DMA Channel Multiplexer
0x4003_7000 PIT
Flash
0x0000_0000 0x4003_8000 LPTPM0
0x07FF_FFFF
Code space 0x4003_9000 LPTPM1
0x07FF_FFFF 0x4003_A000 LPTPM2
0x1C00_0000
0x1C00_0000 0x4003_B000 ADC0
ROM 0x4003_D000 RTC
Boot ROM
0x4003_F000 DAC
0x1C00_3FFF
0x1C00_4000 0x4004_0000 LPTMR
0x1FFF_E000 0x4004_1000 System register file
0x1FFF_E000 0x4004_7000 SIM low power logic
Data Space SRAM_L 0x4004_8000 SIM
0x2000_0000 0x4004_9000 PORTA
0x2000_5FFF
Reserved SRAM_U 0x4004_A000 PORTB
0x4000_0000 0x2000_5FFF 0x4004_B000 PORTC
Public 0x4004_C000 PORTD
peripheral 0x4000_0000 0x4004_D000 PORTE
AIPS
0x400F_F000 peripherals 0x4005_3000 SLCD
0x4007_FFFF
Reserved 0x4005_4000 LPUART0
0x4400_0000
BME 0x400F_F000 0x4005_5000 LPUART1
0x6000_0000 GPIO 0x4005_F000 FlexIO
Reserved 0x400F_FFFF
0xE000_0000 0x4006_4000 MCG Lite
Private
Reserved 0x4006_5000 OSC
peripheral
0xE010_0000
MTB 0x4006_6000 I2C0
0x4006_7000 I2C1
MTBDWT
0x4006_C000 UART2
4 Pinouts
64 64 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
MAP LQFP
BGA
F1 10 PTE21 LCD_P60/ LCD_P60/ PTE21 TPM1_CH1 LPUART0_RX FXIO0_D5 LCD_P60
ADC0_DM0/ ADC0_DM0/
ADC0_SE4a ADC0_SE4a
G2 11 PTE22 ADC0_DP3/ ADC0_DP3/ PTE22 TPM2_CH0 UART2_TX FXIO0_D6
ADC0_SE3 ADC0_SE3
F2 12 PTE23 ADC0_DM3/ ADC0_DM3/ PTE23 TPM2_CH1 UART2_RX FXIO0_D7
ADC0_SE7a ADC0_SE7a
F4 13 VDDA VDDA VDDA
G4 14 VREFH VREFH VREFH
G3 15 VREFL VREFL VREFL
F3 16 VSSA VSSA VSSA
H1 17 PTE29 CMP0_IN5/ CMP0_IN5/ PTE29 TPM0_CH2 TPM_CLKIN0
ADC0_SE4b ADC0_SE4b
H2 18 PTE30 DAC0_OUT/ DAC0_OUT/ PTE30 TPM0_CH3 TPM_CLKIN1 LPUART1_TX LPTMR0_
ADC0_SE23/ ADC0_SE23/ ALT1
CMP0_IN4 CMP0_IN4
H3 19 PTE31 DISABLED PTE31 TPM0_CH4
H4 20 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL
H5 21 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA
D3 22 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK
D4 23 PTA1 DISABLED PTA1 LPUART0_RX TPM2_CH0
E5 24 PTA2 DISABLED PTA2 LPUART0_TX TPM2_CH1
D5 25 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO
G5 26 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b
F5 27 PTA5 DISABLED PTA5 USB_CLKIN TPM0_CH2
H6 28 PTA12 DISABLED PTA12 TPM1_CH0
G6 29 PTA13 DISABLED PTA13 TPM1_CH1
G7 30 VDD VDD VDD
H7 31 VSS VSS VSS
H8 32 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RX TPM_CLKIN0
G8 33 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TX TPM_CLKIN1 LPTMR0_
ALT1
F8 34 PTA20 RESET_b
F7 35 PTB0/ LCD_P0/ LCD_P0/ PTB0/ I2C0_SCL TPM1_CH0 LCD_P0
LLWU_P5 ADC0_SE8 ADC0_SE8 LLWU_P5
F6 36 PTB1 LCD_P1/ LCD_P1/ PTB1 I2C0_SDA TPM1_CH1 LCD_P1
ADC0_SE9 ADC0_SE9
E7 37 PTB2 LCD_P2/ LCD_P2/ PTB2 I2C0_SCL TPM2_CH0 LCD_P2
ADC0_SE12 ADC0_SE12
E8 38 PTB3 LCD_P3/ LCD_P3/ PTB3 I2C0_SDA TPM2_CH1 LCD_P3
ADC0_SE13 ADC0_SE13
E6 39 PTB16 LCD_P12 LCD_P12 PTB16 SPI1_MOSI LPUART0_RX TPM_CLKIN0 SPI1_MISO LCD_P12
64 64 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
MAP LQFP
BGA
D7 40 PTB17 LCD_P13 LCD_P13 PTB17 SPI1_MISO LPUART0_TX TPM_CLKIN1 SPI1_MOSI LCD_P13
D6 41 PTB18 LCD_P14 LCD_P14 PTB18 TPM2_CH0 LCD_P14
C7 42 PTB19 LCD_P15 LCD_P15 PTB19 TPM2_CH1 LCD_P15
D8 43 PTC0 LCD_P20/ LCD_P20/ PTC0 EXTRG_IN audioUSB_ CMP0_OUT LCD_P20
ADC0_SE14 ADC0_SE14 SOF_OUT
C6 44 PTC1/ LCD_P21/ LCD_P21/ PTC1/ I2C1_SCL TPM0_CH0 LCD_P21
LLWU_P6/ ADC0_SE15 ADC0_SE15 LLWU_P6/
RTC_CLKIN RTC_CLKIN
B7 45 PTC2 LCD_P22/ LCD_P22/ PTC2 I2C1_SDA TPM0_CH1 LCD_P22
ADC0_SE11 ADC0_SE11
C8 46 PTC3/ LCD_P23 LCD_P23 PTC3/ SPI1_SCK LPUART1_RX TPM0_CH2 CLKOUT LCD_P23
LLWU_P7 LLWU_P7
E3 47 VSS VSS VSS
E4 — VDD VDD VDD
C5 48 VLL3 VLL3 VLL3
A6 49 VLL2 VLL2/ VLL2/ PTC20 LCD_P4
LCD_P4 LCD_P4
B5 50 VLL1 VLL1/ VLL1/ PTC21 LCD_P5
LCD_P5 LCD_P5
B4 51 VCAP2 VCAP2/ VCAP2/ PTC22 LCD_P6
LCD_P6 LCD_P6
A5 52 VCAP1 VCAP1/ VCAP1/ PTC23 LCD_P39
LCD_P39 LCD_P39
B8 53 PTC4/ LCD_P24 LCD_P24 PTC4/ SPI0_SS LPUART1_TX TPM0_CH3 LCD_P24
LLWU_P8 LLWU_P8
A8 54 PTC5/ LCD_P25 LCD_P25 PTC5/ SPI0_SCK LPTMR0_ CMP0_OUT LCD_P25
LLWU_P9 LLWU_P9 ALT2
A7 55 PTC6/ LCD_P26/ LCD_P26/ PTC6/ SPI0_MOSI EXTRG_IN SPI0_MISO LCD_P26
LLWU_P10 CMP0_IN0 CMP0_IN0 LLWU_P10
B6 56 PTC7 LCD_P27/ LCD_P27/ PTC7 SPI0_MISO audioUSB_ SPI0_MOSI LCD_P27
CMP0_IN1 CMP0_IN1 SOF_OUT
C3 57 PTD0 LCD_P40 LCD_P40 PTD0 SPI0_SS TPM0_CH0 FXIO0_D0 LCD_P40
A4 58 PTD1 LCD_P41/ LCD_P41/ PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 LCD_P41
ADC0_SE5b ADC0_SE5b
C2 59 PTD2 LCD_P42 LCD_P42 PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO FXIO0_D2 LCD_P42
B3 60 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI FXIO0_D3 LCD_P43
A3 61 PTD4/ LCD_P44 LCD_P44 PTD4/ SPI1_SS UART2_RX TPM0_CH4 FXIO0_D4 LCD_P44
LLWU_P14 LLWU_P14
C1 62 PTD5 LCD_P45/ LCD_P45/ PTD5 SPI1_SCK UART2_TX TPM0_CH5 FXIO0_D5 LCD_P45
ADC0_SE6b ADC0_SE6b
B2 63 PTD6/ LCD_P46/ LCD_P46/ PTD6/ SPI1_MOSI LPUART0_RX SPI1_MISO FXIO0_D6 LCD_P46
LLWU_P15 ADC0_SE7b ADC0_SE7b LLWU_P15
A2 64 PTD7 LCD_P47 LCD_P47 PTD7 SPI1_MISO LPUART0_TX SPI1_MOSI FXIO0_D7 LCD_P47
32 48 Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
QFN QFN
3 3 USB0_DP USB0_DP USB0_DP
4 4 USB0_DM USB0_DM USB0_DM
5 5 VOUT33 VOUT33 VOUT33
6 6 VREGIN VREGIN VREGIN
7 9 VDDA VDDA VDDA
8 12 VSSA VSSA VSSA
9 14 PTE30 DAC0_OUT/ DAC0_OUT/ PTE30 TPM0_CH3 TPM_CLKIN1 LPUART1_TX LPTMR0_
ADC0_SE23/ ADC0_SE23/ ALT1
CMP0_IN4 CMP0_IN4
10 17 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK
11 18 PTA1 DISABLED PTA1 LPUART0_RX TPM2_CH0
12 19 PTA2 DISABLED PTA2 LPUART0_TX TPM2_CH1
13 20 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO
14 21 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b
15 22 VDD VDD VDD
16 23 VSS VSS VSS
17 24 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RX TPM_CLKIN0
18 25 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TX TPM_CLKIN1 LPTMR0_
ALT1
19 26 PTA20 RESET_b
20 27 PTB0/ ADC0_SE8 ADC0_SE8 PTB0/ I2C0_SCL TPM1_CH0
LLWU_P5 LLWU_P5
21 28 PTB1 ADC0_SE9 ADC0_SE9 PTB1 I2C0_SDA TPM1_CH1
22 34 PTC1/ ADC0_SE15 ADC0_SE15 PTC1/ I2C1_SCL TPM0_CH0
LLWU_P6/ LLWU_P6/
RTC_CLKIN RTC_CLKIN
23 35 PTC2 ADC0_SE11 ADC0_SE11 PTC2 I2C1_SDA TPM0_CH1
24 36 PTC3/ DISABLED PTC3/ SPI1_SCK LPUART1_RX TPM0_CH2 CLKOUT
LLWU_P7 LLWU_P7
25 37 PTC4/ DISABLED PTC4/ SPI0_SS LPUART1_TX TPM0_CH3
LLWU_P8 LLWU_P8
26 38 PTC5/ DISABLED PTC5/ SPI0_SCK LPTMR0_ CMP0_OUT
LLWU_P9 LLWU_P9 ALT2
27 39 PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_MOSI EXTRG_IN SPI0_MISO
LLWU_P10 LLWU_P10
28 40 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MISO audioUSB_ SPI0_MOSI
SOF_OUT
29 45 PTD4/ DISABLED PTD4/ SPI1_SS UART2_RX TPM0_CH4 FXIO0_D4
LLWU_P14 LLWU_P14
30 46 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 FXIO0_D5
31 47 PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ SPI1_MOSI LPUART0_RX SPI1_MISO FXIO0_D6
LLWU_P15 LLWU_P15
32 48 PTD7 DISABLED PTD7 SPI1_MISO LPUART0_TX SPI1_MOSI FXIO0_D7
Pin interrupt
Open drain
Pin name
64 LQFP
1 A1 PTE0 ND Hi-Z — SS N N N
2 B1 PTE1 ND Hi-Z — SS N N N
3 — VDD — — — — — — —
4 C4 VSS — — — — — — —
5 E1 USB0_DP — — — — — — —
6 D1 USB0_DM — — — — — — —
7 E2 VOUT33 — — — — — — —
8 D2 VREGIN — — — — — — —
9 G1 PTE20 ND Hi-Z — SS N N N
10 F1 PTE21 ND Hi-Z — SS N N N
11 G2 PTE22 ND Hi-Z — SS N N N
12 F2 PTE23 ND Hi-Z — SS N N N
13 F4 VDDA — — — — — — —
14 G4 VREFH — — — — — — —
15 G3 VREFL — — — — — — —
16 F3 VSSA — — — — — — —
17 H1 PTE29 ND Hi-Z — SS N N N
18 H2 PTE30 ND Hi-Z — SS N N N
19 H3 PTE31 ND Hi-Z — SS N N N
20 H4 PTE24 ND Hi-Z — SS N N N
21 H5 PTE25 ND Hi-Z — SS N N N
22 D3 PTA0 ND L PD SS N N Y
23 D4 PTA1 ND Hi-Z — SS N N Y
24 E5 PTA2 ND Hi-Z — SS N N Y
Pin interrupt
Open drain
Pin name
64 LQFP
25 D5 PTA3 ND H PU FS N N Y
26 G5 PTA4 ND H PU SS N N Y
27 F5 PTA5 ND Hi-Z — SS N N Y
28 H6 PTA12 ND Hi-Z — SS N N Y
29 G6 PTA13 ND Hi-Z — SS N N Y
30 G7 VDD — — — — — — —
31 H7 VSS — — — — — — —
32 H8 PTA18 ND Hi-Z — SS N N Y
33 G8 PTA19 ND Hi-Z — SS N N Y
34 F8 PTA20 ND H PU SS Y Y Y
35 F7 PTB0/LLWU_P5 HD Hi-Z — SS N N N
36 F6 PTB1 HD Hi-Z — SS N N N
37 E7 PTB2 ND Hi-Z — SS N N N
38 E8 PTB3 ND Hi-Z — SS N N N
39 E6 PTB16 ND Hi-Z — FS N N N
40 D7 PTB17 ND Hi-Z — FS N N N
41 D6 PTB18 ND Hi-Z — SS N N N
42 C7 PTB19 ND Hi-Z — SS N N N
43 D8 PTC0 ND Hi-Z — SS N N Y
44 C6 PTC1/LLWU_P6/ ND Hi-Z — SS N N Y
RTC_CLKIN
45 B7 PTC2 ND Hi-Z — SS N N Y
46 C8 PTC3/LLWU_P7 HD Hi-Z — FS N N Y
47 E3 VSS — — — — — — —
— E4 VDD — — — — — — —
48 C5 VLL3 — — — — — — —
49 A6 VLL2 — — — — — — —
50 B5 VLL1 — — — — — — —
51 B4 VCAP2 — — — — — — —
Pin interrupt
Open drain
Pin name
64 LQFP
52 A5 VCAP1 — — — — — — —
53 B8 PTC4/LLWU_P8 HD Hi-Z — FS N N Y
54 A8 PTC5/LLWU_P9 ND Hi-Z — FS N N Y
55 A7 PTC6/LLWU_P10 ND Hi-Z — FS N N Y
56 B6 PTC7 ND Hi-Z — FS N N Y
57 C3 PTD0 ND Hi-Z — SS N N Y
58 A4 PTD1 ND Hi-Z — SS N N Y
59 C2 PTD2 ND Hi-Z — SS N N Y
60 B3 PTD3 ND Hi-Z — SS N N Y
61 A3 PTD4/LLWU_P14 ND Hi-Z — FS N N Y
62 C1 PTD5 ND Hi-Z — FS N N Y
63 B2 PTD6/LLWU_P15 HD Hi-Z — FS N N Y
64 A2 PTD7 HD Hi-Z — FS N N Y
The following table lists the pin properties of 32/48 QFN package.
Pullup/ pulldown setting after POR
Pin interrupt
Open drain
Pin name
32 QFN
48 QFN
— 1 VDD — — — — — — —
Pin interrupt
Open drain
Pin name
32 QFN
48 QFN
— 7 PTE20 ND Hi-Z — SS N N N
— 8 PTE21 ND Hi-Z — SS N N N
— 10 VREFH — — — — — — —
— 11 VREFL — — — — — — —
— 13 PTE29 ND Hi-Z — SS N N N
— 15 PTE24 ND Hi-Z — SS N N N
— 16 PTE25 ND Hi-Z — SS N N N
— 29 PTB2 ND Hi-Z — SS N N N
— 30 PTB3 ND Hi-Z — SS N N S
— 31 PTB16 ND Hi-Z — FS N N N
— 32 PTB17 ND Hi-Z — FS N N N
— 33 PTC0 ND Hi-Z — SS N N Y
— 41 PTD0 ND Hi-Z — SS N N Y
— 42 PTD1 ND Hi-Z — SS N N Y
— 43 PTD2 ND Hi-Z — SS N N Y
— 44 PTD3 ND Hi-Z — SS N N Y
1 — PTE0 ND Hi-Z — SS N N N
2 2 VSS — — — — — — —
3 3 USB0_DP — — — — — — —
4 4 USB0_DM — — — — — — —
5 5 VOUT33 — — — — — — —
6 6 VREGIN — — — — — — —
7 9 VDDA — — — — — — —
8 12 VSSA — — — — — — —
9 14 PTE30 ND Hi-Z — SS N N N
10 17 PTA0 ND L PD SS N N Y
11 18 PTA1 ND Hi-Z — SS N N Y
12 19 PTA2 ND Hi-Z — SS N N Y
13 20 PTA3 ND H PU FS N N Y
Pin interrupt
Open drain
Pin name
32 QFN
48 QFN
14 21 PTA4 ND H PU SS N N Y
15 22 VDD — — — — — — —
16 23 VSS — — — — — — —
17 24 PTA18 ND Hi-Z — SS N N Y
18 25 PTA19 ND Hi-Z — SS N N Y
19 26 PTA20 ND H PU SS Y Y Y
20 27 PTB0/LLWU_P5 HD Hi-Z — SS N N N
21 28 PTB1 HD Hi-Z — SS N N N
22 34 PTC1/LLWU_P6/ ND Hi-Z — SS N N Y
RTC_CLKIN
23 35 PTC2 ND Hi-Z — SS N N Y
24 36 PTC3/LLWU_P7 HD Hi-Z — FS N N Y
25 37 PTC4/LLWU_P8 HD Hi-Z — FS N N Y
26 38 PTC5/LLWU_P9 ND Hi-Z — FS N N Y
27 39 PTC6/LLWU_P10 ND Hi-Z — FS N N Y
28 40 PTC7 ND Hi-Z — FS N N Y
29 45 PTD4/LLWU_P14 ND Hi-Z — FS N N Y
30 46 PTD5 ND Hi-Z — FS N N Y
31 47 PTD6/LLWU_P15 HD Hi-Z — FS N N Y
32 48 PTD7 HD Hi-Z — FS N N Y
1. When I2C module is enabled and a pin is functional for I2C, this pin is (pseudo-) open drain enabled. When UART or
LPUART module is enabled and a pin is functional for UART or LPUART, this pin is (pseudo-) open drain
configurable.
2. PTA20 is a true open drain pin that must never be pulled above VDD.
4.4.4 Analog
This table presents the signal descriptions of the ADC0 module.
Table 13. ADC0 signal descriptions
Chip signal name Module signal Description I/O
name
ADC0_DPn DADP3–DADP0 Differential Analog Channel Inputs I
ADC0_DMn DADM3–DADM0 Differential Analog Channel Inputs I
ADC0_SEn ADn Single-Ended Analog Channel Inputs I
VREFH VREFSH Voltage Reference Select High I
VREFL VREFSL Voltage Reference Select Low I
VDDA VDDA Analog Power Supply I
VSSA VSSA Analog Ground I
1. RTC_CLKOUT can also be driven with OSCERCLK via SIM control bit SIM_SOPT[RCTCLKOUTSEL]
PTD4/LLWU_P14
PTD6/LLWU_P15
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
VCAP2
VCAP1
PTD5
PTD2
PTD3
PTD1
PTC7
PTD0
PTD7
VLL2
VLL1
61
51
62
52
59
55
49
58
56
60
50
64
63
57
54
53
PTE0 1 48 VLL3
PTE1 2 47 VSS
VDD 3 46 PTC3/LLWU_P7
VSS 4 45 PTC2
USB0_DP 5 44 PTC1/LLWU_P6/RTC_CLKIN
USB0_DM 6 43 PTC0
VOUT33 7 42 PTB19
VREGIN 8 41 PTB18
PTE20 9 40 PTB17
PTE21 10 39 PTB16
PTE22 11 38 PTB3
PTE23 12 37 PTB2
VDDA 13 36 PTB1
VREFH 14 35 PTB0/LLWU_P5
VREFL 15 34 PTA20
VSSA 16 33 PTA19
21
31
22
25
26
28
29
23
24
27
32
30
20
19
18
17
PTE31
PTE30
PTE24
PTE29
PTE25
VSS
PTA0
PTA3
PTA4
PTA13
PTA12
PTA1
PTA2
PTA5
PTA18
VDD
1 2 3 4 5 6 7 8
PTD4/ PTC6/
A PTE0 PTD7 PTD1 VCAP1 VLL2 PTC5/ A
LLWU_P14 LLWU_P10 LLWU_P9
PTD6/ PTC4/
B PTE1 PTD3 VCAP2 VLL1 PTC7 PTC2 B
LLWU_P15 LLWU_P8
PTC1/
PTC3/
C PTD5 PTD2 PTD0 VSS VLL3 LLWU_P6/ PTB19 C
LLWU_P7
RTC_CLKIN
PTB0/
F PTE21 PTE23 VSSA VDDA PTA5 PTB1 PTA20 F
LLWU_P5
1 2 3 4 5 6 7 8
PTD6/LLWU_P15
PTD4/LLWU_P14
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
PTD7
PTD5
PTC7
31
32
29
25
30
28
26
27
PTE0 1 24 PTC3/LLWU_P7
VSS 2 23 PTC2
USB0_DP 3 22 PTC1/LLWU_P6/RTC_CLKIN
USB0_DM 4 21 PTB1
VOUT33 5 20 PTB0/LLWU_P5
VREGIN 6 19 PTA20
VDDA 7 18 PTA19
VSSA 8 17 PTA18
12
13
14
15
16
10
11
9
PTA1
PTA2
PTE30
VDD
PTA0
VSS
PTA3
PTA4
PTD6/LLWU_P15
PTD4/LLWU_P14
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
PTD7
PTD5
PTD3
PTD2
PTD1
PTD0
PTC7
41
42
48
46
45
47
44
43
39
40
38
37
VDD 1 36 PTC3/LLWU_P7
VSS 2 35 PTC2
USB0_DP 3 34 PTC1/LLWU_P6/RTC_CLKIN
USB0_DM 4 33 PTC0
VOUT33 5 32 PTB17
VREGIN 6 31 PTB16
PTE20 7 30 PTB3
PTE21 8 29 PTB2
VDDA 9 28 PTB1
VREFH 10 27 PTB0/LLWU_P5
VREFL 11 26 PTA20
VSSA 12 25 PTA19
21
22
23
24
20
13
14
15
16
18
19
17
PTE24
PTA2
PTE25
PTA1
PTA3
PTE29
PTE30
PTA0
PTA4
VDD
VSS
PTA18
8
(0.22)
B B BASE METAL
0.20 0.16
0.09 0.09 8
8
60X
0.5
0.23 PLATING
0.25 0.17
8
X X=A, B OR D
SECTION B-B
DETAIL Y
(0.2)
0° MIN
1.45
1.35 2X R0.2
0.1
0.05
0.25
GAUGE
PLANE
0.15 (0.5)
0.05 0.75 7°
0.45 0°
(1.00)
DETAIL AA
NOTES:
5 B
64X 0.08 A
A1 INDEX AREA C
D A
5 // 0.2 A SEATING
PLANE 4
4X 0.15
TOP VIEW
D
0.25
7X 0.5
H
G 7X 0.5
F 0.25
E
D
C
0.25
B 64X Ø 0.35 0.15
0.25 3
A
Ø0.15 M A B C 1.23 MAX
Ø0.05 M A
3
8
7
4
1
6
5
2
A1 INDEX AREA
VIEW D-D
BOTTOM VIEW
NOTES:
45°
(0.05) 0.25
0.95
1.13
DETAIL F
// 0.1 C
48X
0.65
0.50 0.08 C 4
0.05
0.00 (0.2) C
SEATING PLANE
(0.5)
DETAIL G
VIEW ROTATED 90℃W
NOTES:
// 0.1 C
32X
0.65 0.08 C
0.50
0.05
0.00 (0.2) C
(0.5) SEATING PLANE
DETAIL G
VIEW ROTATED 90℃W
NOTES:
5 Electrical characteristics
5.1 Ratings
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5.2 General
Low High
VIH
80%
Input Signal Midpoint1 50%
20%
VIL
Fall Time Rise Time
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
Table 37. VDD supply LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLVW4H • Level 3 falling (LVWV = 10) 2.92 3.00 3.08 V
• Level 4 falling (LVWV = 11)
1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the
associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
• VLLS0 → RUN
— 152 166 μs
• VLLS1 → RUN
— 152 166 μs
• VLLS3 → RUN
— 93 104 μs
• LLS → RUN
— 7.5 8 μs
• VLPS → RUN
— 7.5 8 μs
• STOP → RUN
— 7.5 8 μs
— 1.81 2.06 mA
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
— 1.00 1.25 mA
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
— 161.93 171.82
• at 50 °C
— 181.45 191.96
• at 85 °C
— 236.29 271.17 μA
• at 105 °C
— 390.33 465.58
IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
— 3.31 5.14
• at 50 °C
— 10.43 17.68
• at 85 °C
— 34.14 61.06 μA
• at 105 °C
— 104.38 164.44
IDD_VLPS Very-low-power stop mode current at 1.8 V
• at 25 °C and below
— 3.21 5.22
• at 50 °C
— 10.26 17.62
• at 85 °C
— 33.49 60.19 μA
• at 105 °C
— 102.92 162.20
IDD_LLS Low-leakage stop mode current, all peripheral
disable, at 3.0 V μA
— 2.06 3.33
• at 25 °C and below
— 4.72 6.85
• at 50 °C
— 8.13 13.30
• at 70 °C
— 13.34 24.70
• at 85 °C
— 41.08 52.43
• at 105 °C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
nA
ICMP CMP peripheral adder measured by 22 22 22 22 22 22 µA
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare. Includes
6-bit DAC power consumption.
IUART UART peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source waiting for RX
data at 115200 baud rate. Includes
selected clock source power consumption.
• IRC8M (8 MHz internal reference
clock) 114 114 114 114 114 114 µA
• IRC2M (2 MHz internal reference
34 34 34 34 34 34
clock)
Table 41. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
ITPM TPM peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source configured for
output compare generating 100 Hz clock
signal. No load is placed on the I/O
generating the clock signal. Includes
selected clock source and I/O switching
currents.
147 147 147 147 147 147 µA
• IRC8M (8 MHz internal reference
clock) 42 42 42 42 42 42
• IRC2M (2 MHz internal reference
clock)
IBG Bandgap adder when BGEN bit is set and 45 45 45 45 45 45 µA
device is placed in VLPx or VLLSx mode.
IADC ADC peripheral adder combining the 330 330 330 330 330 330 µA
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
ILCD LCD peripheral adder measured by 4.5 4.5 4.5 4.5 4.5 4.5 µA
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by means
of the OSC0_CR[EREFSTEN,
EREFSTEN] bits. VIREG disabled, resistor
bias network enabled, 1/8 duty cycle, 8 x
36 configuration for driving 288 Segments,
32 Hz frame rate, no LCD glass
connected. Includes ERCLK32K (32 kHz
external crystal) power consumption.
1. The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher
than the specified maximum frequency when IRC 48 MHz is used as the clock source.
2. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
3. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
5. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.
J2
J3 J3
SWD_CLK (input)
J4 J4
SWD_CLK
J9 J10
J11
J12
SWD_DIO
J11
1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard
deviation (mean +/-3sigma).
— 0 — kΩ
Vpp 5 Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V
mode) — low-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator — VDD — V
mode) — low-frequency, high-gain mode
(HGO=1)
Peak-to-peak amplitude of oscillation (oscillator — 0.6 — V
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator — VDD — V
mode) — high-frequency, high-gain mode
(HGO=1)
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
5.3.6 Analog
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. VREFH can act as VREF_OUT when VREFV1 module is enabled.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT ZADIN
Pad
SIMPLIFIED
ZAS leakage CHANNEL SELECT
CIRCUIT
ADC SAR
RAS RADIN ENGINE
VADIN
VAS CAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
Table 57. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1 Min. Typ.2 Max. Unit Notes
–0.7 to
+0.5
EFS Full-scale error • 12-bit modes — –4 –5.4 LSB4 VADIN = VDDA5
• <12-bit modes — –1.4 –1.8
EQ Quantization error • 16-bit modes — –1 to 0 — LSB4
• ≤13-bit modes — — ±0.5
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
14.70
14.40
14.10
13.80
ENOB
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
12.30 Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.00
1 2 3 4 5 6 7 8 9 10 11 12
ADC Clock Frequency (MHz)
Figure 23. Typical ENOB vs. ADC_CLK for 16-bit differential mode
13.75
13.50
13.25
13.00
12.75
ENOB
12.50
12.25
12.00
11.75
11.50
Figure 24. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
0.05
CMP Hystereris (V)
Setting
00
0.04 01
10
11
0.03
0.02
0.01
0
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
Vin level (V)
Figure 25. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
0.18
0.16
0.14
0.12
HYSTCTR
CMP Hysteresis (V)
Setting
0.1 00
01
0.08 10
11
0.06
0.04
0.02
0
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
Vin level (V)
Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
2
DAC12 INL (LSB)
-2
-4
-6
-8
0 500 1000 1500 2000 2500 3000 3500 4000
Digital Code
1.499
1.4985
1.498
DAC12 Mid Level Code Voltage
1.4975
1.497
1.4965
1.496
-40 25 55 85 105 125
Temperature °C
5.4 Timers
See General switching specifications.
NOTE
The IRC48M do not meet the USB jitter specifications for
certification for Host mode operation.
This device cannot support Host mode operation.
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 67. SPI master mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x ns 2
tperiph
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 1024 x ns —
tperiph
6 tSU Data setup time (inputs) 96 — ns —
7 tHI Data hold time (inputs) 0 — ns —
Table 67. SPI master mode timing on slew rate enabled pads (continued)
Num. Symbol Description Min. Max. Unit Note
8 tv Data valid (after SPSCK edge) — 52 ns —
9 tHO Data hold time (outputs) 0 — ns —
10 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
11 tRO Rise time output — 36 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
SS1
(OUTPUT)
3 2 10 11 4
SPSCK 5
(CPOL=0)
(OUTPUT) 5
10 11
SPSCK
(CPOL=1)
(OUTPUT)
6 7
MISO
MSB IN2 BIT 6 . . . 1 LSB IN
(INPUT)
8 9
MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
SS1
(OUTPUT)
2
3 10 11 4
SPSCK
(CPOL=0)
(OUTPUT)
5 5 10 11
SPSCK
(CPOL=1)
(OUTPUT)
6 7
MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN
8 9
MOSI
(OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA
Table 68. SPI slave mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 — ns —
6 tSU Data setup time (inputs) 2.5 — ns —
7 tHI Data hold time (inputs) 3.5 — ns —
8 ta Slave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
10 tv Data valid (after SPSCK edge) — 31 ns —
11 tHO Data hold time (outputs) 0 — ns —
12 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
13 tRO Rise time output — 25 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
38 <<CLASSIFICATION>>
K32 L2B Microcontroller, Rev. 3, 09/2020 95
<<NDA MESSAGE>>
NXP Semiconductors
Electrical characteristics
Table 69. SPI slave mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 — ns —
6 tSU Data setup time (inputs) 2 — ns —
7 tHI Data hold time (inputs) 7 — ns —
8 ta Slave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
10 tv Data valid (after SPSCK edge) — 122 ns —
11 tHO Data hold time (outputs) 0 — ns —
12 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
13 tRO Rise time output — 36 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
SS
(INPUT)
2 12 13 4
SPSCK
(CPOL=0)
(INPUT)
3 5 5
SPSCK 12 13
(CPOL=1)
(INPUT)
9
8 10 11 11
6 7
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
SS
(INPUT)
2 4
3 12 13
SPSCK
(CPOL=0)
(INPUT)
5 5 12 13
SPSCK
(CPOL=1)
(INPUT)
10 11 9
MISO see
SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT
(OUTPUT) note
8 6 7
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN
5.5.4 I2C
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the high
drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
2
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT tf
tf tLOW tr tHD; STA tSP tr tBUF
SCL
5.5.5 UART
See General switching specifications.
6 Design considerations
Design considerations
MCU
5 4
Input signal
1 2 ADCx
R
1
C
2
OSCILL
MCU
EXTAL
Figure 34. RC circuit for ADC input
1
High voltage measurement circuits require voltage division, current limiting, and over- CRY
voltage protection as shown the following figure.
Analog input
The1 voltage
2 divider
ADCx
formed by R1 –
R4 must yield a voltage less than or equal to VREFH. The current must be limited to
1
R
less than the injection current limit. Since the ADC pins do notC have diodes to VDD,
2
external clamp diodes must be included to protect against transient over-voltages.
D
OSCILL
EXTAL
MCU 1
R1 VDD
1 2 RF
R2 R5
1 2 1 2 ADCx 1
High voltage input
1
R4 CRY
1
R3 1 2 C
1 2
2
2
BAT54SW
NOTE
VDD
For more details of ADC related usage, refer to AN5250: VDD MCU
1
10k
an Application.
VDD
J1 10k
2
C 1 2 SWD_DIO
3 4 SWD_CLK
2
5 6 RESET_b
RESET_b
1
7 8
1
0.1uF 9 10 RESET_b
0.1uF
2
HDR_5X2
2
10k
102 K32 L2B Microcontroller, Rev. 3, 09/2020
NXP Semiconductors
2
1 2 1
1
CRYSTAL
Cx
1 2 ADCx Design considerations
Analog input
2
1
R
C
6.1.4 Digital design
2
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).
OSCILLATOR OSC
EXTAL XTAL EXTAL
CAUTION 1 2 1
MCU
R1 Do not provide power to I/O pins prior to VDD, especiallyRF
VDD
1
2
the RESET_b pin. RS
R2
• RESET_b1 pin
R5
2
2 2 ADCx 1 2 1
1
1
R4 CRYSTAL
The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An
1
Cx
R3 1 2 C
external RC circuit is recommended to filter noise as shown in the following
2
2
2
figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the
2
BAT54SW
recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable
digital filter to reject spurious noise.
VDD
1
10k
J1 10k 10k
2
1 2 SWD_DIO
3 4 SWD_CLK
2
2
5 6 RESET_b NMI_b
RESET_b
7 8
1
9 10 RESET_b
0.1uF
1
HDR_5X2
2
10k
2
OUT 1 2 RESET_b
1
Active high, RS
open drain 0.1uF
2
2
4 Design considerations 3
1
1 2 1 2 1 3
10k
1
CRYSTAL CRYSTAL
Cx Cy RESONATOR
2
2
2
OUT 1 2 RESET_b
1
RS
0.1uF
2
OSCILLATOR OSCILLATOR OSCILLATOR
EXTAL XTAL EXTAL XTAL EXTAL XTAL
• NMI pin
1
1
RF RF RF
RS RS RS
Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low level
2
2
on this pin will trigger non-maskable
1 2
interrupt. When
1
this
2
pin is enabled as the
1
NMI 3
1
function, an external pull-up resistor (10 kΩ)Cxas shown
CRYSTAL
in the following
CRYSTAL
Cy figure is RESONATOR
2
recommended for robustness. 2
2
If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is
required to disable the NMI function by remapping to another function. The NMI
function is disabled by programming the FOPT[NMI_DIS] bit to zero.
10k 10k
2
RESET_b NMI_b
1
0.1uF
2
VDD
This MCU
MCU
uses the standard Arm SWD interface protocol as shown in the
following figure. While pull-up or pull-down resistors are not required (SWD_DIO
1
10k has an internal pull-up and SWD_CLK has an internal pull-down), external 10 kΩ
pull resistors are recommended for system robustness. The RESET_b pin
2
2 RESET_b
recommendations mentioned above must also be considered.
1
0.1uF
2
4
R4
1
R3 1 2 C
1 2
2
2
BAT54SW
Design considerations
VDD
VDD MCU
1
10k
VDD
J1 10k
2
C 1 2 SWD_DIO
3 4 SWD_CLK
2
5 6 RESET_b
RESET_b
1
7 8
1
0.1uF 9 10 RESET_b
0.1uF
1
HDR_5X2
2
10k
2
Figure 39. SWD debug interface
• Low leakage stop mode wakeup Supervisor Chip VDD MCU
1
Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the10k
low leakage stop modes (LLS/VLLSx). See the pinout table for pin selection.
2
1 2 OUT RESET_b
• Unused pin
1
Active high, RS
open drain 0.1uF
2
Unused GPIO pins must be left floating (no electrical connections) with the MUX
field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital
input path to the MCU.
B
If the USB module is not used, leave the USB data pins (USB0_DP, USB0_DM)
floating.
that have a 12.5 pF CL specification. The internal load capacitor selection must not be
used for high frequency crystals and resonators.
1
CRYSTAL CRYSTAL
1 2 Cx 1 2 Cy 1
Cx
2
1
1
CRYSTAL CRYSTAL
Cx Cy
ADCx Figure 40. Crystal connection – Diagram 1
2
OSCILLATOR OSCILLATOR
OSCILLATOR XTAL
EXTAL OSCILLATOR
EXTAL XTAL OSC
EXTAL XTAL EXTAL XTAL EXTAL
MCU 1 2 1 2
MCU 1 2 1 2 1
1
1
RF RF
1
1
RF RF
RS RS
RS RS
2
2
Cx 11 22 12 2
2
2
ADCx 1 1
1
1
1
1
CRYSTAL
CRYSTAL CRYSTAL
CRYSTAL
Cx Cx Cy Cy
Figure 41. Crystal connection – Diagram 2
2
2
3 2
2
2
OSCILLATOR OSCILLATOR OSCILLATOR
EXTAL XTAL EXTAL XTAL EXTAL XTAL
1 2 1 2 1 3
1
CRYSTAL CRYSTAL
Cx Cy RESONATOR
2
2
VDD
OSCILLATOR
Figure
MCU 42. Crystal connection
OSCILLATOR
VDD – Diagram
OSCILLATOR
3
MCU
VDD EXTAL MCU
XTAL EXTAL XTAL VDDEXTAL XTAL MCU
1
1 2 1 2 1 2
10k 10k
1
1
1
RF RF RF
RS RS RS
2
1 2 1 2 1 3
1
CRYSTAL CRYSTAL
2
Cx Cy
0.1uF RESONATOR
RESET_b NMI_b
2
2
2
2
1
0.1uF
106 K32 L2B Microcontroller, Rev. 3, 09/2020
2
NXP Semiconductors
1
CRYSTAL CRYSTAL
Cx Cy RESONATOR
2
2
2
Part identification
1 2 1 2 1 2
1
1
RF RF RF
RS RS RS
2
2
1 2 1 2 1 3
1
CRYSTAL CRYSTAL
Cx Cy RESONATOR
2
2
2
Figure 43. Crystal connection – Diagram 4
and software
10k enablement solutions, which can reduce development costs and time to
market. Featured software and tools are listed below.
2
NMI_b
Evaluation and Prototyping Hardware
• NXP Freedom Development Platform: http://www.nxp.com/freedom
• Tower System Development Platform: http://www.nxp.com/tower
IDEs for K32 L2B MCUs
• MCUXpresso: https://mcuxpresso.nxp.com
Run-time Software
• K32 L2B SDK: http://mcuxpresso.nxp.com
For all other partner-developed software and tools, visit http://www.nxp.com/partners.
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
B PF S FS SPF T PG FR SR PT
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 74. Part number fields descriptions
Field Description Values
B Brand • K32
PF Product Family • L2
S Sub-family • A= Sub-family A
• B= Sub-family B
FS Flash size • 1 = 64 KB
• 2 = 128 KB
• 3 = 256 KB
• 4 = 512 KB
SPF Special Feature • 0 = Dual core
• 1 = Single core
T Temperature range (°C) • V = -40 to 105
PG Package • FM = 32 QFN
• FT = 48 QFN
• MP = 64 BGA
• LH = 64 LQFP
FR Frequency (MHz) • 0 = 0 - 50 MHz
SR Silicon Revision • A = Initial Mask Set
• B = 1st Major Spin
PT Packaging Type • R = Std Reel
7.4 Example
This is an example part number:
K32L2B31VLH0A
For example:
KL2B6V = K32L2B11VFM0A
10 Revision History
The following table provides a revision history for this document.
Table 75. Revision History
Rev. No. Date Substantial Changes
3 September • Updated value of ADC to 461 ksps from 818 in front page of the Data sheet.
2020 • Removed "RESET_b" from ALT7 column and "PTA20" from ALT1 column
corresponding to PTA20 pin in K32 L2B Signal Multiplexing and Pin Assignments
(LQFP and MAPBGA) and K32 L2B Signal Multiplexing and Pin Assignments (QFN).
Also added the following note: When FTFA_FOPT[RESET_PIN_CONFIG]=0, PTA20
pin acts as RESET_B function only during ............of PORTA_PCR20[MUX]'s setting
value.
• Added Package marking information and Small package marking.
• Removed "OTG/On the Go" references.
2 December • Added Related Resources table in front page of the Data sheet.
2019 • Corrected description of PD/PU in Table 8 Pin Properties section.
• Updated values in "Default" column for pins 1, 2, 9, 10, 49-52 in K32 L2B Signal
Multiplexing and Pin Assignments (LQFP and MAPBGA).
• Added EXTRG_IN signal in TPM signal descriptions and Table 29.
1 September Initial public release.
2019 • Removed support of CRC throughout.
• Replaced name of function pin VREFO with VREF_OUT.
• Changed the high drive pin number to 6 for 48 QFN in Ordering information.
• Updated flash and RAM in Figure 1. System diagram in the Overview section.
Table continues on the next page...