MSP430F22x2 Automotive Mixed-Signal Microcontrollers: 1 Features

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MSP430F2272-Q1, MSP430F2252-Q1
SLAS770B – NOVEMBER 2011 – REVISED MARCH 2014
MSP430F22x2 Automotive Mixed-Signal Microcontrollers

1
1 Features
• Qualified for Automotive Applications – MSP430F2272
• Low Supply Voltage Range: 1.8 V to 3.6 V – 32KB + 256B Flash Memory
• Ultra-Low-Power Consumption – 1KB RAM
– Active Mode: 270 µA at 1 MHz, 2.2 V • Available in a 40-Pin QFN Package (RHA)
– Standby Mode: 0.7 µA • For Complete Module Descriptions, See the
– Off Mode (RAM Retention): 0.1 µA MSP430x2xx Family User's Guide (SLAU144)
• Ultra-Fast Wakeup From Standby Mode in Less
Than 1 µs 2 Applications
• 16-Bit RISC Architecture, 62.5-ns Instruction • Analog Sensor Systems
Cycle Time • Radio-Frequency (RF) Sensor Front Ends
• Basic Clock Module Configurations • Power-Management Systems
– Internal Frequencies up to 16 MHz With Four • LIN Node
Calibrated Frequencies to ±1%
– Internal Very-Low-Power Low-Frequency 3 Description
Oscillator The Texas Instruments MSP430™ family of ultra-low-
power microcontrollers consists of several devices
– 32-kHz Crystal
featuring different sets of peripherals targeted for
– High-Frequency (HF) Crystal up to 16 MHz various applications. The architecture, combined with
– Resonator five low-power modes, is optimized to achieve
– External Digital Clock Source extended battery life in portable measurement
applications. The device features a powerful 16-bit
– External Resistor RISC CPU, 16-bit registers, and constant generators
• 16-Bit Timer_A With Three Capture/Compare that contribute to maximum code efficiency. The
Registers digitally controlled oscillator (DCO) allows the device
• 16-Bit Timer_B With Three Capture/Compare to wake up from low-power modes to active mode in
less than 1 µs.
Registers
• Universal Serial Communication Interface (USCI) The MSP430F22x2 series is an ultra-low-power
mixed-signal microcontroller with two built-in 16-bit
– Enhanced UART With Automatic Baud Rate timers, a universal serial communication interface
Detection (LIN) (USCI), a 10-bit analog-to-digital converter (ADC)
– IrDA Encoder and Decoder with integrated reference and data transfer controller
– Synchronous SPI (DTC), and 32 I/O pins.
– I2C Typical applications include sensor systems that
• 10-Bit 200-ksps Analog-to-Digital Converter (ADC) capture analog signals, convert them to digital values,
With Internal Reference, Sample-and-Hold, and then process the data for display or for
transmission to a host system. Stand-alone radio-
Autoscan, and Data Transfer Controller
frequency (RF) sensor front ends are another area of
• Brownout Detector application.
• Serial Onboard Programming, No External
Programming Voltage Needed, Programmable Device Information (1)
Code Protection by Security Fuse ORDER NUMBER PACKAGE (PIN) BODY SIZE
• Bootstrap Loader (BSL) MSP430F2272TRHARQ1 RHA (40) 6 mm x 6 mm
• On-Chip Emulation Module MSP430F2252TRHARQ1 RHA (40) 6 mm x 6 mm
• Family Members
– MSP430F2252
– 16KB + 256B Flash Memory (1) For the most current part, package, and ordering information,
see the Package Option Addendum at the end of this
– 512B RAM document, or see the TI web site at www.ti.com.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F2272-Q1, MSP430F2252-Q1
SLAS770B – NOVEMBER 2011 – REVISED MARCH 2014 www.ti.com
4 Functional Block Diagram
VCC VSS P1.x/P2.x P3.x/P4.x

2x8 2x8
XIN XOUT
ADC10 Ports P1/P2
ACLK
Basic Clock Flash RAM 10−Bit Ports P3/P4
System+ 2x8 I/O
SMCLK 32kB 1kB 12 Interrupt 2x8 I/O
16kB 512B Channels, capability, pullup/down
MCLK Autoscan, pullup/down resistors
DTC resistors
16MHz MAB
CPU
incl. 16
Registers MDB
Emulation
(2BP) Timer_B3 USCI_A0:
Watchdog Timer_A3 UART/LIN,
JTAG Brownout WDT+ 3 CC IrDA, SPI
Interface Protection 3 CC Registers,
15/16−Bit Registers Shadow USCI_B0:
Reg SPI, I2C
Spy-Bi-Wire
RST/NMI
Figure 1. Functional Block Diagram
2 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430F2272-Q1 MSP430F2252-Q1

MSP430F2272-Q1, MSP430F2252-Q1
www.ti.com SLAS770B – NOVEMBER 2011 – REVISED MARCH 2014
Table of Contents
1 Features ................................................................. 1 8.21 Wakeup From Lower-Power Modes (LPM3/4) .... 32
2 Applications .......................................................... 1 8.22 Typical Characteristics - DCO Clock Wakeup Time
From LPM3, LPM4 .................................................. 32
3 Description ............................................................ 1
8.23 DCO With External Resistor ROSC ....................... 33
4 Functional Block Diagram ................................... 2
8.24 Typical Characteristics - DCO With External
5 Revision History ................................................... 4 Resistor ROSC ......................................................... 33
6 Terminal Configuration and Functions ............... 5 8.25 Crystal Oscillator LFXT1, Low-Frequency Mode . 34
6.1 40-Pin RHA Package (Top View) ............................ 5 8.26 Internal Very-Low-Power Low-Frequency Oscillator
6.2 Terminal Functions .................................................. 6 (VLO) ...................................................................... 34
7 Detailed Description ............................................. 9 8.27 Crystal Oscillator LFXT1, High-Frequency Mode 35
7.1 CPU .......................................................................... 9 8.28 Typical Characteristics - LFXT1 Oscillator in HF
Mode (XTS = 1) ...................................................... 36
7.2 Instruction Set .......................................................... 9
8.29 Timer_A ................................................................ 36
7.3 Operating Modes ................................................... 10
8.30 Timer_B ................................................................ 36
7.4 Interrupt Vector Addresses .................................... 11
8.31 USCI (UART Mode) ............................................. 37
7.5 Special Function Registers .................................... 12
8.32 USCI (SPI Master Mode) ..................................... 37
7.6 Memory Organization ............................................. 13
8.33 USCI (SPI Slave Mode) ....................................... 37
7.7 Bootstrap Loader (BSL) ......................................... 13
8.34 USCI (I2C Mode) ................................................. 40
7.8 Flash Memory ........................................................ 13
8.35 10-Bit ADC, Power Supply and Input Range
7.9 Peripherals ............................................................. 14
Conditions ............................................................... 41
7.10 Oscillator and System Clock ................................ 14
8.36 10-Bit ADC, Built-In Voltage Reference ............... 42
7.11 Brownout .............................................................. 14
8.37 10-Bit ADC, External Reference .......................... 43
7.12 Digital I/O ............................................................. 14
8.38 10-Bit ADC, Timing Parameters ........................... 43
7.13 Watchdog Timer (WDT+) ..................................... 14
8.39 10-Bit ADC, Linearity Parameters ........................ 44
7.14 Timer_A3 .............................................................. 15
8.40 10-Bit ADC, Temperature Sensor and Built-In VMID
7.15 Timer_B3 .............................................................. 16 ................................................................................. 44
7.16 Universal Serial Communications Interface (USCI) 8.41 Flash Memory ..................................................... 45
................................................................................. 16
8.42 RAM ..................................................................... 45
7.17 ADC10 .................................................................. 16
8.43 JTAG and Spy-Bi-Wire Interface .......................... 46
7.18 Peripheral File Map .............................................. 17
8.44 JTAG Fuse ........................................................... 46
8 Specifications ...................................................... 20 9 I/O Port Schematics ............................................ 47
8.1 Absolute Maximum Ratings ................................... 20
9.1 Port P1 Pin Schematic: P1.0 to P1.3, Input/Output
8.2 Handling Ratings .................................................... 20 With Schmitt Trigger ............................................... 47
8.3 Recommended Operating Conditions .................... 20 9.2 Port P1 Pin Schematic: P1.4 to P1.6, Input/Output
8.4 Active Mode Supply Current (into DVCC + AVCC) With Schmitt Trigger and In-System Access Features
Excluding External Current ..................................... 21 ................................................................................. 48
8.5 Typical Characteristics - Active-Mode Supply Current 9.3 Port P1 Pin Schematic: P1.7, Input/Output With
(Into DVCC + AVCC) ................................................. 21 Schmitt Trigger and In-System Access Features ... 49
8.6 Low-Power-Mode Supply Currents (Into VCC ) 9.4 Port P2 Pin Schematic: P2.0, P2.2, Input/Output With
Excluding External Current ..................................... 22 Schmitt Trigger ........................................................ 50
8.7 Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and 9.5 Port P2 Pin Schematic: P2.1, Input/Output With
RST/NMI) ................................................................ 23 Schmitt Trigger ........................................................ 51
8.8 Inputs (Ports P1, P2) .............................................. 23 9.6 Port P2 Pin Schematic: P2.3, Input/Output With
8.9 Leakage Current (Ports P1, P2, P3, and P4) ........ 23 Schmitt Trigger ........................................................ 52
8.10 Outputs (Ports P1, P2, P3, and P4) ..................... 24 9.7 Port P2 Pin Schematic: P2.4, Input/Output With
Schmitt Trigger ........................................................ 53
8.11 Output Frequency (Ports P1, P2, P3, and P4) .... 24
9.8 Port P2 Pin Schematic: P2.5, Input/Output With
8.12 Typical Characteristics - Outputs ......................... 25
Schmitt Trigger and External ROSC for DCO ........ 54
8.13 POR and BOR ..................................................... 26
8.14 Main DCO Characteristics ................................... 28 Schmitt Trigger and Crystal Oscillator Input ........... 55
8.15 DCO Frequency ................................................... 28 9.10 Port P2 Pin Schematic: P2.7, Input/Output With
8.16 Calibrated DCO Frequencies - Tolerance at Schmitt Trigger and Crystal Oscillator Output ........ 56
Calibration ............................................................... 29 9.11 Port P3 Pin Schematic: P3.0, Input/Output With
8.17 Calibrated DCO Frequencies - Tolerance Over Schmitt Trigger ........................................................ 57
Temperature 0°C to 85°C ....................................... 29 9.12 Port P3 Pin Schematic: P3.1 to P3.5, Input/Output
8.18 Calibrated DCO Frequencies - Tolerance Over With Schmitt Trigger ............................................... 58
Supply Voltage VCC ................................................ 30 9.13 Port P3 Pin Schematic: P3.6 to P3.7, Input/Output
8.19 Calibrated DCO Frequencies - Overall Tolerance With Schmitt Trigger ............................................... 59
................................................................................. 30 9.14 Port P4 Pin Schematic: P4.0 to P4.2, Input/Output
8.20 Typical Characteristics - Calibrated 1-MHz DCO With Schmitt Trigger ............................................... 60
Frequency ............................................................... 31 9.15 Port P4 Pin Schematic: P4.3 to P4.4, Input/Output
Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 3

MSP430F2272-Q1, MSP430F2252-Q1
With Schmitt Trigger ............................................... 61 10.1 Device Support .................................................... 67

9.16 Port P4 Pin Schematic: P4.5, Input/Output With 10.2 Documentation Support ....................................... 68
Schmitt Trigger ........................................................ 63 10.3 Related Links ....................................................... 69
9.17 Port P4 Pin Schematic: P4.6, Input/Output With 10.4 Community Resources ......................................... 69
Schmitt Trigger ........................................................ 64
10.5 Trademarks .......................................................... 69
10.6 Electrostatic Discharge Caution ........................... 69
Schmitt Trigger ........................................................ 65
10.7 Glossary ............................................................... 69
9.19 JTAG Fuse Check Mode ...................................... 66
11 Mechanical, Packaging, and Orderable
10 Device and Documentation Support ................ 67
Information .......................................................... 69
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Literature Summary
Number
SLAS770 Product Preview release
SLAS770A Production Data release
Formatting and document organization changes throughout.

SLAS770B Added Device and Documentation Support and Mechanical, Packaging, and Orderable Information.
Removed MSP430F2232.

MSP430F2272-Q1, MSP430F2252-Q1
6 Terminal Configuration and Functions
6.1 40-Pin RHA Package (Top View)
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI
P1.4/SMCLK/TCK
TEST/SBWTCK
P1.5/TA0/TMS
P2.5/ROSC
P1.3/TA2
P1.2/TA1
DVCC
DVCC
39 38 37 36 35 34 33 32
DVSS 1 30 P1.1/TA0
XOUT/P2.7 2 29 P1.0/TACLK/ADC10CLK
XIN/P2.6 3 28 P2.4/TA2/A4/VREF+/VeREF+
DVSS 4 27 P2.3/TA1/A3/VREF−/VeREF−
RST/NMI/SBWTDIO 5 26 P3.7/A7
P2.0/ACLK/A0 6 25 P3.6/A6
P2.1/TAINCLK/SMCLK/A1 7 24 P3.5/UCA0RXD/UCA0SOMI
P2.2/TA0/A2 8 23 P3.4/UCA0TXD/UCA0SIMO
P3.0/UCB0STE/UCA0CLK/A5 9 22 P4.7/TBCLK
P3.1/UCB0SIMO/UCB0SDA 10 21 P4.6/TBOUTH/A15
12 13 14 15 16 17 18 19
P4.1/TB1
P3.3/UCB0CLK/UCA0STE
AVSS
P4.2/TB2
P4.0/TB0
P4.3/TB0/A12
P4.4/TB1/A13
P4.5/TB2/A14
AVCC
P3.2/UCB0SOMI/UCB0SCL

MSP430F2272-Q1, MSP430F2252-Q1
6.2 Terminal Functions
Table 1. Terminal Functions

TERMINAL
NO. I/O DESCRIPTION
NAME
RHA
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK 29 I/O Timer_A, clock signal TACLK input
ADC10, conversion clock
P1.1/TA0 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output
BSL transmit
P1.2/TA1 31 I/O
Timer_A, capture: CCI1A input, compare: OUT1 output
P1.3/TA2 32 I/O
Timer_A, capture: CCI2A input, compare: OUT2 output
P1.4/SMCLK/TCK 33 I/O SMCLK signal output
Test Clock input for device programming and test
P1.5/TA0/TMS 34 I/O Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
P1.6/TA1/TDI/TCLK 35 I/O Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
(1)
P1.7/TA2/TDO/TDI 36 I/O Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
P2.0/ACLK/A0 6 I/O ACLK output
ADC10, analog input A0
Timer_A, clock signal at INCLK
P2.1/TAINCLK/SMCLK/A1 7 I/O
SMCLK signal output
P2.2/TA0/A2 8 I/O Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
Timer_A, capture CCI1B input, compare: OUT1 output
P2.3/TA1/A3/VREF-/ VeREF- 27 I/O
Negative reference voltage input
Timer_A, compare: OUT2 output
P2.4/TA2/A4/VREF+/ VeREF+ 28 I/O
Positive reference voltage output or input
P2.5/ROSC 40 I/O
Input for external DCO resistor to define DCO frequency
(1) TDO or TDI is selected via JTAG instruction.


MSP430F2272-Q1, MSP430F2252-Q1
Terminal Functions (continued)

Table 1. Terminal Functions (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME
RHA
Input terminal of crystal oscillator
XIN/P2.6 3 I/O
Output terminal of crystal oscillator
XOUT/P2.7 2 I/O
General-purpose digital I/O pin (2)
USCI_B0 slave transmit enable
P3.0/UCB0STE/UCA0CLK/A5 9 I/O
USCI_A0 clock input/output
P3.1/UCB0SIMO/ UCB0SDA 10 I/O USCI_B0 SPI mode: slave in/master out
USCI_B0 I2C mode: SDA I2C data
P3.2/UCB0SOMI/UCB0SCL 11 I/O USCI_B0 SPI mode: slave out/master in
USCI_B0 I2C mode: SCL I2C clock
P3.3/UCB0CLK/UCA0STE 12 I/O USCI_B0 clock input/output
USCI_A0 slave transmit enable
P3.4/UCA0TXD/ UCA0SIMO 23 I/O USCI_A0 UART mode: transmit data output
USCI_A0 SPI mode: slave in/master out
P3.5/UCA0RXD/ UCA0SOMI 24 I/O USCI_A0 UART mode: receive data input
USCI_A0 SPI mode: slave out/master in
P3.6/A6 25 I/O
ADC10 analog input A6
P3.7/A7 26 I/O
P4.0/TB0 15 I/O
Timer_B, capture: CCI0A input, compare: OUT0 output
P4.1/TB1 16 I/O
P4.2/TB2 17 I/O
P4.3/TB0/A12 18 I/O Timer_B, capture: CCI0B input, compare: OUT0 output
P4.4/TB1/A13 19 I/O Timer_B, capture: CCI1B input, compare: OUT1 output
P4.5/TB2/A14 20 I/O Timer_B, compare: OUT2 output
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
MSP430F2272-Q1, MSP430F2252-Q1
Terminal Functions (continued)

Table 1. Terminal Functions (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME
RHA
P4.6/TBOUTH/A15 21 I/O Timer_B, switch all TB0 to TB3 outputs to high impedance
P4.7/TBCLK 22 I/O
Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
RST/NMI/SBWTDIO 5 I
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to
TEST/SBWTCK 37 I TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC 38, 39 Digital supply voltage
AVCC 14 Analog supply voltage
DVSS 1, 4 Digital ground reference
AVSS 13 Analog ground reference
QFN Pad Pad NA QFN package pad; connection to DVSS recommended.

MSP430F2272-Q1, MSP430F2252-Q1
7 Detailed Description
Instruction Set (continued)
7.1 CPU
Program Counter PC/R0
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
Stack Pointer SP/R1
operations, other than program-flow instructions, are
performed as register operations in conjunction with
Status Register SR/CG1/R2
seven addressing modes for source operand and four
addressing modes for destination operand. Constant Generator CG2/R3
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to- General-Purpose Register R4
register operation execution time is one cycle of the

General-Purpose Register R5
CPU clock.
Four of the registers, R0 to R3, are dedicated as General-Purpose Register R6
program counter, stack pointer, status register, and
constant generator respectively. The remaining General-Purpose Register R7
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with General-Purpose Register R9
all instructions.
7.2 Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each General-Purpose Register R12
instruction can operate on word and byte data.
Table 2 shows examples of the three types of General-Purpose Register R13
instruction formats; Table 3 shows the address
modes. General-Purpose Register R14
Table 2. Instruction Word Formats

INSTRUCTION FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 → R5
Single operands, destination only CALL R8 PC → (TOS), R8 → PC
Relative jump, unconditional/conditional JNE Jump-on-equal bit = 0
Table 3. Address Mode Descriptions

(1) (2)
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 → R11
Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6)
Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) → M(TONI)
Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) → M(TCDAT)
Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)
M(R10) → R11
Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11
R10 + 2 → R10
Immediate ✓ MOV #X,TONI MOV #45,TONI #45 → M(TONI)
(1) S = source
(2) D = destination

MSP430F2272-Q1, MSP430F2252-Q1
7.3 Operating Modes

The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation.
An interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled.
– ACLK and SMCLK remain active. MCLK is disabled.
– CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.
– DCO dc-generator is disabled if DCO not used in active mode.
– MCLK and SMCLK are disabled.
– DCO dc-generator remains enabled.
– ACLK remains active.
– DCO dc-generator is disabled.
– ACLK remains active.
– ACLK is disabled.
– DCO dc-generator is disabled.
– Crystal oscillator is stopped.

MSP430F2272-Q1, MSP430F2252-Q1
7.4 Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 4. Interrupt Vector Addresses

SYSTEM
INTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITY
INTERRUPT
Power-up
PORIFG
External reset
RSTIFG
Watchdog Reset 0FFFEh 31, highest
WDTIFG
Flash key violation
KEYV (2)
PC out-of-range (1)
NMI NMIIFG (non)-maskable,
Oscillator fault OFIFG (non)-maskable, 0FFFCh 30
Flash memory access violation ACCVIFG (2) (3) (non)-maskable
Timer_B3 TBCCR0 CCIFG (4) maskable 0FFFAh 29
TBCCR1 and TBCCR2 CCIFGs,
Timer_B3 maskable 0FFF8h 28
TBIFG (2) (4)
0FFF6h 27
Watchdog Timer WDTIFG maskable 0FFF4h 26
Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25
TACCR1 CCIFG
Timer_A3 TACCR2 CCIFG maskable 0FFF0h 24
TAIFG (2) (4)
USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG (2) maskable 0FFEEh 23
USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG (2) maskable 0FFECh 22
ADC10 ADC10IFG (4) maskable 0FFEAh 21
0FFE8h 20
I/O Port P2 (2) (4)
P2IFG.0 to P2IFG.7 maskable 0FFE6h 19
(eight flags)
I/O Port P1
P1IFG.0 to P1IFG.7 (2) (4) maskable 0FFE4h 18
(eight flags)
0FFE2h 17
0FFE0h 16
(5)
0FFDEh 15
(6)
0FFDCh to 0FFC0h 14 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
(4) Interrupt flags are located in the module.
(5) This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
(6) The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.

MSP430F2272-Q1, MSP430F2252-Q1
7.5 Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw Bit can be read and written.
rw-0, 1 Bit can be read and written. It is Reset or Set by PUC.
rw-(0), (1) Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Table 5. Interrupt Enable 1

Address 7 6 5 4 3 2 1 0
00h ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0
WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
OFIE Oscillator fault interrupt enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Table 6. Interrupt Enable 2

Address 7 6 5 4 3 2 1 0
01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw-0 rw-0 rw-0 rw-0
UCA0RXIE USCI_A0 receive-interrupt enable

UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
Table 7. Interrupt Flag Register 1

Address 7 6 5 4 3 2 1 0
02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw-0 rw-(0) rw-(1) rw-1 rw-(0)
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
PORIFG Power-on reset interrupt flag. Set on VCC power up.
NMIIFG Set via RST/NMI pin
Table 8. Interrupt Flag Register 2

Address 7 6 5 4 3 2 1 0
03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
rw-1 rw-0 rw-1 rw-0
UCA0RXIFG USCI_A0 receive-interrupt flag

UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag

MSP430F2272-Q1, MSP430F2252-Q1
7.6 Memory Organization
Table 9. Memory Organization

MSP430F2252 MSP430F2272
Memory Size 16KB Flash 32KB Flash
Main: interrupt vector Flash 0FFFFh-0FFC0h 0FFFFh-0FFC0h
Main: code memory Flash 0FFFFh-0C000h 0FFFFh-08000h
Size 256 Byte 256 Byte
Information memory
Flash 010FFh-01000h 010FFh-01000h
Size 1KB 1KB
Boot memory
ROM 0FFFh-0C00h 0FFFh-0C00h
512 Byte 1KB
RAM Size
03FFh-0200h 05FFh-0200h
16-bit 01FFh-0100h 01FFh-0100h
Peripherals 8-bit 0FFh-010h 0FFh-010h
8-bit SFR 0Fh-00h 0Fh-00h
7.7 Bootstrap Loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap
Loader User’s Guide (SLAU319).
Table 10. BSL Function Pins

BSL FUNCTION RHA PACKAGE PINS
Data transmit 30 - P1.1
Data receive 8 - P2.2
7.8 Flash Memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.

MSP430F2272-Q1, MSP430F2252-Q1
7.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
7.10 Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and
a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low
system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in
less than 1 µs. The basic clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal very-
low-power LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 11. DCO Calibration Data

(Provided From Factory in Flash Information Memory Segment A)
DCO FREQUENCY CALIBRATION REGISTER SIZE ADDRESS
CALBC1_1MHZ byte 010FFh
1 MHz
CALDCO_1MHZ byte 010FEh
CALBC1_8MHZ byte 010FDh
8 MHz
CALDCO_8MHZ byte 010FCh
CALBC1_12MHZ byte 010FBh
12 MHz
CALDCO_12MHZ byte 010FAh
CALBC1_16MHZ byte 010F9h
16 MHz
CALDCO_16MHZ byte 010F8h
7.11 Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
7.12 Digital I/O

There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all eight bits of port P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and
write data is ignored.
7.13 Watchdog Timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.

MSP430F2272-Q1, MSP430F2252-Q1
7.14 Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 12. Timer_A3 Signal Connections

OUTPUT PIN
INPUT PIN NUMBER DEVICE INPUT MODULE INPUT MODULE OUTPUT
MODULE BLOCK NUMBER
SIGNAL NAME SIGNAL
RHA RHA
29 - P1.0 TACLK TACLK Timer NA
ACLK ACLK
SMCLK SMCLK
7 - P2.1 TAINCLK INCLK
30 - P1.1 TA0 CCI0A CCR0 TA0 30 - P1.1
8 - P2.2 TA0 CCI0B 8 - P2.2
VSS GND 34 - P1.5
VCC VCC
31 - P1.2 TA1 CCI1A CCR1 TA1 31 - P1.2
27 - P2.3 TA1 CCI1B 27 - P2.3
VSS GND 35 - P1.6
VCC VCC
32 - P1.3 TA2 CCI2A CCR2 TA2 32 - P1.3
ACLK (internal) CCI2B 28 - P2.4
VSS GND 36 - P1.7
VCC VCC

MSP430F2272-Q1, MSP430F2252-Q1
7.15 Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 13. Timer_B3 Signal Connections

OUTPUT PIN
INPUT PIN NUMBER DEVICE INPUT MODULE INPUT MODULE OUTPUT
MODULE BLOCK NUMBER
SIGNAL NAME SIGNAL
RHA RHA
22 - P4.7 TBCLK TBCLK Timer NA
ACLK ACLK
SMCLK SMCLK
22 - P4.7 TBCLK INCLK
15 - P4.0 TB0 CCI0A CCR0 TB0 15 - P4.0
18 - P4.3 TB0 CCI0B 18 - P4.3
VSS GND
VCC VCC
16 - P4.1 TB1 CCI1A CCR1 TB1 16 - P4.1
19 - P4.4 TB1 CCI1B 19 - P4.4
VSS GND
VCC VCC
17 - P4.2 TB2 CCI2A CCR2 TB2 17 - P4.2
ACLK (internal) CCI2B 20 - P4.5
VSS GND
VCC VCC
7.16 Universal Serial Communications Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART,
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
7.17 ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.

MSP430F2272-Q1, MSP430F2252-Q1
7.18 Peripheral File Map

Table 14. Peripherals With Word Access
MODULE REGISTER NAME SHORT NAME ADDRESS
OFFSET
ADC10 ADC data transfer start address ADC10SA 1BCh
ADC memory ADC10MEM 1B4h
ADC control register 1 ADC10CTL1 1B2h
ADC control register 0 ADC10CTL0 1B0h
ADC analog enable 0 ADC10AE0 04Ah
ADC analog enable 1 ADC10AE1 04Bh
ADC data transfer control register 1 ADC10DTC1 049h
ADC data transfer control register 0 ADC10DTC0 048h
Timer_B Capture/compare register TBCCR2 0196h
Capture/compare register TBCCR1 0194h
Capture/compare register TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control TBCCTL2 0186h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Timer_A Capture/compare register TACCR2 0176h
Capture/compare register TACCR1 0174h
Capture/compare register TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control TACCTL2 0166h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Flash Memory Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
Watchdog Timer+ Watchdog/timer control WDTCTL 0120h

MSP430F2272-Q1, MSP430F2252-Q1
Table 15. Peripherals With Byte Access

OFFSET
USCI_B0 USCI_B0 transmit buffer UCB0TXBUF 06Fh
USCI_B0 receive buffer UCB0RXBUF 06Eh
USCI_B0 status UCB0STAT 06Dh
USCI_B0 bit rate control 1 UCB0BR1 06Bh
USCI_B0 bit rate control 0 UCB0BR0 06Ah
USCI_B0 control 1 UCB0CTL1 069h
USCI_B0 control 0 UCB0CTL0 068h
USCI_B0 I2C slave address UCB0SA 011Ah
USCI_B0 I2C own address UCB0OA 0118h
USCI_A0 USCI_A0 transmit buffer UCA0TXBUF 067h
USCI_A0 receive buffer UCA0RXBUF 066h
USCI_A0 status UCA0STAT 065h
USCI_A0 modulation control UCA0MCTL 064h
USCI_A0 baud rate control 1 UCA0BR1 063h
USCI_A0 baud rate control 0 UCA0BR0 062h
USCI_A0 control 1 UCA0CTL1 061h
USCI_A0 control 0 UCA0CTL0 060h
USCI_A0 IrDA receive control UCA0IRRCTL 05Fh
USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh
USCI_A0 auto baud rate control UCA0ABCTL 05Dh
Basic Clock System+ Basic clock system control 3 BCSCTL3 053h
Basic clock system control 2 BCSCTL2 058h
Basic clock system control 1 BCSCTL1 057h
DCO clock frequency control DCOCTL 056h
Port P4 Port P4 resistor enable P4REN 011h
Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 resistor enable P2REN 02Fh
Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah

MSP430F2272-Q1, MSP430F2252-Q1
Table 15. Peripherals With Byte Access (continued)

OFFSET
Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Special Function SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h

MSP430F2272-Q1, MSP430F2252-Q1
8 Specifications
8.1 Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS -0.3 V to 4.1 V
(2)
Voltage applied to any pin -0.3 V to VCC + 0.3 V
Diode current at any device terminal ±2 mA
(1) Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
8.2 Handling Ratings

MIN MAX UNIT
Unprogrammed device -55 150 °C
Tstg Storage temperature (1)
Programmed device -55 150
(1) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
8.3 Recommended Operating Conditions (1) (2)

MIN NOM MAX UNIT
During program
1.8 3.6 V
execution
VCC Supply voltage AVCC = DVCC = VCC
During program or erase
2.2 3.6 V
flash memory
VSS Supply voltage AVSS = DVSS = VSS 0 V
TA Operating free-air temperature T version -40 105 °C
VCC = 1.8 V, Duty cycle = 50% ±10% dc 4.15
Processor frequency
fSYSTEM (maximum MCLK frequency) (1) (2) VCC = 2.7 V, Duty cycle = 50% ±10% dc 12 MHz
(see Figure 2)
VCC ≥ 3.3 V, Duty cycle = 50% ±10% dc 16
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
16 MHz
Supply voltage range,
during flash memory
System Frequency −MHz
programming
12 MHz
Supply voltage range,

during program execution
7.5 MHz
4.15 MHz
1.8 V 2.2 V 2.7 V 3.3 V 3.6 V
Supply Voltage −V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 2. Operating Area


MSP430F2272-Q1, MSP430F2252-Q1
(1) (2)
8.4 Active Mode Supply Current (into DVCC + AVCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz, 2.2 V 270 390
fACLK = 32768 Hz,
Program executes in flash,
Active mode (AM)
IAM,1MHz BCSCTL1 = CALBC1_1MHZ, µA
current (1 MHz) 3V 390 550
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 1 MHz, 2.2 V 240
fACLK = 32768 Hz,
Program executes in RAM,
Active mode (AM)
IAM,1MHz BCSCTL1 = CALBC1_1MHZ, µA
current (1 MHz) 3.3 V 340
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK = fACLK = 32768 Hz/8 = -40°C to
5 9
4096 Hz, 85°C 2.2 V
fDCO = 0 Hz,
105°C 18
Active mode (AM) Program executes in flash,
IAM,4kHz -40°C to µA
current (4 kHz) SELMx = 11, SELS = 1, 6 10
DIVMx = DIVSx = DIVAx = 11, 85°C
3V
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0 105°C 20
-40°C to
60 85
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz, 85°C 2.2 V
fACLK = 0 Hz, 105°C 95
Active mode (AM)
IAM,100kHz Program executes in flash, µA
current (100 kHz) -40°C to
RSELx = 0, DCOx = 0, CPUOFF = 0, 72 95
SCG0 = 0, SCG1 = 0, OSCOFF = 1 85°C 3V
105°C 105
(1) All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
8.5 Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC)
8.0 5.0
f DCO = 16 MHz
7.0 TA = 85 °C
4.0
6.0 TA = 25 °C
Active Mode Current − mA
Active Mode Current − mA
f DCO = 12 MHz
5.0
3.0
4.0 VCC = 3 V
f DCO = 8 MHz
TA = 85 °C
2.0
3.0
TA = 25 °C
2.0
1.0
1.0 VCC = 2.2 V
f DCO = 1 MHz
0.0 0.0
1.5 2.0 2.5 3.0 3.5 4.0 0.0 4.0 8.0 12.0 16.0
VCC − Supply Voltage − V f DCO − DCO Frequency − MHz
TA = 25°C Figure 4. Active-Mode Current vs DCO Frequency
Figure 3. Active-Mode Current vs Supply Voltage

MSP430F2272-Q1, MSP430F2252-Q1
(1) (2)
8.6 Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current
fMCLK = 0 MHz, 2.2 V 75 90
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 0
ILPM0,1MHz BCSCTL1 = CALBC1_1MHZ, µA
(LPM0) current (3) 3V 90 120
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
fMCLK = 0 MHz, 2.2 V 37 48
fSMCLK = fDCO(0, 0) ≈ 100 kHz,
Low-power mode 0 fACLK = 0 Hz,
ILPM0,100kHz µA
(LPM0) current (3) RSELx = 0, DCOx = 0, 3V 41 65
fMCLK = fSMCLK = 0 MHz, -40°C to
22 29
fDCO = 1 MHz, 85°C 2.2 V
fACLK = 32768 Hz, 105°C 31
Low-power mode 2
ILPM2 BCSCTL1 = CALBC1_1MHZ, µA
(LPM2) current (4) -40°C to
DCOCTL = CALDCO_1MHZ, 25 32
CPUOFF = 1, SCG0 = 0, 85°C 3V
SCG1 = 1, OSCOFF = 0 105°C 34
-40°C 0.7 1.4
25°C 0.7 1.4
2.2 V
85°C 2.4 3.3
fDCO = fMCLK = fSMCLK = 0 MHz,
Low-power mode 3 fACLK = 32768 Hz, 105°C 5 10
ILPM3,LFXT1 µA
(LPM3) current (4) CPUOFF = 1, SCG0 = 1, -40°C 0.9 1.5
25°C 0.9 1.5
3V
85°C 2.6 3.8
105°C 6 12
-40°C 0.4 1
25°C 0.5 1
2.2 V
fDCO = fMCLK = fSMCLK = 0 MHz, 85°C 1.8 2.9
fACLK from internal LF oscillator 105°C 4.5 9
Low-power mode 3
ILPM3,VLO (VLO), µA
current, (LPM3) (4) -40°C 0.5 1.2
SCG1 = 1, OSCOFF = 0 25°C 0.6 1.2
3V
85°C 2.1 3.3
105°C 5.5 11
-40°C 0.1 0.5
fDCO = fMCLK = fSMCLK = 0 MHz,
Low-power mode 4 fACLK = 0 Hz, 25°C 2.2 V, 0.1 0.5
ILPM4 µA
(LPM4) current (5) CPUOFF = 1, SCG0 = 1, 85°C 3V 1.5 3
105°C 4.5 9
(1) All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.

MSP430F2272-Q1, MSP430F2252-Q1
8.7 Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
0.45 VCC 0.75 VCC
VIT+ Positive-going input threshold voltage 2.2 V 1 1.65 V
3V 1.35 2.25
0.25 VCC 0.55 VCC
VIT- Negative-going input threshold voltage 2.2 V 0.55 1.20 V
3V 0.75 1.65
2.2 V 0.1 1
Vhys Input voltage hysteresis (VIT+ - VIT- ) V
3V 0.3 1
For pullup: VIN = VSS,
RPull Pullup or pulldown resistor 3V 20 35 50 kΩ
For pulldown: VIN = VCC
CI Input capacitance VIN = VSS or VCC 5 pF
8.8 Inputs (Ports P1, P2)

Port P1, P2: P1.x to P2.x, External trigger
t(int) External interrupt timing 2.2 V, 3 V 20 ns
pulse width to set interrupt flag (1)
(1) An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int) .
8.9 Leakage Current (Ports P1, P2, P3, and P4)

(1) (2)
Ilkg(Px.y) High-impedance leakage current 2.2 V, 3 V ±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.

MSP430F2272-Q1, MSP430F2252-Q1
8.10 Outputs (Ports P1, P2, P3, and P4)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
(1)
IOH(max) = -1.5 mA VCC - 0.25 VCC
(2)
2.2 V
IOH(max) = -6 mA VCC - 0.6 VCC
VOH High-level output voltage V
IOH(max) = -1.5 mA (1) VCC - 0.25 VCC
3V
IOH(max) = -6 mA (2) VCC - 0.6 VCC
(1)
IOL(max) = 1.5 mA VSS VSS + 0.25
2.2 V
IOL(max) = 6 mA (2) VSS VSS + 0.6
VOL Low-level output voltage V
IOL(max) = 1.5 mA (1) VSS VSS + 0.25
3V
IOL(max) = 6 mA (2) VSS VSS + 0.6
(1) The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
8.11 Output Frequency (Ports P1, P2, P3, and P4)

P1.4/SMCLK, CL = 20 pF, 2.2 V 10
fPx.y Port output frequency (with load) MHz
RL = 1 kΩ against VCC/2 (1) (2) 3V 12
2.2 V 12
fPort_CLK Clock output frequency P2.0/ACLK, P1.4/SMCLK, CL = 20 pF (2) MHz
3V 16
(1) Alternatively, a resistive divider with two 2-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap
of the divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

MSP430F2272-Q1, MSP430F2252-Q1
8.12 Typical Characteristics - Outputs

One output loaded at a time.
25.0 50.0
VCC = 2.2 V TA = 25°C VCC = 3 V
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA

P4.5 P4.5 TA = 25°C
20.0 TA = 85°C 40.0
TA = 85°C
15.0 30.0
10.0 20.0
5.0 10.0
0.0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOL − Low-Level Output V oltage − V VOL − Low-Level Output V oltage − V
Figure 5. Typical Low-Level Output Current vs Low-Level Figure 6. Typical Low-Level Output Current vs Low-Level
Output Voltage Output Voltage
0.0 0.0
VCC = 2.2 V VCC = 3 V
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
P4.5 P4.5
−5.0 −10.0
−10.0 −20.0
−15.0 −30.0
TA = 85°C
−20.0 −40.0
TA = 85°C
TA = 25°C TA = 25°C
−25.0 −50.0
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOH − High-Level Output V oltage − V VOH − High-Level Output V oltage − V
Figure 7. Typical High-Level Output Current vs High-Level Figure 8. Typical High-Level Output Current vs High-Level
Output Voltage Output Voltage

MSP430F2272-Q1, MSP430F2252-Q1
8.13 POR and BOR (1) (2)

0.7 ×
VCC(start) See Figure 9 dVCC /dt ≤ 3 V/s V
V(B_IT-)
V(B_IT-) See Figure 9 through Figure 11 dVCC /dt ≤ 3 V/s 1.71 V
Vhys(B_IT-) See Figure 9 dVCC /dt ≤ 3 V/s 70 130 210 mV
td(BOR) See Figure 9 2000 µs
Pulse duration needed at RST/NMI
t(reset) 3V 2 µs
pin to accepted reset internally
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT-) is ≤ 1.8 V.
(2) During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-) . The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
t d(BOR)
Figure 9. POR and BOR vs Supply Voltage
VCC t pw
2
VCC = 3 V 3V
Typical Conditions
1.5
VCC(drop) − V
VCC(drop)
0.5
0
0.001 1 1000
1 ns 1 ns
t pw − Pulse Width − µs t pw − Pulse Width − µs
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal

MSP430F2272-Q1, MSP430F2252-Q1
VCC t pw
2 3V
VCC = 3 V
VCC(drop) − V
1.5 Typical Conditions
1
VCC(drop)
0.5
t f = tr
0
0.001 1 1000 tf tr
t pw − Pulse Width − µs t pw − Pulse Width − µs
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal

MSP430F2272-Q1, MSP430F2252-Q1
8.14 Main DCO Characteristics

• All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
• DCO control bits DCOx have a step size as defined by parameter SDCO .
• Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
faverage =
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
8.15 DCO Frequency

RSELx < 14 1.8 3.6
VCC Supply voltage range RSELx = 14 2.2 3.6 V
RSELx = 15 3.0 3.6
fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 2.2 V, 3 V 0.06 0.14 MHz
fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V 12.0 18.5 MHz
fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V 16.0 26.0 MHz
Frequency step between
SRSEL SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO) 2.2 V, 3 V 1.55 ratio
range RSEL and RSEL+1
Frequency step between tap
SDCO SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO) 2.2 V, 3 V 1.05 1.08 1.12 ratio
DCO and DCO+1
Duty cycle Measured at P1.4/SMCLK 2.2 V, 3 V 40 50 60 %

MSP430F2272-Q1, MSP430F2252-Q1
8.16 Calibrated DCO Frequencies - Tolerance at Calibration

Frequency tolerance at calibration 25°C 3V -1 ±0.2 +1 %
BCSCTL1 = CALBC1_1MHZ,
fCAL(1MHz) 1-MHz calibration value DCOCTL = CALDCO_1MHZ, 25°C 3V 0.990 1 1.010 MHz
Gating time: 5 ms
Gating time: 5 ms
Gating time: 5 ms
Gating time: 2 ms
8.17 Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C

1-MHz tolerance over
0°C to 85°C 3V -2.5 ±0.5 +2.5 %
temperature
0°C to 85°C 3V -2.5 ±1.0 +2.5 %
temperature
0°C to 85°C 3V -2.5 ±1.0 +2.5 %
temperature
0°C to 85°C 3V -3 ±2.0 +3 %
temperature
2.2 V 0.97 1 1.03
fCAL(1MHz) 1-MHz calibration value DCOCTL = CALDCO_1MHZ, 0°C to 85°C 3V 0.975 1 1.025 MHz
Gating time: 5 ms
3.6 V 0.97 1 1.03
2.2 V 7.76 8 8.4
Gating time: 5 ms
3.6 V 7.6 8 8.24
2.2 V 11.7 12 12.3
Gating time: 5 ms
3.6 V 11.7 12 12.3
BCSCTL1 = CALBC1_16MHZ, 3V 15.52 16 16.48
fCAL(16MHz) 16-MHz calibration value DCOCTL = CALDCO_16MHZ, 0°C to 85°C MHz
Gating time: 2 ms 3.6 V 15 16 16.48

MSP430F2272-Q1, MSP430F2252-Q1
8.18 Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC

1-MHz tolerance over VCC 25°C 1.8 V to 3.6 V -3 ±2 +3 %
16-MHz tolerance over VCC 25°C 3 V to 3.6 V -6 ±2 +3 %
fCAL(1MHz) 1-MHz calibration value DCOCTL = CALDCO_1MHZ, 25°C 1.8 V to 3.6 V 0.97 1 1.03 MHz
Gating time: 5 ms
Gating time: 5 ms
Gating time: 5 ms
fCAL(16MHz) 16-MHz calibration value DCOCTL = CALDCO_16MHZ, 25°C 3 V to 3.6 V 15 16 16.48 MHz
Gating time: 2 ms
8.19 Calibrated DCO Frequencies - Overall Tolerance

1-MHz tolerance
-40°C to 105°C 1.8 V to 3.6 V -5 ±2 +5 %
overall
8-MHz tolerance
-40°C to 105°C 1.8 V to 3.6 V -5 ±2 +5 %
overall
12-MHz
-40°C to 105°C 2.2 V to 3.6 V -5 ±2 +5 %
tolerance overall
16-MHz
-40°C to 105°C 3 V to 3.6 V -6 ±3 +6 %
tolerance overall
1-MHz
fCAL(1MHz) DCOCTL = CALDCO_1MHZ, -40°C to 105°C 1.8 V to 3.6 V 0.95 1 1.05 MHz
calibration value
Gating time: 5 ms
8-MHz
calibration value
Gating time: 5 ms
12-MHz
calibration value
Gating time: 5 ms
16-MHz
fCAL(16MHz) DCOCTL = CALDCO_16MHZ, -40°C to 105°C 3 V to 3.6 V 15 16 17 MHz
calibration value
Gating time: 2 ms

MSP430F2272-Q1, MSP430F2252-Q1
8.20 Typical Characteristics - Calibrated 1-MHz DCO Frequency
1.03 1.03
1.02 1.02
VCC = 1.8 V
1.01 1.01 TA = 105 °C
Frequency − MHz
Frequency − MHz
VCC = 2.2 V TA = 85 °C
1.00 1.00
VCC = 3.0 V
TA = 25 °C
0.99 0.99
VCC = 3.6 V TA = −40 °C

0.98 0.98
0.97 0.97
−50.0 −25.0 0.0 25.0 50.0 75.0 100.0 1.5 2.0 2.5 3.0 3.5 4.0
TA − Temperature − °C VCC − Supply Voltage − V
Figure 12. Calibrated 1-MHz Frequency vs Temperature Figure 13. Calibrated 1-MHz Frequency vs Supply Voltage

MSP430F2272-Q1, MSP430F2252-Q1
8.21 Wakeup From Lower-Power Modes (LPM3/4)

2
DCOCTL = CALDCO_1MHZ
2.2 V, 3 V 1.5
DCO clock wake-up time DCOCTL = CALDCO_8MHZ
tDCO,LPM3/4 µs
from LPM3/4 (1) BCSCTL1 = CALBC1_12MHZ,
1
3V 1
CPU wake-up time from 1 / fMCLK +
tCPU,LPM3/4
LPM3/4 (2) tClock,LPM3/4
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
8.22 Typical Characteristics - DCO Clock Wakeup Time From LPM3, LPM4
10.00
DCO Wake-Up Time − µs
RSELx = 0...11
1.00 RSELx = 12...15
0.10
0.10 1.00 10.00
DCO Frequency − MHz
Figure 14. Clock Wakeup Time From LPM3 vs DCO Frequency

MSP430F2272-Q1, MSP430F2252-Q1
8.23 DCO With External Resistor ROSC (1)

DCOR = 1, 2.2 V 1.8
fDCO,ROSC DCO output frequency with ROSC RSELx = 4, DCOx = 3, MODx = 0, MHz
TA = 25°C 3V 1.95
DCOR = 1,
DT Temperature drift 2.2 V, 3 V ±0.1 %/°C
RSELx = 4, DCOx = 3, MODx = 0
DCOR = 1,
DV Drift with VCC 2.2 V, 3 V 10 %/V
RSELx = 4, DCOx = 3, MODx = 0
(1) ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = ±50 ppm/°C.
8.24 Typical Characteristics - DCO With External Resistor ROSC
10.00 10.00

1.00 1.00
0.10 0.10
RSELx = 4 RSELx = 4
0.01 0.01
10.00 100.00 1000.00 10000.00 10.00 100.00 1000.00 10000.00
ROSC − External Resistor − kW ROSC − External Resistor − kW
VCC = 2.2 V TA = 25°C VCC = 3 V TA = 25°C
Figure 15. DCO Frequency vs ROSC Figure 16. DCO Frequency vs ROSC
2.50 2.50
2.25 2.25
ROSC = 100k ROSC = 100k
2.00 2.00
1.75 1.75
1.50 1.50
1.25 1.25
1.00 1.00
ROSC = 270k ROSC = 270k
0.75 0.75
0.50 0.50
ROSC = 1M ROSC = 1M
0.25 0.25
0.00 0.00
−50.0 −25.0 0.0 25.0 50.0 75.0 100.0 2.0 2.5 3.0 3.5 4.0
TA − Temperature − C VCC − Supply Voltage − V
Figure 17. DCO Frequency vs Temperature TA = 25°C
Figure 18. DCO Frequency vs Supply Voltage

MSP430F2272-Q1, MSP430F2252-Q1
8.25 Crystal Oscillator LFXT1, Low-Frequency Mode (1)

LFXT1 oscillator crystal
fLFXT1,LF XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32768 Hz
frequency, LF mode 0, 1
LFXT1 oscillator logic level
fLFXT1,LF,logic square wave input frequency, XTS = 0, LFXT1Sx = 3 1.8 V to 3.6 V 10000 32768 50000 Hz
LF mode
XTS = 0, LFXT1Sx = 0,
500
Oscillation allowance for fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
OALF kΩ
LF crystals XTS = 0, LFXT1Sx = 0,
200
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0 1
Integrated effective load XTS = 0, XCAPx = 1 5.5
CL,eff pF
capacitance, LF mode (2) XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 11
XTS = 0, Measured at P2.0/ACLK,
Duty cycle, LF mode 2.2 V, 3 V 30 50 70 %
fLFXT1,LF = 32768 Hz
Oscillator fault frequency,
fFault,LF XTS = 0, LFXT1Sx = 3 (4) 2.2 V, 3 V 10 10000 Hz
LF mode (3)
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and techniques that avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the crystal that is used.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4) Measured with logic-level input frequency but also applies to operation with crystals.
8.26 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

PARAMETER TA VCC MIN TYP MAX UNIT
-40°C to 85°C 4 12 20
fVLO VLO frequency 2.2 V, 3 V kHz
105°C 22
(1)
dfVLO/dT VLO frequency temperature drift -40°C to 105°C 2.2 V, 3 V 0.5 %/°C
(2)
dfVLO/dVCC VLO frequency supply voltage drift 25°C 1.8 V to 3.6 V 4 %/V
(1) Calculated using the box method:

I version: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]
T version: [MAX(-40...105°C) - MIN(-40...105°C)]/MIN(-40...105°C)/[105°C - (-40°C)]
(2) Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)

MSP430F2272-Q1, MSP430F2252-Q1
8.27 Crystal Oscillator LFXT1, High-Frequency Mode (1)

fLFXT1,HF0 XTS = 1, LFXT1Sx = 0 1.8 V to 3.6 V 0.4 1 MHz
frequency, HF mode 0
fLFXT1,HF1 XTS = 1, LFXT1Sx = 1 1.8 V to 3.6 V 1 4 MHz
1.8 V to 3.6 V 2 10
fLFXT1,HF2 XTS = 1, LFXT1Sx = 2 2.2 V to 3.6 V 2 12 MHz
3 V to 3.6 V 2 16
1.8 V to 3.6 V 0.4 10
LFXT1 oscillator logic-level
fLFXT1,HF,logic square-wave input frequency, HF XTS = 1, LFXT1Sx = 3 2.2 V to 3.6 V 0.4 12 MHz
mode
3 V to 3.6 V 0.4 16
fLFXT1,HF = 1 MHz, 2700
CL,eff = 15 pF
Oscillation allowance for HF XTS = 1, LFXT1Sx = 1,
OAHF crystals (see Figure 19 and fLFXT1,HF = 4 MHz, 800 Ω
Figure 20) CL,eff = 15 pF
fLFXT1,HF = 16 MHz, 300
CL,eff = 15 pF
Integrated effective load
CL,eff XTS = 1 (3) 1 pF
capacitance, HF mode (2)
XTS = 1,
Measured at P2.0/ACLK, 40 50 60
fLFXT1,HF = 10 MHz
Duty cycle, HF mode 2.2 V, 3 V %
XTS = 1,
Measured at P2.0/ACLK, 40 50 60
fLFXT1,HF = 16 MHz
fFault,HF Oscillator fault frequency (4) XTS = 1, LFXT1Sx = 3 (5) 2.2 V, 3 V 30 300 kHz
(1) To improve EMI on the XT1 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and techniques that avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
(3) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
(5) Measured with logic-level input frequency, but also applies to operation with crystals.

MSP430F2272-Q1, MSP430F2252-Q1
8.28 Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
100000.00 800.0
LFXT1Sx = 3
700.0
XT Oscillator Supply Current − uA

Oscillation Allowance − Ohms
10000.00 600.0
500.0
1000.00 400.0
LFXT1Sx = 3 300.0
100.00 LFXT1Sx = 2
200.0
LFXT1Sx = 1 LFXT1Sx = 2
100.0
LFXT1Sx = 1
10.00 0.0
0.10 1.00 10.00 100.00 0.0 4.0 8.0 12.0 16.0 20.0
Crystal Frequency − MHz Crystal Frequency − MHz
CL,eff = 15 pF TA = 25°C CL,eff = 15 pF TA = 25°C
Figure 19. Oscillation Allowance vs Crystal Frequency Figure 20. Oscillator Supply Current vs Crystal Frequency
8.29 Timer_A
Internal: SMCLK, ACLK 2.2 V 10
fTA Timer_A clock frequency External: TACLK, INCLK MHz
Duty cycle = 50% ± 10% 3V 16
tTA,cap Timer_A capture timing TA0, TA1, TA2 2.2 V, 3 V 20 ns
8.30 Timer_B
Internal: SMCLK, ACLK 2.2 V 10
fTB Timer_B clock frequency External: TACLK, INCLK MHz
Duty cycle = 50% ± 10% 3V 16
tTB,cap Timer_B capture timing TB0, TB1, TB2 2.2 V, 3 V 20 ns

MSP430F2272-Q1, MSP430F2252-Q1
8.31 USCI (UART Mode)

PARAMETER CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
fBITCLK 2.2 V, 3 V 1 MHz
(equals baud rate in MBaud)
2.2 V 50 150 600
tτ UART receive deglitch time (1) ns
3V 50 100 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
8.32 USCI (SPI Master Mode) (1)

(see Figure 21 and Figure 22)
SMCLK, ACLK
fUSCI USCI input clock frequency fSYSTEM MHz
2.2 V 110
tSU,MI SOMI input data setup time ns
3V 75
2.2 V 0
tHD,MI SOMI input data hold time ns
3V 0
UCLK edge to SIMO valid, 2.2 V 30
tVALID,MO SIMO output data valid time ns
CL = 20 pF 3V 20
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).

For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
8.33 USCI (SPI Slave Mode) (1)

(see Figure 23 and Figure 24)
tSTE,LEAD STE lead time, STE low to clock 2.2 V, 3 V 50 ns
tSTE,LAG STE lag time, Last clock to STE high 2.2 V, 3 V 10 ns
tSTE,ACC STE access time, STE low to SOMI data out 2.2 V, 3 V 50 ns
STE disable time, STE high to SOMI high
tSTE,DIS 2.2 V, 3 V 50 ns
impedance
2.2 V 20
tSU,SI SIMO input data setup time ns
3V 15
2.2 V 10
tHD,SI SIMO input data hold time ns
3V 10
UCLK edge to SOMI valid, 2.2 V 75 110
tVALID,SO SOMI output data valid time ns
CL = 20 pF 3V 50 75
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).

For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.

MSP430F2272-Q1, MSP430F2252-Q1
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI tLO/HI tSU,MI

tHD,MI
SOMI
tVALID,MO
SIMO
Figure 21. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI tLO/HI
tHD,MI
tSU,MI
SOMI
tVALID,MO
SIMO
Figure 22. SPI Master Mode, CKPH = 1

MSP430F2272-Q1, MSP430F2252-Q1
tSTE,LEAD tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI tLO/HI tSU,SI

tHD,SI
SIMO
tSTE,ACC tVALID,SO tSTE,DIS
SOMI
Figure 23. SPI Slave Mode, CKPH = 0
tSTE,LEAD tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC tVALID,SO tSTE,DIS
SOMI
Figure 24. SPI Slave Mode, CKPH = 1

MSP430F2272-Q1, MSP430F2252-Q1
8.34 USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 25)
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz
fSCL SCL clock frequency 2.2 V, 3 V 0 400 kHz
fSCL ≤ 100 kHz 4
tHD,STA Hold time (repeated) START 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
fSCL ≤ 100 kHz 4.7
tSU,STA Setup time for a repeated START 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
tHD,DAT Data hold time 2.2 V, 3 V 0 ns
tSU,DAT Data setup time 2.2 V, 3 V 250 ns
tSU,STO Setup time for STOP 2.2 V, 3 V 4 µs
2.2 V 50 150 600
tSP Pulse width of spikes suppressed by input filter ns
3V 50 100 600
tHD,STA tSU,STA tHD,STA
SDA
1/fSCL tSP
SCL
tSU,DAT tSU,STO
tHD,DAT
Figure 25. I2C Mode Timing

MSP430F2272-Q1, MSP430F2252-Q1
8.35 10-Bit ADC, Power Supply and Input Range Conditions (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
Analog supply voltage
VCC VSS = 0 V 2.2 3.6 V
range
All Ax terminals,
Analog input voltage
VAx Analog inputs selected in 0 VCC V
range (2)
ADC10AE register
fADC10CLK = 5 MHz, 2.2 V 0.52 1.05
ADC10ON = 1, REFON = 0,
IADC10 ADC10 supply current (3) ADC10SHT0 = 1, -40°C to 105°C mA
ADC10SHT1 = 0, 3V 0.6 1.2
ADC10DIV = 0
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 0, 2.2 V, 3 V 0.25 0.4
Reference supply REFON = 1, REFOUT = 0
IREF+ current, reference buffer -40°C to 105°C mA
disabled (4) fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 1, 3V 0.25 0.4
REFON = 1, REFOUT = 0
fADC10CLK = 5 MHz -40°C to 85°C 2.2 V, 3 V 1.1 1.4
Reference buffer supply
IREFB,0 current with mA
REF2_5V = 0, REFOUT = 1, 105°C 2.2 V, 3 V 1.8
ADC10SR = 0 (4)
ADC10SR = 0
fADC10CLK = 5 MHz, -40°C to 85°C 2.2 V, 3 V 0.5 0.7
Reference buffer supply
IREFB,1 current with mA
REF2_5V = 0, REFOUT = 1, 105°C 2.2 V, 3 V 0.8
ADC10SR = 1 (4)
ADC10SR = 1
Only one terminal Ax selected at
CI Input capacitance -40°C to 105°C 27 pF
a time
Input MUX ON
RI 0 V ≤ VAx ≤ VCC -40°C to 105°C 2.2 V, 3 V 2000 Ω
resistance
(1) The leakage current is defined in the leakage current table with Px.y/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC10.
(4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

MSP430F2272-Q1, MSP430F2252-Q1
8.36 10-Bit ADC, Built-In Voltage Reference

IVREF+ ≤ 1 mA, REF2_5V = 0 2.2
Positive built-in
VCC,REF+ reference analog IVREF+ ≤ 0.5 mA, REF2_5V = 1 2.8 V
supply voltage range
IVREF+ ≤ 1 mA, REF2_5V = 1 2.9
Positive built-in IVREF+ ≤ IVREF+max, REF2_5V = 0 2.2 V, 3 V 1.41 1.5 1.59
VREF+ V
reference voltage IVREF+ ≤ IVREF+max, REF2_5V = 1 3V 2.35 2.5 2.65
Maximum VREF+ 2.2 V ±0.5
ILD,VREF+ mA
load current 3V ±1
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 0.75 V, 2.2 V, 3 V ±2
VREF+ load REF2_5V = 0
LSB
regulation IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V, 3V ±2
REF2_5V = 1
IVREF+ = 100 µA to 900 µA, ADC10SR = 0 400
VREF+ load
VAx ≈ 0.5 x VREF+,
regulation response 3V ns
Error of conversion result ADC10SR = 1 2000
time
≤1 LSB
Maximum
IVREF+ ≤ ±1 mA,
CVREF+ capacitance at pin 2.2 V, 3 V 100 pF
REFON = 1, REFOUT = 1
VREF+ (1)
Temperature IVREF+ = constant with
TCREF+ 2.2 V, 3 V ±100 ppm/°C
coefficient (2) 0 mA ≤ IVREF+ ≤ 1 mA
Settling time of
IVREF+ = 0.5 mA, REF2_5V = 0,
tREFON internal reference 3.6 V 30 µs
REFON = 0 to 1
voltage (3)
IVREF+ = 0.5 mA, ADC10SR = 0 1
REF2_5V = 0,
2.2 V
REFON = 1, ADC10SR = 1 2.5
Settling time of REFBURST = 1
tREFBURST µs
reference buffer (3) IVREF+ = 0.5 mA, ADC10SR = 0 2
REF2_5V = 1,
3V
REFON = 1, ADC10SR = 1 4.5
REFBURST = 1
(1) The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA 2/A4/VREF+/ VeREF+ (REFOUT = 1),
must be limited; the reference buffer may become unstable otherwise.
(2) Calculated using the box method:
I temperature: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
T temperature: (MAX(-40 to 105°C) – MIN(-40 to 105°C)) / MIN(-40 to 105°C) / (105°C – (–40°C))
(3) The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.

MSP430F2272-Q1, MSP430F2252-Q1
8.37 10-Bit ADC, External Reference (1)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VeREF+ > VeREF-,
1.4 VCC
Positive external reference input SREF1 = 1, SREF0 = 0
VeREF+ V
voltage range (2) VeREF- ≤ VeREF+ ≤ VCC - 0.15 V,
1.4 3
SREF1 = 1, SREF0 = 1 (3)
Negative external reference input
VeREF- VeREF+ > VeREF- 0 1.2 V
voltage range (4)
Differential external reference
ΔVeREF input voltage range VeREF+ > VeREF- (5) 1.4 VCC V
ΔVeREF = VeREF+ - VeREF-
0 V ≤ VeREF+ ≤ VCC,
±1
SREF1 = 1, SREF0 = 0
IVeREF+ Static input current into VeREF+ 2.2 V, 3 V µA
0 V ≤ VeREF+ ≤ VCC - 0.15 V ≤ 3 V,
0
SREF1 = 1, SREF0 = 1 (3)
IVeREF- Static input current into VeREF- 0 V ≤ VeREF- ≤ VCC 2.2 V, 3 V ±1 µA
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
8.38 10-Bit ADC, Timing Parameters

ADC10 input clock For specified performance of ADC10SR = 0 0.45 6.3
fADC10CLK 2.2 V, 3 V MHz
frequency ADC10 linearity parameters ADC10SR = 1 0.45 1.5
ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0,
fADC10OSC 2.2 V, 3 V 3.7 6.3 MHz
frequency fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
2.2 V, 3 V 2.06 3.51
fADC10CLK = fADC10OSC
tCONVERT Conversion time µs
fADC10CLK from ACLK, MCLK or SMCLK, 13 × ADC10DIVx ×
ADC10SSELx ≠ 0 1 / fADC10CLK
Turn on settling time of
tADC10ON 100 ns
the ADC (1)
(1) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.

MSP430F2272-Q1, MSP430F2252-Q1
8.39 10-Bit ADC, Linearity Parameters

EI Integral linearity error 2.2 V, 3 V ±1 LSB
ED Differential linearity error 2.2 V, 3 V ±1 LSB
EO Offset error Source impedance RS < 100 Ω 2.2 V, 3 V ±1 LSB
SREFx = 010, unbuffered external reference,
2.2 V ±1.1 ±2
VeREF+ = 1.5 V
3V ±1.1 ±2
VeREF+ = 2.5 V
EG Gain error LSB
SREFx = 011, buffered external reference (1),
2.2 V ±1.1 ±4
VeREF+ = 1.5 V
3V ±1.1 ±3
VeREF+ = 2.5 V
2.2 V ±2 ±5
VeREF+ = 1.5 V
3V ±2 ±5
VeREF+ = 2.5 V
ET Total unadjusted error LSB
2.2 V ±2 ±7
VeREF+ = 1.5 V
3V ±2 ±6
VeREF+ = 2.5 V
(1) The reference buffer offset adds to the gain and total unadjusted error.
(1)
8.40 10-Bit ADC, Temperature Sensor and Built-In VMID
Temperature sensor supply REFON = 0, INCHx = 0Ah, 2.2 V 40 120
ISENSOR µA
current (1) TA = 25°C 3V 60 160
TCSENSOR ADC10ON = 1, INCHx = 0Ah (2) 2.2 V, 3 V 3.44 3.55 3.66 mV/°C
(2)
VOffset,Sensor Sensor offset voltage ADC10ON = 1, INCHx = 0Ah -100 100 mV
Temperature sensor voltage at
1265 1365 1465
TA = 105°C (T version only)
VSENSOR Sensor output voltage (3) Temperature sensor voltage at TA = 85°C 2.2 V, 3 V 1195 1295 1395 mV
Temperature sensor voltage at TA = 25°C 985 1085 1185
Temperature sensor voltage at TA = 0°C 895 995 1095
Sample time required if ADC10ON = 1, INCHx = 0Ah,
tSENSOR(sample) 2.2 V, 3 V 30 µs
channel 10 is selected (4) Error of conversion result ≤ 1 LSB
Current into divider at 2.2 V N/A
IVMID ADC10ON = 1, INCHx = 0Bh µA
channel 11 (4) 3V N/A
ADC10ON = 1, INCHx = 0Bh, 2.2 V 1.06 1.1 1.14
VMID VCC divider at channel 11 V
VMID ≈ 0.5 × VCC 3V 1.46 1.5 1.54
Sample time required if ADC10ON = 1, INCHx = 0Bh, 2.2 V 1400
tVMID(sample) ns
channel 11 is selected (5) Error of conversion result ≤ 1 LSB 3V 1220
(1) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high).When REFON = 1, ISENSOR is included in IREF+.When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
(2) The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
(3) Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
(4) No additional current is needed. The VMID is used during sampling.
(5) The on time, tVMID(on), is included in the sampling time, tVMID(sample); no additional on time is needed.

MSP430F2272-Q1, MSP430F2252-Q1
8.41 Flash Memory

VCC
Program and erase supply voltage 2.2 3.6 V
(PGM/ERASE)
fFTG Flash timing generator frequency 257 476 kHz
IPGM Supply current from VCC during program 2.2 V, 3.6 V 1 5 mA
IERASE Supply current from VCC during erase 2.2 V, 3.6 V 1 7 mA
tCPT Cumulative program time (1) 2.2 V, 3.6 V 10 ms
tCMErase Cumulative mass erase time 2.2 V, 3.6 V 20 ms
4 5
Program and erase endurance 10 10 cycles
tRetention Data retention duration TJ = 25°C 15 years
(2)
tWord Word or byte program time 30 tFTG
(2)
tBlock, 0 Block program time for first byte or word 25 tFTG
Block program time for each additional byte (2)
tBlock, 1-63 18 tFTG
or word
(2)
tBlock, End Block program end-sequence wait time 6 tFTG
(2)
tMass Erase Mass erase time 10593 tFTG
(2)
tSeg Erase Segment erase time 4819 tFTG
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).
8.42 RAM
PARAMETER TEST CONDITIONS MIN MAX UNIT
(1)
V(RAMh) RAM retention supply voltage CPU halted 1.6 V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.

MSP430F2272-Q1, MSP430F2252-Q1
8.43 JTAG and Spy-Bi-Wire Interface

fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 µs
Spy-Bi-Wire enable time
tSBW,En 2.2 V, 3 V 1 µs
(TEST high to acceptance of first clock edge (1))
tSBW,Ret Spy-Bi-Wire return to normal operation time 2.2 V, 3 V 15 100 µs
2.2 V 0 5 MHz
fTCK TCK input frequency (2)
3V 0 10 MHz
RInternal Internal pulldown resistance on TEST 2.2 V, 3 V 25 60 90 kΩ
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
8.44 JTAG Fuse (1)

PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V
VFB Voltage level on TEST for fuse blow 6 7 V
IFB Supply current into TEST during fuse blow 100 mA
tFB Time to blow fuse 1 ms
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.

MSP430F2272-Q1, MSP430F2252-Q1
9 I/O Port Schematics
9.1 Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
DVSS 0
DVCC 1 1
P1DIR.x 0 Direction
1 0: Input
1: Output
P1OUT.x 0
Module X OUT 1 P1.0/TACLK/ADC10CLK
P1.1/TA0
P1SEL.x P1.2/TA1
P1.3/TA2
P1IN.x
EN
Module X IN D
P1IE.x EN
P1IRQ.x
Q
Set
P1IFG.x
P1SEL.x Interrupt
Edge
P1IES.x Select
Table 16. Port P1 (P1.0 to P1.3) Pin Functions

CONTROL BITS OR SIGNALS
PIN NAME (P1.x) x FUNCTION
P1DIR.x P1SEL.x
P1.0 (1) I: 0; O: 1 0
P1.0/TACLK/ADC10CLK 0 Timer_A3.TACLK 0 1
ADC10CLK 1 1
P1.1 (1) (I/O) I: 0; O: 1 0
P1.1/TA0 1 Timer_A3.CCI0A 0 1
Timer_A3.TA0 1 1
P1.2 (1) (I/O) I: 0; O: 1 0
Timer_A3.TA1 1 1
P1.3 (1) (I/O) I: 0; O: 1 0
Timer_A3.TA2 1 1
(1) Default after reset (PUC or POR)

MSP430F2272-Q1, MSP430F2252-Q1
9.2 Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System
Access Features
Pad Logic
P1REN.x
DVSS 0
DVCC 1 1
P1DIR.x 0 Direction
1 0: Input
1: Output
P1OUT.x 0
Module X OUT 1
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1SEL.x Bus
P1.6/TA1/TDI
Keeper
P1IN.x EN
EN
Module X IN D
P1IE.x EN
P1IRQ.x
Q
Set
P1IFG.x
P1SEL.x Interrupt
Edge
P1IES.x Select
To JTAG
From JTAG

CONTROL BITS OR SIGNALS (1)
P1DIR.x P1SEL.x 4-Wire JTAG
P1.4 (2) (I/O) I: 0; O: 1 0 0
P1.4/SMCLK/TCK 4 SMCLK 1 1 0
TCK X X 1
P1.5 (2) (I/O) I: 0; O: 1 0 0
P1.5/TA0/TMS 5 Timer_A3.TA0 1 1 0
TMS X X 1
P1.6 (2) (I/O) I: 0; O: 1 0 0
P1.6/TA1/TDI/TCLK 6 Timer_A3.TA1 1 1 0
TDI/TCLK (3) X X 1
(1) X = Don't care

(3) Function controlled by JTAG

MSP430F2272-Q1, MSP430F2252-Q1
9.3 Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access
Features
Pad Logic
P1REN.7
DVSS 0
DVCC 1 1
P1DIR.7 0 Direction
1 0: Input
1: Output
P1OUT.7 0
Module X OUT 1
P1.7/TA2/TDO/TDI
P1SEL.7 Bus
Keeper
P1IN.7 EN
EN
Module X IN D
P1IE.7 EN
P1IRQ.7
Q
Set
P1IFG.7
P1SEL.7 Interrupt
Edge
P1IES.7 Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
Table 18. Port P1 (P1.7) Pin Functions

P1DIR.x P1SEL.x 4-Wire JTAG
(2)
P1.7 (I/O) I: 0; O: 1 0 0
P1.7/TA2/TDO/TDI 7 Timer_A3.TA2 1 1 0
TDO/TDI (3) X X 1
(1) X = Don't care

(3) Function controlled by JTAG

MSP430F2272-Q1, MSP430F2252-Q1
9.4 Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = y
ADC10AE0.y
P2REN.x
DVSS 0
DVCC 1 1
P2DIR.x 0 Direction
1 0: Input
1: Output
P2OUT.x 0
Module X OUT 1 P2.0/ACLK/A0
P2.2/TA0/A2
P2SEL.x Bus
Keeper
P2IN.x EN
EN
Module X IN D
P2IE.x EN
P2IRQ.x
Q
Set
P2IFG.x
P2SEL.x Interrupt
Edge
P2IES.x Select
Table 19. Port P2 (P2.0, P2.2) Pin Functions

Pin Name (P2.x) x y FUNCTION
P2DIR.x P2SEL.x ADC10AE0.y
(2)
P2.0 (I/O) I: 0; O: 1 0 0
P2.0/ACLK/A0 0 0 ACLK 1 1 0
A0 (3) X X 1
(2)
P2.2 (I/O) I: 0; O: 1 0 0
Timer_A3.CCI0B 0 1 0
P2.2/TA0/A2 2 2
Timer_A3.TA0 1 1 0
(3)
A2 X X 1
(1) X = Don't care

(3) Setting the ADC10AE0.y bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.

MSP430F2272-Q1, MSP430F2252-Q1
9.5 Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = 1
ADC10AE0.1
P2REN.1
DVSS 0
DVCC 1 1
P2DIR.1 0 Direction
1 0: Input
1: Output
P2OUT.1 0
Module X OUT 1 P2.1/TAINCLK/
SMCLK/A1
P2SEL.1 Bus
Keeper
P2IN.1 EN
EN
Module X IN D
P2IE.1 EN
P2IRQ.1
Q
Set
P2IFG.1
P2SEL.1 Interrupt
Edge
P2IES.1 Select

PIN NAME (P2.x) x y FUNCTION
(2)
P2.1 (I/O) I: 0; O: 1 0 0
P2.1/TAINCLK/SMCLK/ Timer_A3.INCLK 0 1 0
1 1
A1 SMCLK 1 1 0
(3)
A1 X X 1
(1) X = Don't care

analog signals.

MSP430F2272-Q1, MSP430F2252-Q1

SREF2
0 VSS Pad Logic

To ADC 10 VR−
1
To ADC 10
INCHx = 3
ADC10AE0.3
P2REN.3
DVSS 0
DVCC 1 1
P2DIR.3 0 Direction
1 0: Input
1: Output
P2OUT.3 0
Module X OUT 1 P2.3/TA1/
A3/VREF−/VeREF−
P2SEL.3 Bus
Keeper
P2IN.3 EN
EN
Module X IN D
P2IE.3 EN
P2IRQ.3
Q
Set
P2IFG.3
P2SEL.3 Interrupt
Edge
P2IES.3 Select

P2.3 (2) (I/O) I: 0; O: 1 0 0
P2.3/TA1/A3/VREF- Timer_A3.CCI1B 0 1 0
3 3
/VeREF- Timer_A3.TA1 1 1 0
A3/VREF-/VeREF- (3) X X 1
(1) X = Don't care

analog signals.

MSP430F2272-Q1, MSP430F2252-Q1
Pad Logic
To /from ADC10
positive reference
To ADC 10
INCHx = 4
ADC10AE0.4
P2REN.4
DVSS 0
DVCC 1 1
P2DIR.4 0 Direction
1 0: Input
1: Output
P2OUT.4 0
Module X OUT 1 P2.4/TA2/A4/
VREF+/VeREF+
P2SEL.4 Bus
Keeper
P2IN.4 EN
EN
Module X IN D
P2IE.4 EN
P2IRQ.4
Q
Set
P2IFG.4
P2SEL.4 Interrupt
Edge
P2IES.4 Select

(2)
P2.4 (I/O) I: 0; O: 1 0 0
P2.4/TA2/A4/VREF+/
4 4 Timer_A3.TA2 1 1 0
VeREF+
A4/VREF+/VeREF+ (3) X X 1
(1) X = Don't care

analog signals.

MSP430F2272-Q1, MSP430F2252-Q1
9.8 Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
Pad Logic
To DCO
DCOR
P2REN.x
DVSS 0
DVCC 1 1
P2DIR.x 0 Direction
1 0: Input
1: Output
P2OUT.x 0
Module X OUT 1 P2.5/ROSC
P2SEL.x Bus
Keeper
P2IN.x EN
EN
Module X IN D
P2IE.x EN
P2IRQ.x
Q
Set
P2IFG.x
P2SEL.x Interrupt
Edge
P2IES.x Select

P2DIR.x P2SEL.x DCOR
P2.5 (2) (I/O) I: 0; O: 1 0 0
(3)
N/A 0 1 0
P2.5/ROSC 5
DVSS 1 1 0
ROSC X X 1
(1) X = Don't care

(3) N/A = Not available or not applicable

MSP430F2272-Q1, MSP430F2252-Q1
9.9 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator
Input
BCSCTL3.LFXT1Sx = 11 LFXT1 Oscillator
P2.7/XOUT
LFXT1 off
0
LFXT1CLK
1
P2SEL.7 Pad Logic
P2REN.6
DVSS 0
DVCC 1 1
P2DIR.6 0 Direction
1 0: Input
1: Output
P2OUT.6 0
Module X OUT 1 P2.6/XIN
P2SEL.6 Bus
Keeper
EN
P2IN.6
EN
Module X IN D
P2IE.6 EN
P2IRQ.6
Q
Set
P2IFG.6
P2SEL.6 Interrupt
Edge
P2IES.6 Select

P2DIR.x P2SEL.x
P2.6 (I/O) I: 0; O: 1 0
P2.6/XIN 6 (2)
XIN X 1
(1) X = Don't care


MSP430F2272-Q1, MSP430F2252-Q1
9.10 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator
Output
BCSCTL3.LFXT1Sx = 11 LFXT1 Oscillator
LFXT1 off
0
LFXT1CLK From P2.6/XIN P2.6/XIN
1
P2SEL.6 Pad Logic
P2REN.7
DVSS 0
DVCC 1 1
P2DIR.7 0 Direction
1 0: Input
1: Output
P2OUT.7 0
Module X OUT 1 P2.7/XOUT
P2SEL.7 Bus
Keeper
EN
P2IN.7
EN
Module X IN D
P2IE.7 EN
P2IRQ.7
Q
Set
P2IFG.7
P2SEL.7 Interrupt
Edge
P2IES.7 Select

P2DIR.x P2SEL.x
P2.7 (I/O) I: 0; O: 1 0
XOUT/P2.7 7 (2) (3)
XOUT X 1
(1) X = Don't care

(3) If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this
pin after reset.

MSP430F2272-Q1, MSP430F2252-Q1
Pad Logic
To ADC 10
INCHx = 5
ADC10AE0.5
P3REN.0
DVSS 0
DVCC 1 1
P3DIR.0 0 Direction
USCI Direction 1 0: Input
Control 1: Output
P3OUT.0 0
Module X OUT 1
P3.0/UCB0STE/UCA0CLK/A5
P3SEL.0 Bus
Keeper
P3IN.0 EN
EN
Module X IN D

P3.0 (2) (I/O) I: 0; O: 1 0 0
P3.0/UCB0STE/
0 5 UCB0STE/UCA0CLK (3) (4)
X 1 0
UCA0CLK/A5
(5)
A5 X X 1
(1) X = Don't care

(3) The pin direction is controlled by the USCI module.
(4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
analog signals.

MSP430F2272-Q1, MSP430F2252-Q1
DVSS Pad Logic
P3REN.x
DVSS 0
DVCC 1 1
P3DIR.x 0 Direction
USCI Direction 1 0: Input
Control 1: Output
P3OUT.x 0
Module X OUT 1
P3.1/UCB0SIMO/UCB0SDA
Bus P3.2/UCB0SOMI/UCB0SCL
P3SEL.x
Keeper P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3IN.x EN P3.5/UCA0RXD/UCA0SOMI
EN
Module X IN D

P3DIR.x P3SEL.x
(2)
P3.1 (I/O) I: 0; O: 1 0
P3.1/UCB0SIMO/UCB0SDA 1
UCB0SIMO/UCB0SDA (3) X 1
P3.2 (2) (I/O) I: 0; O: 1 0
P3.2/UCB0SOMI/UCB0SCL 2 (3)
UCB0SOMI/UCB0SCL X 1
P3.3 (2) (I/O) I: 0; O: 1 0
P3.3/UCB0CLK/UCA0STE 3
UCB0CLK/UCA0STE (3) (4)
X 1
(2)
P3.4 (I/O) I: 0; O: 1 0
P3.4/UCA0TXD/UCA0SIMO 4
UCA0TXD/UCA0SIMO (3) X 1
P3.5 (2) (I/O) I: 0; O: 1 0
P3.5/UCA0RXD/UCA0SOMI 5
UCA0RXD/UCA0SOMI (3) X 1
(1) X = Don't care

(3) The pin direction is controlled by the USCI module.
(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode even if 4-wire SPI mode is selected.

MSP430F2272-Q1, MSP430F2252-Q1
Pad Logic
To ADC 10
INCHx = y
ADC10AE0.y
P3REN.x
DVSS 0
DVCC 1 1
P3DIR.x 0 Direction
DVSS 1 0: Input
1: Output
P3OUT.x 0
Module X OUT 1 P3.6/A6
P3.7/A7
P3SEL.x Bus
Keeper
P3IN.x EN
EN
Module X IN D
Table 28. Port P3 (P3.6, P3.7) Pin Functions

P3.6 (2) (I/O) I: 0; O: 1 0 0
P3.6/A6 6 6 (3)
A6 X X 1
P3.7 (2) (I/O) I: 0; O: 1 0 0
P3.7/A7 7 7
A7 (3) X X 1
(1) X = Don't care

analog signals.

MSP430F2272-Q1, MSP430F2252-Q1
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15
P4SEL.6 Pad Logic
P4DIR.6
ADC10AE1.7
P4REN.x
DVSS 0
DVCC 1 1
P4DIR.x 0 Direction
1 0: Input
1: Output
P4OUT.x 0
Module X OUT 1
P4.0/TB0
P4.1/TB1
P4SEL.x Bus
P4.2/TB2
Keeper
P4IN.x EN
EN
Module X IN D

P4DIR.x P4SEL.x
P4.0 (1) (I/O) I: 0; O: 1 0
P4.0/TB0 0 Timer_B3.CCI0A 0 1
Timer_B3.TB0 1 1
P4.1 (1) (I/O) I: 0; O: 1 0
Timer_B3.TB1 1 1
P4.2 (1) (I/O) I: 0; O: 1 0
Timer_B3.TB2 1 1

MSP430F2272-Q1, MSP430F2252-Q1
P4.6/TBOUTH/A15
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC 10
INCHx = 8+y
ADC10AE1.y
P4REN.x
DVSS 0
DVCC 1 1
P4DIR.x 0 Direction
1 0: Input
1: Output
P4OUT.x 0
Module X OUT 1 P4.3/TB0/A12
P4.4/TB1/A13
P4SEL.x Bus
Keeper
P4IN.x EN
EN
Module X IN D

MSP430F2272-Q1, MSP430F2252-Q1
Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger (continued)
P4.3 (2) (I/O) I: 0; O: 1 0 0
Timer_B3.CCI0B 0 1 0
P4.3/TB0/A12 3 4
Timer_B3.TB0 1 1 0
A12 (3) X X 1
P4.4 (2) (I/O) I: 0; O: 1 0 0
Timer_B3.CCI1B 0 1 0
P4.4/TB1/A13 4 5
Timer_B3.TB1 1 1 0
A13 (3) X X 1
(1) X = Don't care

analog signals.

MSP430F2272-Q1, MSP430F2252-Q1

P4.6/TBOUTH/A15
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC 10
INCHx = 14
ADC10AE1.6
P4REN.5
DVSS 0
DVCC 1 1
P4DIR.5 0 Direction
1 0: Input
1: Output
P4OUT.5 0
Module X OUT 1 P4.5/TB3/A14
P4SEL.5 Bus
Keeper
P4IN.5 EN
EN
Module X IN D

P4.5 (2) (I/O) I: 0; O: 1 0 0
P4.5/TB3/A14 5 6 Timer_B3.TB2 1 1 0
A14 (3) X X 1
(1) X = Don't care

analog signals.

MSP430F2272-Q1, MSP430F2252-Q1
Pad Logic
To ADC 10
INCHx = 15
ADC10AE1.7
P4REN.6
DVSS 0
DVCC 1 1
P4DIR.6 0 Direction
1 0: Input
1: Output
P4OUT.6 0
Module X OUT 1
P4.6/TBOUTH/A15
P4SEL.6 Bus
Keeper
P4IN.6 EN
EN
Module X IN D

P4.6 (2) (I/O) I: 0; O: 1 0 0
TBOUTH 0 1 0
P4.6/TBOUTH/A15 6 7
DVSS 1 1 0
A15 (3) X X 1
(1) X = Don't care

analog signals.

MSP430F2272-Q1, MSP430F2252-Q1
DVSS Pad Logic
P4REN.x
DVSS 0
DVCC 1 1
P4DIR.x 0 Direction
1 0: Input
1: Output
P4OUT.x 0
Module X OUT 1 P4.7/TBCLK
P4SEL.x Bus
Keeper
P4IN.x EN
EN
Module X IN D
Table 33. Port P4 (Pr.7) Pin Functions

P4DIR.x P4SEL.x
(1)
P4.7 (I/O) I: 0; O: 1 0
P4.7/TBCLK 7 Timer_B3.TBCLK 0 1
DVSS 1 1

MSP430F2272-Q1, MSP430F2252-Q1
9.19 JTAG Fuse Check Mode

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is
being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 26). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITF
ITEST
Figure 26. Fuse Check Mode Current
NOTE
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit
bootloader access key is used. Also, see the Bootstrap Loader section for more
information.

MSP430F2272-Q1, MSP430F2252-Q1
10 Device and Documentation Support
10.1 Device Support

10.1.1 Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430™ MCU devices and support tools. Each MSP430™ MCU commercial family member has one of three
prefixes: MSP, PMS, or XMS (for example, MSP430F5259). Texas Instruments recommends two of three
possible prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
PMS – Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed Texas Instruments internal qualification
testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZP) and temperature range (for example, T). Figure 27 provides a legend for reading the
complete device name for any family member.

MSP430F2272-Q1, MSP430F2252-Q1
Device Support (continued)

MSP 430 F 5 438 A I ZQW T XX
Processor Family Optional: Additional Features
430 MCU Platform Optional: Tape and Reel
Device Type Packaging
Series Optional: Temperature Range
Feature Set Optional: A = Revision
Processor Family CC = Embedded RF Radio

MSP = Mixed Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 MCU Platform TI’s Low Power Microcontroller Platform
Device Type Memory Type Specialized Application
C = ROM AFE = Analog Front End
F = Flash BT = Preprogrammed with Bluetooth
FR = FRAM BQ = Contactless Power
G = Flash or FRAM (Value Line) CG = ROM Medical
L = No Nonvolatile Memory FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series 1 Series = Up to 8 MHz 5 Series = Up to 25 MHz
2 Series = Up to 16 MHz 6 Series = Up to 25 MHz w/ LCD
3 Series = Legacy 0 = Low Voltage Series
4 Series = Up to 16 MHz w/ LCD
Feature Set Various Levels of Integration Within a Series
Optional: A = Revision N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = -40°C to 85°C
T = -40°C to 105°C
Packaging www.ti.com/packaging
Optional: Tape and Reel T = Small Reel (7 inch)
R = Large Reel (11 inch)
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (-40°C to 105°C)
-HT = Extreme Temperature Parts (-55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 27. Device Nomenclature
10.2 Documentation Support

10.2.1 Related Documents
The following documents describe the MSP430F22x2 devices. Copies of these documents are available on the
Internet at www.ti.com.
SLAU144 MSP430x2xx Family User's Guide. Detailed information on the modules and peripherals available in
this device family.
SLAZ168 MSP430F2272 Device Erratasheet. Describes the known exceptions to the functional specifications
for the MSP430F2272 device.
SLAZ166 MSP430F2252 Device Erratasheet. Describes the known exceptions to the functional specifications
for the MSP430F2252 device.

MSP430F2272-Q1, MSP430F2252-Q1
10.3 Related Links

Table 34 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 34. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
MSP430F2272-Q1 Click here Click here Click here Click here Click here
MSP430F2252-Q1 Click here Click here Click here Click here Click here
10.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you
can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
10.5 Trademarks
MSP430 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
MSP430F2252TRHARQ1 ACTIVE VQFN RHA 40 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 F2252
TQ1
MSP430F2272TRHARQ1 ACTIVE VQFN RHA 40 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 F2272
TQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
OTHER QUALIFIED VERSIONS OF MSP430F2252-Q1, MSP430F2272-Q1 :
• Catalog: MSP430F2252, MSP430F2272
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F2252TRHARQ1 VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
MSP430F2272TRHARQ1 VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Oct-2020
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F2252TRHARQ1 VQFN RHA 40 2500 853.0 449.0 35.0
MSP430F2272TRHARQ1 VQFN RHA 40 2500 853.0 449.0 35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHA 40 VQFN - 1 mm max height
6 x 6, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040B SCALE 2.200
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6.1 B
A
5.9
PIN 1 INDEX AREA
6.1
5.9
1 MAX
SEATING PLANE
0.05
0.00 0.08
2X 4.5
4.15 0.1 (0.2) TYP

11 20
36X 0.5
10
21
EXPOSED
THERMAL PAD
2X 41 SYMM
4.5
30 0.27
1 40X
0.17
PIN 1 ID 0.1 C A B
(OPTIONAL) 40 31
SYMM 0.05
0.5
40X
0.3
4219052/A 06/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040B VQFN - 1 mm max height
( 4.15)
SYMM
40X (0.6)
40 31
40X (0.22)
1
30
(0.25) TYP
41 SYMM
(0.685) (5.8)
TYP
36X (0.5) (1.14)

TYP
( 0.2) TYP
VIA
10 21
(R0.05) TYP
11 20
(0.685) (1.14)
TYP TYP
(5.8)
LAND PATTERN EXAMPLE

SCALE:12X
0.07 MAX 0.07 MIN

ALL AROUND ALL SIDES
SOLDER MASK
METAL OPENING
SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4219052/A 06/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040B VQFN - 1 mm max height
9X ( 1.17)
(1.37) TYP
40X (0.6) 40 31
40X (0.22)
1
41 30
(1.37)
(0.25) TYP TYP
SYMM
(5.8)
36X (0.5)
(R0.05) TYP
10 21
11 20
METAL
TYP
SYMM
(5.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:

72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4219052/A 06/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated

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MSP430F22x2 Automotive Mixed-Signal Microcontrollers

• On-Chip Emulation Module MSP430F2252TRHARQ1 RHA (40) 6 mm x 6 mm

4 Functional Block Diagram

VCC VSS P1.x/P2.x P3.x/P4.x

Figure 1. Functional Block Diagram

2 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: MSP430F2272-Q1 MSP430F2252-Q1

Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 3

With Schmitt Trigger ............................................... 61 10.1 Device Support .................................................... 67

Formatting and document organization changes throughout.

4 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: MSP430F2272-Q1 MSP430F2252-Q1

6 Terminal Configuration and Functions

6.1 40-Pin RHA Package (Top View)

Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 5

6.2 Terminal Functions

Table 1. Terminal Functions

(1) TDO or TDI is selected via JTAG instruction.

Product Folder Links: MSP430F2272-Q1 MSP430F2252-Q1

Terminal Functions (continued)

Terminal Functions (continued)

8 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: MSP430F2272-Q1 MSP430F2252-Q1

register operation execution time is one cycle of the

General-Purpose Register R15

Table 2. Instruction Word Formats

Table 3. Address Mode Descriptions

Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 9

7.3 Operating Modes

10 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: MSP430F2272-Q1 MSP430F2252-Q1

7.4 Interrupt Vector Addresses

Table 4. Interrupt Vector Addresses

Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 11

7.5 Special Function Registers

Table 5. Interrupt Enable 1

Table 6. Interrupt Enable 2

UCA0RXIE USCI_A0 receive-interrupt enable

Table 7. Interrupt Flag Register 1

Table 8. Interrupt Flag Register 2

UCA0RXIFG USCI_A0 receive-interrupt flag

12 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: MSP430F2272-Q1 MSP430F2252-Q1

7.6 Memory Organization

Table 9. Memory Organization

7.7 Bootstrap Loader (BSL)

Table 10. BSL Function Pins

7.8 Flash Memory

Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 13

7.10 Oscillator and System Clock

Table 11. DCO Calibration Data

7.12 Digital I/O

7.13 Watchdog Timer (WDT+)

14 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated

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Table 12. Timer_A3 Signal Connections

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