STM 32 H 503 Eb

STM32H503xx
Arm® Cortex®-M33 32-bit MCU+FPU, 375 DMIPS, 250 MHz,

128 Kbytes flash memory, 32 Kbytes RAM, I3C
Datasheet - production data
Features
Includes ST state-of-the-art patented technology
Core
WLCSP25
• Arm® Cortex®-M33 CPU with FPU, frequency LQFP64 (10 x 10 mm) UFQFPN48 (2.33 x 2.24 mm)
up to 250 MHz, MPU, 375 DMIPS (Dhrystone LQFP48 (7 x 7 mm) (7 x 7 mm)
2.1), and DSP instructions UFQFPN32
(5 x 5 mm)
ART Accelerator
Low-power modes
• 8-Kbyte instruction cache allowing
0-wait-state execution from flash memory • Sleep, Stop and Standby modes
(frequency up to 250 MHz) • VBAT supply for RTC, 32 backup registers
(32 bits)
Benchmarks
• 1.5 DMIPS/MHz (Drystone 2.1) General-purpose inputs/outputs
• 1023 CoreMark® (4.092 CoreMark®/MHz) • Up to 49 fast I/Os with interrupt capability (most
5 V tolerant)
Memories • Up to 9 I/Os with independent supply down to
• 128 Kbytes of embedded flash memory with 1.08 V
ECC, two banks of read-while-write
Analog
• 2-Kbyte OTP (one-time programmable)
• One 12-bit ADC, up to 2.5 MSPS
• 32-Kbyte SRAM with ECC
• One 12-bit dual-channel DAC
• 2 Kbytes of backup SRAM (available in the
lowest power modes) • One ultra-low-power comparator
• One operational amplifier (7 MHz bandwidth)
Clock, reset, and supply management
• 1.71 V to 3.6 V application supply and I/O One digital temperature sensor
• POR, PDR, PVD, and BOR
Up to 11 timers
• Embedded regulator (LDO)
• Six 16-bit (including two low-power 16-bit timer
• Internal oscillators: 64 MHz HSI, 48 MHz available in Stop mode) and one 32-bit timer
HSI48, 4 MHz CSI, 32 kHz LSI
• Two watchdogs
• Two PLLs for system clock, USB, audio, and
• One SysTick timer
ADC
• RTC with hardware calendar, alarms, and
• External oscillators: 4 to 50 MHz HSE,
calibration
32.768 kHz LSE
September 2023 DS14053 Rev 3 1/174

This is information on a product in full production. www.st.com
STM32H503xx
Communication interfaces Two DMA controllers to offload the CPU

• Up to two I2Cs FM + interfaces
(SMBus/PMBus®)
Security
• Up to two I3Cs shared with I2C • HASH (SHA-1, SHA-2), HMAC
• Up to three USARTs (ISO7816 interface, LIN, • True random generator

IrDA, modem control) and one LPUART • 96-bit unique ID
• Up to three SPIs including three muxed with • Active tamper
full-duplex I2S for audio class accuracy via
internal audio PLL or external clock and up to Debug
three additional SPI from three USART when
• Authenticated debug
configured in synchronous mode
• Serial wire-debug (SWD) and JTAG interfaces
• One FDCAN
• One USB 2.0 full-speed host and device ECOPACK2 compliant packages
Table 1. Device summary
Reference Part numbers
STM32H503xx STM32H503EB, STM32H503KB, STM32H503CB, STM32H503RB
2/174 DS14053 Rev 3

STM32H503xx Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Arm Cortex-M33 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 ART Accelerator (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1 Flash privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.1 SRAMs privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7 Global privilege controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.8.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8.4 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8.5 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.13 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 General-purpose direct memory access controller (GPDMA) . . . . . . . . . 26
3.15 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 28
3.15.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 28
3.16 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 29
3.17 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Contents STM32H503xx
3.17.1 Analog temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.17.2 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.3 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.4 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.19 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.20 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.21 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.22 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.23.1 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.23.2 General-purpose timers (TIM2, TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.4 Low-power timers (LPTIM1, LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.24 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 36
3.24.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.24.2 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.25 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.26 Improved inter-integrated circuit (I3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.27 Universal synchronous/asynchronous receiver transmitter
(USART/UART) and low-power universal asynchronous
receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.27.1 Universal synchronous/asynchronous receiver transmitter
(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.27.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . 42
3.28 Serial peripheral interface (SPI)/inter-integrated sound interfaces (I2S) . 44
3.29 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.30 Universal serial bus full-speed host/device interface (USB) . . . . . . . . . . . 46
3.31 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.31.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.31.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 Pinout, pin description, and alternate function . . . . . . . . . . . . . . . . . . 48
4/174 DS14053 Rev 3

STM32H503xx Contents
4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 80
5.3.4 Embedded reset and power control block characteristics . . . . . . . . . . . 81
5.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 108
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 123
5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.3.18 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.3.19 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 134
5.3.20 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 135
5.3.21 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
DS14053 Rev 3 5/174

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Contents STM32H503xx
5.3.22 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

5.3.23 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.3.24 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.3.25 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.3.26 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.27 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.2 WLCSP25 package information (B0GN) . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3 UFQFPN32 package information (A0B8) . . . . . . . . . . . . . . . . . . . . . . . . 159
6.4 LQFP48 package information (5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.5 UFQFPN48 package information (A0B9) . . . . . . . . . . . . . . . . . . . . . . . . 164
6.6 LQFP64 package information (5W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.7 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.7.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6/174 DS14053 Rev 3

STM32H503xx List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32H503xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 6. I3C peripheral controller/target features versus MIPI v1.1 . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7. USART, UART, and LPUART features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 8. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 10. STM32H503xx pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 12. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 13. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 14. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 15. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 16. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 17. Maximum allowed clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 18. VCAP operating condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 19. Operating conditions at power-up/power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . . 80
Table 20. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 21. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 22. Internal reference voltage calibration value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 23. Typical and maximum current consumption in run mode, code with data processing
running from flash memory, 2-ways instruction cache ON, PREFETCH ON . . . . . . . . . . . 84
running from flash memory, 1-way instruction cache ON, PREFETCH ON . . . . . . . . . . . . 85
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from SRAM with cache 1-WAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
running from SRAM with cache 2-WAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 27. Typical current consumption in run mode with CoreMark. . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 28. Typical current consumption in run mode with SecureMark running from flash memory . . 89
Table 29. Typical and maximum current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 30. Typical and maximum current consumption in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 31. Typical and maximum current consumption in standby mode . . . . . . . . . . . . . . . . . . . . . . 90
Table 32. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 33. Peripheral current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 34. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 35. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 36. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 37. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 39. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 40. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 41. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 42. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 43. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 44. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DS14053 Rev 3 7/174

9
List of tables STM32H503xx
Table 45. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 46. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 47. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 48. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 49. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 52. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 53. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 54. Output voltage characteristics for all I/Os except PC13, PC14 and PC15 . . . . . . . . . . . . 112
Table 55. Output voltage characteristics for PC13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 56. Output voltage characteristics for PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 57. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 58. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 59. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF) . . . . . . . . . . . . . . . . . . . 119
Table 60. Output timing characteristics VDDIO2 1.2 V (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 61. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 62. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 63. 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 64. Minimum sampling time versus RAIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 65. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 66. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 67. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 68. Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 69. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 70. Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 71. VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 72. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 73. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 74. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 75. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 76. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 77. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 78. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 79. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 80. I3C open-drain measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 81. I3C push-pull measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 82. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 83. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 84. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 85. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 86. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 87. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 88. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 89. Dynamic JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 90. Dynamic SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 91. WLCSP25 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 92. WLCSP25 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 93. UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 94. LQFP48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 95. UFQFPN48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 96. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
8/174 DS14053 Rev 3

STM32H503xx List of tables
Table 97. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 98. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
DS14053 Rev 3 9/174

9
List of figures STM32H503xx
List of figures
Figure 1. STM32H503xx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 2. STM32H503xx power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. WLCSP25 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 5. UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 6. LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 7. UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 8. LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 13. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 15. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 18. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 19. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 20. ADC conversion timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 21. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 22. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 23. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 130
Figure 24. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 25. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 26. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 27. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 28. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 29. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 30. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 31. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 32. USB timings - definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 33. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 34. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 35. WLCSP25 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 36. WLCSP25 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 37. WLCSP25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 38. UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 39. UFQFPN32 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 40. LQFP48 – Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 41. LQFP48 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 42. UFQFPN48 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 43. UFQFPN48 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 44. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 45. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
10/174 DS14053 Rev 3

STM32H503xx Introduction
1 Introduction
This document provides the ordering information and mechanical device characteristics of
the STM32H503xx microcontrollers.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32H503xx errata sheet.
For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33

Technical Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS14053 Rev 3 11/174

11
Description STM32H503xx
2 Description
The STM32H503xx devices are a high-performance microcontrollers family (STM32H5

series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. They operate
at a frequency of up to 250 MHz.
The Cortex®-M33 core features a single-precision floating-point unit (FPU) that supports all
the Arm® single-precision data-processing instructions and all the data types.
The Cortex®-M33 core also implements a full set of DSP (digital signal processing)
instructions and a memory protection unit (MPU) that enhances the application security.
The devices embed high-speed memories (128 Kbytes of dual bank flash memory and
32 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected
to three APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix.
The devices feature several protection mechanisms for embedded flash memory and
SRAM: secure life cycle management, write protection and hide protection areas.
The devices embed several peripherals reinforcing security: a HASH hardware accelerator
and a true random number generator.
The devices offer active tamper detection and protection against transient and
environmental perturbation attacks. It is done thanks to several internal monitoring that
generate a secret data erase in case of an attack.
The devices offer a fast 12-bit ADC, two DAC channels, an OPAMP, a comparator, a
low-power RTC, one 32-bit general-purpose timer, one 16-bit PWM timer dedicated to motor
control, one 16-bit general-purpose timer, two 16-bit basic timers and two 16-bit low-power
timers.
The devices also feature standard and advanced communication interfaces such as: two
I²Cs, two I3Cs shared with I²C, three SPIs with muxed full-duplex I2S, three USARTs and
one low-power UART, one FDCAN, and one USB full-speed.
The devices operate in the - 40 to + 85 °C/105 °C, and up to 125 °C at low dissipation
(+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.
A comprehensive set of power-saving modes allows the design of low-power applications.
Some independent power supplies are supported like an analog independent supply input
for ADC, DACs, COMP and OPAMP, and a dedicated supply input for some GPIOs. A VBAT
input is available for connecting a backup battery. This battery preserves the RTC
functionality and backup 32x 32-bit registers and 2-Kbyte SRAM.
The devices offer five packages from 25-pin to 64-pin.
12/174 DS14053 Rev 3

STM32H503xx Description
Table 2. STM32H503xx features and peripheral counts
STM32H503KB
STM32H503CB
STM32H503RB
STM32H503EB
Peripherals
Flash memory (Kbytes) 128

System (Kbytes) 32 (16 +16)
SRAM
Backup (bytes) 2 Kbytes
Advanced control 1 (16 bits)
General purpose 1 (32 bits) and 1 (16 bits)
Basic 2 (16 bits)
Timers Low power 2 (16 bits)

SysTick timer 1
Watchdog timers
(independent, 2
window)
SPI/I2S 3/3
I2C 2
I3C(1) 2
Communication
USART 3
interfaces
LPUART 1
FDCAN 1
USB Yes
Real-time clock (RTC) Yes
Tamper pins 1 2
Active tampers 0 1
True random number generator Yes
HASH (SHA-256) Yes
GPIOs 19 24 35 49
Wakeup pins 2(2) 3 4 5
Number of I/Os down to 1.08 V 9(3) 0 0 0
12-bit ADC 1
ADC
Number of channels 10 16
12-bit DAC controller 1
DAC
Number of channels 1 2
Comparator 1
Operational amplifier 1(4)
Maximum CPU frequency 250 MHz
DS14053 Rev 3 13/174

15
Description STM32H503xx
Table 2. STM32H503xx features and peripheral counts (continued)
STM32H503KB
STM32H503CB
STM32H503RB
STM32H503EB
Peripherals
Operating voltage 1.71 to 3.6 V

(5)
VDDIO2 separate supply pin 1 -
Ambient operating temperature:
– -40 to 85 °C/105° C, up to 125 °C at low dissipation
Operating temperature Junction temperature:
– Voltage range VOS0 (up to 250 MHz): Tj from -40 to 105 °C
– Voltage range VOS1 (up to 200 MHz): Tj from -40 to 130 °C
UFQFPN48
Package WLCSP25 UFQFPN32 LQFP64
LQFP48
1. I3C1 and I3C2 shares respectively the same IOs than I2C1 and I2C2.
2. Two wakeup pins (PA0 and PB7) from standby are available on the WLCSP25 package. Note that the PB7 pin can only be
used when the VDDIO2 supply is present.
3. On WLCSP package nine I/Os (PA8, PA9, PA15, and PB[3:8]) have a dedicated supply pin VDDIO2. They can only be
used when the VDDIO2 pin is connected to a valid power supply.
4. OPAMP1_VINM is not available on the WLCSP25 package.
5. The dedicated VDDIO2 supply is only available on the WLCSP25 package, it represents the external power supply for nine
I/Os (PA8, PA9, PA15, and PB[3:8]).
Note: VREF+ and VDDA are mapped on the same pin on all packages (no VREF+ separate pin).
14/174 DS14053 Rev 3

STM32H503xx Description
Figure 1. STM32H503xx block diagram
NJTRST, JTDI,
JTCK/SWCLK, JTAG/ SW MPU
JTMS/SWDIO, JTDO
ETM NVIC
(8 Kbytes)
TRACECLK,
ICACHE
TRACED[3:0] Arm Cortex-M33
250 MHz C-BUS
Flash memory RNG
with FPU (128 Kbytes)
AHB bus-matrix
HASH
S-BUS
SRAM1 (16 Kbytes)
@VDDA
DAC1_OUT1
SRAM2 (16 Kbytes)
ITF DAC1
DAC1_OUT2
AHB2 250 MHz

GPDMA1
@VDD
VDD Power management
@VDD
GPDMA2
Voltage regulator LDO VDD = 1.71 to 3.6 V
HSI48 3.3 to 1.2 V VSS
HS64 @VDD
Reset Supply supervision
CSI BOR
@VBAT Int
VDDIO, VDDA, VSSA, VDD,
LSI PVD, PVM VSS, NRST
PA[15:0] GPIO port A BKPSRAM
(2 Kbytes) @VDD
PB[15:0] GPIO port B PLL 1, 2
AHB1 250 MHz
AHB3 250 MHz

XTAL OSC OSC_IN
PC[15:0] GPIO port C
4- 50 MHz OSC_OUT
PD[2] GPIO port D
IWDG
RAMCFG
Reset and clock control

Standby
interface WKUPx (x=1 to 5)
CRC
FCLK
HCLKx
PCLKx
PH[1:0] GPIO port H TIM2 32b 4 channels, ETR as AF
GTZC1 TIM3 16b 4 channels, ETR as AF

16 AF EXT IT. WKP
@VDDA CRS
smcard
RX, TX, CK, CTS, RTS as AF
16xIN ADC1 ITF USART2 irDA
EXTI smcard
USART3 irDA RX, TX, CK, CTS, RTS as AF
3 compl. channels
(TIM1_CH[1:3]N), TIM1/PWM 16b AHB/APB2 AHB/APB1
6 channels (TIM1_CH[1:4]),
MOSI, MISO, SCK, NSS / SDO,
ETR, BKIN, BKIN2 as AF SPI2/I2S2
SDI, CK, WS, MCK, as AF
APB1 250 MHz (max)
APB2 250 MHz
RX, TX, CK,CTS, smcard AUDIOCLK as AF

USART1
RTS as AF irDA
MOSI, MISO, SCK, MOSI, MISO, SCK, NSS / SDO,
SPI3/I2S3
NSS / SDO, SDI, CK, WS, SPI1/I2S1 SDI, CK, WS, MCK, as AF
MCK, as AF
I2C1/SMBUS SCL, SDA, SMBA as AF
AUDIOCLK as AF I2C2/SMBUS SCL, SDA, SMBA as AF

FIFO
PHY
DP USB DTS
FIFO
DM FDCAN1 TX, RX as AF
WWDG
AHB/APB3
Temperature
monitoring IWDG IN1, IN2, CH1, CH2,
LPTIM2
ETR as AF
@VBAT
RTC_OUT1, RTC_OUT2, XTAL 32k TIM6 16b
RTC_REFIN, RTC_TS
RTC I3C1 SCL, SDA
TAMP_IN[2:1], TIM7 16b
APB3 250 MHz
TAMP
TAMP_OUT[2:1]
@VDDA OPAMP_VINM
OPAMP_VINP
OPAMP
IN1, IN2, CH1, CH2, OPAMP_VOUT
LPTIM1
ETR as AF
@VDDA COMP_INP, COMP_INM
RX, TX, CTS, LPUART1 COMP COMP_OUT as AF
RTS_DE as AF
SCL, SDA I3C2
SBS
VDD power domain VDDIO2 power domain* VBAT power domain VDDA power domain
* VDDIO2 is the external power supply for 9 I/Os (PA8, PA9, PA15 and PB3:8)
MSv68846V11
DS14053 Rev 3 15/174

15
Functional overview STM32H503xx
3 Functional overview
3.1 Arm Cortex-M33 core with FPU

The Cortex-M33 with FPU is a highly energy-efficient processor designed for
microcontrollers and deeply embedded applications, especially those requiring efficient
security.
The Cortex-M33 processor delivers a high-computational performance with low-power
consumption and an advanced response to interrupts. It features:
• Memory protection units (MPUs), supporting eight regions
• Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
The Cortex-M33 processor supports the following bus interfaces:
• System AHB bus:
The system AHB (S-AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, or Vendor_SYS regions of the
Armv8-M memory map.
• Code AHB bus:
The code AHB (C-AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32H503xx devices.
3.2 ART Accelerator (ICACHE)
3.2.1 Instruction cache (ICACHE)

The instruction cache (ICACHE) is introduced on the C-AHB code bus of the Cortex-M33
processor to improve performance when fetching instruction (or data) from internal
memories.
ICACHE offers the following features:
• Multibus interface:
– Slave port receiving the memory requests from the Cortex-M33 C-AHB code
execution port
– Master port performing refill requests to internal memories (flash memory and
SRAMs)
– A second slave port dedicated to ICACHE registers access
• Close to zero wait-states instructions/data access performance:
– 0 wait-state on cache hit
– Hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
– Critical-word-first refill policy, minimizing processor stalls on cache miss
16/174 DS14053 Rev 3

STM32H503xx Functional overview
– Hit ratio improved by two-ways set-associative architecture and pLRU-t

replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– Optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– Performance monitoring by means of a hit counter and a miss counter
• Extension of cacheable region beyond the code memory space, by means of address
remapping logic that allows four cacheable external regions to be defined
• Power consumption is reduced intrinsically with more accesses to cache memory
rather than to bigger main memories. It is even improved by configuring ICACHE as a
direct mapped rather than the default two-ways set-associative mode
• Maintenance operation for software management of cache coherency
• Error management: detection of unexpected cacheable write access, with optional
interrupt raising
3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory. It
also prevents one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to eight protected areas.
The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. An RTOS (real-time operating system)
usually manages the MPU.
If a program accesses a memory location that is prohibited by the MPU, the RTOS can
detect it and take action. In an RTOS environment, the kernel can dynamically update the
MPU area setting based on the process to be executed.
3.4 Embedded flash memory

The devices feature 128 Kbytes of embedded flash memory that is available for storing
programs and data.
The flash memory interface features:
• Dual-bank operating modes
• Read-while-write (RWW)
This allows a read operation to be performed from one bank while an erase or program
operation is performed to the other bank. Each bank contains eight pages of 8 Kbytes.
The flash memory embeds 2-Kbytes OTP (one-time programmable) for user data.
DS14053 Rev 3 17/174

47
Enhanced flash memory protection mechanisms are available. These mechanisms can be
activated by option bytes:
• Different product states for protecting memory content from debug access
• Write protection (WRP) to protect areas against erasing and programming. Two areas
per bank can be selected with 8-Kbyte granularity.
• Sector group write-protection (WRPSG), protecting up to 32 groups of four sectors
(32 Kbytes) per bank
• One HDP area per bank providing temporal isolation for startup code
The whole nonvolatile memory embeds the error correction code (ECC) feature supporting:
• Single-error detection and correction
• Double-error detection
• ECC fail address report
3.4.1 Flash privilege protection

Each flash memory sector can be programmed on the fly as privileged or unprivileged.
3.5 Embedded SRAMs

Three SRAMs are embedded in the STM32H503xx devices, each with specific features.
SRAM1 and SRAM2 are the main SRAMs.
These SRAMs are made of several blocks that can be powered down in Stop mode to
reduce consumption:
• SRAM1: 16 Kbytes with ECC
• SRAM2: 16 Kbytes with ECC
• BKPSRAM (backup SRAM): 2 Kbytes with ECC. The BKPSRAM can be retained in all
low-power modes and when VDD is off in VBAT mode.
Note: ECC is by default disabled on SRAM1, SRAM2, and BKPSRAM, it can be enabled by
clearing the option bit SRAM1_ECC, SRAM2_ECC, and BKPRAM_ECC respectively.
3.5.1 SRAMs privilege protection

The SRAM1 and SRAM2 can be programmed as privileged or nonprivileged by blocks,
using the MPCBB. The granularity of SRAM privilege block based is a page of 512 bytes.
Backup SRAM regions can be programmed as privileged or nonprivileged with watermark,
using the TZSC (privilege controller) in the GTZC (global privilege controller).
3.6 Boot modes

At startup, the BOOT0 pin allows the system to boot either from the user Flash or from the
bootloader.
When boot from user Flash is selected, NSBOOTADD defines the boot address. This
address can be locked thanks to NSBOOT_LOCK.
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When boot from bootloader is selected, the bootloader (natively embedded in the flash
memory) is launched allowing to reprogram the flash memory by using USART, I2C, I3C,
SPI, FDCAN, or USB in device mode through the DFU (device firmware upgrade).
The debug authentication feature can be launched from STMicroelectronics tools (such as
STM32CubeProgrammer or IDEs). An authentication password should be used for debug
authentication in order to launch a full regression of the product.
For more details about system configuration and boot modes, refer to the product reference
manual.
The embedded bootloader is located in the system memory, programmed by
STMicroelectronics during production. It is used to reprogram the flash memory by using
USART, I2C, I3C, SPI, FDCAN, or USB in device mode through the DFU (device firmware
upgrade).
Refer to the application note STM32 microcontroller system memory boot mode (AN2606)
for more information.
3.7 Global privilege controller (GTZC)

GTZC is used to configure privileged attributes within the full system.
The GTZC includes two different subblocks:
• TZSC: privilege controller
This subblock defines the privilege state of slave/master peripherals. It also controls
the privileged area size for the watermark memory peripheral controller (MPCWM). The
TZSC block informs some peripherals (such as RCC or GPIOs) about the privilege
status of each privileged peripheral, by sharing with RCC and I/O logic.
• MPCBB: block-based memory protection controller
This subblock controls the privilege states of all memory blocks (512-byte pages) of the
associated SRAM. This peripheral aim at configuring the internal RAM in a privileged
system product having segmented SRAM with programmable privilege attributes.
The GTZC main features are:
• Two independent 32-bit AHB interfaces for TZSC and MPCBB
• Privileged and unprivileged access to TZSC and MPCBB
• Set of registers to define product-privileged settings:
– Privileged blocks for internal SRAMs (with MPCBB)
– Privileged regions for internal backup SRAM (with MPCWM)
– Privileged access mode for peripherals
– Privileged access mode for masters
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3.8 Power supply management

The power controller (PWR) main features are:
• Power supplies and supply domains
– Core domains (VCORE)
– VDD domain
– Backup domain (VBAT)
– Analog domain (VDDA)
– VDDIO2 domain
• System supply voltage regulation
– Voltage regulator (LDO)
• Power supply supervision
– POR/PDR monitor
– BOR monitor
– PVD monitor
• Power management
– Operating modes
– Voltage-scaling control
– Low-power modes
• VBAT battery charging
• Privilege protection
3.8.1 Power supply schemes

The devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator, and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
• VDDA = 1.62 V (ADC, COMP) or 1.8 V (DAC) or 2.0 V (OPAMP) to 3.6 V
VDDA is the external analog power supply for ADCs, DACs, operational amplifier, and
comparator. The VDDA voltage level is independent from the VDD voltage and must
preferably be connected to VDD when these peripherals are not used.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for nine I/Os (PA8, PA9, PA15, PB3:8). The VDDIO2
voltage level is independent from the VDD voltage and must preferably be connected to
VDD when those pins are not used.
• VBAT = 1.2 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator, and backup
registers (through power switch) when VDD is not present.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs.
VREF- and VREF+ pins are not available and they are bonded to VSSA and VDDA,
respectively.
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The STM32H503xx devices embed an LDO regulator to provide the VCORE supply for digital
peripherals, SRAM1, SRAM2, and embedded flash memory. The LDO generates this
voltage on the VCAP pin connected to an external capacitor of 2x 2.2 μF typical.
The LDO regulator can provide four different voltages (voltage scaling) and can operate in
Stop modes.
Figure 2. STM32H503xx power supply overview
VDDA domain
A/D converters
VDDA Comparators
VSSA D/A converters
Operational amplifiers
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS
VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temperature sensor Core
2 x PLL
VSS Internal RC oscillators SRAM1
SRAM2
Standby circuitry
VDD (Wakeup logic, IWDG)
VCORE
VCAP Digital
peripherals
LDO regulator
Flash memory
Low-voltage detector
Backup domain
LSE crystal 32kHz oscillator
VBAT Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
MSv68848V2
During power-up and power-down phases, the following power sequence requirements
must be respected (refer to Figure 3: Power-up/down sequence):
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2) must remain below VDD
+ 300 mV.
• When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1 mJ. This allows external-decoupling
capacitors to be discharged with different time constants during the power-down-transient
phase.
DS14053 Rev 3 21/174

47
Figure 3. Power-up/down sequence
3.6
VDDX(1)
VDD
VPOR
VPDR
0.3
Power-on Operating mode Power-down time
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V2
1. VDDX refers to any power supply among VDDA and VDDIO2.
3.8.2 Power supply supervisor

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a brownout reset (BOR) circuitry:
• Power-on reset (POR)
The POR supervisor monitors the VDD power supply and compares it to a fixed
threshold. The devices remain in reset mode when VDD is below this threshold.
• Power-down reset (PDR)
The PDR supervisor monitors the VDD power supply. A reset is generated when VDD
drops below a fixed threshold.
• Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. It can be enabled/disabled through
BORH_EN option bit. Once enabled, three BOR thresholds (from 2.1 to 2.7 V) can be
configured through option bytes. A reset is generated when VDD drops below this
threshold.
• Programmable voltage detector (PVD)
The PVD monitors the VDD power supply by comparing it with a threshold selected
from a set of predefined values.
It can also monitor the voltage level of the PVD_IN pin by comparing it with an internal
VREFINT voltage reference level.
An interrupt can be generated when VDD drops below the VPVD threshold and/or
when VDD is higher than the VPVD threshold. The interrupt service routine can then
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generate a warning message and/or put the device into a safe state. The PVD is
enabled by software
• Analog voltage detector (AVD)
The AVD monitors the VDDA power supply by comparing it with a threshold selected
from a set of predefined values.
• VDDIO2 voltage monitor (IO2VM)
The IO2VM monitors the independent supply voltage VDDIO2 to ensure that the
peripheral is in its functional supply range.
• Backup domain voltage monitoring
The backup domain voltage level (VBAT battery voltage) can be monitored by
comparing it with two thresholds levels.
• Temperature monitoring
A dedicated temperature sensor monitors the junction temperature and compare it with
two threshold levels.
3.8.3 Voltage regulator

The devices support dynamic voltage scaling to optimize power consumption in Run mode.
The voltage regulator output, which supplies the logic (VCORE), can be adjusted according
to application needs through the following power supply levels:
– Run mode (VOS0 to VOS3)
– Scale 0 (VOS0) and scale 1 (VOS1): high performance
– Scale 2 (VOS2): balanced mode with medium performance and consumption
– Scale 3 (VOS3): optimized power consumption
• Stop mode (SVOS3 to SVOS5)
– Scale 3 (SVOS3): peripheral with wakeup from stop mode capabilities (such as
UART, SPI, I2C, LPTIM) can be kept operational.
– Scale 4 and 5 (SVOS4 and SVOS5): reduced set of peripherals (including GPIOs
through EXTI) with wakeup from Stop capability.
Regulator bypass (Regulator OFF)

When VCORE is supplied in bypass mode, the VCORE voltage must first settle at a default
level higher than 1.1 V.
Due to the LDO default state after power-up (enabled by default), the external VCORE
voltage must remain higher than 1.1 V until the LDO is disabled by software.
When the LDO is disabled, the external VCORE voltage can be adjusted according to the
user application needs.
Low-power modes
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop modes
DS14053 Rev 3 23/174

47
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the CSI, the
HSI, the HSI48, and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
The system clock when exiting from Stop mode can be either HSI up to 64 MHz or CSI
(4 MHz), depending on software configuration.
• Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
PLL, the HSI, the CSI, the HSI48, and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The BOR always remains active in Standby mode.
The I/Os state during Standby mode can be retained.
After entering Standby mode, SRAMs and register contents are lost except for registers
and backup SRAM in the backup domain and Standby circuitry.
The device exits Standby mode in the following cases:
- in an external reset with NRST pin)
- in an IWDG reset
- in a WKUP pin event (configurable rising or falling edge)
- when an RTC event occurs (alarm, periodic wakeup, timestamp),
- or in a tamper detection. The tamper detection can be raised either due to external
pins or due to an internal failure detection.
The system clock after wakeup is HSI at 32 MHz.
3.8.4 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O Schmitt trigger is “disable”).
3.8.5 VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery or an
external super-capacitor.
The VBAT pin supplies the RTC with LSE, antitamper detection (TAMP), backup registers,
and 2-Kbyte backup SRAM. Two antitamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when VDD is present.
Note: When the microcontroller is supplied from VBAT, the external interrupts nor the RTC
alarm/events exit the microcontroller from the VBAT operation.
3.9 Peripheral interconnect matrix

Several peripherals have direct connections between them. These connections allow
autonomous communication between them and support the saving of CPU resources (thus
power supply consumption). In addition, these hardware connections allow fast and
predictable latency.
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Depending on the peripherals, these interconnections can operate in Run and Sleep modes.
3.10 Reset and clock controller (RCC)

The clock controller distributes the clocks coming from the different oscillators to the core
and to the peripherals. It also manages the clock gating for low-power modes and ensures
the clock robustness. It features:
• Clock prescaler: in order to get the best trade-off between speed and current
consumption, the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
• Clock security system: clock sources can be changed safely on the fly in Run mode
through a configuration register.
• Clock management: to reduce the power consumption, the clock controller can stop
the clock to the core, individual peripherals, or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 4 to 50 MHz high-speed external crystal or ceramic resonator (HSE) that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
– 64 MHz high-speed internal RC oscillator (HSI), trimmable by software that can
supply a PLL.
– 4 MHz low-power internal oscillator (CSI), trimmable by software that can supply a
PLL.
– System PLL that can be fed by HSE, HSI, or CSI, with a maximum frequency at
250 MHz.
• RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)
can be used to drive the USB.
• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
• Peripheral clock sources: several peripherals have their own independent clock
whatever the system clock. Two PLLs, each having two independent outputs allowing
the highest flexibility, can generate independent clocks for the ADC, USB, RNG and
FDCAN1.
• Startup clock: after reset, the microcontroller restarts by default with an internal
32 MHz clock (HSI). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If an HSE
clock failure occurs, the master clock automatically switches to HSI, and a software
interrupt is generated if enabled. LSE failure can also be detected and generates an
interrupt.
• Clock-out capability:
– MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application.
DS14053 Rev 3 25/174

47
– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except Standby and VBAT).
Several prescalers allow AHB and APB frequencies configuration. The maximum frequency
of the AHB and the APB clock domains is 250 MHz.
3.11 Clock recovery system (CRS)

The devices embed a special block that allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device-operational range. This
automatic trimming is based on the external synchronization signal. This signal is either
derived from USB SOF signalization, from an LSE oscillator, from an external signal on the
CRS_SYNC pin or generated by user software. For faster lock-in during startup, automatic-
trimming and manual-trimming action can be combined.
3.12 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in analog mode to reduce power consumption.
In order to avoid spurious writing to the I/Os registers, if needed, the I/Os alternate function
configuration can be locked following a specific sequence
On WLCSP25, nine IOs (PA8, PA9, PA15, PB3:8) can be independently supplied by a
dedicated VDDIO2 supply.
The I/O high-speed low-voltage feature (HSLV) should be activated in order to maximize the
I/O performance when the device is operating at low voltage.
This is needed to achieve the performance required for communication interface peripherals
such SPI. The HSLV feature must be used only when the supply voltage (VDD or VDDIO2)
is lower than 2.7 V. To enable it, the corresponding HSLV user option bit (IO_VDD_HSLV or
IO_VDDIO2_HSLV) and the HSLVx bits should be set.
3.13 Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all the masters (CPU, GPDMA1, GPDMA2) and
the slaves (flash memory, SRAMs, AHB, and APB) peripherals. It also ensures a seamless
and efficient operation even when several high-speed peripherals work simultaneously.
3.14 General-purpose direct memory access controller (GPDMA)

The general-purpose direct memory access (GPDMA) controller is a bus master and system
peripheral.
The GPDMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.
The GPDMA main features are:
26/174 DS14053 Rev 3

• Dual bidirectional AHB master

• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep mode
• Transfers arbitration based on a four-grade-programmed priority at a channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non-
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete or half
transfer complete or data transfer error or user setting error, and/or update linked-list
item error or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable per
event
• 8 concurrent DMA channels:
– Per channel FIFO for queuing source and destination transfers
– Intra-channel DMA transfers chaining via a programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and interchannel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– 12 channels with linear source and destination addressing: either fixed or
contiguously incremented addressing, programmed at a block level, between
successive single transfers
– Four channels with 2D source and destination addressing: programmable-signed
address offsets between successive burst transfers (noncontiguous addressing
DS14053 Rev 3 27/174

47
within a block, combined with programmable-signed address offsets between

successive blocks, at a second-2D/repeated block level)
– Support for scatter-gather (multibuffer transfers), data interleaving and
deinterleaving via 2D addressing
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting including FIFO level and event flags
• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at a channel
level
– Privileged-aware AHB slave port.
3.15 Interrupts and events
3.15.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller that is able to manage 16 priority
levels and to handle up to 134 maskable interrupt channels plus the 16 interrupt lines of the
Cortex-M33.
The NVIC benefits are the following:
• Closely coupled NVIC giving low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.15.2 Extended interrupt/event controller (EXTI)

The EXTI handles up to 54 independent event/interrupt lines, it manages the individual
CPU, and system wakeup through configurable event inputs. It provides wakeup requests to
the power control, and generates an interrupt request to the CPU NVIC and events to the
CPU event input. For the CPU, an additional event generation block (EVG) is needed to
generate the CPU event signal.
The EXTI wakeup requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run modes. The
EXTI also includes the EXTI multiplexer IO port selection.
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The EXTI main features are the following:

• All event inputs allowed to wake up the system
• Configurable events (signals from I/Os or peripherals able to generate a pulse)
– Selectable active trigger edge
– Interrupt pending status register bit independent for the rising and falling edge
– Individual interrupt and event generation mask, used for conditioning the CPU
wakeup, interrupt, and event generation
– Software trigger possibility
• EXTI IO port selection
3.16 Cyclic redundancy check calculation unit (CRC)

The CRC is used to get a CRC code using a configurable generator with polynomial value
and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime that
can be ulteriorly compared with a reference signature generated at link time and that can be
stored at a given memory location.
3.17 Analog-to-digital converter (ADC1)

The devices embed one successive approximation analog-to-digital converter.
Table 3. ADC features

ADC modes/features(1) ADC1
Resolution 12 bits
Maximum sampling-speed 2.5 Msps
Hardware-offset calibration X
Single-ended inputs X
Differential inputs X
Injected channel conversion X
Oversampling up to x1024
Data register 32 bits
DMA support X
Offset compensation X
Gain compensation X
Number of analog watchdogs 3
1. X = supported.
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3.17.1 Analog temperature sensor

The STM32H503xx embed an analog temperature sensor that generates a voltage VSENSE
that varies linearly with temperature. The temperature sensor is internally connected to the
ADC input channel that is used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the
temperature measurement. As the offset of the temperature sensor varies from chip to chip
due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by STMicroelectronics in the system memory area, accessible in read-only mode.
3.17.2 Digital temperature sensor (DTS)

The STM32H503xx embed a sensor that converts the temperature into a square wave,
which frequency is proportional to the temperature. The PCLK or the LSE clock can be used
as a reference clock for the measurements. A formula given in the product reference
manual (RM0492) allows to calculate the temperature according to the measured frequency
stored in the DTS_DR register.
3.17.3 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC input
channel.
The precise voltage of VREFINT is individually measured for each part by
STMicroelectronics during production test and stored in the system memory area. It is
accessible in read-only mode.
3.17.4 VBAT battery voltage monitoring

This embedded hardware enables the application to measure the VBAT battery voltage by
using the ADC input channel. As the VBAT voltage may be higher than the VDDA, and thus
outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
four. As a consequence, the converted digital value is a quarter of the VBAT voltage.
3.18 Digital to analog converter (DAC)

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In
12-bit mode, the data may be left- or right-aligned.
The DAC features two output channels, each with its own converter. In dual DAC channel
mode, conversions can be done independently or simultaneously when both channels are
grouped together for synchronous update operations.
The DAC_OUTx pin can be used as a general-purpose input/output (GPIO) when the DAC
output is disconnected from the output pad and connected to the on-chip peripheral. The
DAC output buffer can be optionally enabled to allow a high drive output current. An
30/174 DS14053 Rev 3

individual calibration can be applied on each DAC output channel. The DAC output
channels support a low-power mode, the sample and hold mode.
The digital interface supports the following features:
• One DAC interface, maximum two output channels
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave and triangular-wave generation
• Sawtooth wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• Double data DMA capability to reduce the bus activity
• External triggers for conversion
• DAC output-channel buffered/unbuffered modes
• Buffer offset calibration
• Each DAC output can be disconnected from the DAC_OUTx output pin
• DAC output connection to on-chip peripherals
• Sample and hold mode for low-power operation in Stop mode.
• Voltage reference input
3.19 Ultra-low-power comparators (COMP)

The STM32H503xx devices embed a comparator COMP1 with a programmable reference
voltage (internal or external), hysteresis, and speed (low speed for low-power) as well as
selectable output polarity.
The reference voltage can be one of the following:
• An external I/O
• A DAC output channel
• An internal reference voltage or submultiple (1/4, 1/2, 3/4)
• The analog temperature sensor
• The VBAT/4 supply.
The comparator can wake up from Stop mode, generate interrupts and breaks for the
timers.
3.20 Operational amplifiers (OPAMP)

The STM32H503xx devices embed an operational amplifier OPAMP1 with external or
internal follower routing and PGA capability, and two inputs and one output. These three
I/Os can be connected to the external pins, thus enabling any type of external
interconnections. The operational amplifier can be configured internally as a follower, as an
amplifier with a noninverting gain ranging from 2 to 16 or with an inverting gain ranging from
-1 to -15.
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The main features of the operational amplifier are:

• PGA with a noninverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
• One positive input connected to the DAC
• Output connected to internal ADC
• Low input bias current down to 1 nA
• Low input offset voltage down to 1.5 mV
• Gain bandwidth up to 7 MHz
3.21 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
nondeterministic random bit generator (NDRBG).
The true random generator:
• delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage
• can be used as an entropy source to construct a nondeterministic random bit generator
(NDRBG)
• produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise)
• embeds start-up and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
• can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration)
• has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored)
3.22 HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-224, SHA-256) and the keyed-hash message authentication code (HMAC)
algorithm. HMAC is suitable for applications requiring message authentication.
The HASH computes FIPS (federal information processing standards) approved digests of
length of 160, 224, 256, 512 bits, for messages of up to (264 – 1).
The HASH main features are:
• Suitable for data authentication applications, compliant with:
– Federal information processing standards publication FIPS PUB 180-4, Secure
hash standard (SHA-1 and SHA-2 family)
– Federal information processing standards publication FIPS PUB 186-4, Digital
signature standard (DSS)
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– Internet engineering task force (IETF) Request for comments RFC 2104, HMAC:
keyed-hashing for message authentication and federal information processing
standards publication FIPS PUB 198-1, The Keyed-Hash message authentication
code (HMAC)
• Fast computation of SHA-1, SHA-224, and SHA-256
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using the
SHA-1 (respectively SHA-256) algorithm
• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit string
– Word swapping supported: bits, bytes, half-words, and 32-bit words
• Automatic padding to complete the input bit string to fit the digest minimum block size
of 512 bits (16 × 32 bits)
• Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,
corresponding to one block size
• AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
• 8 × 32-bit words (H0 to H7) for output message digest
• Automatic data flow control with support of direct memory access (DMA) using one
channel. Single or fixed burst of four supported.
• Interruptible message digest computation, on a per-32-bit word basis
– Reloadable digest registers
– Hashing computation suspend/resume mechanism, including using DMA
3.23 Timers and watchdogs

The devices include one advanced control timer, up to two general-purpose timers, two
basic timers, two low-power timers, two watchdog timers and one SysTick timer.
The table below compares the features of the advanced control, general-purpose and basic
timers.
Table 4. Timer feature comparison

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Any integer
Advanced Up, down,
TIM1 16 bits between 1 and Yes 4 4
control Up/down
65536
Any integer
General- Up, down,
TIM2 32 bits between 1 and Yes 4 No
purpose Up/down
65536
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Table 4. Timer feature comparison (continued)

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Any integer
General- Up, down,
TIM3 16 bits between 1 and Yes 4 No
purpose Up/down
65536
Any integer
Basic TIM6, TIM7 16 bits Up between 1 and Yes 0 No
65536
3.23.1 Advanced-control timers (TIM1)

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability
(0 - 100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in the next
section) using the same architecture, so the advanced-control timers can work together with
the TIMx timers via the Timer Link feature for synchronization or event chaining.
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3.23.2 General-purpose timers (TIM2, TIM3)

There are two general-purpose timers that can be synchronized, embedded in the
STM32H503xx devices (see Table 4 for differences). Each general-purpose timer can be
used to generate PWM outputs, or act as a simple time base.
• TIM2
They are full-featured general-purpose timers with 32-bit auto-reload up/downcounter
and 32-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM, or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
• TIM3
They are full-featured general-purpose timers with 16-bit auto-reload up/downcounter
and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM, or one-pulse mode output.
They can work together, or with the other general-purpose timers via the Timer Link
feature for synchronization or event chaining.
The counters can be frozen in debug mode. All have independent DMA request
generation and support quadrature encoders.
3.23.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebase.
3.23.4 Low-power timers (LPTIM1, LPTIM2)

The devices embed six low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI, or an external clock. They are able to
wake up the system from Stop mode.
The low-power timer supports the following features:
• 16-bit up counter with 16-bit auto reload register
• 3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)
• Selectable clock
– Internal clock sources: LSE, LSI, HSI, or APB clock
– External clock source over LPTIM input (working with no LP oscillator running,
used by Pulse Counter application)
• 16-bit ARR auto reload register
• 16 bit capture/compare register
• Continuous/One-shot mode
• Selectable software/hardware input trigger
• Programmable digital glitch filter
• Configurable output: pulse, PWM
• Configurable I/O polarity
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• Encoder mode
• Repetition counter
• Up to two independent channels for:
– Input capture
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Interrupt generation on 10 events
• DMA request generation on the following events:
– Update event
– Input capture
3.23.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.23.6 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.23.7 SysTick timer

The Cortex-M33 embeds one SysTick timer.
This timer is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
• A 24-bit down counter
• Auto reload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.
3.24 Real-time clock (RTC), tamper and backup registers
3.24.1 Real-time clock (RTC)

The RTC supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date,
month, year, in BCD (binary-coded decimal) format
• Binary mode with 32-bit free-running counter
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
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• Two programmable alarms

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period
• Privilege protection support:
– Alarm A, alarm B, wakeup timer, and timestamp individual privileged protection
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be one of the following:
• 32.768 kHz external crystal (LSE)
• external resonator or oscillator (LSE)
• internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
• high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (alarm, wakeup timer, timestamp) can generate an interrupt and wakeup the
device from the low-power modes.
3.24.2 Tamper and backup registers (TAMP)

The antitamper detection circuit is used to protect sensitive data from external attacks. 32
32-bit backup registers are retained in all low-power modes and also in VBAT mode. The
backup registers, as well as other secrets in the device, are protected by this anti-tamper
detection circuit with height tamper pins and nine internal tampers. The external tamper pins
can be configured for edge detection, or level detection with or without filtering, or active
tamper that increases the security level by auto checking that the tamper pins are not
externally opened or shorted.
TAMP main features:
• A tamper detection can erase the backup registers, backup SRAM, SRAM2, and
I-cache.
• 32 32-bit backup registers:
– The backup registers (TAMP_BKPxR) are implemented in the backup domain that
remains powered-on by VBAT when the VDD power is switched off.
• Up to two tamper pins for two external tamper detection events:
– Active tamper mode: continuous comparison between tamper output and input to
protect from physical open-short attacks
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– Passive tampers: ultra-low power edge or level detection with internal pull-up
hardware management
– Configurable digital filter
• 11 internal tamper events to protect against transient or environmental perturbation
attacks:
– Backup domain voltage monitoring
– Temperature monitoring
– LSE monitoring
– HSE monitoring
– RTC calendar overflow
– JTAG/SWD access if product state different from 0
– Voltage monitoring through ADC analog watchdogs
– Monotonic counter overflow
– Fault generation for RNG
– Independent watchdog reset when tamper flag is already set
– System fault detection
• Each tamper can be configured in two modes:
– Hardware mode: immediate erase of secrets on tamper detection, including
backup registers erase
– Software mode: erase of secrets following a tamper detection launched by
software
• Any tamper detection can generate an RTC time stamp event.
• Tamper configuration and backup registers privilege protection
• Monotonic counter
3.25 Inter-integrated circuit interface (I2C)

The device embeds two I2C. Refer to Table 5: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration, and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bit rate up to 100 Kbit/s
– Fast-mode (Fm), with a bit rate up to 400 Kbit/s
– Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
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– Address resolution protocol (ARP) support

– SMBus alert
• Power system management protocol (PMBus) specification rev 1.3 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
• Wakeup from Stop capability
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 5. I2C implementation

I2C features(1) I2C1 I2C2
Standard-mode (up to 100 Kbit/s) X X

Fast-mode (up to 400 Kbit/s) X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X
Programmable analog and digital noise filters X X
SMBus/PMBus hardware support X X
Independent clock X X
Wakeup capability X X
1. X: supported
3.26 Improved inter-integrated circuit (I3C)

The I3C interface handles communication between this device and others, like sensors and
host processor(s) that are all connected on an I3C bus.
The I3C peripheral implements all the required features of the MIPI I3C specification v1.1. It
can control all I3C bus-specific sequencing, protocol, arbitration and timing, and can be
acting as controller (formerly known as master) or as target (formerly known as slave).
The I3C peripheral, acting as controller, improves the features of the I2C interface still
preserving some backward compatibility: it allows an I2C target to operate on an I3C bus in
legacy I2C fast-mode (Fm) or legacy I2C fast-mode plus (Fm+), provided that this latter
does not perform clock stretching.
The I3C peripheral can be used with DMA in order to off-load the CPU.
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Table 6. I3C peripheral controller/target features versus MIPI v1.1

I3C I3C
MIPI
peripheral peripheral
Feature I3C Comments
when when
v1.1
controller target
I3C SDR message X X X -

Mandatory when controller and the I3C bus
Legacy I2C message (Fm/Fm+) X X - is mixed with (external) legacy I2C target(s).
Optional in MIPI v1.1 when target.
HDR DDR message X - - Optional in MIPI v1.1
HDR-TSL/TSP, HDR-BT X - - Optional in MIPI v1.1
Dynamic address assignment X X X -
No (intended) support of I3C peripheral as a
Static address X X -
target on an I2C bus.
Grouped addressing X X - Optional in MIPI v1.1
Mandatory CCCs and some optional CCCs
CCCs X X X
are supported
Error detection and recovery X X X -
In-band interrupt (with MDB) X X X -
Secondary controller X X X -
Hot-join mechanism X X X -
Target reset X X X -
Synchronous timing control X X - Optional in MIPI v1.1
Asynchronous timing control 0 X X - Optional in MIPI v1.1
Asynchronous timing control 1,2, 3 X - - Optional in MIPI v1.1
Device-to-device tunneling X X - Optional in MIPI v1.1
Multilane data transfer X X - Optional in MIPI v1.1
Monitoring device early termination X - - Optional in MIPI v1.1
3.27 Universal synchronous/asynchronous receiver transmitter

(USART/UART) and low-power universal asynchronous
receiver transmitter (LPUART)
The devices have six embedded universal synchronous receiver transmitters
(USART1/USART2/USART3), and one low-power universal asynchronous receiver
transmitter (LPUART1).
Table 7. USART, UART, and LPUART features

USART modes/features(1) USART1/2/3 LPUART1
Hardware flow control for modem X X

Continuous communication using DMA X X
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Table 7. USART, UART, and LPUART features (continued)

USART modes/features(1) USART1/2/3 LPUART1
Multiprocessor communication X X
Synchronous mode (master/slave) X -
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X -
LIN mode X -
(2)
Dual-clock domain and wakeup from Stop mode X X(2)
Receiver timeout interrupt X -
Modbus communication X -
Auto-baud rate detection X -
Driver enable X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X
Tx/Rx FIFO size 8 bytes
1. X = supported.
2. Wakeup supported from Stop mode.
3.27.1 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
The USART offers a flexible means to perform full-duplex data exchange with external
equipment requiring an industry standard NRZ asynchronous serial data format. A very wide
range of baud rates can be achieved through a fractional baud rate generator.
The USART supports both synchronous one-way and half-duplex single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS).
Multiprocessor communications are also supported.
High-speed data communications up to 20 Mbauds are possible by using the DMA (direct
memory access) for multibuffer configuration.
The USART main features are:
• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to achieve the best compromise
between speed and clock tolerance
• Baud rate generator systems
• Two internal FIFOs for transmit and receive data
Each FIFO can be enabled/disabled by software and come with a status flag.
• A common programmable transmit and receive baud rate
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Auto baud rate detection
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• Programmable data word length (7, 8 or 9 bits)

• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous Master/Slave mode and clock output/input for synchronous
communications
• SPI slave transmission underrun error flag
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications: wakeup from Mute mode by idle line detection or
address mark detection
• Wakeup from Stop mode
• LIN master-synchronous break send capability and LIN slave break detection capability
– 13-bit break generation and 10/11 bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16 bit duration for Normal mode
• Smartcard mode
– Supports the T=0 and T=1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
– 0.5 and 1.5 stop bits for Smartcard operation
• Support for Modbus communication
– Timeout feature
– CR/LF character recognition
3.27.2 Low-power universal asynchronous receiver transmitter (LPUART)

The LPUART supports bidirectional asynchronous serial communication with minimum
power consumption. It also supports half-duplex single-wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher-speed clock can be used to
reach higher baudrates.
The LPUART interface can be served by the DMA controller.
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The LPUART main features are:

• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate
• From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
• Higher baud rates can be achieved by using a higher frequency clock source
• Two internal FIFOs to transmit and receive data
Each FIFO can be enabled/disabled by software and come with status flags for FIFOs
states.
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Programmable data word length (7 or 8 or 9 bits)
• Configurable stop bits (1 or 2 stop bits)
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– Busy and end of transmission flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Four error detection flags:
– Overrun error
– Noise detection
– Frame error
– Parity error
• Interrupt sources with flags
• Multiprocessor communications: wakeup from Mute mode by idle line detection or
address mark detection
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3.28 Serial peripheral interface (SPI)/inter-integrated sound

interfaces (I2S)
The devices embed three serial peripheral interfaces (SPI) that can be used to
communicate with external devices while using the specific synchronous protocol. The SPI
protocol supports half-duplex, full-duplex, and simplex synchronous, serial communication
with external devices.
The interface can be configured as master or slave and can operate in multislave or
multimaster configurations. The device configured as master provides communication clock
(SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied
optionally just to set up communication with a concrete slave and to assure it handles the
data flow properly. The Motorola data format is used by default, but some other specific
modes are supported as well.
The SPI main features are:
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only
• Multimaster or multislave mode capability
• Dual-clock domain, separated clock for the peripheral kernel that can be independent
of PCLK
• Baud rate prescaler up to kernel frequency/2 or bypass from RCC in master mode
• Protection of configuration and setting
• Hardware or software management of SS for both master and slave
• Adjustable minimum delays between data and between SS and data flow
• Configurable SS signal polarity and timing, MISO x MOSI swap capability
• Programmable clock polarity and phase
• Programmable number of data within a transaction to control SS and CRC
• Dedicated transmission and reception flags with interrupt capability
• SPI Motorola and TI formats support
• Hardware CRC feature can secure communication at the end of a transaction by:
– Adding CRC value in Tx mode
– Automatic CRC error checking for Rx mode
• Error detection with interrupt capability in case of data overrun, CRC error, data
underrun at slave, mode fault at master
• Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability
• Programmable number of data in transaction
• Configurable FIFO thresholds (data packing)
• Configurable behavior at slave underrun condition (support of cascaded circular
buffers)
• Optional status pin RDY signalizing the slave device ready to handle the data flow.
44/174 DS14053 Rev 3

Three standard I2S interfaces (multiplexed with SPI1, SPI2, and SPI3) are available. They
can be operated in master or slave mode, in full-duplex communication modes, and can be
configured to operate with configurable resolutions as an input or output channel.
I2S main features:
• Full duplex communication
• Simplex communication (only transmitter or receiver)
• Master or slave operations
• 8-bit programmable linear prescaler
• Data length may be 16, 24 or 32 bits
• Channel length can be 16 or 32 in master, any value in slave
• Programmable clock polarity
• Error flags signaling for improved reliability: underrun, overrun, and frame error
• Embedded Rx and TxFIFOs
• Supported I2S protocols:
– I2S Philips standard
– MSB-Justified standard (left-justified)
– LSB-Justified standard (right-justified)
– PCM standard (with short and long frame synchronization)
• Data ordering programmable (LSb or MSb first)
• DMA capability for transmission and reception
• Master clock can be output to drive an external audio component. The ratio is fixed at
256 x FWS (where FWS is the audio sampling frequency)
Table 8. SPI features

SPI1, SPI2, SPI3
SPI feature
(full feature set instances)
Data size Configurable from 4 to 32-bit

CRC polynomial length configurable from 5
CRC computation
to 33-bit
Size of FIFOs 16x 8-bit
Number of transferred data Unlimited, expandable
I2S feature Yes
3.29 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN module, a shared
message RAM memory, and a configuration block.
The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs, and
transmits FIFOs.
The FDCAN main features are:
DS14053 Rev 3 45/174

47
• Conform with CAN protocol version 2.0 part A, B, and ISO 11898-1: 2015, -4
• CAN FD with maximum 64 data bytes supported
• CAN error logging
• AUTOSAR and J1939 support
• Improved acceptance filtering
• 2 receive FIFOs of three payloads each (up to 64 bytes per payload)
• Separate signaling on reception of high priority messages
• Configurable transmit FIFO/queue of three payloads (up to 64 bytes per payload)
• Configurable transmit event FIFO
• Programmable loop-back test mode
• Maskable module interrupts
• Two clock domains: APB bus interface and CAN core kernel clock
• Power-down support
3.30 Universal serial bus full-speed host/device interface (USB)

USB main features
• USB specification version 2.0 full-speed compliant
• Host and device functions
• 2048bytes of dedicated SRAM data buffer memory with 32-bit access
• Configurable number of endpoints from 1 to 8
• Cyclic redundancy check (CRC) generation/checking, non-return-to-zero inverted
(NRZI) encoding/decoding, and bit-stuffing
• Isochronous transfers support
• Double-buffered bulk/isochronous endpoint support
• USB suspend/resume operations
• Frame-locked clock pulse generation
• USB 2.0 Link power management support
• Battery charging specification revision 1.2 support in device
• USB connect / disconnect capability (controllable embedded pull-up resistor on
USB_DP line)
3.31 Development support
3.31.1 Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can
be reused as GPIO with an alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
46/174 DS14053 Rev 3

3.31.2 Embedded Trace Macrocell

The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high rate from
the devices through a small number of ETM pins to an external hardware trace port analyzer
(TPA) device.
Real-time instruction and data flow activity be recorded and then formatted for display on
the host computer that runs the debugger software. TPA hardware is commercially available
from common development tool vendors.
The ETM operates with third-party debugger software tools.
DS14053 Rev 3 47/174

47
Pinout, pin description, and alternate function STM32H503xx
4 Pinout, pin description, and alternate function
4.1 Pinout/ballout schematics

Figure 4. WLCSP25 pinout
1 2 3 4 5
A PA12 PA15 BOOT0 PB7 PB8
PC14-
B PA11 VDDIO2 PB5 PB6 OSC32_
IN
VSS/ PC15-
C PA8 PA14 VSSA/ PB4 OSC32_
VREF- OUT
VDD/
D PA9 PA13 PB3 VDDA/ NRST
VREF+
E PB15 VCAP PA7 PA5 PA0
MSv68853V4
1. The above figure shows the package top view.
Figure 5. UFQFPN32 pinout(a)

BOOT0
PA15
PB8
PB7
PB6
PB5
PB4
PB3
32
31
30
29
28
27
26
25
VDD 1 24 PA14
PC14-OSC32_IN 2 23 PA13
PC15-OSC32_OUT 3 22 PA12
NRST 4 21 PA11
VDDA/VREF+ 5
UFQFPN32 20 PA9
PA0 6 19 PA8
PA1 7 18 PB15
Exposed pad
PA2 8 17 VDD
10
12
13
14
15
16
11
VSS/VSSA/VREF-
9
PB0
PB1
VCAP
PA3
PA4
PA5
PA6
PA7
MSv68852V4
a. There is an exposed die pad on the underside of the UFQFPN package. This backside pad must be
connected and soldered to PCB ground.
48/174 DS14053 Rev 3

STM32H503xx Pinout, pin description, and alternate function
Figure 6. LQFP48 pinout
BOOT0
VCAP
PA15
PA14
VDD
VSS
PB8
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA/VREF- 8 29 PA8
VDDA/VREF+ 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3
PA4
PA5
PA6
PA7
MSv68850V2
Figure 7. UFQFPN48 pinout

BOOT0
VCAP
PA15
PA14
VDD
VSS
PB8
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
NRST 7
UFQFPN48 30 PA9
VSSA/VREF- 8 29 PA8
PA0 10 27 PB14
PA1 11 Exposed pad 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3
PA4
PA5
PA6
PA7
MSv68851V3
DS14053 Rev 3 49/174

51
Pinout, pin description, and alternate function STM32H503xx
Figure 8. LQFP64 pinout
BOOT0
VCAP
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD2
PB8
PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDD
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD
PC4
PC5
PB0
PB1
PB2
VSS
PB10
VCAP
VDD
PA3
PA4
PA5
PA6
PA7
MSv68849V2
50/174 DS14053 Rev 3

STM32H503xx Pinout, pin description, and alternate function
4.2 Pin description

Table 9. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during
Pin name
and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/output pin
FT 5V-tolerant I/O
TT 3.6V-tolerant I/O
B Dedicated BOOT pin
Bidirectional reset pin with embedded weak pull-up
RST
resistor
I/O structure Option for TT or FT I/Os(1)

_a I/O, with analog switch function supplied by VDDA
_f I/O, Fm+ capable
_h I/O with high-speed low-voltage mode (HSLV)
_s I/O supplied only by VDDIO2(2)
_t I/O with tamper function functional in VBAT mode
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, TT_a.
2. Refer to Table 2: STM32H503xx features and peripheral counts for the list of packages featuring VDDIO2 separate supply
pin.
DS14053 Rev 3 51/174

51
52/174
Table 10. STM32H503xx pin/ball definition
Pin Number
Pin name (function after Pin I/O
Notes Alternate functions Additional functions
WLCSP UFQFPN LQFP UFQFP LQFP reset) type structure
25 32 48 N48 64
- - 1 1 1 VBAT S - - - -
TAMP_IN1/TAMP_OUT2,
(1)(2)
- - 2 2 2 PC13 I/O FT_t EVENTOUT RTC_OUT1/RTC_TS,
WKUP4
PC14- (1)(2)
B5 2 3 3 3 I/O FT EVENTOUT OSC32_IN
OSC32_IN(OSC32_IN)
PC15- (1)(2)
C5 3 4 4 4 I/O FT EVENTOUT OSC32_OUT
OSC32_OUT(OSC32_OUT)
- - 5 5 5 PH0-OSC_IN(PH0) I/O FT - EVENTOUT OSC_IN
DS14053 Rev 3
- - 6 6 6 PH1-OSC_OUT(PH1) I/O FT - EVENTOUT OSC_OUT

D5 4 7 7 7 NRST I/O RST - - -
TIM1_ETR, LPTIM1_CH2,
- - - - 8 PC0 I/O FT_ah - SPI1_SCK/I2S1_CK, ADC1_INP10
SPI2_RDY, EVENTOUT
TRACED0, TIM3_ETR,
SPI1_NSS/I2S1_WS,
SPI2_MOSI/I2S2_SDO, ADC1_INP11,
- - - - 9 PC1 I/O FT_ah -
USART1_CTS/USART1_N ADC1_INN10, WKUP3
SS, LPUART1_CTS,
LPTIM2_IN1, EVENTOUT
PWR_CSLEEP,
SPI1_MISO/I2S1_SDI,
SPI2_MISO/I2S2_SDI, ADC1_INP12,
- - - - 10 PC2 I/O FT_ah -
USART1_RTS, ADC1_INN11
LPUART1_RTS,
STM32H503xx
EVENTOUT
Table 10. STM32H503xx pin/ball definition (continued)
STM32H503xx
Pin Number
25 32 48 N48 64
PWR_CSTOP,
LPUART1_TX,
SPI1_MOSI/I2S1_SDO,
ADC1_INP13,
- - - - 11 PC3 I/O FT_ah - SPI2_MOSI/I2S2_SDO,
ADC1_INN12
USART2_CTS/USART2_N
SS, LPTIM2_IN2,
EVENTOUT
C3 - 8 8 12 VSSA S - - - -
D4 5 9 9 13 VDDA S - - - -
RTC_OUT2, TIM2_CH1,
TIM3_CH1, LPTIM2_ETR,
DS14053 Rev 3
LPTIM1_ETR, LPTIM1_IN2,
SPI3_RDY,
USART2_CTS/USART2_N
ADC1_INP0, ADC1_INN1,
SS,
OPAMP1_VINP,
USART1_CTS/USART1_N
E5 6 10 10 14 PA0 I/O FT_ah - COMP1_INP1,
SS,
TAMP_IN2/TAMP_OUT1,
USART3_CTS/USART3_N
WKUP1
SS, SPI3_NSS/I2S3_WS,
I2S2_MCK,
SPI1_MISO/I2S1_SDI,
USART3_CK, TIM2_ETR,
EVENTOUT
TIM2_CH2,
SPI1_NSS/I2S1_WS,
LPTIM1_IN1,
SPI3_SCK/I2S3_CK,
- 7 11 11 15 PA1 I/O FT_ah - ADC1_INP1
USART2_RTS,
USART1_RX, USART2_CK,
SPI2_RDY, TIM1_CH3,
EVENTOUT
53/174
54/174 Pin Number
25 32 48 N48 64
TIM2_CH3, TIM3_ETR,
LPUART1_RX,
SPI1_SCK/I2S1_CK,
- 8 12 12 16 PA2 I/O FT_ah - LPTIM1_IN2, ADC1_INP14, WKUP2
SPI3_MISO/I2S3_SDI,
USART2_TX, USART1_TX,
TIM1_CH4, EVENTOUT
TIM2_CH4, LPUART1_TX,
SPI1_MISO/I2S1_SDI,
SPI2_NSS/I2S2_WS,
- 9 13 13 17 PA3 I/O FT_ah - SPI3_MOSI/I2S3_SDO, ADC1_INP15
USART2_RX, USART1_CK,
DS14053 Rev 3
USART3_RX, TIM1_CH1N,
EVENTOUT
- - - - 18 VSS S - - - -
- - - - 19 VDD S - - - -
TIM1_CH2N, LPTIM2_CH1,
SPI1_MOSI/I2S1_SDO,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
ADC1_INP18,
- 10 14 14 20 PA4 I/O TT_ah - USART2_CK,
DAC1_OUT1
USART1_RTS,
SPI3_MISO/I2S3_SDI,
USART3_TX, TIM1_BKIN,
EVENTOUT
STM32H503xx
STM32H503xx
Pin Number
25 32 48 N48 64
LPTIM2_CH2,
LPTIM1_CH1,
SPI1_SCK/I2S1_CK,
I2S1_MCK, ADC1_INP19,
SPI2_SCK/I2S2_CK, ADC1_INN18,
E4 11 15 15 21 PA5 I/O TT_ah -
LPUART1_RTS, DAC1_OUT2,
USART2_TX, COMP1_INM3
SPI3_MOSI/I2S3_SDO,
USART2_CTS/USART2_N
SS, USART3_RX,
TIM2_ETR, EVENTOUT
DS14053 Rev 3
TIM1_BKIN, TIM3_CH1,
- 12 16 16 22 PA6 I/O FT_ah - SPI1_MISO/I2S1_SDI, ADC1_INP3
EVENTOUT
TIM1_CH1N, TIM3_CH2,
LPTIM2_ETR, I2S1_MCK,
SPI1_MOSI/I2S1_SDO,
I2S2_MCK, AUDIOCLK,
ADC1_INP7, ADC1_INN3,
E3 13 17 17 23 PA7 I/O TT_ah - USART1_RTS,
OPAMP1_VOUT
USART3_RTS, I2S3_MCK,
SPI2_MISO/I2S2_SDI,
USART3_CK, TIM2_CH3,
EVENTOUT
ADC1_INP4,
- - - - 24 PC4 I/O FT_ah - SPI1_RDY, I2S1_MCK,
COMP1_INM1
USART3_RX, EVENTOUT
TIM1_CH4N,
SPI1_SCK/I2S1_CK, ADC1_INP8, ADC1_INN4,
- - - - 25 PC5 I/O TT_ah -
COMP1_OUT, OPAMP1_VINM
LPTIM2_CH1, EVENTOUT
55/174
56/174 Pin Number
25 32 48 N48 64
TIM1_CH2N, TIM3_CH3, ADC1_INP9, ADC1_INN5,

- 14 18 18 26 PB0 I/O FT_ah - LPTIM1_IN1, USART2_TX, OPAMP1_VINP,
TIM1_ETR, EVENTOUT COMP1_INP2
TIM1_CH3N, TIM3_CH4,
LPTIM2_ETR, LPTIM1_IN2,
ADC1_INP5,
SPI2_MOSI/I2S2_SDO,
- 15 19 19 27 PB1 I/O FT_ah - OPAMP1_VINM,
USART2_RX,
COMP1_INM2
COMP1_OUT, TIM1_CH1,
EVENTOUT
RTC_OUT2, TIM1_CH2N,
LPTIM1_CH2, SPI1_RDY,
LPTIM1_CH1,
DS14053 Rev 3
- - 20 20 28 PB2 I/O FT_ah - SPI2_SCK/I2S2_CK, COMP1_INP3, LSCO

SPI3_MOSI/I2S3_SDO,
USART2_CK, TIM2_CH1,
EVENTOUT
TIM2_CH3, LPTIM2_IN1,
I2C2_SCL,
SPI2_SCK/I2S2_CK,
SPI3_NSS/I2S3_WS,
- - 21 21 29 PB10 I/O FT_fh - -
USART3_TX, I3C1_SDA,
FDCAN1_TX, I3C2_SCL,
I2C1_SDA, USART3_CK,
E2 16 22 22 30 VCAP S - - - -
- - 23 23 31 VSS S - - - -
- 17 24 24 32 VDD S - - - -
STM32H503xx
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
- - 25 25 33 PB12 I/O FT_h - -
USART3_CK, USART1_CK,
FDCAN1_RX, EVENTOUT
STM32H503xx
Pin Number
25 32 48 N48 64
TIM1_CH1N, LPTIM2_CH1,
I2C2_SDA,
SPI2_SCK/I2S2_CK,
- - 26 26 34 PB13 I/O FT_fh - USART3_CTS/USART3_N -
SS, LPUART1_CTS,
FDCAN1_TX, I3C2_SDA,
I2C1_SMBA, EVENTOUT
TIM1_CH2N, LPTIM1_ETR,
USART1_TX,
SPI2_MISO/I2S2_SDI,
- - 27 27 35 PB14 I/O FT_h - -
USART3_RTS,
LPUART1_RTS,
DS14053 Rev 3
EVENTOUT
RTC_REFIN, TIM1_CH3N,
LPTIM1_CH1, LPTIM2_IN2,
USART1_RX,
SPI2_MOSI/I2S2_SDO,
SPI3_MISO/I2S3_SDI,
USART3_CTS/USART3_N
E1 18 28 28 36 PB15 I/O FT_ah - PVD_IN
SS, LPUART1_RX,
FDCAN1_TX, I2S3_MCK,
USART2_RTS,
COMP1_OUT,
USART2_RX, TIM3_CH4,
EVENTOUT
TIM1_CH1, TIM3_CH1,
I3C2_SCL, I2C1_SMBA,
- - - - 37 PC6 I/O FT_fh - I2S2_MCK, I2C2_SCL, -
FDCAN1_RX, USART2_TX,
EVENTOUT
57/174
58/174 Pin Number
25 32 48 N48 64
TRGIO, TIM1_CH2,
TIM3_CH2, I3C2_SDA,
SPI1_MOSI/I2S1_SDO,
- - - - 38 PC7 I/O FT_fh - -
I2S3_MCK, I2C2_SDA,
FDCAN1_TX, USART2_RX,
EVENTOUT
TRACED1, TIM1_CH3,
TIM3_CH3, I3C1_SCL,
I2C1_SCL,
- - - - 39 PC8 I/O FT_fh - -
SPI1_NSS/I2S1_WS,
I2C2_SMBA, FDCAN1_RX,
USART2_CK, EVENTOUT
DS14053 Rev 3
MCO2, TIM1_CH4,
TIM3_CH4, I3C1_SDA,
I2C1_SDA, AUDIOCLK,
- - - - 40 PC9 I/O FT_fh - SPI3_RDY, USART3_RTS, -
FDCAN1_TX,
USART2_CTS/USART2_N
SS, EVENTOUT
MCO1, TIM1_CH1,
TIM3_CH3, LPTIM2_IN1,
USART2_TX, SPI1_RDY,
SPI2_MOSI/I2S2_SDO,
USART1_CK,
C1 19 29 29 41 PA8 I/O FT_hs - LPUART1_CTS, -
FDCAN1_RX, USB_SOF,
SPI2_NSS/I2S2_WS,
SPI1_SCK/I2S1_CK,
USART3_TX, TIM1_CH4N,
STM32H503xx
EVENTOUT
STM32H503xx
Pin Number
25 32 48 N48 64
TRACED2, TIM1_CH2,
LPUART1_TX,
SPI1_MISO/I2S1_SDI,
D1 20 30 30 42 PA9 I/O FT_hs - SPI2_SCK/I2S2_CK, -
USART1_TX,
SPI3_MOSI/I2S3_SDO,
USART3_CK, EVENTOUT
TIM1_CH3, LPUART1_RX,
- - 31 31 43 PA10 I/O FT_h - LPTIM2_IN2, USART1_RX, -
EVENTOUT
TRGIO, TIM1_CH4,
TIM3_CH2,
DS14053 Rev 3
LPUART1_CTS,
USART2_RX,
SPI2_NSS/I2S2_WS,
B1 21 32 32 44 PA11 I/O FT_h - SPI3_RDY, -
USART1_CTS/USART1_N
SS, USART1_RX,
FDCAN1_RX, USB_DM,
USART3_RTS,
TRACED3, TIM1_ETR,
TIM3_CH4,
LPUART1_RTS,
USART2_TX,
A1 22 33 33 45 PA12 I/O FT_h - SPI2_SCK/I2S2_CK, -
SPI2_RDY, USART1_RTS,
USART1_TX, FDCAN1_TX,
USB_DP, USART3_RX,
TIM2_CH4, EVENTOUT
59/174
60/174 Pin Number
25 32 48 N48 64
JTMS/SWDIO, TIM1_CH1,
LPTIM1_CH1,
USART1_RX,
D2 23 34 34 46 PA13(JTMS/SWDIO) I/O FT_h (3)
LPUART1_CTS, -
USART2_RX,
COMP1_OUT, TIM1_ETR,
EVENTOUT
- - 35 35 47 VSS S - - - -
- - 36 36 48 VDD S - - - -
JTCK/SWCLK, TIM1_CH2,
TIM3_CH1, LPTIM2_CH1,
DS14053 Rev 3
LPTIM1_ETR,
C2 24 37 37 49 PA14(JTCK/SWCLK) I/O FT_h (3)
USART1_TX, -
LPUART1_RTS,
USART2_TX, TIM1_CH4N,
EVENTOUT
JTDI, TIM2_CH1,
LPTIM1_IN2, LPTIM2_CH1,
USART2_CK,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
(3) SPI2_MISO/I2S2_SDI,
A2 25 38 38 50 PA15(JTDI) I/O FT_hs -
USART1_CTS/USART1_N
SS, USART2_RX,
SPI3_SCK/I2S3_CK,
USART2_RTS,
USART3_RX, TIM2_ETR,
EVENTOUT
STM32H503xx
STM32H503xx
Pin Number
25 32 48 N48 64
TIM1_BKIN2, I3C2_SCL,
SPI1_MISO/I2S1_SDI,
SPI3_SCK/I2S3_CK,
- - - - 51 PC10 I/O FT_fh - -
USART3_TX, I2C2_SCL,
FDCAN1_RX,
USART2_RTS, EVENTOUT
TIM2_CH2, I3C2_SDA,
I2C1_SMBA, SPI1_RDY,
- - - - 52 PC11 I/O FT_fh - SPI3_MISO/I2S3_SDI, -
USART3_RX, I2C2_SDA,
TIM1_BKIN2, EVENTOUT
TRACED3, TIM2_CH4,
DS14053 Rev 3
LPTIM1_CH1,
LPTIM2_CH2,
- - - - 53 PC12 I/O FT_h - -
SPI3_MOSI/I2S3_SDO,
USART3_CK, I2C2_SMBA,
TIM1_CH4, EVENTOUT
TRACED2, TIM2_CH3,
TIM3_ETR,
SPI3_NSS/I2S3_WS,
- - - - 54 PD2 I/O FT_h - -
USART3_CTS/USART3_N
SS, USART2_RTS,
TIM2_ETR, EVENTOUT
JTDO/TRACESWO,
TIM2_CH2, LPTIM1_CH1,
I3C2_SCL, I2C2_SDA,
SPI1_SCK/I2S1_CK,
(3)
D3 26 39 39 55 PB3(JTDO/TRACESWO) I/O FT_fhs SPI3_SCK/I2S3_CK, -
I2S2_MCK, I2C2_SCL,
FDCAN1_RX, CRS_SYNC,
I2C1_SMBA, USART3_TX,
TIM1_BKIN, EVENTOUT
61/174
62/174 Pin Number
25 32 48 N48 64
NJTRST, TIM1_CH4N,
TIM3_CH1, I3C2_SDA,
LPTIM1_CH2,
SPI1_MISO/I2S1_SDI,
C4 27 40 40 56 PB4(NJTRST) I/O FT_fhs (3)
SPI3_MISO/I2S3_SDI, -
SPI2_NSS/I2S2_WS,
I2C2_SDA, FDCAN1_TX,
TIM1_CH2, EVENTOUT
TRACECLK, TIM1_CH3,
TIM3_CH2, I3C2_SCL,
I2C1_SMBA,
DS14053 Rev 3
SPI1_MOSI/I2S1_SDO,
SPI2_MISO/I2S2_SDI,
B3 28 41 41 57 PB5 I/O FT_fhs - -
SPI3_MOSI/I2S3_SDO,
I2C2_SCL, FDCAN1_RX,
I3C1_SDA, I2C1_SDA,
USART2_RX, LPTIM1_IN1,
EVENTOUT
TRACED0, TIM1_CH3N,
TIM3_CH3, I3C1_SCL,
I2C1_SCL, I2S1_MCK,
SPI3_RDY, USART1_TX,
B4 29 42 42 58 PB6 I/O FT_fhs - LPUART1_TX, -
FDCAN1_TX,
USART2_CTS/USART2_N
SS, USART2_CK,
TIM1_CH2, EVENTOUT
STM32H503xx
STM32H503xx
Pin Number
25 32 48 N48 64
TRACED1, TIM1_CH2N,
TIM3_ETR, I3C1_SDA,
I2C1_SDA, AUDIOCLK,
SPI3_SCK/I2S3_CK,
A4 30 43 43 59 PB7 I/O FT_fhs - USART1_RX, WKUP5
LPUART1_RX,
FDCAN1_TX, I2S3_MCK,
TIM1_CH1, EVENTOUT
A3 31 44 44 60 BOOT0 I B - - -
TRACED2, TIM1_BKIN2,
LPTIM1_CH2, I3C1_SCL,
DS14053 Rev 3
I2C1_SCL, SPI2_RDY,
I2S2_MCK, USART1_CK,
A5 32 45 45 61 PB8 I/O FT_fhs - I2C2_SDA, FDCAN1_RX, -
I3C2_SDA, I2C2_SMBA,
SPI1_NSS/I2S1_WS,
USART3_RX,
- - 46 46 62 VCAP S - - - -
- - 47 47 63 VSS S - - - -
- 1 48 48 64 VDD S - - - -
B2 - - - - VDDIO2 S - - - -
1. PC13, PC14 and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current, the use of PC13 to PC15 GPIOs in output
mode is limited: - The speed must not exceed 2 MHz with a maximum load of 30 pF. These GPIOs must not be used as current sources (for example to drive a LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the
system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the product reference manual.
3. After reset, these pins are configured as JTAG/SW debug alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are
activated too.
63/174
4.3 Alternate functions
64/174
Table 11. Alternate function AF0 to AF7(1)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Port
I3C1/2/LPTIM2/ I2C1/2/LPTIM1/2/SPI LPTIM1/SPI1/I2S1/ SPI1/I2S1/SPI2/I2S SPI2/I2S2/SPI3/I2S3
SYS TIM1/2 LPTIM1/TIM3
LPUART1 1/I2S1/USART1/2 SPI2/I2S2 2/SPI3/I2S3 /USART1/2/3
USART2_CTS/USA
PA0 RTC_OUT2 TIM2_CH1 TIM3_CH1 LPTIM2_ETR LPTIM1_ETR LPTIM1_IN2 SPI3_RDY
RT2_NSS
PA1 - TIM2_CH2 - - SPI1_NSS/I2S1_WS LPTIM1_IN1 SPI3_SCK/I2S3_CK USART2_RTS
SPI3_MISO/I2S3_S
PA2 - TIM2_CH3 TIM3_ETR LPUART1_RX SPI1_SCK/I2S1_CK LPTIM1_IN2 USART2_TX
DI
SPI2_NSS/I2S2_W SPI3_MOSI/I2S3_S
PA3 - TIM2_CH4 - LPUART1_TX SPI1_MISO/I2S1_SDI USART2_RX
S DO
DS14053 Rev 3
TIM1_CH2 SPI1_MOSI/I2S1_SD SPI1_NSS/I2S1_W SPI3_NSS/I2S3_W

PA4 - - LPTIM2_CH1 USART2_CK
N O S S
PA5 - TIM2_CH1 LPTIM1_ETR LPTIM2_CH2 LPTIM1_CH1 SPI1_SCK/I2S1_CK I2S1_MCK SPI2_SCK/I2S2_CK
TIM1_ SPI1_MISO/I2S1_S
PA6 - TIM3_CH1 - - - -
BKIN DI
Port A
TIM1_ SPI1_MOSI/I2S1_S
PA7 - TIM3_CH2 LPTIM2_ETR I2S1_MCK I2S2_MCK AUDIOCLK
CH1N DO
SPI2_MOSI/I2S2_S
PA8 MCO1 TIM1_CH1 TIM3_CH3 LPTIM2_IN1 USART2_TX SPI1_RDY USART1_CK
DO
PA9 TRACED2 TIM1_CH2 - LPUART1_TX SPI1_MISO/I2S1_SDI SPI2_SCK/I2S2_CK - USART1_TX
PA10 - TIM1_CH3 - LPUART1_RX LPTIM2_IN2 - - USART1_RX
SPI2_NSS/I2S2_W USART1_CTS/USA
PA11 TRGIO TIM1_CH4 TIM3_CH2 LPUART1_CTS USART2_RX SPI3_RDY
S RT1_NSS
PA12 TRACED3 TIM1_ETR TIM3_CH4 LPUART1_RTS USART2_TX SPI2_SCK/I2S2_CK SPI2_RDY USART1_RTS
STM32H503xx
PA13 JTMS/SWDIO TIM1_CH1 LPTIM1_CH1 - - - - USART1_RX
PA14 JTCK/SWCLK TIM1_CH2 TIM3_CH1 LPTIM2_CH1 LPTIM1_ETR - - USART1_TX
SPI1_NSS/I2S1_W SPI3_NSS/I2S3_W SPI2_MISO/I2S2_S
PA15 JTDI TIM2_CH1 LPTIM1_IN2 LPTIM2_CH1 USART2_CK
S S DI
Table 11. Alternate function AF0 to AF7(1) (continued)
STM32H503xx
Port
TIM1_CH2
PB0 - TIM3_CH3 - LPTIM1_IN1 - - -
N
TIM1_CH3 SPI2_MOSI/I2S2_S
PB1 - TIM3_CH4 LPTIM2_ETR - LPTIM1_IN2 -
N DO
TIM1_CH2 SPI3_MOSI/I2S3_S
PB2 RTC_OUT2 LPTIM1_CH2 - SPI1_RDY LPTIM1_CH1 SPI2_SCK/I2S2_CK
N DO
JTDO/TRACE
PB3 TIM2_CH2 LPTIM1_CH1 I3C2_SCL I2C2_SDA SPI1_SCK/I2S1_CK SPI3_SCK/I2S3_CK I2S2_MCK
SWO
TIM1_CH4 SPI1_MISO/I2S1_S SPI3_MISO/I2S3_S
PB4 NJTRST TIM3_CH1 I3C2_SDA LPTIM1_CH2 SPI2_NSS/I2S2_WS
N DI DI
DS14053 Rev 3
SPI1_MOSI/I2S1_S SPI2_MISO/I2S2_S SPI3_MOSI/I2S3_S

PB5 TRACECLK TIM1_CH3 TIM3_CH2 I3C2_SCL I2C1_SMBA
DO DI DO
TIM1_CH3
PB6 TRACED0 TIM3_CH3 I3C1_SCL I2C1_SCL I2S1_MCK SPI3_RDY USART1_TX
N
Port B
TIM1_CH2
PB7 TRACED1 TIM3_ETR I3C1_SDA I2C1_SDA AUDIOCLK SPI3_SCK/I2S3_CK USART1_RX
N
TIM1_BKI
PB8 TRACED2 LPTIM1_CH2 I3C1_SCL I2C1_SCL SPI2_RDY I2S2_MCK USART1_CK
N2
SPI3_NSS/I2S3_W
PB10 - TIM2_CH3 - LPTIM2_IN1 I2C2_SCL SPI2_SCK/I2S2_CK USART3_TX
S
TIM1_BKI SPI2_NSS/I2S2_W
PB12 - - - I2C2_SMBA - USART3_CK
N S
TIM1_CH1 USART3_CTS/USA
PB13 - - LPTIM2_CH1 I2C2_SDA SPI2_SCK/I2S2_CK -
N RT3_NSS
TIM1_CH2 SPI2_MISO/I2S2_S
PB14 - LPTIM1_ETR - USART1_TX - USART3_RTS
N DI
TIM1_CH3 SPI2_MOSI/I2S2_S SPI3_MISO/I2S3_S USART3_CTS/USA
PB15 RTC_REFIN LPTIM1_CH1 LPTIM2_IN2 USART1_RX
N DO DI RT3_NSS
65/174
66/174 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Port
PC0 - TIM1_ETR LPTIM1_CH2 - - SPI1_SCK/I2S1_CK - SPI2_RDY

SPI2_MOSI/I2S2_S USART1_CTS/USA
PC1 TRACED0 - TIM3_ETR - SPI1_NSS/I2S1_WS -
DO RT1_NSS
PWR_ SPI2_MISO/I2S2_S
PC2 - - - SPI1_MISO/I2S1_SDI - USART1_RTS
CSLEEP DI
SPI1_MOSI/I2S1_SD SPI2_MOSI/I2S2_S USART2_CTS/USA
PC3 PWR_CSTOP - - LPUART1_TX -
O DO RT2_NSS
PC4 - TIM2_CH4 - LPTIM2_ETR SPI1_RDY I2S1_MCK - USART3_RX
TIM1_CH4
PC5 - - - - SPI1_SCK/I2S1_CK - -
N
DS14053 Rev 3
PC6 - TIM1_CH1 TIM3_CH1 I3C2_SCL I2C1_SMBA I2S2_MCK - -

SPI1_MOSI/I2S1_S
PC7 TRGIO TIM1_CH2 TIM3_CH2 I3C2_SDA - I2S3_MCK -
Port C
DO
SPI1_NSS/I2S1_W
PC8 TRACED1 TIM1_CH3 TIM3_CH3 I3C1_SCL I2C1_SCL - -
S
PC9 MCO2 TIM1_CH4 TIM3_CH4 I3C1_SDA I2C1_SDA AUDIOCLK SPI3_RDY USART3_RTS
TIM1_BKI SPI1_MISO/I2S1_S
PC10 - - I3C2_SCL - SPI3_SCK/I2S3_CK USART3_TX
N2 DI
SPI3_MISO/I2S3_S
PC11 - TIM2_CH2 - I3C2_SDA I2C1_SMBA SPI1_RDY USART3_RX
DI
SPI3_MOSI/I2S3_S
PC12 TRACED3 TIM2_CH4 LPTIM1_CH1 LPTIM2_CH2 - - USART3_CK
DO
PC13 - - - - - - - -
PC14 - - - - - - - -
STM32H503xx
PC15 - - - - - - - -
Port D
SPI3_NSS/I2S3_W USART3_CTS/USA
PD2 TRACED2 TIM2_CH3 TIM3_ETR - - -
S RT3_NSS
STM32H503xx
Port
PH0 - - - - - - - -
Port H
PH1 - - - - - - - -
1. Refer to the next table for AF8 to AF15.
DS14053 Rev 3
67/174
Table 12. Alternate function AF8 to AF15(1)
Port
I2C2/I3C1/LPUA FDCAN1/USAR CRS/I3C1/2/SPI I2C1/2/SPI2/I2S COMP/SPI1/I2S LPTIM1/2/TIM1/
USART2/3 SYS
RT1/USART1 T2/3 3/I2S3/USB 2/USART2 1 2/3
USART1_CTS/U USART3_CTS/U SPI3_NSS/I2S3 SPI1_MISO/I2S

PA0 I2S2_MCK USART3_CK TIM2_ETR EVENTOUT
SART1_NSS SART3_NSS _WS 1_SDI
PA1 USART1_RX USART2_CK - SPI2_RDY - - TIM1_CH3 EVENTOUT
PA2 USART1_TX - - - - - TIM1_CH4 EVENTOUT
PA3 USART1_CK - - - - USART3_RX TIM1_CH1N EVENTOUT
SPI3_MISO/I2S
PA4 USART1_RTS - - - USART3_TX TIM1_BKIN EVENTOUT
3_SDI
SPI3_MOSI/I2S USART2_CTS/U
PA5 LPUART1_RTS USART2_TX - USART3_RX TIM2_ETR EVENTOUT
3_SDO SART2_NSS
DS14053 Rev 3
PA6 - - - - - - - EVENTOUT
SPI2_MISO/I2S
PA7 USART1_RTS USART3_RTS I2S3_MCK - USART3_CK TIM2_CH3 EVENTOUT
Port A
2_SDI
SPI2_NSS/I2S2 SPI1_SCK/I2S1
PA8 LPUART1_CTS FDCAN1_RX USB_SOF USART3_TX TIM1_CH4N EVENTOUT
_WS _CK
SPI3_MOSI/I2S
PA9 - - - - USART3_CK - EVENTOUT
3_SDO
PA10 - - - - - - - EVENTOUT
PA11 USART1_RX FDCAN1_RX USB_DM - - USART3_RTS LPTIM2_CH2 EVENTOUT
PA12 USART1_TX FDCAN1_TX USB_DP - - USART3_RX TIM2_CH4 EVENTOUT
PA13 LPUART1_CTS USART2_RX - - COMP1_OUT - TIM1_ETR EVENTOUT
PA14 LPUART1_RTS USART2_TX - - - - TIM1_CH4N EVENTOUT
USART1_CTS/U SPI3_SCK/I2S3
STM32H503xx
PA15 USART2_RX USART2_RTS - USART3_RX TIM2_ETR EVENTOUT
SART1_NSS _CK
STM32H503xx
Port
USART2/3 SYS
PB0 - USART2_TX - - - - TIM1_ETR EVENTOUT

PB1 - USART2_RX - - COMP1_OUT - TIM1_CH1 EVENTOUT
PB2 - USART2_CK - - - - TIM2_CH1 EVENTOUT
PB3 I2C2_SCL FDCAN1_RX CRS_SYNC I2C1_SMBA - USART3_TX TIM1_BKIN EVENTOUT
PB4 I2C2_SDA FDCAN1_TX - I2C1_SMBA - USART2_TX TIM1_CH2 EVENTOUT
PB5 I2C2_SCL FDCAN1_RX I3C1_SDA I2C1_SDA - USART2_RX LPTIM1_IN1 EVENTOUT
USART2_CTS/U
PB6 LPUART1_TX FDCAN1_TX - - USART2_CK TIM1_CH2 EVENTOUT
SART2_NSS
Port B
PB7 LPUART1_RX FDCAN1_TX I2S3_MCK I2C2_SMBA - USART3_TX TIM1_CH1 EVENTOUT

DS14053 Rev 3
SPI1_NSS/I2S1
PB8 I2C2_SDA FDCAN1_RX I3C2_SDA I2C2_SMBA USART3_RX LPTIM2_CH1 EVENTOUT
_WS
PB10 I3C1_SDA FDCAN1_TX I3C2_SCL I2C1_SDA - USART3_CK LPTIM2_CH2 EVENTOUT
PB12 USART1_CK FDCAN1_RX - - - - - EVENTOUT
PB13 LPUART1_CTS FDCAN1_TX I3C2_SDA I2C1_SMBA - - - EVENTOUT
PB14 LPUART1_RTS - - - - - - EVENTOUT
PB15 LPUART1_RX FDCAN1_TX I2S3_MCK USART2_RTS COMP1_OUT USART2_RX TIM3_CH4 EVENTOUT
69/174
Port
USART2/3 SYS
PC0 - - - - - - - EVENTOUT
PC1 LPUART1_CTS - - - - - LPTIM2_IN1 EVENTOUT
PC2 LPUART1_RTS - - - - - - EVENTOUT
PC3 - - - - - - LPTIM2_IN2 EVENTOUT
PC4 - - - - - - - EVENTOUT
PC5 - - - - COMP1_OUT - LPTIM2_CH1 EVENTOUT
PC6 I2C2_SCL FDCAN1_RX - - - USART2_TX - EVENTOUT
PC7 I2C2_SDA FDCAN1_TX - - - USART2_RX - EVENTOUT
Port C
DS14053 Rev 3
PC8 I2C2_SMBA FDCAN1_RX - - - USART2_CK - EVENTOUT

USART2_CTS/U
PC9 - FDCAN1_TX - - - - EVENTOUT
SART2_NSS
PC10 I2C2_SCL FDCAN1_RX - - - USART2_RTS - EVENTOUT
PC11 I2C2_SDA - - - - - TIM1_BKIN2 EVENTOUT
PC12 I2C2_SMBA - - - - - TIM1_CH4 EVENTOUT
PC13 - - - - - - - EVENTOUT
PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT
Port H Port D
PD2 - USART2_RTS - - - - TIM2_ETR EVENTOUT
PH0 - - - - - - - EVENTOUT
STM32H503xx
PH1 - - - - - - - EVENTOUT
1. Refer to the previous table for AF0 to AF7.
STM32H503xx Electrical characteristics
5 Electrical characteristics
5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage, and frequencies by tests in production
on 100% of the devices with an ambient temperature at TJ = 25 °C and TJ = TJmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes, and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2 Typical values

Unless otherwise specified, typical data is based on TJ = 25 °C, VDD = VDDA = 3.3 V (for the
1.71 ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.
5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9. Pin loading conditions Figure 10. Pin input voltage
MCU pin MCU pin

C = 50 pF VIN
MS19210V1 MS19211V1
DS14053 Rev 3 71/174

154
Electrical characteristics STM32H503xx
5.1.6 Power supply scheme
Figure 11. Power supply scheme
STM32H503
VCAP1/2 Core domain

ȝ) 100 nF
LDO enabled LDO disabled

(Bypass)
Two different possible use cases LDO
Voltage VDDLDO
regulator
VDDIO2(1) VDDIO2
ȝ)
100 nF VDDIO2
IOs
Two different possible use cases VDD

100 nF VDD
IOs
VDD
VDD
ȝ)
100 nF VDD
domain
VSS Power switch
Backup
Two different possible use cases VSW
VBAT domain
Battery ȝ) 100 nF
BKUP
IOs
VDDA VDDA/VREF+
Analog domain
ȝ) 100 nF
VREF+
VREF-
VSSA/VREF-
Defines different use case options
Define power domains
1.: Dedicated VDDIO2 supply pin is only available on WLCSP25 package; it represents the external power supply
for nine I/Os (PA8, PA9, PA15, and PB[3:8]). On packages without VDDIO2 pin, those I/Os are supplied by VDD.
MS71332V2
Caution: If there are two VCAP pins (such as the LQFP64 package), each pin must be connected to
a 2.2 μF (typical) capacitor (for a total around 4.4 μF). If only one VCAP pin is available, it
must be connected to a 4.7 µF capacitor.
72/174 DS14053 Rev 3

Note: Refer to “Getting started with STM32H5 MCU hardware development” (AN5711) for more
details.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA, and so on) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device. It is not recommended to remove filtering capacitors to reduce
PCB size or cost. This might cause incorrect operation of the device.
5.1.7 Current consumption measurement

The IDD parameters given in various tables in the next sections represent the total MCU
consumption including the current supplying VDD, VDDIO2, VDDA, and VBAT.
Figure 12. Current consumption measurement scheme
LDO ON
IDD_VBAT
VBAT
VDDIO2
IDD
VDD
VDDA
MSv71333V2
5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics,
Table 14: Current characteristics, and Table 15: Thermal characteristics can cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with the JEDEC JESD47 qualification standard. Extended mission profiles are
available on demand.
Table 13. Voltage characteristics(1)

Symbol Ratings Min Max Unit
External main supply voltage (including

VDDx - VSS -0.3 4.0 V
VDD(2)(3)(4), VDDA, and VDDIO2, and VBAT)
I/O supply when HSLV= 0 -0.3 4.0
VDDIOx(3)- VSS V
I/O supply when HSLV = 1 -0.3 2.75
DS14053 Rev 3 73/174

154
Table 13. Voltage characteristics(1) (continued)

Symbol Ratings Min Max Unit
min (min(VDD, VDDA,

Input voltage on FT_xxx pins VSS-0.3
VDDIO2) + 4.0, 6.0 V)(6)(7)
min (min(VBAT, VDDA,
Input voltage on FT_t in VBAT mode VSS-0.3
VDDIO2) + 4.0, 6.0 V)(6)(7)
VIN(5) V
Input voltage on TT_xx pins VSS-0.3 4.0
min (min(VDD, VDDA,
Input voltage on BOOT0 pin VSS-0.3
VDDIO2) + 4.0, 6.0 V)(3)(4)
Input voltage on any other pins VSS-0.3 4.0
Variations between different VDDX power pins
|∆VDDx| - 50.0
of the same domain
mV
Variations between all the different ground
|VSSx-VSS| - 50.0
pins
1. All main power (VDD, VDDA, VDDIO2, and VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supply, in the permitted range.
2. If HSLV = 0.
3. VDDIO1 or VDDIO2. VDDIO1 = VDD.
4. HSLV = High-speed low-voltage mode. Refer to “General-purpose I/Os” (GPIO) section of RM0492.
5. VIN maximum must always be respected. Refer to for the maximum allowed injected current values.
6. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
7. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
Table 14. Current characteristics

Symbol Ratings Max Unit
∑IVDD (1)
Total current into sum of all VDD power lines (source) 200
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 200
IVDD Maximum current into each VDD power pin (source)(1) 100
(1)
IVSS Maximum current out of each VSS ground pin (sink) 100
IIO(PIN) Output current sunk/sourced by any I/O and control pin 20 mA
Total output current sunk by sum of all I/Os and control pins(2) 140
∑IIO(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 140
IINJ(PIN)(3)(4) Injected current on FT_xxx, TT_xx, NRST pins -5 / 0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VDDIO2, and VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 13:
Voltage characteristics for the minimum allowed input voltage values.
74/174 DS14053 Rev 3

5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).
Table 15. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C

TJ Maximum junction temperature 130(1) °C
1. The junction temperature is limited to 105 °C in the VOS0 voltage range.
5.3 Operating condition
5.3.1 General operating conditions

Table 16. General operating conditions
Symbol Parameter Operating conditions Min Typ Max Unit
HSLV(1) = 0 1.71(2) - 3.6 V

Standard operating
VDD
voltage
HSLV(1) = 1 1.71(2) - 2.7 V
At least one I/O in PA8, PA9, PA15

1.08 - 3.6
and PB[3:8] is used, HSLV(1) = 0
PA8, PA9, PA15 and
At least one I/O in PA8, PA9, PA15
VDDIO2(3) PB[3:8] I/Os supply 1.08 - 2.7 V
and PB[3:8] is used, HSLV(1) = 1
voltage
PA8, PA9, PA15, and PB[3:8] are
0 - 3.6
not used, HSLV(1) = 0
COMP is used 1.62 -
DAC is used 1.8 -
VDDA Analog supply voltage OPAMP is used 2.0 - 3.6 V
ADC is used 1.62 -
ADC, DAC, OPAMP, and COMP

0 -
are not used
VBAT Backup operating voltage - 1.2 - 3.6 V
DS14053 Rev 3 75/174

154
Table 16. General operating conditions (continued)

min (min (VDD,

All I/O except TT_xx -0.3 - VDDA, VDDIO2) +
3.6V, 5.5 V)(4)(5)
VIN I/O input voltage min (min (VBAT, V
Input voltage on FT_t in VBAT
-0.3 - VDDA, VDDIO2) +
mode
3.6 V, 5.5 V)(4)(5)
TT_xx I/O -0.3 VDDIOx + 0.3
(6)
VOS0 1.30 1.35 1.40
VOS1 1.15 1.20 1.26
Internal regulator ON V
VOS2 1.05 1.10 1.15
VOS3 0.95 1.00 1.05
Regulator OFF: VOS0(6) 1.32 1.35 1.40

VCORE external VCORE voltage VOS1 1.17 1.20 1.26
must be supplied from V
external regulator on VOS2 1.07 1.10 1.15
VCAP pins. VOS3 0.97 1.00 1.05
SVOS3 - 1.0 -
Stop mode SVOS4 - 0.9 - V
SVOS5 - 0.74 -
(6)
VOS0 - - 250
VOS1 - - 200
fHCLK AHB clock frequency MHz
VOS2 - - 150
VOS3 - - 100
VOS0(6) - - 250
fPCLKx APB1, APB2, APB3 clock VOS1 - - 200

MHz
(x=1,2,3) frequency VOS2 - - 150
VOS3 - - 100
76/174 DS14053 Rev 3

Table 16. General operating conditions (continued)

WLCSP25 - - 557.62
UFQFPN32 - - 1122.19
Power dissipation at
UFQFPN48 - - 1525.42 mW
TA = 85 °C for suffix 6(8)
LQFP48 - - 831.79
LQFP64 - - 920.25
WLCSP25 - - 309.79
UFQFPN32 - - 623.44
(7) Power dissipation at
PD UFQFPN48 - - 847.46 mW
LQFP48 - - 462.11
LQFP64 - - 511.25
WLCSP25 - - 61.96
UFQFPN32 - - 124.69
Power dissipation at
UFQFPN48 - - 169.49 mW
LQFP48 - - 92.42
LQFP64 - - 102.25
Ambient temperature for
Maximum power dissipation - 85
the suffix 6 version
TA Maximum power dissipation -40 - 105 °C
Ambient temperature for
the suffix 7 version LDO bypass mode,
- 125
or in low dissipation at 125 °C (9)
VOS0 -40 - 105
Junction temperature Suffix 6 and 7
TJ VOS1, VOS2, and °C
range version -40 - 130
VOS3
1. IO_VDD_HSLV option byte to be used for all I/Os, which are supplied by VDD pin except PA8, PA9, PA15, and PB[3:8]
I/Os. IO_VDDIO2_HSLV option byte to be used for PA8, PA9, PA15, and PB[3:8] I/Os, which are supplied by the VDDIO2
pin. When the VDDIO2 power supply pin is not available, enabling HSLV on PA8, PA9, PA15, and PB[3:8] pins is still
possible via the IO_VDDIO2_HSLV option byte.
2. When RESET is released, the functionality is guaranteed down to VPDR minimum.
3. Dedicated power supply pin VDDIO2 is only available on the WLCSP25 package.
4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum
I/O input voltage is the smallest value between min (VDD, VDDA, VDDIO2) + 3.6 V and 5.5 V.
5. For operation with voltage higher than min (VDD, VDDA, VDDIO2) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
6. In VOS0 mode, the max TJ is 105 °C.
7. PDmax is calculated based on relevant ΘJA (characterized in line with JEDEC51-2), for further details, see Section 6.7:
Package thermal characteristics and the AN5036.
8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 6.7: Package thermal
characteristics).
9. In the low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 6.7:
Package thermal characteristics).
DS14053 Rev 3 77/174

154
Table 17. Maximum allowed clock frequencies

(1)(2) VOS1
Symbol Parameter VOS0 VOS2 VOS3 Unit
fCPU CPU 250 200 150 100
fHCLK AHB 250 200 150 100
fPCLK APB 250 200 150 100
ffdcan_ker_ck FDCAN 250 200 150 100
fI2C_ker_ck I2C[1:2] 250 200 150 100
fI3C_ker_ck I3C[1:2] 250 200 150 100
flptim_ker_ck LPTIM[1:2] 250 200 150 100
frcc_tim_ker_ck TIM[1:3],TIM[6:7] 250 200 150 100

MHz
frng_clk RNG 50 50 50 50
fspi_ker_ck SPI[1:3] 250 200 150 100
flpuart_ker_ck LPUART1 250 200 150 100
fusart_ker_ck USART1/2/3 250 200 150 100
fusb_ker_ck USB 50 50 50 50
fadc_ker_ck ADC 125 100 75 50
fdac_pclk DAC 250 200 150 100
frtc_ker_ck RTC 1 1 1 1
1. Specified by design - Not tested in production.

2. The maximum kernel clock frequencies can be limited by the maximum peripheral clock frequency (refer to
each peripheral electrical characteristic).
5.3.2 VCAP external capacitor

Stabilization for the embedded LDO regulator is achieved by connecting an external
capacitor CEXT to the VCAPx (one or two pins depending on the packages). CEXT is
specified in Table 18: VCAP operating condition. Two external capacitors must be
connected to VCAP pins (for more information, refer to the AN5711 (Getting started with
STM32H5 MCU hardware development).
78/174 DS14053 Rev 3

Figure 13. External capacitor CEXT
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
Table 18. VCAP operating condition

Symbol Parameter Conditions
CEXT External capacitor for LDO enabled 2.2 μF(1)
ESR ESR of external capacitor < 100 mΩ
1. This value corresponds to the CEXT typical value. A variation of ±20 % is tolerated.
When the internal LDO voltage regulator is switched OFF, the two 2.2 μF VCAP capacitors
are not required. However, all VCAPx package pins must be connected and it is
recommended to add a ceramic filtering capacitor of 100 nF as close as possible to each
VCAPx pin.
DS14053 Rev 3 79/174

154
5.3.3 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.
Operating conditions at power-up / power-down (regulator ON)
Table 19. Operating conditions at power-up/power-down (regulator ON)

Symbol Parameter Min Max Unit
VDD rise time rate 0 ∞

TVDD
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞

TVDDA
VDDA fall time rate 10 ∞
μs/V
TVDDIO2 rise time rate 0 ∞
TVDDIO2
TVDDIO2 fall time rate 10 ∞
TVBAT rise time rate 0 ∞

TVBAT
TVBAT fall time rate 10 ∞
80/174 DS14053 Rev 3

5.3.4 Embedded reset and power control block characteristics

The parameters given in Table 20: Embedded reset and power control block characteristics
are derived from tests performed under ambient temperature and VDD supply voltage
conditions summarized in Table 16: General operating conditions.
Table 20. Embedded reset and power control block characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit
Reset temporization after POR is

tRSTTEMPO(2) VDD rising - 377 550 μs
detected
Power-on/power-down reset threshold Rising edge 1.62 1.67 1.71

VPOR/PDR
(BORH_EN =0) Falling edge 1.58 1.62 1.68
Brownout reset threshold 1 Rising edge 2.04 2.10 2.15

VBOR1

VBOR2

VBOR3
Programmable voltage detector (PVD) Rising edge 1.90 1.96 2.01

VPVD0
threshold 0 Falling edge 1.81 1.86 1.91

VPVD1 V

VPVD2

VPVD3

VPVD4

VPVD5

VPVD6
Hysteresis for power-on/power-down Hysteresis in run
VPOR/PDR - 43 -
reset mode
mV
Hysteresis voltage of BOR (unless Hysteresis in run
Vhyst_BOR_PVD - 100 -
BORH_EN = 0) and PVD mode
IDD_BOR_PVD(2) BOR and PVD consumption from VDD - - - 0.630
µA
IDD_POR_PDR POR and PDR consumption from VDD - 0.8 - 1.2
DS14053 Rev 3 81/174

154
Table 20. Embedded reset and power control block characteristics(1) (continued)
Rising edge 1.66 1.71 1.76

VAVD0 VDDA voltage monitor 0 threshold
Falling edge 1.56 1.61 1.66
Rising edge 2.06 2.12 2.19
VAVD1 VDDA voltage monitor 1threshold
V
Rising edge 2.42 2.50 2.58
Rising edge 2.74 2.83 2.91
VIO2VM VDDIO2 voltage monitor threshold - - 0.9 - V
Vhyst_AVD Hysteresis of VDDA voltage detector - - 100 - mV
Power voltage detector consumption
IDD_AVD_IO2VM(2) - - - 0.25
from VDD (AVD, IO2VM)
VDDA analog voltage detector µA
IDD_AVD_A (2) consumption from VDDA (resistor - - - 0.25
bridge)
1. Evaluated by characterization and not tested in production, unless otherwise specified.
5.3.5 Embedded reference voltage

The parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in Table 21.
Table 21. Embedded reference voltage

VREFINT(1) Internal reference voltage -40 °C < TJ < +130 °C 1.180 1.216 1.255 V
ADC sampling time when reading the
tS_vrefint(2)(3) - 4.3 - -
internal reference voltage
VBAT sampling time when reading the
tS_vbat 9 - - µs
internal VBAT voltage
Start time of reference voltage buffer
tstart_vrefint(3) - - - 4.4
when the ADC is enabled
Irefbuf(3) Reference buffer consumption for ADC VDD = 3.3 V 9 13.5 23 µA
Internal reference voltage spread
∆VREFINT(3) -40°C < TJ < +130 °C - 5 15 mV
over the temperature range
Average temperature
TCoeff Average temperature coefficient - 20 70 ppm/°C
coefficient
VDDcoeff Average voltage coefficient 3.0 V < VDD < 3.6 V - 10 1370 ppm/V
82/174 DS14053 Rev 3

Table 21. Embedded reference voltage (continued)

(3)
VREFINT_DIV1 1/4 reference voltage - 25 -
%
VREFINT_DIV2(3) 1/2 reference voltage - - 50 -
VREFINT
VREFINT_DIV3(3) 3/4 reference voltage - 75 -
1. VREFINT does not take into account package and soldering effects.
2. The shortest sampling time for the application can be determined by multiple iterations.
Table 22. Internal reference voltage calibration value

Symbol Parameter Memory address
VREFINT_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 0x08FF F810 - 0x08FF F811
5.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 12: Current consumption
measurement scheme.
All the run mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The flash memory access time is adjusted with the minimum wait-state number,
depending on the fHCLK frequency (refer to the table “FLASH recommended number of
wait states and programming delay” available in the reference manual).
• When the peripherals are enabled, fPCLK = HCLK.
The parameters given in the below tables are derived from tests performed under supply
voltage conditions summarized in Table 16: General operating conditions and unless
otherwise specified at ambient temperature.
The typical and maximum current consumptions provided in the following tables are given
for LDO regulator ON.
DS14053 Rev 3 83/174

154
running from flash memory, 2-ways instruction cache ON, PREFETCH ON
Parameter Max(1)
Symbol
fHCLK Typ
Conditions Unit
(MHz) LDO TJ = TJ = TJ = TJ =
25°C 85°C 105°C 130°C
250 25.5 27.16 34.76 41.26 -

VOS0 215 22.0 23.57 31.24 37.75 -
200 20.0 21.63 29.37 35.89 -
200 17.5 18.67 23.89 28.64 37.39
180 16.0 17.19 22.45 27.21 35.94
VOS1
All peripherals 168 14.5 15.83 21.13 25.88 34.60
disabled 150 13.5 14.25 19.59 24.34 33.04
150 12.0 13.01 17.12 20.98 28.19
VOS2
100 8.5 9.11 13.34 17.20 24.40
100 7.8 8.36 11.57 14.70 20.62
VOS3 60 5.0 5.52 8.81 11.92 17.82
IDD Supply current
25 2.5 2.96 6.31 9.41 15.30 mA
(Run) in run mode
250 43.0 45.89 53.12 59.58 -
VOS0 215 37.0 39.68 47.02 53.51 -
200 34.0 36.63 44.04 50.54 -
200 30.0 31.82 36.69 41.41 50.19
VOS1 180 27.5 29.02 33.97 38.70 47.47
All peripherals
150 22.5 24.09 29.17 33.91 42.66
enabled
150 20.5 21.99 25.82 29.66 36.90
VOS2
100 14.0 15.08 19.13 22.99 30.20
100 13.0 13.77 16.81 19.92 25.84
VOS3 60 8.2 8.73 11.94 15.05 20.96
25 3.8 4.28 7.60 10.69 16.59
1. Evaluated by characterization - Not tested in production.
84/174 DS14053 Rev 3

running from flash memory, 1-way instruction cache ON, PREFETCH ON
Parameter Max(1)
Symbol
fHCLK Typ
Conditions Unit
25°C 85°C 105°C 130°C
250 22.5 24.26 31.96 38.49 -

VOS0
200 17.7 19.32 27.14 33.65 -
200 15.5 16.67 21.97 26.74 35.48
VOS1 180 14.3 15.40 20.73 25.50 34.24
All peripherals
150 11.8 12.76 18.16 22.93 31.65
disabled
150 10.9 11.66 15.83 19.71 26.93
VOS2
IDD Supply current 100 7.6 8.24 12.51 16.37 23.58
mA
(Run) in run mode 100 6.9 7.48 10.77 13.89 19.83
VOS3
25 2.3 2.76 6.12 9.23 15.14
VOS0 250 40.3 42.96 50.28 56.78 -
200 28.1 29.79 34.74 39.48 48.27
All peripherals VOS1
180 25.6 27.20 32.22 36.96 45.75
enabled
VOS2 150 19.5 20.62 24.52 28.38 35.63
VOS3 100 12.1 12.90 15.98 19.10 25.05
DS14053 Rev 3 85/174

154
running from SRAM with cache 1-WAY
Parameter Max(1)
Symbol
fHCLK Typ
Conditions Unit
25°C 85°C 105°C 130°C
250 21.5 23.20 30.91 37.44 -

VOS0 215 18.6 20.14 27.95 34.46 -
200 17.0 18.47 26.29 32.79 -
200 14.9 15.90 21.21 25.98 34.73
VOS1 180 13.7 14.72 20.06 24.83 33.57
IDD Supply current All peripherals
150 11.3 12.19 17.61 22.37 31.11 mA
(Run) in run mode disabled
150 10.4 11.15 15.33 19.20 26.43
VOS2
100 7.2 7.90 12.17 16.04 23.25
100 6.7 7.20 10.47 13.59 19.53
VOS3 60 4.3 4.81 8.15 11.27 17.20
25 2.2 2.69 6.05 9.16 15.07
86/174 DS14053 Rev 3

running from SRAM with cache 2-WAY
Parameter Max(1)
Symbol
fHCLK Typ
Conditions Unit
25°C 85°C 105°C 130°C
250 24.6 26.30 33.94 40.48 -

VOS0 215 21.2 22.80 30.54 37.06 -
200 19.4 20.93 28.70 35.19 -
200 17.0 18.04 23.28 28.05 36.84
180 15.6 16.62 21.92 26.70 35.45
VOS1
IDD Supply current All peripherals 168 14.3 15.31 20.64 25.43 34.17
mA
(Run) in run mode disabled 150 12.8 13.78 19.15 23.92 32.66
150 11.8 12.57 16.71 20.58 27.82
VOS2
100 8.2 8.83 13.08 16.95 24.18
100 7.6 8.10 11.33 14.47 20.42
VOS3 60 4.9 5.37 8.67 11.81 17.73
25 2.4 2.90 6.26 9.37 15.29
DS14053 Rev 3 87/174

154
Table 27. Typical current consumption in run mode with CoreMark
Parameter
Conditions
Symbol
fHCLK Typ Typ

Unit Unit
(MHz) LDO LDO
Peripheral Code
250 25.5 102.0

200 17.5 87.5
All peripherals disabled,
instruction cache 2-WAY, FLASH 168 14.5 86.3
prefetch ON
150 12.0 80.0
100 7.8 78.0
250 22.5 90.0
All peripherals disabled, 200 15.5 77.5
instruction cache 1-WAY, FLASH
prefetch ON 150 10.9 72.7
IDD Supply current 100 6.9 69.0

mA μA/MHz
(Run) in run mode 250 26.1 104.4
200 17.0 85.0
SRAM 168 14.3 85.1
instruction cache 2-WAY
150 11.8 78.7
100 7.6 76.0
250 21.5 86.0
All peripherals disabled, 200 14.9 74.5

SRAM
instruction cache 1-WAY 150 10.4 69.3
100 6.7 67.0
88/174 DS14053 Rev 3

Table 28. Typical current consumption in run mode with SecureMark running from flash memory
Parameter
Conditions
Symbol
fHCLK Typ Typ

Unit Unit
(MHz) LDO LDO
Peripheral Code
250 27.2 108.8

180 17.3 96.4
prefetch ON
150 13.3 88.5
IDD Supply current 100 8.5 85.4

mA μA/MHz
(Run) in run mode 250 24.6 98.3
180 15.7 87.3
prefetch ON
150 12.1 80.5
100 7.8 77.7
Table 29. Typical and maximum current consumption in sleep mode

Max(1)
Parameter
Symbol
fHCLK Typ
Conditions Unit
25°C 85°C 105°C 130°C
250 5.1 6.34 14.19 20.59 -

VOS0
200 3.9 5.06 12.91 19.29 -
200 3.4 4.14 9.65 14.33 22.95
180 3.4 4.14 9.65 14.33 22.95
VOS1
IDD Supply current All peripherals 168 2.9 3.68 9.19 13.87 22.48
mA
(sleep) in sleep mode disabled 150 2.7 3.42 8.94 13.61 22.22
150 2.5 3.00 7.36 11.17 18.31
VOS2
100 2.0 2.50 6.86 10.67 17.79
100 1.8 2.20 5.63 8.71 14.59
VOS3
60 1.4 1.83 5.27 8.35 14.21
DS14053 Rev 3 89/174

154
Table 30. Typical and maximum current consumption in stop mode
Max(1)
Parameter
Symbol
Typ
Conditions Unit
LDO TJ = TJ = TJ = TJ =
25°C 85°C 105°C 130°C
SVOS3 0.088 0.38 3.05 5.48 10.15

Flash memory in
low power mode, SVOS4 0.070 0.28 2.33 4.26 8.04
SRAM1/2 ON
SVOS5 0.054 0.18 1.60 3.01 5.82
Flash memory in SVOS3 0.103 0.40 3.07 5.51 10.19
normal mode,
Supply SRAM1/2 ON SVOS4 0.085 0.29 2.35 4.29 8.08
IDD
current in mA
(stop) stop SVOS3 0.085 0.37 2.99 5.37 9.95
Flash memory in
low power mode, SVOS4 0.068 0.27 2.29 4.18 7.88
SRAM1/2 OFF
SVOS5 0.052 0.17 1.56 2.91 5.64
Flash memory in SVOS3 0.100 0.39 3.02 5.40 9.99
normal mode,
SRAM1/2 OFF SVOS4 0.083 0.29 2.31 4.21 7.93
Table 31. Typical and maximum current consumption in standby mode
Conditions Typ Max(1)

Parameter
Symbol
Unit
RTC
Backup TJ = TJ = TJ = TJ =
and 1.8 V 2.4 V 3V 3.3 V
RAM 25 °C 85 °C 105 °C 130 °C
LSE(2)
OFF OFF 2.47 2.66 2.91 3.05 4.02 8.05 13.86 30.71
Supply current
IDD in standby ON OFF 3.49 3.73 4.01 4.20 5.67 12.90 22.16 48.95
μA
(standby) mode, OFF ON 2.84 3.05 3.31 3.49 - - - -
IWDG OFF
ON ON 3.86 4.12 4.44 4.66 - - - -
2. LSE is in medium low-drive mode.
90/174 DS14053 Rev 3

Table 32. Typical and maximum current consumption in VBAT mode
Conditions Typ (V) Max(1) (°C)
Parameter
Symbol
Unit
RTC
Backup TJ = TJ = TJ = TJ =
and 1.62 2 3 3.3
RAM 25 85 105 130
LSE(2)
OFF OFF 0.01 0.01 0.02 0.03 0.10 1.34 3.39 9.76
IDD Supply current ON OFF 0.73 0.86 1.07 1.16 1.98 8.33 14.91 34.23
μA
(VBAT) in VBAT mode OFF ON 0.32 0.35 0.38 0.45 - - - -
ON ON 1.33 1.39 1.52 1.65 - - - -
2. LSE is in medium low-drive mode.
I/O system current consumption

I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 53: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins, which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption

In addition to the internal peripheral current consumption, the I/Os used by an application
also contribute to the current consumption. When an I/O pin switches, it uses the current
from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the
capacitive load (internal or external) connected to the pin:
I SW = V DDx × f SW × C L
DS14053 Rev 3 91/174

154
Where:
• ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
• VDDx is the MCU supply voltage
• fSW is the I/O switching frequency
• CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• fHCLK is the CPU clock.
The given value is calculated by measuring the difference of current consumption:
• With all peripherals clocked off
• With only one peripheral clocked on
• fHCLK = 250 MHz (scale 0), fHCLK = 200 MHz (scale 1), fHCLK = 150 MHz (scale 2),
fHCLK= 100 MHz (scale 3)
• The ambient operating temperature and supply voltage conditions are summarized in
Table 16: General operating conditions
Table 33. Peripheral current consumption in sleep mode

IDD (typ)
BUS Peripheral Unit
VOS0 VOS1 VOS2 VOS3
SRAM1 0.69 0.60 0.55 0.51

BKPSRAM 1.01 0.89 0.81 0.74
GTZC1 1.12 0.98 0.90 0.81
ICACHE 0.84 0.75 0.68 0.62
AHB1 RAMCFG 0.48 0.41 0.38 0.35 μA/MHz
CRC 0.35 0.31 0.28 0.27
FLASH 7.88 6.89 6.28 5.71
GPDMA2 0.33 0.29 0.26 0.25
GPDMA1 0.43 0.38 0.35 0.32
92/174 DS14053 Rev 3

Table 33. Peripheral current consumption in sleep mode (continued)

IDD (typ)
BUS Peripheral Unit
VOS0 VOS1 VOS2 VOS3
SRAM2 0.95 0.85 0.77 0.70

RNG 0.81 0.72 0.66 0.59
HASH 0.87 0.77 0.71 0.64
DAC1 1.18 1.04 0.95 0.86
ADC1 1.30 1.15 1.05 0.95
AHB2 μA/MHz
GPIOH 0.08 0.08 0.07 0.06
GPIOD 0.05 0.05 0.04 0.03
GPIOC 0.06 0.05 0.05 0.04
GPIOB 0.09 0.07 0.07 0.06
GPIOA 0.06 0.05 0.05 0.04
FDCAN SRAM 3.14 2.76 2.51 2.29
FDCAN1 3.20 2.82 2.58 2.34
LPTIM2 0.91 0.81 0.72 0.67
DTS 1.49 1.31 1.20 1.11
CRS 0.24 0.22 0.18 0.18
I3C1 0.31 0.29 0.25 0.24
I2C2 0.63 0.57 0.50 0.47
I2C1 0.61 0.54 0.48 0.44
USART3 1.35 1.19 1.08 0.99
APB1 USART2 1.37 1.22 1.10 1.35 μA/MHz
COMP 0.23 0.21 0.17 0.17
SPI3/I2S3 1.08 0.96 0.85 0.78
SPI2/I2S2 1.10 0.97 0.87 0.79
OPAMP 0.13 0.13 0.10 0.10
WWDG 1.18 0.17 0.14 0.13
TIM7 0.57 0.51 0.46 0.42
TIM6 0.54 0.49 0.44 0.40
TIM3 2.44 2.15 1.96 1.78
TIM2 2.81 2.49 2.27 2.07
USB 2.49 2.17 1.99 1.80
USART1 1.34 1.18 1.08 0.97
APB2 μA/MHz
SPI1/I2S1 1.15 1.01 0.93 0.83
TIM1 4.39 3.87 3.55 3.23
DS14053 Rev 3 93/174

154
Table 33. Peripheral current consumption in sleep mode (continued)

IDD (typ)
BUS Peripheral Unit
VOS0 VOS1 VOS2 VOS3
RTC 1.72 1.51 1.38 1.26

LPTIM1 0.92 0.82 0.75 0.68
APB3 μA/MHz
I3C2 0.31 0.28 0.25 0.23
SBS 0.45 0.40 0.37 0.34
Wakeup time from low-power modes

The wakeup times given in Table 34: Low-power mode wakeup timings are measured
starting from the wakeup event trigger up to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PA1) pin is used to wakeup from Standby, Stop, and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.0 V.
Table 34. Low-power mode wakeup timings(1)

Symbol Parameter Conditions Typ Max Unit
Instruction cache enabled 15 16 CPU

Wakeup time from
tWUSLEEP clock
sleep Instruction cache disabled 15 16 cycles
SVOS3, HSI 64MHz, flash memory in normal mode 4.0 4.8
SVOS3, HSI 64MHz, flash memory in low-power mode 7.9 11.5
SVOS4, HSI 64MHz, flash memory in normal mode 13.8 16.0
SVOS4, HSI 64MHz, flash memory in low-power mode 17.7 21.9
Wakeup time from SVOS5, HSI 64MHz, flash memory in low-power mode 31.4 36.8
tWUSTOP
stop mode SVOS3, CSI 4MHz, flash memory in normal mode 25.5 31.0 µs
SVOS3, CSI 4MHz, flash memory in low power mode 27.7 34.2
SVOS4, CSI 4MHz, flash memory in normal mode 35.3 40.8
SVOS4, CSI 4 MHz, flash memory in low-power mode 37.5 44.0
SVOS5, CSI 4 MHz, flash memory in low-power mode 51.2 58.9
Wakeup time from
tWUSTBY VCAP capacitors discharged 506.0 653.6
standby mode
94/174 DS14053 Rev 3

5.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the Table 35: High-speed external user clock
characteristics in addition to Table 53: I/O static characteristics. The external clock can be
low-swing (analog) or digital. In case of a low-swing analog input clock, the clock squarer
must be activated (refer to RM0492).
Table 35. High-speed external user clock characteristics(1)

User external clock External digital/analog

fHSE_ext 4 25 50 MHz
source frequency clock
Digital OSC_IN input
VHSEH 0.7 VDD - VDD
high-level voltage
External digital clock V
Digital OSC_IN input
VHSEL VSS - 0.3 VDD
low-level voltage
tw(HSEH)/tw(HSEL) Digital OSC_IN input
(2) External digital clock 7 - - ns
high or low time
Visw(HSEH) Analog low-swing

(3) OSC_IN peak-to-peak 0.2 - 2/3 VDD V
(VHSEH -VHSEH) External analog low
amplitude
swing clock
Analog low-swing
DuCyHSE 45 50 55 %
OSC_IN duty cycle
Analog low-swing External analog low
tr(HSE)/tf(HSE) OSC_IN rise and fall swing clock, 10% to 0.05 / fHSE_ext - 0.3 / fHSE_ext ns
times 90%
2. The rise and fall times for a digital input signal are not specified. However, the VHSEH and VHSEL conditions must be fulfilled.
3. The DC component of the signal must ensure that the signal peaks are located between VDD and VSS.
DS14053 Rev 3 95/174

154
Figure 14. High-speed external clock source AC timing diagram
VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t
THSE
External fHSE_ext
IL
clock source OSC_IN
STM32
ai17528b
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the Table 36: Low-speed external user clock
characteristics in addition to Table 53: I/O static characteristics. The external clock can be
low-swing (analog) or digital. In case of a low-swing analog input clock, the clock squarer
must be activated (refer to RM0492).
Table 36. Low-speed external user clock characteristics(1)

User external clock source

fLSE_ext External digital/analog clock - 32.768 1000 kHz
frequency
Digital OSC32_IN input
VLSEH 0.7 VDD - VDD
high-level voltage
External digital clock V
OSC32_IN input low-level
VLSEL VSS - 0.3 VDD
voltage
OSC32_IN high or low
tw(LSEH)/tw(LSEL) External digital clock 250 - - ns
time
Analog low-swing OSC_IN
Vlsw_H 0.6 - 1.225
high-level voltage
Vlsw_L 0.35 - 0.8 V
low-level voltage External analog low swing
VlswLSE Analog low-swing OSC_IN clock
0.2 - 0.875
(VLSEH -VLSEL) peak-to-peak amplitude
DuCyLSE 45 50 55 %
duty cycle
Analog low-swing OSC_IN External analog low swing
tr(LSE)/tf(LSE) - 100 200 ns
rise and fall times clock, 10% to 90%
96/174 DS14053 Rev 3

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 15. Low-speed external clock source AC timing diagram
VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t
TLSE
External fLSE_ext
OSC32_IN IL
clock source
STM32
ai17529b
DS14053 Rev 3 97/174

154
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic
resonator oscillator.
All the information given in this paragraph are based on characterization results obtained
with the typical external components specified in Table 37. In the application, the resonator
and the load capacitors have to be placed as close as possible to the oscillator pins in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package,
accuracy).
Table 37. HSE oscillator characteristics(1)

Operating
Symbol Parameter Min Typ Max Unit
conditions(2)
F Oscillator frequency - 4 - 50 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 10
VDD = 3 V,
Rm = 20 Ω, - 0 -
CL = 10 pF at 4 MHz
VDD = 3 V,
Rm = 20 Ω, - 0 -
CL = 10 pF@8 MHz
IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 20 Ω, - 1 -
CL = 10 pF@16 MHz
VDD = 3 V,
Rm = 20 Ω, - 1 -
CL = 10 pF@32 MHz
VDD = 3 V,
Rm = 20 Ω, - 1 -
CL = 10 pF@48 MHz
Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment that it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
design guide for ST microcontrollers” available from the ST website www.st.com.
98/174 DS14053 Rev 3

Figure 16. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain
REXT(1) OSC_OU T STM32

CL2
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 38. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
DS14053 Rev 3 99/174

154
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

Symbol Parameter Conditions(2) Min Typ Max Unit
F Oscillator frequency - - 32.768 - kHz

LSEDRV[1:0] = 01
- 333.000 -
Medium low drive capability
LSEDRV[1:0] = 10
IDD LSE current consumption - 462.000 - nA
Medium high drive capability
LSEDRV[1:0] = 11
- 747.000 -
High drive capability
LSEDRV[1:0] = 01
- - 0.75
Medium low drive capability
LSEDRV[1:0] = 10
Gmcritmax Maximum critical crystal gm - - 1.7 µA/V
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Specified by design - Not tested in production, unless otherwise specified.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
STM8AF/AL/S, STM32 MCUs and MPUs”.
3. tSU(LSE) is the startup time measured from the moment that it is enabled (by software) to a stabilized 32.768 kHz oscillation
is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.
design guide for STM8AF/AL/S, STM32 MCUs and MPUs available from the ST website
www.st.com.
Figure 17. Typical application with a 32.768 kHz crystal

Resonator with
integrated capacitors CL1
OSC32_IN fHSE
Bias
32.768 kHz
RF controlled
resonator
gain
OSC32_OUT
STM32
CL2
ai17531c
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
100/174 DS14053 Rev 3

5.3.8 Internal clock source characteristics

The parameters given in Table 39: HSI48 oscillator characteristics to Table 42: LSI oscillator
characteristics are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 16: General operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
Table 39. HSI48 oscillator characteristics

fHSI48 (1) (1)

HSI48 frequency VDD=3.3 V, TJ=30 °C 47.5 48 48.5 MHz
TRIM(2) User trimming step - - 0.175 0.250
USER TRIM %
User trimming coverage ± 32 steps ±4.70 ±5.6 -
COVERAGE(3)
DuCy(HSI48)(2) Duty Cycle - 45 - 55 %
Accuracy of the HSI48
ACCHSI48_REL(3)(4) oscillator over temperature TJ= -40 to 130 °C -4.5 - 4 %
(reference is 30 °C)
HSI48 oscillator frequency VDD= 3.0 to 3.6 V - 0.025 0.05 %
∆VDD(HSI48)(2) drift with VDD (reference is
3.3 V) VDD= 1.71 to 3.6 V - 0.05 0.1 %
tsu(HSI48)(2) HSI48 oscillator start-up time - - 2.1 4.0 μs
HSI48 oscillator power
IDD(HSI48)(2) - - 350 400 μA
consumption
Next transition jitter
NT jitter(2) accumulated jitter on 28 - - ±0.15 - ns
cycles
Paired transition jitter
PT jitter(2) accumulated jitter on 56 - - ±0.25 - ns
cycles(5)
1. Calibrated during manufacturing tests.
4. ∆fHSI = ACCHSI48_REL + ∆VDD.
5. Jitter measurements are performed without clock sources activated in parallel.
DS14053 Rev 3 101/174

154
64 MHz high-speed internal RC oscillator (HSI)
Table 40. HSI oscillator characteristics(1)

fHSI HSI frequency VDD=3.3 V, TJ=30 °C 63.7(2) 64(2) 64.3(2) MHz

Trimming is not a
- 0.24 0.32
multiple of 32(3)
Trimming is 128, 256
-5.2 -1.8 -
and 384(3)
TRIM User trimming step Trimming is 64, 192, %

-1.4 -0.8 -
320 and 488(3)
Other trimming are a
multiple of 32 (not
-0.6 -0.25 -
including multiple of 64
and 128)(3)
DuCy(HSI) Duty cycle - 45 - 55 %
HSI oscillator frequency drift
∆VDD(HSI) VDD= 1.71 to 3.6 V -0.12 - 0.03 %
with VDD (reference is 3.3 V)
HSI oscillator frequency drift TJ= -20 to 105 °C -1(4) - 1(4) %
∆TEMP(HSI) with VDD (reference is 64
MHz) TJ= -40 to 130 °C -2(4) - 1(4) %
tsu(HSI) HSI oscillator start-up time - - 1.4 2 μs
at 1% of target
- 4 8
HSI oscillator stabilization frequency
tstab(HSI) μs
time at 5% of target
- - 4
frequency
HSI oscillator power
IDD(HSI) - - 300 450 μA
consumption
3. Trimming value of HSICAL[8:0.]
4. Evaluated by characterization. Not tested in production.
102/174 DS14053 Rev 3

4 MHz low-power internal RC oscillator (CSI)
Table 41. CSI oscillator characteristics(1)

fCSI CSI frequency VDD=3.3 V, TJ=30 °C 3.96(2) 4 4.04(2) MHz

Trimming is not a
- 0.40 0.75
multiple of 16
Trimming is a multiple
-4.75 -2.75 0.75
of 32
TRIM User trimming step %
Other trimming are a
multiple of 16 (not
-0.43 0.00 0.75
including multiple of
32)
DuCy(CSI) Duty Cycle - 45 - 55 %
CSI oscillator frequency drift TJ= 0 to 85 °C -3.7(3) - 4.5(3) %

∆TEMP(CSI)
over temperature TJ= -40 to 130 °C -11(3) - 7.5(3) %
CSI oscillator frequency drift
∆VDD(CSI) VDD= 1.71 to 3.6 V -0.06 - 0.06 %
over VDD
tsu(CSI) CSI oscillator start-up time - - 1 2 μs
CSI oscillator stabilization
tstab(CSI) - - - 4 Cycle
time (to reach ± 3% of fCSI)
CSI oscillator power
IDD(CSI) - - 23 30 μA
consumption
Low-speed internal (LSI) RC oscillator
Table 42. LSI oscillator characteristics

VDD=3.3 V, TJ= 25 °C 31.4(1) 32 32.6(1)

29.76
fLSI LSI frequency TJ= -40 to 110 °C, VDD=1.71 to 3.6 V (2) - 33.6(2) kHz
TJ= -40 to 130 °C, VDD=1.71 to 3.6 V 29.4(2) - 33.6(2)

tsu(LSI)(3) LSI oscillator start-up time - - 80 130
LSI oscillator stabilization μs
tstab(LSI)(3) - - 120 170
time (5% of final value)
LSI oscillator power
IDD(LSI)(3) - - 130 280 nA
consumption
DS14053 Rev 3 103/174

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5.3.9 PLL characteristics

The parameters given in Table 43 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 16: General operating conditions.
Table 43. PLL characteristics (wide VCO frequency range)(1)

PLL input clock - 2 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1 - 250(2)
PLL multiplier output clock VOS1 1 - 200(2)

fPLL_P_OUT
P, Q, R VOS2 1 - 150(2) MHz
VOS3 1 - 100(2)
fVCO_OUT PLL VCO output - 128 - 560(2)
Normal mode - 45 100(3) μs
tLOCK PLL lock time
Sigma-delta mode (fPLL_IN ≥ 8 MHz) - 60 120(3)
fVCO_OUT = 128 MHz - 60 -
Cycle-to-cycle jitter ±ps
Normal mode (f PLL_IN = 2 MHz),
- ±0.2 -
Jitter fVCO_OUT = 560 MHz
Normal mode (f PLL_IN = 16 MHz),
- ±0.8 -
fVCO_OUT = 560 MHz
Long term jitter %
Sigma-delta mode (f PLL_IN = 2 MHz),
- ±0.2 -
fVCO_OUT = 560 MHz
Sigma-delta mode (f PLL_IN = 16 MHz),
- ±0.8 -
fVCO_OUT = 560 MHz
VDD - 330 420
fVCO_OUT = 560 MHz
PLL power consumption on VCORE - 630 -
IDD(PLL) μA
VDD VDD - 155 230
fVCO_OUT = 128 MHz
VCORE - 170 -
2. This value must be limited to the maximum frequency due to the product limitation.
104/174 DS14053 Rev 3

Table 44. PLL characteristics (medium VCO frequency range)

Symbol Parameter Conditions Min(1) Typ(1) Max(1) Unit
PLL input clock - 1 - 2 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1.17 - 210
PLL multiplier output clock VOS1 1.17 - 210

fPLL_OUT
P, Q, R VOS2 1.17 - 160(2) MHz
(2)
VOS3 1.17 - 88
fVCO_OUT PLL VCO output - 150 - 420
Normal mode - 45 80(3)
tLOCK PLL lock time μs
Sigma-delta mode forbidden
fVCO_OUT = 150 MHz - - 60 -
fVCO_OUT = 200 MHz - - 40 -
Cycle-to-cycle jitter
fVCO_OUT = 400 MHz - - 18 -
±ps
Jitter fVCO_OUT = 420 MHz - - 15 -
fVCO_OUT = 150 MHz fPLL_OUT = - 75 -
Period jitter
fVCO_OUT = 400 MHz 50 MHz - 25 -
Long term jitter Normal mode fVCO_OUT = 400 MHz - ±0.2 - %
VDD - 275 360
fVCO_OUT = 420 MHz
PLL power consumption on VCORE - 450 -
IDD(PLL) μA
VDD VDD - 160 240
fVCO_OUT = 150 MHz
VCORE - 165 -
2. This value must be limited to the maximum frequency due to the product limitation.
5.3.10 Memory characteristics

Flash memory
The characteristics are given at TJ = -40 to 130 °C unless otherwise specified.
The devices are shipped to customers with the flash memory erased.
Table 45. Flash memory characteristics(1)

Word program (50% of bits at 0) - 2.7 -

IDD Supply current Sector erase - 1.7 - mA
Mass erase - 1.7 -
DS14053 Rev 3 105/174

154
Table 46. Flash memory programming(1)

128 bits (user area) - 31 -

tprog Word program time µs
16 bits (OTP area) - 31 -
tERASE Sector erase time (8 Kbytes) - - 2 - ms
Bank erase time - 16 -
tME ms
Mass erase time - 32 -
Vprog Programming voltage 1.71 - 3.6 V
Table 47. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
NEND Endurance TJ = -40 to +130 °C 10 kcycles

1 kcycle at TA = 85 °C 30
tRET Data retention Years
10 kcycles at TA = 55 °C 30
5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports),
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 48. They are based on the EMS levels and classes
defined in application note AN1709 “EMC design guide for STM8, STM32 and legacy
MCUs”.
106/174 DS14053 Rev 3

Table 48. EMS characteristics

Level/
Symbol Parameter Conditions
Class
Voltage limits to be applied on any I/O pin to

VFESD 2B
induce a functional disturbance VDD = 3.3 V, TA = 25 °C,
Fast transient voltage burst limits to be LQFP64, fHCLK = 250 MHz,
VFTB applied through 100 pF on V and V pins conforms to IEC 61000-4-2
DD SS 5A
to induce a functional disturbance
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as

possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on the PCB).
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore, it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015 “Software
techniques for improving microcontrollers EMC performance”).
Electromagnetic interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application,
executing the EEMBC code, is running. This emission test is compliant with the SAE
IEC61967-2 standard, which specifies the test board and the pin loading.
DS14053 Rev 3 107/174

154
Table 49. EMI characteristics

Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
8/250 MHz
0.1 MHz to 30 MHz 13

30 MHz to 130 MHz 6
VDD = 3.6 V, TA = 25 °C, dBµV
SEMI Peak level 130 MHz to 1 GHz 23
LQFP64 package compliant with IEC 61967-2
1 GHz to 2 GHz 10
EMI level 3.5 -
5.3.12 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 50. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)
Electrostatic discharge
TA = 25 °C conforming to
VESD(HBM) voltage (human body All packages 2 2000 V
ANSI/ESDA/JEDEC JS-001
model)
Electrostatic discharge
TA = +25 °C conforming to
VESD(CDM) voltage (charge device All packages C2a 500 V
ANSI/ESDA/JEDEC JS-002
model)
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output, and configurable I/O pin
These tests are compliant with the JESD78 IC latchup standard.
Table 51. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latchup class TJ = 130 °C, conforming to JESD78, II level A
108/174 DS14053 Rev 3

5.3.13 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of -5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 52. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on pins PA4, PA5, and PB1 0 0

IINJ Injected current on pins PB10, and PC6 0 N/A(2) mA
Injected current on all other I/Os 5 N/A
2. Not applicable.
5.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 53: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 16: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Note: For information on GPIO configuration, refer to application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption”, available from the ST
website www.st.com.
DS14053 Rev 3 109/174

154
Table 53. I/O static characteristics(1)

Symbol Parameter Condition Min Typ Max Unit
I/O input low level voltage

- 0.3VDDIOx(2)
except BOOT0
I/O input low level voltage
VIL 1.08 V<VDDIOx<3.6 V - 0.4VDDIOx-0.1(3) V
except BOOT0
BOOT0 I/O input low level
- 0.19VDDIOx + 0.1(3)
voltage
I/O input high level
0.7VDDIOx(2)
voltage except BOOT0
I/O input high level
VIH 1.08 V<VDDIOx<3.6 V 0.52VDDIOx+0.18(3) V
voltage except BOOT0
BOOT0 I/O input high
0.17VDDIOx+0.6(3)
level voltage
TT_xx, FT_xxx and NRST
1.08 V< VDDIOx <3.6 V - 250
I/O input hysteresis
VHYS(3) mV
BOOT0 I/O input
1.71 V< VDD <3.6 V - 200
hysteresis
0< VIN ≤
- - ±200
Max(VDDXXX)(7)
Max(VDDXXX) <
FT_xx Input leakage
VIN ≤ Max(VDDXXX)+ - - 2500
current(3)
1 V) (5)(7) nA
Ileak(4) Max(VDDXXX) < VIN ≤
- - 750
5.5 V (5)(7)
TT_xx Input leakage 0< VIN ≤ Max(VDDXXX)
(7) - - ±200
current
BOOT0 0< VIN ≤ VDDIOx - - 15
Weak pull-up equivalent

RPU VIN=VSS 30 40 50
resistor(6)
kΩ
Weak pull-down
RPD VIN=VDD(7) 30 40 50
equivalent resistor(6)
CIO I/O pin capacitance - - 5 - pF
1. VDDIOx represents VDD or VDDIO2.
2. Compliant with CMOS requirements.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ieak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. VIN must be less than Max(VDDXXX) + 3.6 V.
6. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
7. Max(VDDXXX) is the maximum value of all the I/O supplies.
110/174 DS14053 Rev 3

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 18.
Figure 18. VIL/VIH for all I/Os except BOOT0
2.5
Minimum required
logic level 1 zone
TTL standard requirement VIHmin = 2V
2
IO
xV DD
= 0.7
V IHmin
ent)
uirem
VIN (V) ar d req
OS stand
1.5 n (CM
roductio
d in p VDDIO +
0.18
Teste = 0.52
on VIHm in Undefined input range
on s imulati
Based
1
VDDIO - 0.1
VILmax = 0.4
simulation = 0.3 VDDIO TTL standard requirement VILmax = 0.8V
Based on ent) VILmax
da rd requirem
(CMOS stan
0.5 Tested in production
Minimum required
logic level 0 zone
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Device characteristics VDDIO (V)

Tested thresholds MSv47925V1
Output driving current

The GPIOs (general-purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins, which can drive current, must be limited to
respect the absolute maximum rating specified in Table 5.2: Absolute maximum ratings. In
particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 14: Current characteristics).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 14: Current characteristics).
DS14053 Rev 3 111/174

154
Output voltage levels

Unless otherwise specified, the parameters given in Table 54: Output voltage characteristics
for all I/Os except PC13, PC14 and PC15 and Table 55: Output voltage characteristics for
PC13 are derived from tests performed under ambient temperature and VDD supply voltage
conditions summarized in Table 16: General operating conditions. All I/Os are CMOS and
TTL compliant.
Table 54. Output voltage characteristics for all I/Os except PC13, PC14 and PC15
Symbol Parameter Conditions(1) Min Max Unit
CMOS port(2)
VOL Output low level voltage IIO = 8 mA - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
VOH Output high level voltage IIO = -8 mA VDD−0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOL(3) Output low level voltage IIO = 8 mA - 0.4
2.7 V≤ VDD ≤ 3.6 V
TTL port(2)
VOH (3) Output high level voltage IIO = -8 mA 2.4 -
2.7 V≤ VDD ≤ 3.6 V
IIO = 20 mA
VOL(3) Output low level voltage - 1.3
2.7 V≤ VDD ≤ 3.6 V
IIO = -20 mA
VOH(3) Output high level voltage VDD - 1.3 - V
2.7 V≤ VDD ≤ 3.6 V
IIO = 4 mA
1.71 V≤ VDD ≤ 3.6 V
IIO = -4 mA
VOH (3) Output high level voltage VDD - 0.4 -
1.71 V≤VDD <3.6 V
IIO = 2 mA 0.3 x VDDIO2

VOL(3) Output low level voltage -
1.08 V≤ VDDIO2 ≤ 1.32 V 0.3
IIO = -2 mA
VOH (3) Output high level voltage 0.7 x VDDIO2 -
1.08 V≤VDDIO2 < 1.32 V
IIO = 20 mA
- 0.4
2.3 V≤ VDD ≤3.6 V
Output low level voltage for an IIO = 10 mA

VOLFM+(3) - 0.4
FTf I/O pin in (FT I/O with “f” option) 1.71 V≤ VDD ≤ 3.6 V
IIO = 4.5 mA
- 0.4
1.08 V≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 13:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
112/174 DS14053 Rev 3

Table 55. Output voltage characteristics for PC13(1)

CMOS port(2) IIO = 3 mA

VOL Output low level voltage - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2) IIO = -3 mA
VOH Output high level voltage VDD - 0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2) IIO = 3 mA
2.7 V≤ VDD ≤3.6 V
V
TTL port(2) IIO = -3 mA
VOH(3) Output high level voltage 2.4 -
2.7 V≤ VDD ≤3.6 V
IIO = 1.5 mA
1.71 V≤ VDD ≤ 3.6 V
IIO = −1.5 mA
VOH(3) Output high level voltage VDD - 0.4 -
1.71 V≤ VDD ≤ 3.6 V
Table 56. Output voltage characteristics for PC14 and PC15(1)

CMOS port(2) IIO = 0.5 mA

VOL Output low level voltage - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2) IIO = -0.5 mA
VOH Output high level voltage VDD - 0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2) IIO = 0.5 mA
2.7 V ≤ VDD ≤3.6 V
V
TTL port(2) IIO = -0.5 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤3.6 V
IIO = 0.25 mA
1.71 V ≤ VDD ≤ 3.6 V
IIO = -0.25 mA
VOH(3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD ≤ 3.6 V
DS14053 Rev 3 113/174

154
Output buffer timing characteristics (HSLV option disabled)

The HSLV feature (can be enabled over option bytes IO_VDDIO2_HSLV and
IO_VDD_HSLV) can be used to optimize the I/O speed when the product voltage is below
2.7 V.
Table 57. Output timing characteristics (HSLV OFF)(1)

Speed Symbol Parameter conditions Min Max Unit
C = 50 pF, 2.7 V≤ VDD ≤ 3.6 V - 8

C = 50 pF, 1.71 V≤VDD ≤ 2 V - 5
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 10
C = 40 pF, 1.71 V≤VDD≤ 2 V - 5
C = 30 pF, 2.7 V≤VDD≤ 3.6 V - 12
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V≤VDD≤ 2 V - 5
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 14
C = 20 pF, 1.71 V≤VDD≤ 2 V - 5
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 16
C = 10 pF, 1.71 V≤VDD≤ 2 V - 5
00
C=50 pF, 2.7 V≤ VDD≤3.6 V - 18.0
C = 50 pF, 1.71 V≤VDD ≤ 2 V - 36.0
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 17.0
C = 40 pF, 1.71 V≤VDD≤ 2 V - 34.0
Output high to low level C = 30 pF, 2.7 V≤VDD≤ 3.6 V - 15.5
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V≤VDD≤ 2 V - 32.0
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 14.2
C = 20 pF, 1.71 V≤VDD≤ 2 V - 30.0
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 12.2
C = 10 pF, 1.71 V≤VDD≤ 2 V - 27
114/174 DS14053 Rev 3

Table 57. Output timing characteristics (HSLV OFF)(1) (continued)

C =50 pF, 2.7 V≤ VDD≤3.6 40

C = 50 pF, 1.71 V≤VDD ≤ 2 V - 12
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 45
C = 40 pF, 1.71 V≤VDD≤ 2 V - 14
C = 30 pF, 2.7 V≤VDD≤ 3.6 V - 50
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V≤VDD≤ 2 V - 16
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 55
C = 20 pF, 1.71 V≤VDD≤ 2 V - 18
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 60
C = 10 pF, 1.71 V≤VDD≤ 2 V - 20
01
C=50 pF, 2.7 V≤ VDD≤3.6 V - 6.2
C = 50 pF, 1.71 V≤VDD ≤ 2 V - 11.4
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 5.7
C = 40 pF, 1.71 V≤VDD≤ 2 V - 10.5
tr/tf(4)(5) fall time and output low ns
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 4.5
C = 20 pF, 1.71 V≤VDD≤ 2 V 8.4
C = 10 pF, 2.7 V≤VDD≤ 3.6 V 3.7
C = 10 pF, 1.71 V≤VDD≤ 2 V 7.0
DS14053 Rev 3 115/174

154

C =50 pF, 2.7 V≤ VDD≤3.6 - 80

C = 50 pF, 1.71 V≤VDD ≤ 2 V - 30
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 90
C = 40 pF, 1.71 V≤VDD≤ 2 V - 35
C = 30 pF, 2.7 V≤VDD≤ 3.6 V - 100
Fmax(2)(3) (6) Maximum frequency MHz
C = 30 pF, 1.71 V≤VDD≤ 2 V - 40
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 110
C = 20 pF, 1.71 V≤VDD≤ 2 V - 45
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 133
C = 10 pF, 1.71 V≤VDD≤ 2 V - 50
10
C=50 pF, 2.7 V≤ VDD≤3.6 V - 3.8
C = 50 pF, 1.71 V≤VDD ≤ 2 V - 7.5
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 3.4
C = 40 pF, 1.71 V≤VDD≤ 2 V - 6.6
tr/tf(4)(5)(6) fall time and output low ns
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 2.5
C = 20 pF, 1.71 V≤VDD≤ 2 V - 4.7
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 1.9
C = 10 pF, 1.71 V≤VDD≤ 2 V - 3.7
116/174 DS14053 Rev 3


C =50 pF, 2.7 V≤ VDD≤3.6 - 100

C = 50 pF, 1.71 V≤VDD ≤ 2 V - 40
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 120
C = 40 pF, 1.71 V≤VDD≤ 2 V - 50
C = 30 pF, 2.7 V≤VDD≤ 3.6 V - 140
Fmax(2)(3)(6) Maximum frequency MHz
C = 30 pF, 1.71 V≤VDD≤ 2 V - 60
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 166
C = 20 pF, 1.71 V≤VDD≤ 2 V - 70
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 200
C = 10 pF, 1.71 V≤VDD≤ 2 V - 80
11
C=50 pF, 2.7 V≤ VDD≤3.6 V - 3.3
C = 50 pF, 1.71 V≤VDD ≤ 2 V - 6.3
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 2.8
C = 40 pF, 1.71 V≤VDD≤ 2 V - 5.5
tr/tf(4)(5)(6) fall time and output low ns
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 1.9
C = 20 pF, 1.71 V≤VDD≤ 2 V - 3.7
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 1.4
C = 10 pF, 1.71 V≤VDD≤ 2 V - 3
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45% < Duty cycle < 55%
3. When 2 V < VDD < 2.7 V maximum frequency is between values given for VDD =1.98 V and VDD =2.7 V
4. The fall and rise times are defined between 90% and 10% and between 10 % and 90 % of the output waveform,
respectively.
5. When 2 V < VDD < 2.7 V maximum tr/tf is between values given for VDD = 1.98 V and VDD = 2.7 V
6. Compensation cell enabled.
DS14053 Rev 3 117/174

154
Output buffer timing characteristics (HSLV option enabled)
Table 58. Output timing characteristics (HSLV ON)(1)

C =50 pF, 1.71 V≤VDD≤2 V - 8

C =40 pF, 1.71 V≤VDD≤2 V - 10
Fmax (2) Maximum frequency C =30 pF, 1.71 V≤VDD≤2 V - 12 MHz
C =20 pF, 1.71 V≤VDD≤2 V - 14
C =10 pF, 1.71 V≤VDD≤2 V - 16
00
C =50 pF, 1.71 V≤VDD≤2 V - 17.8
C =40 pF, 1.71 V≤VDD≤2 V - 15.8
Output high to low level
tr/tf(3) fall time and output low C =30 pF, 1.71 V≤VDD≤2 V - 14.4 ns
to high level rise time
C =20 pF, 1.71 V≤VDD≤2 V - 13.1
C =10 pF, 1.71 V≤VDD≤2 V - 11.4
C = 50 pF, 1.71 V≤VDD≤2 V - 40
C = 40 pF, 1.71 V≤VDD≤2 V - 45
Fmax(2) Maximum frequency C = 30 pF, 1.71 V≤VDD≤2 V - 50 MHz
C = 20 pF, 1.71 V≤VDD≤2 V - 55
C =10 pF, 1.71 V≤VDD≤2 V - 60
01
C = 50 pF, 1.71 V≤VDD≤2 V - 7.2
C = 40 pF, 1.71 V≤VDD≤2 V - 6.5
tr/tf(3)(4) fall time and output low C = 30 pF, 1.71 V≤VDD≤2 V - 5.6 ns
C = 20 pF, 1.71 V≤VDD≤2 V - 4.8
C =10 pF, 1.71 V≤VDD≤2 V - 3.8
C = 50 pF, 1.71 V≤VDD≤2 V - 60
C = 40 pF, 1.71 V≤VDD≤2 V - 70
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.71 V≤VDD≤2 V - 90 MHz
C = 20 pF, 1.71 V≤VDD≤2 V - 110
C =10 pF, 1.71 V≤VDD≤2 V - 140
10
C = 50 pF, 1.71 V≤VDD≤2 V - 5.3
C = 40 pF, 1.71 V≤VDD≤2 V - 4.6
(3)(4)
tr/tf fall time and output low C = 30 pF, 1.71 V≤VDD≤2 V - 3.8 ns
C = 20 pF, 1.71 V≤VDD≤2 V - 3.0
C =10 pF, 1.71 V≤VDD≤2 V - 2.2
118/174 DS14053 Rev 3

Table 58. Output timing characteristics (HSLV ON)(1) (continued)

C=50 pF, 1.71 V≤VDD≤2 V - 67

C = 40 pF, 1.71 V≤VDD≤2 V - 100
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.71 V≤VDD≤2 V - 120 MHz
C = 20 pF, 1.71 V≤VDD≤2 V - 155
C=10 pF, 1.71 V≤VDD≤2 V - 200
11
C = 50 pF, 1.71 V≤VDD≤2 V - 5.0
C = 40 pF, 1.71 V≤VDD≤2 V - 4.1
tr/tf(3)(4) fall time and output low C = 30 pF, 1.71 V≤VDD≤2 V - 3.3 ns
C = 20 pF, 1.71 V≤VDD≤2 V - 2.5
C=10 pF, 1.71 V≤VDD≤2 V - 1.8
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
Table 59. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF)(1)
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 1

C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 1
Fmax(2) Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 1 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 1
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 1
00
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 83.0
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 79.0
tr/tf(3) fall time and output low C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 46.0 ns
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 72.0
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 68.0
DS14053 Rev 3 119/174

154
Table 59. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF)(1) (continued)
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 5

C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 5
(2)
Fmax Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 5 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 5
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 5
01
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 24.5
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 22.2
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 17.8
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 15.0
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 10
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 10
Fmax (2) Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 10 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 10
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 10
10
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 16.2
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 14.3
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 10.0
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 7.9
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 20
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 23
(2)(4)
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 28
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 30
11
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 14.0
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 12.0
tr/tf(3)(4) fall time and output low C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 10.0 ns
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 8.0
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 6.0
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
120/174 DS14053 Rev 3

Table 60. Output timing characteristics VDDIO2 1.2 V (HSLV ON)(1)

C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 5

C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 5
Fmax (2)
Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 5 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 5
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 5
00
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 32.5
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 30.0
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 25.0
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 22.5
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 15.0
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 17.5
(2)
Fmax Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 20.0 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 22.5
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 25.0
01
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 14.6
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 12.9
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 9.3
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 7.3
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 25
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 30
Fmax (2)(4)
Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 33 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 44
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 55
10
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 11.6
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 9.7
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 6.1
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 4.3
DS14053 Rev 3 121/174

154
Table 60. Output timing characteristics VDDIO2 1.2 V (HSLV ON)(1) (continued)
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 30

C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 35
(2)(4)
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 55
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 77
11
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 11.1
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 9.2
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 5.4
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 3.6
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
5.3.15 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 53: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 16: General operating conditions.
Table 61. NRST pin characteristics

Weak pull-up equivalent

RPU(2) VIN = VSS 30 40 50 ㏀
resistor(1)
VF(NRST)(2) NRST Input filtered pulse 1.71 V < VDD < 3.6 V - - 50
ns
VNF(NRST)(2) NRST Input not filtered pulse 1.71 V < VDD < 3.6 V 350 - -
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10 % order).
122/174 DS14053 Rev 3

Figure 19. Recommended NRST pin protection
VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53. Otherwise, the reset is not taken into account by the device.
5.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 62. EXTI input characteristics(1)

PLEC Pulse length to event controller - 20 - - ns
5.3.17 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 63 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 16: General operating conditions.
Table 63. 12-bit ADC characteristics(1)(2)

Analog supply voltage

VDDA - 1.62 - 3.6
for ADC ON
Positive reference
VREF+ - 1.62 - VDDA V
voltage
Negative reference
VREF- - VSSA
voltage
fADC ADC clock frequency 1.62 V ≤ VDDA ≤ 3.6 V 1.5 - 37.5 MHz
DS14053 Rev 3 123/174

154
Table 63. 12-bit ADC characteristics(1)(2) (continued)

Resolution =
- 2.50 -
12 bits
Resolution =
Sampling rate for - 2.88 -
10 bits 1.6 V ≤ -40 ≤
All fADC = SMP =
direct channels VDDA ≤ TJ ≤
modes 37.5 MHz 2.5
(VIN[0:5]) Resolution = 3.6 V 130 °C
- 3.41 -
8 bits
fs
with Resolution =
- 4.17 -
6 bits
RAIN=47
MSps
Ω and
Resolution =
CPCB=22 - 2.00 -
12 bits
pF
Resolution =
- 2.31 -
10 bits 1.6 V ≤ -40 ≤
Sampling rate for slow All fADC = SMP =
VDDA ≤ TJ ≤
channels modes 30 MHz 2.5
Resolution = 3.6 V 130 °C
- 2.73 -
8 bits
Resolution =
- 3.33 -
6 bits
1/
tTRIG External trigger period Resolution = 12 bits - - 15
fADC
Conversion voltage
VAIN(3) - 0 - VREF+ V
range
Common mode input VREF/2 - VREF/2

VCMIV - VREF/2 V
voltage 10% +10%
Resolution = 12 bits, TJ = 130 °C (tolerance 4 LSBs - - 321
Resolution = 12 bits, TJ = 125 °C - - 220
Resolution = 10 bits, TJ =130 °C - - 1039
External input Resolution = 10 bits, TJ = 125 °C - - 2100

RAIN(4) Ω
impedance
Internal sample and

CADC - - 3 - pF
hold capacitor
tADCVREG
ADC LDO startup time - - 5 - μs
_STUP
Conversion
tSTAB ADC power-up time LDO already started 1 - -
cycle
tOFF_ 1/
Offset calibration time - 1335
CAL fADC
CKMODE = 00 1.5 2 2.5

Trigger conversion
latency regular and CKMODE = 01 - - 2.5
tLATR injected channels 1/fADC
without conversion CKMODE = 10 - - 2.5
abort
CKMODE = 11 - - 2.25
CKMODE = 00 2.5 3 3.5

Trigger conversion
latency regular CKMODE = 01 - - 3.5
tLATRINJ injected channels 1/fADC
aborting a regular CKMODE = 10 - - 3.5
conversion
CKMODE = 11 - - 3.25
tS Sampling time - 2.5 - 640.5 1/fADC
124/174 DS14053 Rev 3

Table 63. 12-bit ADC characteristics(1)(2) (continued)

Total conversion time

tS +
tCONV (including sampling N bits resolution - - 1/fADC
0.5 + N
time)
fS = 2.5 MSPS - 320 -

ADC consumption on
IDDA_
VDDA and VREF+ fS = 1 MSPS - 190 - μA
D(ADC) Differential mode
fS = 0.1 MSPS - 50 -
fS = 2.5 MSPS - 240 -

ADC consumption on
IDDA_
VDDA and VREF+ fS = 1 MSPS - 150 - μA
SE(ADC) Single-ended mode
fS = 0.1 MSPS - 50 -
fADC= 37.5 MHz - 135 -
fADC= 30 MHz - 110 -
IDD fADC= 25 MHz - 90 -

ADC consumption on
μA
(ADC) VDD
fADC= 12.5 MHz - 45 -
fADC= 6.25 MHz - 22 -
fADC= 3.125 MHz - 11 -

2. The voltage booster on ADC switches must be used for VDDA < 2.7 V (embedded I/O switches).
3. VREF+ is internally connected to VDDA and VREF- to VSSA.
4. The tolerance is 2 LSBs, otherwise it is specified.
Table 64. Minimum sampling time versus RAIN(1)(2)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channel Slow channel(3)
47 3.75E-08 6.12E-08
68 3.94E-08 6.25E-08
100 4.36E-08 6.51E-08
150 5.11E-08 7.00E-08
12 bits
220 6.54E-08 7.86E-08
330 8.80E-08 9.57E-08
470 1.17E-07 1.23E-07
680 1.60E-07 1.65E-07
DS14053 Rev 3 125/174

154
Table 64. Minimum sampling time versus RAIN(1)(2) (continued)

47 3.19E-08 5.17E-08
68 3.35E-08 5.28E-08
100 3.66E-08 5.45E-08
150 4.35E-08 5.83E-08
220 5.43E-08 6.50E-08
330 7.18E-08 7.89E-08
10 bits
470 9.46E-08 1.00E-07
680 1.28E-07 1.33E-07
1000 1.81E-07 1.83E-07
1500 2.63E-07 2.63E-07
2200 3.79E-07 3.76E-07
3300 5.57E-07 5.52E-07
47 2.64E-08 4.17E-08
68 2.76E-08 4.24E-08
100 3.02E-08 4.39E-08
150 3.51E-08 4.66E-08
220 4.27E-08 5.13E-08
330 5.52E-08 6.19E-08
470 7.17E-08 7.72E-08
680 9.68E-08 1.00E-07
8 bits
1000 1.34E-07 1.37E-07
1500 1.93E-07 1.94E-07
2200 2.76E-07 2.74E-07
3300 4.06E-07 4.01E-07
4700 5.73E-07 5.62E-07
6800 8.21E-07 7.99E-07
10000 1.20E-06 1.17E-06
15000 1.79E-06 1.74E-06
126/174 DS14053 Rev 3

Table 64. Minimum sampling time versus RAIN(1)(2) (continued)

47 2.14E-08 3.16E-08
68 2.23E-08 3.21E-08
100 2.40E-08 3.31E-08
150 2.68E-08 3.52E-08
220 3.13E-08 3.87E-08
330 3.89E-08 4.51E-08
470 4.88E-08 5.39E-08
680 6.38E-08 6.79E-08
6 bits
1000 8.70E-08 8.97E-08
1500 1.23E-07 1.24E-07
2200 1.73E-07 1.73E-07
3300 2.53E-07 2.49E-07
4700 3.53E-07 3.45E-07
6800 5.04E-07 4.90E-07
10000 7.34E-07 7.11E-07
15000 1.09E-06 1.05E-06
2. Data valid up to 130 °C, with a 22 pF PCB capacitor, and VDDA = 1.6 V.
3. Slow channels correspond to all ADC inputs except for the fast channels.
Figure 20. ADC conversion timing diagram
CLK
Mux Sampling(1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1/2 SMP Number of CLK clock cycles = ADC resolution / 2
Total conversion time: 0.5 +Tsamp + N/2
1. The sampling time defines the minimum sampling clock cycles (SMP) to be programmed in the ADC (refer to the product reference manual for details).
DS14053 Rev 3 127/174

154
Table 65. ADC accuracy(1)(2)

Fast and Single ended - ±3.5 ±12

ET Total unadjusted error slow
channels Differential - ±2.5 ±7.5
- Single ended - ±3 ±5.5

EO Offset error
- Differential - ±2 ±3.5
- Single ended - ±3.5 ±11
EG Gain error LSB
- Differential ±2.5 ±7
- Single ended - ±0.75 +2/-1
ED Differential linearity error
- Differential - ±0.75 +2/-1
Fast and Single ended - ±2 ±6.5
EL Integral linearity error slow
channels Differential - ±1 ±4
Single ended - 10.8 -

ENOB Effective number of bits Bits
Differential - 11.5 -
Signal-to-noise and Single ended - 68 -

SINAD
distortion ratio Differential - 71 -
Single ended - 70 -
SNR Signal-to-noise ratio dB
Differential - 72 -
Single ended - -70 -
THD Total harmonic distortion
Differential - -80 -
2. ADC DC accuracy values are measured after internal calibration in continuous mode.
Note: ADC accuracy versus negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
the ground) to analog pins, which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 5.3.13: I/O current injection characteristics does not affect the ADC accuracy.
128/174 DS14053 Rev 3

Figure 21. ADC accuracy characteristics
VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA
MSv19880V6
1. Example of an actual transfer curve.

2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
5. EO = Offset error: deviation between the first actual transition and the first ideal one.
6. EG = Gain error: deviation between the last ideal transition and the last actual one.
7. ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
8. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.
Figure 22. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function
VDDA(4) VREF+(4)
I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing
VSS VSS VSSA
MSv67871V3
1. Refer to Table 63: 12-bit ADC characteristics for the values of RAIN, and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 53: I/O static characteristics). A high Cparasitic value downgrades
conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 53: I/O static characteristics for the value of Ilkg.
4. Refer to Figure 11: Power supply scheme.
DS14053 Rev 3 129/174

154
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 23. The 100 nF
capacitors should be ceramic (good quality). They should be placed as close to the chip as
possible.
Figure 23. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32
VREF+/VDDA(1)
1 μF // 100 nF
VREF-/VSSA(1)
MSv50649V1
1. VREF+ input is internally connected to VDDA while VREF- is internally connected to VSSA (refer to Table 2:
STM32H503xx features and peripheral counts).
5.3.18 DAC characteristics
Table 66. DAC characteristics(1)

VDDA Analog supply voltage - 1.8 3.3 3.6

VREF+ Positive reference voltage - 1.80 - VDDA
V
Negative reference
VREF- - - VSSA -
voltage
connected
5 - -
DAC output buffer to VSSA
RL Resistive Load
ON connected kΩ
25 - -
to VDDA
RO Output Impedance DAC output buffer OFF 10.3 13 16
Output impedance VDD = 2.7 V - - 1.6
DAC output buffer
RBON sample and hold mode, kΩ
ON VDD = 2.0 V - - 2.6
output buffer ON
Output impedance VDD = 2.7 V - - 17.8
DAC output buffer
RBOFF sample and hold mode, kΩ
OFF VDD = 2.0 V - - 18.7
output buffer OFF
130/174 DS14053 Rev 3

Table 66. DAC characteristics(1) (continued)

CL DAC output buffer OFF - - 50 pF

Capacitive Load
CSH Sample and Hold mode - 0.1 1 µF
VDDA
Voltage on DAC_OUT DAC output buffer ON 0.2 -
VDAC_OUT −0.2 V
output
DAC output buffer OFF 0 - VREF+
±0.5 LSB - 2.05 3
Settling time (full scale:
for a 12-bit code transition Normal mode, DAC ±1 LSB - 1.97 2.87
between the lowest and output buffer ON,
±2 LSB - 1.67 2.84
the highest input codes CL ≤ 50 pF,
tSETTLING RL ≥ 5 ㏀ ±4 LSB - 1.66 2.78 µs
when DAC_OUT reaches
the final value of ±0.5LSB, ±8 LSB - 1.65 2.7
±1LSB, ±2LSB, ±4LSB,
±8LSB) Normal mode, DAC output buffer
- 1.7 2
OFF, ±1LSB CL=10 pF
Wakeup time from off Normal mode, DAC output buffer
- 5 7.5
state (setting the ENx bit ON, CL ≤ 50 pF, RL = 5 ㏀
tWAKEUP(2) in the DAC Control µs
register) until the final Normal mode, DAC output buffer
- 2 5
value of ±1LSB is reached OFF, CL ≤ 10 pF
DC VDDA supply rejection Normal mode, DAC output buffer

PSRR - -80 -28 dB
ratio ON, CL ≤ 50 pF, RL = 5 ㏀
Sampling time in Sample MODE<2:0>_V12=100/101
- 0.7 2.6
and Hold mode (BUFFER ON)
ms
CL=100 nF MODE<2:0>_V12=110
(code transition between - 11.5 18.7
tSAMP (BUFFER OFF)
the lowest input code and
the highest input code MODE<2:0>_V12=111(3)
when DAC_OUT reaches - 0.3 0.6 µs
(INTERNAL BUFFER OFF)
the ±1LSB final value)
Ileak Output leakage current - - - (4) nA
Internal sample and hold
CIint - 1.8 2.2 2.6 pF
capacitor
Middle code offset trim Minimum time to verify the each
tTRIM 50 - - µs
time code
Middle code offset for 1 VREF+ = 3.6 V - 850 -

Voffset µV
trim code step VREF+ = 1.8 V - 425 -
DS14053 Rev 3 131/174

154
Table 66. DAC characteristics(1) (continued)

No load,
middle code - 360 -
DAC output buffer (0x800)
ON No load,
worst code - 490 -
(0xF1C)
DAC quiescent
IDDA(DAC) No load,
consumption from VDDA
DAC output buffer middle/
- 20 -
OFF worst code
(0x800)
360*TON/
Sample and Hold mode,
- (TON+TOFF) -
CSH=100 nF (5)
No load,
middle code - 170 - µA
DAC output buffer (0x800)
ON No load,
worst code - 170 -
(0xF1C)
No load,
DAC consumption from DAC output buffer middle/
IDDV(DAC) - 160 -
VREF+ OFF worst code
(0x800)
170*TON/
Sample and Hold mode, Buffer
- (TON+TOFF) -
ON, CSH=100 nF (worst code) (5)
160*TON/
Sample and Hold mode, Buffer
- (TON+TOFF) -
OFF, CSH=100 nF (worst code) (5)

2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
3. DACx_OUT pin is not connected externally (internal connection only).
4. Refer to Table 53: I/O static characteristics.
5. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.
Table 67. DAC accuracy(1)

Differential non DAC output buffer ON −2 - 2

DNL LSB
linearity(2) DAC output buffer OFF −2 - 2
- Monotonicity 10 bits - - - -
132/174 DS14053 Rev 3

Table 67. DAC accuracy(1) (continued)

DAC output buffer ON, CL ≤ 50 pF,
−4 - 4
RL ≥ 5 ㏀
INL Integral non linearity(3) LSB
DAC output buffer OFF,
−4 - 4
CL ≤ 50 pF, no RL
DAC output VREF+ = 3.6 V - - ±12
buffer ON,
Offset error at code CL ≤ 50 pF, VREF+ = 1.8 V - - ±25
Offset RL ≥ 5 ㏀ LSB
0x800 (3)
- - ±8
CL ≤ 50 pF, no RL
Offset error at code DAC output buffer OFF,
Offset1 - - ±5 LSB
0x001(4) CL ≤ 50 pF, no RL
DAC output VREF+ = 3.6 V - - ±5
Offset error at code
buffer ON,
OffsetCal 0x800 after factory LSB
calibration CL ≤ 50 pF, VREF+ = 1.8 V - - ±7
RL ≥ 5 ㏀
DAC output buffer ON,CL ≤ 50 pF,
- - ±1
RL ≥ 5 ㏀
Gain Gain error(5) %
- - ±1
CL ≤ 50 pF, no RL
- - ±30
RL ≥ 5 ㏀
TUE Total unadjusted error
DAC output buffer OFF, CL ≤
±12 LSB
50 pF, no RL
Total unadjusted error DAC output buffer ON, CL ≤ 50 pF,
TUECal - - ±23
after calibration RL ≥ 5 ㏀
DAC output buffer ON,CL ≤ 50 pF,
- 67.8 -
RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz
SNR Signal-to-noise ratio(6) DAC output buffer OFF, dB
CL ≤ 50 pF, no RL,1 kHz, BW = - 67.8 -
500 KHz
- −78.6 -
Total harmonic RL ≥ 5 ㏀ , 1 kHz
THD dB
distortion(6) DAC output buffer OFF,
- −78.6 -
CL ≤ 50 pF, no RL, 1 kHz
- 67.5 -
Signal-to-noise and RL ≥ 5 ㏀ , 1 kHz
SINAD dB
distortion ratio(6) DAC output buffer OFF,
- 67.5 -
DAC output buffer ON,
- 10.9 -
Effective number of CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz
ENOB bits
bits DAC output buffer OFF,
- 10.9 -
DS14053 Rev 3 133/174

154

2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is -0.5 dBFS with Fsampling=1 MHz.
Figure 24. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RL
12-bit DAC_OUTx
digital to
analog
converter
CL
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
5.3.19 Analog temperature sensor characteristics
Table 68. Analog temperature sensor characteristics

VSENSE linearity with temperature (from VSENSOR voltage) - - 3

TL(1) °C
VSENSE linearity with temperature (from ADC counter) - - 3
Average slope (from VSENSOR voltage) - 2 -
Avg_Slope(2) mV/°C
Average slope (from ADC counter) - 2 -
V30(3) Voltage at 30°C ± 5 °C - 0.62 - V
tstart_run Startup time in Run mode (buffer startup) - - 25.2
µs
(1)
tS_temp ADC sampling time when reading the temperature 9 - -
Isens(1) Sensor consumption - 0.18 0.31
µA
Isensbuf(1) Sensor buffer consumption - 3.8 6.5
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.
134/174 DS14053 Rev 3

Table 69. Temperature sensor calibration values

Symbol Parameter Memory address
Temperature sensor raw data acquired value at

TS_CAL1 0x08FF F814 -0x08FF F815
30 °C, VDDA=3.3 V
Temperature sensor raw data acquired value at
TS_CAL2 0x08FF F818 - 0x08FF F819
130 °C, VDDA=3.3 V
5.3.20 Digital temperature sensor characteristics
Table 70. Digital temperature sensor characteristics(1)

fDTS (2)
Output Clock frequency - 500 750 1150 kHz
Hz/°
TLC(2) Temperature linearity coefficient VOS2 1660 2100 2750
C
TJ = −40°C to
-13 - 4
TTOTAL_ERROR Temperature offset 30°C
(2) °C
measurement, all VOS TJ = 30°C to
-7 - 2
Tjmax
VOS2 0 - 0
Additional error due to supply
TVDD_CORE VOS0, VOS1, °C
variation -1 - 1
VOS3
tTRIM Calibration time - - - 2 ms
Wake-up time from off state until
tWAKE_UP - - 67 116.00 μs
DTS ready bit is set
DTS consumption on
IDDCORE_DTS - 8.5 30 70.0 μA
VDD_CORE
5.3.21 VCORE monitoring characteristics
Table 71. VCORE monitoring characteristics(1)

TS_VCORE ADC sampling time when reading the VCORE voltage 1 - - μs

DS14053 Rev 3 135/174

154
5.3.22 Temperature and VBAT monitoring
Table 72. VBAT monitoring characteristics

R Resistor bridge for VBAT - 4 x 26 - KΩ

Q Ratio on VBAT measurement - 4 - -
(1)
Er Error on Q -10 - +10 %
tS_vbat(1) ADC sampling time when reading VBAT input 9 - - µs
VBAThigh High supply monitoring 3.5 3.575 3.63
V
VBATlow Low supply monitoring - 1.36 -
IVBATbuf Sensor buffer consumption - 3.8 6.5 µA
Table 73. VBAT charging characteristics

VBRS in PWR_BDCR = 0 - 5 -
RBC Battery charging resistor KΩ
VBRS in PWR_BDCR = 1 1.5 -
Table 74. Temperature monitoring characteristics

TEMPhigh High temperature monitoring - 126 -

°C
TEMPlow Low temperature monitoring - -37 -
5.3.23 Voltage booster for analog switch
Table 75. Voltage booster for analog switch characteristics(1)

VDD Supply voltage - 1.71 2.6 3.6 V

tSU(BOOST) Booster startup time - - - 50 µs
1.71 V ≤ VDD ≤ 2.7 V - - 125
IDD(BOOST) Booster consumption µA
2.7 V < VDD < 3.6 V - - 250
136/174 DS14053 Rev 3

5.3.24 Comparator characteristics
Table 76. COMP characteristics(1)

VDDA Analog supply voltage - 1.62 3.3 3.6

Comparator input voltage
VIN - 0 - VDDA V
range
VBG(2) Scaler input voltage - -
VSC Scaler offset voltage - - ±5 ±10 mV
Scaler static consumption BRG_EN=0 (bridge disable) - 0.2 0.3

IDDA(SCALER) µA
from VDDA BRG_EN=1 (bridge enable) - 0.8 1
tSTART_SCALER Scaler startup time - - 140 250 µs
High-speed mode - 2 5
Comparator startup time to
tSTART reach propagation delay Medium mode - 5 20 µs
specification
Ultra-low-power mode - 15 80
High-speed mode - 50 80 ns
Propagation delay for
200 mV step with 100 mV Medium mode - 0.5 0.9
overdrive µs
Ultra-low-power mode - 2.5 7
tD(3)
Propagation delay for step High-speed mode - 50 120 ns
> 200 mV with 100 mV
Medium mode - 0.5 1.2
overdrive only on positive µs
inputs Ultra-low-power mode - 2.5 7
Voffset Comparator offset error Full common mode range - ±5 ±20 mV
No hysteresis - 0 -
Low hysteresis 4 10 22
Vhys Comparator hysteresis mV
Medium hysteresis 8 20 37
High hysteresis 16 30 52
Static - 400 600
Ultra-low- With 50 kHz nA
power mode ±100 mV overdrive - 800 -
square signal
Static - 5 7
Comparator consumption
IDDA(COMP) Medium mode With 50 kHz
from VDDA ±100 mV overdrive - 6 -
square signal
µA
Static - 70 100
High-speed With 50 kHz
mode ±100 mV overdrive - 75 -
square signal
2. Refer to Section 5.3.5: Embedded reference voltage.
DS14053 Rev 3 137/174

154
5.3.25 Operational amplifier characteristics
Table 77. Operational amplifier characteristics(1)

Analog supply voltage

VDDA - 2 3.3 3.6
Range
V
Common Mode Input
CMIR - 0 - VDDA
Range
25°C, no load on output - - ±1.5
VIOFFSET Input offset voltage All voltages and mV
- - ±2.5
temperature, no load
ΔVIOFFSET Input offset voltage drift - - ±3.0 - μV/°C
Offset trim step at low
TRIMOFFSETP,
common input voltage - - 1.1 1.5
TRIMLPOFFSETP (0.1*VDDA)
mV
Offset trim step at high
TRIMOFFSETN,
common input voltage - - 1.1 1.5
TRIMLPOFFSETN (0.9*VDDA)
ILOAD Drive current - - - 500
μA
ILOAD_PGA Drive current in PGA mode - - - 270
CLOAD Capacitive load - - - 50 pF
Common mode rejection
CMRR - - 80 - dB
ratio
CLOAD ≤ 50pf /
Power supply rejection
PSRR RLOAD ≥ 4 kΩ(2) at 1 kHz, 50 66 - dB
ratio
Vcom=VDDA/2
Gain bandwidth for high 200 mV ≤ Output dynamic
GBW 4 7.3 12.3 MHz
supply range range ≤ VDDA - 200 mV
Slew rate (from 10% and Normal mode - 3 -

SR V/µs
90% of output voltage) High-speed mode - 24 -
200 mV ≤ Output dynamic
AO Open loop gain 59 90 129 dB
range ≤ VDDA - 200 mV
φm Phase margin - - 55 - °
GM Gain margin - - 12 - dB
Iload=max or RLOAD=min, VDDA
VOHSAT High saturation voltage - -
Input at VDDA −100 mV
mV
Iload=max or RLOAD=min,
VOLSAT Low saturation voltage - - 100
Input at 0 V
138/174 DS14053 Rev 3

Table 77. Operational amplifier characteristics(1) (continued)

CLOAD ≤ 50pf,
Normal RLOAD ≥ 4 kΩ,
- 0.8 3.2
mode follower
Wake up time from OFF configuration
tWAKEUP µs
state CLOAD ≤ 50pf,
High
RLOAD ≥ 4 kΩ,
speed - 0.9 2.8
follower
mode
configuration
PGA gain = 2 -1 - 1
Non inverting gain error PGA gain = 4 -2 - 2

value PGA gain = 8 -2.5 - 2.5
PGA gain = 16 -3 - 3
PGA gain = 2 -1 - 1
PGA gain = 4 -1 - 1
PGA gain Inverting gain error value %
PGA gain = 8 -2 - 2
PGA gain = 16 -3 - 3
PGA gain = 2 -1 - 1
External non-inverting gain PGA gain = 4 -3 - 3

error value PGA gain = 8 -3.5 - 3.5
PGA gain = 16 -4 - 4
PGA Gain=2 - 10/10 -
R2/R1 internal resistance PGA Gain=4 - 30/10 -
values in non-inverting
PGA mode(3) PGA Gain=8 - 70/10 -
PGA Gain=16 - 150/10 - kΩ/
Rnetwork
PGA Gain = -1 - 10/10 - kΩ
R2/R1 internal resistance PGA Gain = -3 - 30/10 -
values in inverting PGA
mode(3) PGA Gain = -7 - 70/10 -
PGA Gain = -15 - 150/10 -
Resistance variation (R1
Delta R - -15 - 15 %
or R2)
DS14053 Rev 3 139/174

154
Table 77. Operational amplifier characteristics(1) (continued)

Gain=2 - GBW/2 -
PGA bandwidth for Gain=4 - GBW/4 -

MHz
different non inverting gain Gain=8 - GBW/8 -
Gain=16 - GBW/16 -
PGA BW
Gain = -1 - 5.00 -
PGA bandwidth for Gain = -3 - 3.00 -

MHz
different inverting gain Gain = -7 - 1.50 -
Gain = -15 - 0.80 -
at
- 140 -
1 KHz output loaded nV/√
en Voltage noise density
at with 4 kΩ Hz
- 55 -
10 KHz
Normal
- 570 1000
mode no Load,
OPAMP consumption from
IDDA(OPAMP) High- quiescent mode, µA
VDDA
speed follower - 610 1200
mode
2. RLOAD is the resistive load connected to VSSA or to VDDA.
3. R2 is the internal resistance between the OPAMP output and the OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
5.3.26 Timer characteristics

The parameters given in Table 78 are specified by design, not tested in production.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 78. TIMx characteristics(1)(2)

AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK = 1 - tTIMxCLK
250 MHz
tres(TIM) Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK = 1 - tTIMxCLK
125 MHz
Timer external clock
fEXT 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 f
TIMxCLK = 250 MHz
ResTIM Timer resolution - 16/32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
140/174 DS14053 Rev 3

1. TIMx is used as a general term to refer to the TIM1 to TIM3 and TIM6/7 timers.
3. The maximum timer frequency on APB1 or APB2 is up to 250 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1, 2, or 4, then TIMxCLK = fHCLK, otherwise
TIMxCLK = 4x fPCLKx or TIMxCLK = 4x fPCLKx.
5.3.27 Communication interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
• Standard-mode (Sm): with a bit rate up to 100 Kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I C timings requirements are specified by design, not tested in production, when the I2C
2
peripheral is properly configured (refer to RM0492 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDDIOx is disabled, but still present.
• Only FT_f I/O pins support Fm+ low level output current maximum requirement. Refer
to Section 5.3.14: I/O port characteristics for the I2C I/Os characteristics
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
ter characteristics:
Table 79. I2C analog filter characteristics(1)(2)

Symbol Parameter Min Max Unit
tAF Maximum pulse width of spikes that are suppressed by analog filter 50(3) 160(4) ns
1. Evaluated by characterization results - Not tested in production.
2. Measurement points are done at 50 % VDD.
3. Spikes with widths below tAF(min) are filtered.
4. Spikes with widths above tAF(max) are not filtered.
I3C interface characteristics

The I3C interface meets the timings requirements of the MIPI® I3C specification v1.1.
The I3C peripheral supports:
• I3C SDR-only as controller
• I3C SDR-only as target
• I3C SCL bus clock frequency up to 12.5 MHz
DS14053 Rev 3 141/174

154
The parameters given in Table 80: I3C open-drain measured timing and Table 81: I3C push-
pull measured timing are obtained with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• I/O compensation cell activated.
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS 0
The I3C timings are in line with the MIPI specification except for the ones given in Table 80:
I3C open-drain measured timing and Table 81: I3C push-pull measured timing. For tSU_OD
and tSU_PP this can be mitigated by increasing the corresponding SCL low duration in the
I3C_TIMINGR0 register. For tSCO this can be mitigated by enabling and adjusting the clock
stall time both on the address ACK phase and on the data read Tbit phase in the
I3C_TIMINGR2 register. This can also be mitigated by increasing the SCL low duration in
the I3C_TIMINGR0 register. For further details, refer to I3C application note AN5879.
Table 80. I3C open-drain measured timing

I3C open drain mode
(specification) Timing
measurements
Min Max
Controller
23
SDA data setup time 1.08 V ≤ VDDIO2(1) ≤ 1.32 V
tSU_OD 3 - ns
during open drain mode Controller
16.5
1.71 V ≤ VDD ≤ 3.6 V
1. On WLCSP25, the I3C is mapped on port A/B I/Os, which is supplied by VDDIO2 with specification down to 1.08 V. The I3C
is tested at this value.
Table 81. I3C push-pull measured timing

I3C open drain mode
(specification) Timing
measurements
Min Max
Clock in to data out for Target

tSCO - 12 18 ns
target 1.08 V ≤ VDDIO2(1) ≤ 1.32 V
Controller
21
SDA signal data setup 1.08 V ≤ VDDIO2(1) ≤ 1.32 V
tSU_PP 3 - ns
in push-pull mode Controller
12
1.71 V ≤ VDD ≤ 3.6 V
1. On WLCSP25, the I3C is mapped on port A/B I/Os, which is supplied by VDDIO2 with specification down to 1.08V. The I3C
is tested at this value.
142/174 DS14053 Rev 3

USART interface characteristics

Unless otherwise specified, the parameters given in Table 82 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency, and VDD supply voltage
conditions summarized in Table 16: General operating conditions, and Section 5.3.1:
General operating conditions with the following configuration:
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• IO compensation cell activated
• VOS level set to VOS0
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
Table 82. USART characteristics(1)(2)

Master receiver 31
Slave receiver 83
Slave transmitter,
32
1.71 V < VDD < 3.6 V
fCK USART clock frequency - - MHz
Slave transmitter,
35
2.7 V < VDD < 3.6 V
Slave transmitter,
22
1.08 V < VDDIO2 < 1.32 V
tsu(NSS) NSS setup time Slave mode tker + 3.5(3) - -
th(NSS) NSS hold time Slave mode 2.5 - -
tw(CKH),
CK high and low time Master mode 1/fck/2-1 1/fck/2 1/fck/2+1
tw(CKL)
ns
Master mode 13/22(4) - -
tsu(RX) Data input setup time
Slave mode 3.5 - -
Master mode 0.5 - -
th(RX) Data input hold time
Slave mode 1.5 - -
Slave mode
- 15.5
1.71 V < VDD < 3.6 V
11.5
Slave mode
- 14
2.7 V < VDD < 3.6 V
Slave mode
tv(TX) Data output valid time - 16 22.5 ns
1.08 V < VDDIO2 < 1.32 V
Master mode
- 3
1.71 V < VDD < 3.6 V
2.5
Master mode
- 3
2.7 V < VDD < 3.6 V
DS14053 Rev 3 143/174

154
Table 82. USART characteristics(1)(2) (continued)

Slave mode
7.5 - -
1.71 V < VDD < 3.6 V
th(TX) Data output hold time Slave mode ns
10.5 - -
1.08 V < VDDIO2 < 1.32 V
Master mode 0 - -
2. For VDDIO2 OSPEEDRy[1:0] = 11.
3. tker is the usart_ker_ck_pres clock period.
4. For VDDIO2.
Figure 25. USART timing diagram in Master mode
1/fCK
CK output
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CK output
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(CKH)
tsu(RX) tw(CKL)
RX
INPUT MSB IN BIT6 IN LSB IN
th(RX)
TX
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX)
MSv65386V4
144/174 DS14053 Rev 3

Figure 26. USART timing diagram in Slave mode
NSS
input
1/fCK th(NSS)
tsu(NSS) tw(CKH)
CPHA = 0
CK input
CPOL = 0
CPHA = 0
CPOL = 1
tw(CKL) tv(TX) th(TX)
TX output First bit OUT Next bits OUT Last bit OUT
th(RX)
tsu(RX)
RX input First bit IN Next bits IN Last bit IN

MSv65387V4
SPI interface characteristics

Unless otherwise specified, the parameters given in Table 83 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency, and VDD supply voltage
conditions summarized in Table 16: General operating conditions and Section 5.3.1:
General operating conditions, with the following configuration:
• IO compensation cell activated.
function characteristics (NSS, SCK, MOSI, MISO for SPI).
DS14053 Rev 3 145/174

154
Table 83. SPI characteristics(1)

Master receiver mode

- - 135
2.7 V < VDD < 3.6 V
- - 120
1.71 V < VDD < 2.7 V
- - 50
1.08 V <VDDIO2< 1.32 V
Master transmitter mode
- - 135
2.7 <VDD< 3.6V
- - 120
1.71 V < VDD< 2.7 V
fSCK 1.08 V < VDDIO2 < - - 50
SPI clock frequency MHz
1/tSCK 1.32 V
Slave receiver mode
- - 120
1.71 V < VDD < 3.6 V
Slave receiver mode
- - 120
1.08 V < VDDIO2 < 1.32 V
Slave transmitter
- - 43
2.7 V < VDD < 3.6V
Slave transmitter
- - 41
1.71V < VDD < 2.7 V
Slave transmitter
- - 23
1.08 V <VDDIO2<1.32 V
tsu(NSS) NSS setup time Slave mode 3.5 - -
th(NSS) NSS hold time Slave mode 4.5 - -
ns
tw(SCKH)
SCK high and low time Master mode (tSCK/2) - 1 (tSCK/2) (tSCK/2) + 1
tw(SCKL)
146/174 DS14053 Rev 3

Table 83. SPI characteristics(1) (continued)

tsu(MI) Master mode 3.5 - -

Data input setup time
tsu(SI) Slave mode 2 - -
th(MI) Master mode 1 - -
Data input hold time
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time Slave mode 6.5 - 15
tdis(SO) Data output disable time Slave mode 7.5 - 18
Slave mode,
- 8.5 11.5
2.7 V ≤ VDD ≤ 3.6 V ns
Slave mode,
tv(SO) - 10 12
Data output valid time 1.71 V ≤ VDD ≤ 2.7 V
Slave mode,
- 18 21.5
1.08 V ≤ VDDIO2 ≤ 1.32 V
tv(MO) Master mode - 1.5 2
Slave mode,
th(SO) 6.5 - -
Data output hold time 1.71 V ≤ VDD ≤ 3.6 V
th(MO) Master mode 0 - -
Figure 27. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
DS14053 Rev 3 147/174

154
Figure 28. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 29. SPI timing diagram - master mode(1)
High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(MO) th(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
148/174 DS14053 Rev 3

I2S interface characteristics

Unless otherwise specified, the parameters given in Table 84 for I2S are derived from tests
performed under the ambient temperature, fPCLKx frequency, and VDD supply voltage
conditions summarized in Table 16: General operating conditions, with the following
configuration:
• IO compensation cell activated.
function characteristics (CK,SD0,SDI, WS).
Table 84. I2S characteristics(1)

Symbol Parameter Conditions Min Max Unit
fMCK I2S main clock output - - 50

Master - 50
MHz
fCK I2S clock frequency Slave TX - 21
Slave RX - 50
tv(WS) WS valid time - 2
Master mode
th(WS) WS hold time 0.5 -
tsu(WS) WS setup time 3 -
Slave mode
th(WS) WS hold time 1.5 -
tsu(SD_MR) Master receiver 4 -
Data input setup time
tsu(SD_SR) Slave receiver 2 -
th(SD_MR) Master receiver 1 -
Data input hold time
th(SD_SR) Slave receiver 1.5 - ns
Slave transmitter
tv(SD_ST) - 14
(after enable edge)
Data output valid time
Master transmitter
tv(SD_MT) - 1
(after enable edge)
Slave transmitter
th(SD_ST) 5.5 -
(after enable edge)
Data output hold time
Master transmitter
th(SD_MT) 0 -
(after enable edge)
1. Evaluated by characterization. - Not tested in production.
DS14053 Rev 3 149/174

154
Figure 30. I2S slave timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 31. I2S master timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
150/174 DS14053 Rev 3

USB full speed (FS) characteristics

The USB interface is fully compliant with the USB specification version 2.0.
Table 85. USB DC electrical characteristics

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
USB full speed transceiver

VDD - 3.0(2) - 3.6 V
operating voltage
VDI(3) Differential input sensitivity Over VCM range 0.2 - -
Differential input common mode
VCM(3) Includes VDI range 0.8 - 2.5
range V
Single ended receiver input
VSE(3) - 0.8 - 2.0
threshold
VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3
V
VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
Pull down resistor on PA11,
RPD(3) VIN = VDD 14.25 - 24.8 kΩ
PA12 (USB_DP/DM)
Pull Up Resistor on PA12
VIN = VSS, during idle 0.9 1.25 1.575 kΩ
(USB_DP)
(3)
RPU
Pull Up Resistor on PA12 VIN = VSS during
1.425 2.25 3.09 kΩ
(USB_DP) reception
1. All the voltages are measured from the local ground potential.
2. The USB full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics, which are degraded in the 2.7-to-3.0 V VDD voltage range.
4. RL is the load connected on the USB full speed drivers.
Figure 32. USB timings - definition of data signal rise and fall time
Cross over
points
Differential
data lines
VCRS
VSS
tf tr
ai14137b
Table 86. USB startup time

Symbol Parameter Max Unit
tSTARTUP(1) USB transceiver startup time 1 μs

DS14053 Rev 3 151/174

154
Table 87. USB electrical characteristics(1)

Driver characteristics
Symbol Parameter Conditions Min Max Unit
trLS Rise time in LS(2) CL = 200 to 600 pF 75 300 ns

(2)
tfLS Fall time in LS CL = 200 to 600 pF 75 300 ns
trfmLS Rise/ fall time matching in LS tr/tf 80 125 %
trFS (2)
Rise time in FS CL = 50 pF 4 20 ns
(2)
tfFS Fall time in FS CL = 50 pF 4 20 ns
trfmFS Rise/ fall time matching in FS tr/tf 90 111 %
VCRS Output signal crossover voltage (LS/FS) - 1.3 2.0 V
ZDRV Output driver impedance(3) Driving high or low 28 44 Ω
2. Measured from 10% to 90% of the data signal. For more detailed information, refer to USB specification -
chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
Table 88. USB BCD DC electrical characteristics(1)

Symbol Parameter Conditions Min. Typ. Max. Unit
Primary detection mode

- - - 300 μA
consumption
IDD(USBBCD)
Secondary detection mode
- - - 300 μA
consumption
Data line leakage
RDAT_LKG - 300 - - kΩ
resistance
VDAT_LKG Data line leakage voltage - 0.0 - 3.6 V
Dedicated charging port
RDCP_DAT - - - 200 Ω
resistance across D+/D-
VLGC_HI Logic high - 2.0 - 3.6 V
VLGC_LOW Logic low - - - 0.8 V
VLGC Logic threshold - 0.8 - 2.0 V
VDAT_REF Data detect voltage - 0.25 - 0.4 V
VDP_SRC D+ source voltage - 0.5 - 0.7 V
VDM_SRC D- source voltage - 0.5 - 0.7 V
IDP_SINK D+ sink current - 25 - 175 μA
IDM_SINK D- sink current - 25 - 175 μA
152/174 DS14053 Rev 3

JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 89 and Table 90 for JTAG/SWD
are derived from tests performed under the ambient temperature, fHCLK frequency, and VDD
supply voltage summarized in Table 16: General operating conditions and Section 5.3.1:
General operating conditions, with the following configuration:
• Capacitive load CL=30 pF
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
characteristics:
Table 89. Dynamic JTAG characteristics

fpp 2.7 V < VDD < 3.6 V - - 50

TCK clock frequency MHz
1/tc(TCK) 1.71 V < VDD < 3.6 V - - 45
tisu(TMS) TMS input setup time - 2 - -
tih(TMS) TMS input hold time - 1.5 - -
tisu(TDI) TDI input setup time - 1.5 - -
tih(TDI) TDI input hold time - 1.5 - - ns
2.7 V < VDD < 3.6 V - 8 10
tov(TDO) TDO output valid time
1.71 V < VDD < 3.6 V - 8 11
toh(TDO) TDO output hold time - 6.5 - -
--
Table 90. Dynamic SWD characteristics

fpp 2.7 V < VDD < 3.6 V - - 80

SWCLK clock frequency MHz
1/tc(TCK) 1.71 V < VDD < 3.6 V - - 71
tisu(SWDIO) SWDIO input setup time - 1.5 - -
tih(SWDIO) SWDIO input hold time - 1.5 - -
2.7 V < VDD < 3.6 V - 10.5 12.5 ns
tov(SWDIO) SWDIO output valid time
1.71 V < VDD < 3.6 V - 10.5 14
toh(SWDIO) SWDIO output hold time - 8.5 - -
DS14053 Rev 3 153/174

154
Figure 33. JTAG timing diagram
tc(TCK)
TCK
tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO) toh(TDO)
TDO
MSv71994V1
Figure 34. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)
tov(SWDIO) toh(SWDIO)
SWDIO
(transmit)
MSv71995V1
154/174 DS14053 Rev 3

STM32H503xx Package information
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions, and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433) available on www.st.com, for the location of pin 1 / ball A1
as well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.
DS14053 Rev 3 155/174

170
Package information STM32H503xx
6.2 WLCSP25 package information (B0GN)

This WLCSP is a 25 ball, 2.33 x 2.24 mm, 0.4 mm pitch, wafer level chip scale package.
Figure 35. WLCSP25 - Outline

bbb Z
F A1 BALL LOCATION A1
e1
DETAIL A
e2 E
e A
D
SIDE VIEW
BOTTOM VIEW
A3 A2
FRONT VIEW
BUMP
X
A1
eee Z
A1 ORIENTATION E
REFERENCE
Z
b(25x)
ccc Z X Y
aaa ddd Z
D Y(4x) SEATING PLAIN
DETAIL A
TOP VIEW ROTATED 90
B0GN_WLCSP25_DIE474_ME_V1
1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
156/174 DS14053 Rev 3

Table 91. WLCSP25 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A(2) - - 0.58 - - 0.0228

A1 - 0.17 - - 0.0067 -
A2 - 0.38 - - 0.0149 -
(3)
A3 - 0.025 - - 0.0010 -
(4)
b 0.23 0.26 0.28 0.0090 0.0102 0.0110
D 2.31 2.33 2.35 0.0909 0.0917 0.0925
E 2.22 2.24 2.26 0.0874 0.0882 0.0890
e - 0.40 - - 0.0157 -
e1 - 1.60 - - 0.0630 -
e2 - 1.60 - - 0.0630 -
F(5) - 0.365 - - 0.0144 -
G(5) - 0.320 - - 0.0126 -
aaa - - 0.10 - - 0.0039
bbb - - 0.10 - - 0.0039
ccc(6) - - 0.10 - - 0.0039
(7)
ddd - - 0.05 - - 0.0020
eee - - 0.05 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
5. Calculated dimensions are rounded to the 3rd decimal place
6. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
7. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true
position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of
each ball must lie simultaneously in both tolerance zones.
DS14053 Rev 3 157/174

170
Figure 36. WLCSP25 - Footprint example
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 92. WLCSP25 - Example of PCB design rules

Dimension Values
Pitch 0.4 mm
Dpad 0,225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm
Figure 37. WLCSP25 marking example (package top view)
Ball A1 identifier
Product identification
Date code
Revision code
Y WW
MSv73079V1
158/174 DS14053 Rev 3

6.3 UFQFPN32 package information (A0B8)

This UFQFPN is a 32 pins, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package
Figure 38. UFQFPN32 - Outline

EXPOSED PAD
D1
E2 E1
e
PIN 1 identifier
Chamfer or
Circular arc shape
e L
b
D2
R0.20 BOTTOM VIEW
A3 A
A1
SEATING PLANE
C
ddd C
DETAIL A
FRONT VIEW
A1
SEATING PLANE
ddd C
PIN 1 IDENTIFIER C
LASER MARKING AREA
DETAIL A
TOP VIEW A0B8_UFQFPN32_ME_V4

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. This backside pad must be
connected and soldered to PCB ground.
DS14053 Rev 3 159/174

170
Table 93. UFQFPN32 - Mechanical data

Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.000 0.0007 0.0020
A3 - 0.152 - - 0.0060 -
b 0.180 - 0.300 0.0071 - 0.0118
(2)
D 4.900 5.000 5.100 0.1929 0.1969 0.2008
D1 3.400 3.500 3.600 0.1339 0.1378 0.1417
D2 3.400 3.500 3.600 0.1339 0.1378 0.1417
(2)
E 4.900 5.000 5.100 0.1929 0.1969 0.2008
E1 3.400 3.500 3.600 0.1339 0.1378 0.1417
E2 3.400 3.500 3.600 0.1339 0.1378 0.1417
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
2. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm.
Figure 39. UFQFPN32 - Footprint example
5.30
3.80
0.60
3.45
5.30 3.80
3.45
0.50
0.30
0.75
3.80
A0B8_UFQFPN32_FP_V3
1. Dimensions are expressed in millimeters.
160/174 DS14053 Rev 3

6.4 LQFP48 package information (5B)

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package
Note: See list of notes in the notes section.
Figure 40. LQFP48 – Outline(15)

BOTTOM VIEW
4x N/4 TIPS
aaa C A-B D
2 1
(2)
R1
H
R2
B
B-
D 1/4
N
O
(6)
TI
C
SE
B GAUGE PLANE
E 1/4
0.25
S
B
bbb H A-B D 4x
L
3
(13) (L1)
0.05 (N – 4)x e (1) (11)
A A2 C SECTION A-A
(12) ccc C
A1 ddd C A-B D
b
D (4)
(2) (5)
D1
(10) D (3) (9) (11)
N b WITH PLATING
1
2 E 1/4
(3) A 3
(6) B (3)
D 1/4 c c1
E1 E (11) (11)
(2) (4)
(5)
A A b1 BASE METAL
(Section A-A) (11)
SECTION B-B
TOP VIEW
5B_LQFP48_ME_V1
DS14053 Rev 3 161/174

170
Table 94. LQFP48 – Mechanical data

Symbol
A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 9.00 BSC 0.3543 BSC
(2)(5)
D1 7.00 BSC 0.2756 BSC
E(4) 9.00 BSC 0.3543 BSC
E1(2)(5) 7.00 BSC 0.2756 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 48
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
(1)(7)
bbb 0.20 0.0079
ccc(1)(7) 0.08 0.0031
(1)(7)
ddd 0.08 0.0031
162/174 DS14053 Rev 3

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
Figure 41. LQFP48 – Footprint example

0.50
1.20
36 25
37 24 0.30
0.20
9.70 7.30
48 13
1 12
5.80
9.70
5B_LQFP48_FP_V1
DS14053 Rev 3 163/174

170
6.5 UFQFPN48 package information (A0B9)

This UFQFPN is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.
Figure 42. UFQFPN48 – Outline

D1 EXPOSED PAD
E2 E1
e
PIN 1 idenfier
L
D2
BOTTOM VIEW
A
A3
A1
SEATING PLANE
C
DETAIL A
ddd C
LEADS COPLANARITY
FRONT VIEW
A1 A
SEATING PLANE
ddd C
PIN 1 IDENTIFIER C
LASER MAKER AREA
TOP VIEW
A0B9_UFQFPN48_ME_V4

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN48 package. It is recommended to connect
and solder this back-side pad to PCB ground.
164/174 DS14053 Rev 3

Table 95. UFQFPN48 – Mechanical data

Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
(2)
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
D1 5.400 5.500 5.600 0.2126 0.2165 0.2205
D2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
(2)
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
E1 5.400 5.500 5.600 0.2126 0.2165 0.2205
E2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimensions D and E do not include mold protrusion, not exceed 0.15 mm.
3. Dimensions D2 and E2 are not in accordance with JEDEC.
Figure 43. UFQFPN48 – Footprint example

7.30
6.20
48 37
1 36
0.20 5.60
7.30
5.80
6.20
5.60
0.30
12 25
13 24
0.50 0.75
0.55
5.80 A0B9_UFQFPN48_FP_V3
DS14053 Rev 3 165/174

170
6.6 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.
Figure 44. LQFP64 - Outline(15)

BOTTOM VIEW
2 1
(2)
R1
H
R2
B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4
0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A
(13) (N – 4)x e
C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C
D (4)
(5) (2) D1 (9) (11)
(10)
D (3) b WITH PLATING
N (4)
1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)
A A SECTION B-B
(Section A-A)
TOP VIEW 5W_LQFP64_ME_V1
166/174 DS14053 Rev 3

Table 96. LQFP64 - Mechanical data

Symbol
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031
DS14053 Rev 3 167/174

170
Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
Figure 45. LQFP64 - Footprint example
48 33
0.30
49 0.5 32
12.70
10.30
10.30
64 17
1.20
1 16
7.80
12.70
5W_LQFP64_FP_V2
168/174 DS14053 Rev 3

6.7 Package thermal characteristics

The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated
using the following equation:
TJmax = TAmax + (PDmax × ΘJA)
Where:
• TAmax is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax),
• PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/Omax represents the maximum power dissipation on output pins where:
• PI/Omax = Σ (VOL × IOL) + Σ((VDD - VOH) × IOH), taking into account the actual VOL / IOL
and VOH / IOH of the I/Os at low and high level in the application.
Table 97. Package thermal characteristics

Symbol Definition Parameter Value Unit
Thermal resistance junction-ambient

80.7
WLCSP25 - 2.33 x 2.24 mm /0.4 mm pitch
40.1
UFQFPN32 - 5 x 5 mm /0.5 mm pitch
Thermal resistance Thermal resistance junction-ambient
ΘJA 54.1 °C/W
junction-ambient LQFP48 - 7 x 7 mm /0.5 mm pitch
29.5
48.9
LQFP64 - 10 x 10 mm /0.5 mm pitch
51.9
22.1
ΘJB 31.6 °C/W
junction-board LQFP48 - 7 x 7 mm /0.5 mm pitch
13.9
31.2
DS14053 Rev 3 169/174

170
Table 97. Package thermal characteristics (continued)

Symbol Definition Parameter Value Unit

5
19.4
ΘJC 16.4 °C/W
junction-case LQFP48 - 7 x 7 mm /0.5 mm pitch
11.3
15.1
6.7.1 Reference documents

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
• For information on thermal management, refer to application note “Thermal
management guidelines for STM32 32-bit Arm Cortex MCUs applications” (AN5036)
available from www.st.com.
170/174 DS14053 Rev 3

STM32H503xx Ordering information
7 Ordering information
Example: STM32 H 503 R B T 6 TR

Device family
STM32 = Arm based 32-bit microcontroller
Product type
H = high performance
Device subfamily
503 = STM32H503xx
Pin count
E = 25 pins
K = 32 pins
C = 48 pins
R = 64 pins
Flash memory size
B = 128 Kbytes
Package
U = UFQFPN
Y = WLCSP
T = LQFP
Temperature range
6 = Temperature range, -40 to 85 °C

7 = Temperature range, -40 to 105 °C, and up to 125 °C at low dissipation
Packing
TR = tape and reel
xxx = programmed parts
For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.
DS14053 Rev 3 171/174

171
Important security notice STM32H503xx
8 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
172/174 DS14053 Rev 3

STM32H503xx Revision history
9 Revision history
Table 98. Document revision history

Date Revision Changes
03-Mar-2023 1 Initial release.

Updated:
– Section 3.10: Reset and clock controller (RCC)
– Table 41: CSI oscillator characteristics
– Figure 18: VIL/VIH for all I/Os except BOOT0
– Table 54: Output voltage characteristics for all I/Os
28-Aug-2023 2
except PC13, PC14 and PC15
– Table 58: Output timing characteristics (HSLV ON)
– Section 6.3: UFQFPN32 package information (A0B8)
– Section 6.4: LQFP48 package information (5B)
– Section 6.5: UFQFPN48 package information (A0B9)
Updated:
– Table 2: STM32H503xx features and peripheral
counts
– Tables from Table 23: Typical and maximum current
consumption in run mode, code with data processing
running from flash memory, 2-ways instruction cache
ON, PREFETCH ON to Table 26: Typical and
maximum current consumption in Run mode, code
with data processing running from SRAM with cache
2-WAY.
26-Sep-2023 3 – Table 29: Typical and maximum current consumption
in sleep mode
– Table 30: Typical and maximum current consumption
in stop mode
– Section 5.3.7: External clock source characteristics
– Section 7: Ordering information
Added:
– Section 6.1: Device marking
– Figure 37: WLCSP25 marking example (package top
view)
DS14053 Rev 3 173/174

173
STM32H503xx
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product
or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2023 STMicroelectronics – All rights reserved
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STM32H503xx

Arm® Cortex®-M33 32-bit MCU+FPU, 375 DMIPS, 250 MHz,

September 2023 DS14053 Rev 3 1/174

Communication interfaces Two DMA controllers to offload the CPU

• Up to three USARTs (ISO7816 interface, LIN, • True random generator

STM32H503xx STM32H503EB, STM32H503KB, STM32H503CB, STM32H503RB

2/174 DS14053 Rev 3

DS14053 Rev 3 3/174

3.17.1 Analog temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4 Pinout, pin description, and alternate function . . . . . . . . . . . . . . . . . . 48

4/174 DS14053 Rev 3

4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

DS14053 Rev 3 5/174

5.3.22 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

6/174 DS14053 Rev 3

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DS14053 Rev 3 7/174

Table 45. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

8/174 DS14053 Rev 3

Table 97. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

DS14053 Rev 3 9/174

Figure 1. STM32H503xx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

10/174 DS14053 Rev 3

For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33

DS14053 Rev 3 11/174

The STM32H503xx devices are a high-performance microcontrollers family (STM32H5

12/174 DS14053 Rev 3

Table 2. STM32H503xx features and peripheral counts

Flash memory (Kbytes) 128

Timers Low power 2 (16 bits)

DS14053 Rev 3 13/174

Table 2. STM32H503xx features and peripheral counts (continued)

Operating voltage 1.71 to 3.6 V

14/174 DS14053 Rev 3

Figure 1. STM32H503xx block diagram

AHB2 250 MHz

AHB3 250 MHz

Reset and clock control

GTZC1 TIM3 16b 4 channels, ETR as AF

RX, TX, CK,CTS, smcard AUDIOCLK as AF

AUDIOCLK as AF I2C2/SMBUS SCL, SDA, SMBA as AF

SCL, SDA I3C2

DS14053 Rev 3 15/174

3.1 Arm Cortex-M33 core with FPU

3.2 ART Accelerator (ICACHE)

3.2.1 Instruction cache (ICACHE)

16/174 DS14053 Rev 3

– Hit ratio improved by two-ways set-associative architecture and pLRU-t

3.3 Memory protection unit

3.4 Embedded flash memory

DS14053 Rev 3 17/174

3.4.1 Flash privilege protection

3.5 Embedded SRAMs

3.5.1 SRAMs privilege protection

3.6 Boot modes