the 4.

7-V Zener and the transistor and establish a collector current through the LED suffi- SUMMARY 233
cient in magnitude to turn on the green LED.
Once the potentiometer is set, the LED will emit its green light as long as the supply
voltage is near 9 V. However, if the terminal voltage of the 9-V battery should decrease,
the voltage set up by the voltage-divider network may drop to 5 V from 5.4 V. At 5 V there
is insufficient voltage to turn on both the Zener and the transistor, and the transistor will be
in the “off” state. The LED will immediately turn off, revealing that the supply voltage has
dropped below 9 V or that the power source has been disconnected.

9V

1k
1k
Green LED

4.7 V
+ –
10 k +
+ 0.7 V
5.4 V
–
–

FIG. 4.112
Voltage level indicator.

4.20 SUMMARY
●
Important Conclusions and Concepts
1. No matter what type of configuration a transistor is used in, the basic relationships
between the currents are always the same, and the base-to-emitter voltage is the
threshold value if the transistor is in the “on” state.
2. The operating point defines where the transistor will operate on its characteristic
curves under dc conditions. For linear (minimum distortion) amplification, the dc
operating point should not be too close to the maximum power, voltage, or current
rating and should avoid the regions of saturation and cutoff.
3. For most configurations the dc analysis begins with a determination of the base current.
4. For the dc analysis of a transistor network, all capacitors are replaced by an open-
circuit equivalent.
5. The fixed-bias configuration is the simplest of transistor biasing arrangements, but it
is also quite unstable due its sensitivity to beta at the operating point.
6. Determining the saturation (maximum) collector current for any configuration can
usually be done quite easily if an imaginary short circuit is superimposed between
the collector and emitter terminals of the transistor. The resulting current through the
short is then the saturation current.
7. The equation for the load line of a transistor network can be found by applying
Kirchhoff’s voltage law to the output or collector network. The Q-point is then deter-
mined by finding the intersection between the base current and the load line drawn on
the device characteristics.
8. The emitter-stabilized biasing arrangement is less sensitive to changes in beta—
providing more stability for the network. Keep in mind, however, that any resistance
in the emitter leg is “seen” at the base of the transistor as a much larger resistor, a
fact that will reduce the base current of the configuration.
9. The voltage-divider bias configuration is probably the most common of all the con-
figurations. Its popularity is due primarily to its low sensitivity to changes in beta
from one transistor to another of the same lot (with the same transistor label). The
exact analysis can be applied to any configuration, but the approximate one can be
applied only if the reflected emitter resistance as seen at the base is much larger than
the lower resistor of the voltage-divider bias arrangement connected to the base of the
transistor.
234 DC BIASING—BJTs 10. When analyzing the dc bias with a voltage feedback configuration, be sure to
remember that both the emitter resistor and the collector resistor are reflected
back to the base circuit by beta. The least sensitivity to beta is obtained when the
reflected resistance is much larger than the feedback resistor between the base and
the collector.
11. For the common-base configuration the emitter current is normally determined
first due to the presence of the base-to-emitter junction in the same loop. Then the fact
that the emitter and the collector currents are essentially of the same magnitude is
employed.
12. A clear understanding of the procedure employed to analyze a dc transistor network
will usually permit a design of the same configuration with a minimum of difficulty
and confusion. Simply start with those relationships that minimize the number of
unknowns and then proceed to make some decisions about the unknown elements of
the network.
13. In a switching configuration, a transistor quickly moves between saturation and cut-
off, or vice versa. Essentially, the impedance between collector and emitter can be
approximated as a short circuit for saturation and an open circuit for cutoff.
14. When checking the operation of a dc transistor network, first check that the base-to-
emitter voltage is very close to 0.7 V and that the collector-to-emitter voltage is
between 25% and 75% of the applied voltage VCC.
15. The analysis of pnp configurations is exactly the same as that applied to npn transis-
tors with the exception that current directions will reverse and voltages will have the
opposite polarities.
16. Beta is very sensitive to temperature, and VBE decreases about 2.5 mV (0.0025 V)
for each 1 increase in temperature on a Celsius scale. The reverse saturation current
typically doubles for every 10° increase in Celsius temperature.
17. Keep in mind that networks that are the most stable and least sensitive to temperature
changes have the smallest stability factors.

Equations
VBE 0.7 V, IE = (b + 1)IB IC, IC = bIB
Fixed bias:
VCC - VBE
IB = , IC = bIB
RB
Emitter stabilized:
VCC - VBE
IB = , Ri = (b + 1)RE
RB + (b + 1)RE
Voltage-divider bias:
R2VCC ETh - VBE
Exact: RTh = R1 } R2, ETh = VR2 = , IB =
R1 + R2 RTh + (b + 1)RE
Approximate: Test bRE Ú 10R2
R2VCC VE
VB = , VE = VB - VBE, IE = IC
R1 + R2 RE
DC bias with voltage feedback:
VCC - VBE
IB = , IC IC IE
RB + b(RC + RE)
Common base:
VEE - VBE
IE = , IC IE
RE
Transistor switching networks:
VCC ICsat VCEsat
ICsat = , IB 7 , Rsat = , ton = tr + td, toff = ts + tf
RC bdc ICsat
Stability factors: COMPUTER ANALYSIS 235
IC IC IC
S(ICO) = , S(VBE) = , S(b) =
ICO VBE b
S(ICO):
Fixed bias: S(ICO) b
b(1 + RB>RE)*
Emitter bias: S(ICO) =
b + RB >RE
*Voltage-divider bias: Change RB to RTh in above equation.
*Feedback bias: Change RE to RC in above equation.
S(VBE):
b
Fixed bias: S(VBE) = -
RB
- b>RE-
Emitter bias: S(VBE) =
b + RB >RE
†
Voltage-divider bias: Change RB to RTh in above equation.
†
Feedback bias: Change RE to RC in above equation.
S(b):
IC 1
Fixed bias: S(b) =
b1
IC1(1 + RB>RE)[
Emitter bias: S(b) =
b1(1 + b2 + RB>RE)
‡
Voltage-divider bias: Change RB to RTh in above equation.
‡
Feedback bias: Change RE to RC in above equation.

4.21 COMPUTER ANALYSIS

●
Cadence OrCAD
Voltage-Divider Configuration The results of Example 4.8 will now be verified using
Cadence OrCAD. Using methods described in detail in the previous chapters, we can con-
struct the network of Fig. 4.113. Recall from the previous chapter that the transistor is
found under the EVAL library, the dc source under the SOURCE library, and the resistors
under the ANALOG library. The capacitor has not been called up earlier but can also be
found in the ANALOG library. For the transistor, the list of available transistors can be
found in the EVAL library.
The value of beta is changed to 140 to match Example 4.8 by first clicking on the
transistor symbol on the screen. It will then appear boxed in red to reveal it is in an active
status. Then proceed with Edit-PSpice Model, and the PSpice Model Editor Demo dialog
box will appear in which Bf can be changed to 140. As you try to leave the dialog box the
Model Editor/16.3 dialog box will appear asking if you want to save the changes in the
network library. Once they are saved, the screen will automatically return with beta set at
its new value.
The analysis can then proceed by selecting the New simulation profile key (looks like
a printout with an asterisk in the top left corner) to obtain the New Simulation dialog box.
Insert Fig. 4.113 and select Create. The Simulation Settings dialog box will appear in
which Bias Point is selected under the Analysis Type heading. An OK, and the system is
ready for simulation.
Proceed by selecting the Run PSpice key (white arrow in green background) or the se-
quence PSpice–Run. The bias voltages will appear as shown in Fig. 4.113 if the V option
selected. The collector-to-emitter voltage is 13.19 V 1.333 V 11.857 V versus 12.22 V
of Example 4.8. The difference is primarily due to the fact that we are using an actual
transistor whose parameters are very sensitive to the operating conditions. Also recall the
difference in beta from the specification value and the value obtained from the plot of the
previous chapter.