energies

Review
Electrically Active Defects in SiC Power MOSFETs
Mayank Chaturvedi , Daniel Haasmann , Hamid Amini Moghadam and Sima Dimitrijev *

Queensland Micro- and Nanotechnology Centre, Griffith University, Brisbane, QLD 4111, Australia
* Correspondence: [email protected]

Abstract: The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semicond
uctor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the
interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier
mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy
levels. To characterize these defects, techniques have evolved from those used for Si devices to
techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the
electrically active defects at and near the interface between SiC and the gate dielectric in SiC power
MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations
and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the
energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC.
Then, representative published results are shown and discussed for each class of defect.

Keywords: 4H-SiC; interface traps; near-interface traps; SiC power MOSFET

1. Introduction
In the current global environment, the demand for clean and cost-effective energy
motivates the development of efficient power conversion systems for applications such
as switch-mode power supplies, inverters for electric vehicles, battery chargers, and high-
frequency power converters [1,2]. The power-conversion systems utilize semiconductor-
based power switches, which need to satisfy four fundamental requirements: (1) high-
Citation: Chaturvedi, M.; blocking voltage, (2) high-power efficiency, (3) high-switching speed, and (4) normally OFF
Haasmann, D.; Moghadam, H.A.; operation of the switch [3].
Dimitrijev, S. Electrically Active The reverse-bias voltage that can be applied across a switch when it is OFF is known
Defects in SiC Power MOSFETs. as blocking voltage. The blocking voltage is limited by the breakdown voltage of the device,
Energies 2023, 16, 1771. https://
which can be determined from the solution of the one-dimensional Poisson’s equation [3]:
doi.org/10.3390/en16041771

Academic Editor: Alexey A. Sokol ε s Ecr 2

VB = (1)
2qND
Received: 17 November 2022
Revised: 5 January 2023 where VB is the breakdown voltage, ε s is the semiconductor permittivity, Ecr is the break-
Accepted: 11 January 2023 down or critical electric field, q is the value of electron charge, and ND is the doping level
Published: 10 February 2023 of the n-type drift region that supports the reverse-bias voltage. The critical electric field
is ten times higher in SiC (Ecr = 300 V/µm) than the Si (Ecr = 30 V/µm) due to the wider
energy gap in SiC (3.2 eV) compared to Si (1.12 eV) [3].
The switching circuits are used for power conversion to maximize the power efficiency
Copyright: © 2023 by the authors.
of the system. However, the resistance of the drift region is a key contributor to static power
Licensee MDPI, Basel, Switzerland.
loss in these switches, which consequently reduces the overall efficiency of the system. The
This article is an open access article
distributed under the terms and
specific resistance of the low doped drift region is given by [3,4]:
conditions of the Creative Commons
4VB 2
Attribution (CC BY) license (https:// Rsp = (2)
creativecommons.org/licenses/by/ ε s µn Ecr 3
4.0/).

Energies 2023, 16, 1771. https://doi.org/10.3390/en16041771 https://www.mdpi.com/journal/energies

Energies 2023, 16, 1771 2 of 16

where µn is the mobility of electrons in the drift region. Given that Ecr 3 is thousand times
higher for SiC than Si, the transition from Si to SiC enabled the development of power
switches with higher blocking voltages and reduced Rsp . The increased blocking voltage
allowed system designers to eliminate the use of bulky and expensive transformers. On the
other hand, the reduced Rsp resulted in the development of SiC power switches with both a
smaller area, hence smaller parasitic capacitances to reduce the dynamic power dissipation,
and a smaller ON resistance (R DS(on) ) to reduce the static power dissipation.
The third requirement, high switching speed is helpful in reduction of the size and cost
of the power system by allowing the use of smaller inductors. To obtain a high switching
speed, long switching delays must be avoided by the device. Therefore, metal–oxide–
semiconductor field-effect transistors (MOSFETs) are the preferred option for the controlled
power switches because they are unipolar devices that do not exhibit reverse and forward
recovery times.
The requirement of a normally controlled switch is significant for power-switching
applications. A normally OFF switch means that the switch is in the ON mode only when an
above-threshold positive voltage is applied at the controlling electrode (gate) and remains
in the OFF mode when no voltage is applied at the gate. This basic requirement can only
be achieved by using MOSFET as a switch, which is the key reason behind the popularity
of MOSFETs amongst other semiconductor devices.
In a nutshell, the wide energy gap and high critical electric field make SiC the best
choice to meet the demand for power switches. SiC is available in various polytypes, but the
most popular polytypes are 3C-SiC, 4H-SiC, and 6H-SiC. However, 4H-SiC is superior to its
counterparts due to its higher electron mobility and wider energy gap [5,6]. In this paper,
we will refer to 4H-SiC as SiC.
At a specific blocking voltage, SiC MOSFETs allow thinner drift layers and higher
doping concentrations in comparison with Si devices [3,7]. Consequently, SiC MOSFETs
have much smaller ON resistance, than Si MOSFETs [4,8], resulting in improved overall
efficiency due to reduced power losses [9]. However, a decade after the commercialization
of the first SiC power MOSFET in 2011, these power switches have still not fully utilized the
theoretical potential of SiC [10]. A high density of electrically active defects at and near the
SiC–SiO2 interface is attributed to the reduced performance and sub-optimal reliability of
these devices [11–13]. Therefore, the characterization of the SiC–SiO2 interface is important
to guide further improvements in the quality of the interface toward the development of
SiC MOSFETs that exploit the full potential of the material properties of SiC.
For a long time, the SiC–SiO2 interface in SiC MOSFETs was characterized by the
standard characterization techniques developed for the Si–SiO2 interface in Si MOSFETs.
However, recent studies reveal that novel characterization techniques are required to
accurately profile electrically active defects in the SiC–SiO2 interface [14,15]. With the
realization of the fact that the physical properties of the interface and characteristics of the
defects are different in SiC MOSFETs and Si MOSFETs, researchers are now focusing on
developing characterization techniques specifically for the SiC–SiO2 interface.
The aim of this review article is to enhance the present understanding of SiC MOS
structure by classifying the defects at and near the interface between SiC and the gate di-
electric and by describing their impact on the performance and reliability of SiC MOSFETs.
The article is presented as follows: in Section 2, electrically active defects are classified
based on their physical location and energy levels. Furthermore, the effect of a particular
type of defect on the device is briefly discussed. Section 3 presents standard characteriza-
tion methods to quantify interface traps. In Section 4, near-interface traps (NITs) below
the bottom of the conduction band and the corresponding measurement techniques are
presented. In Section 5, characterization techniques for NITs with energy levels above
the bottom of the conduction band are described. The introduced classification and the
reviewed results are summarized in Section 6.
Energies 2023, 16, 1771 3 of 16

2. Classification of Defects
The electrically active defects, situated at or near the SiC surface, trap mobile charge
carriers from and release them to the semiconductor. These defects, also known as traps,
have different energy levels. Subject to their physical locations and energy levels, these traps
cause distinct effects. To enable adequate analysis of these effects, we define the following
three classes of defects at and near the interface between SiC and the gate dielectric:
• Interface traps;
• Near-interface traps with energy levels aligned to the energy gap of SiC;
• Near-interface traps with energy levels aligned to the conduction band of SiC.
This classification is illustrated in Figure 1.

Interface Traps
E (eV)
NITs below EC
NITs above EC

0V
EC x

−3.2 V
EV
SiCxOy

SiC SiO2
Figure 1. Schematic diagram and classification of electrically active defects in the SiC MOS structure.

2.1. Interface Traps

The traps positioned at the interface between SiC and the gate dielectric, with energy
levels inside the energy gap, are known as interface traps. They are shown by circles
in Figure 1. These defects are analogous to the interface traps at the Si–SiO2 interface.
As illustrated in Figure 2a, the interface traps can capture carriers from the energy bands
and emit carriers into the bands via thermal emission. These processes are modeled by
Shockley–Read–Hall statistics [16,17]. Interface traps are usually quantified by their density
per unit area and unit energy, labeled D IT , to show their energy distribution.

Thermal Thermal Tunneling

emission/capture emission/capture
E (eV) Tunneling E (eV) E (eV)

EC x EC x EC x

EF EF EF
SiC SiCxOy SiO2 SiC SiCxOy SiO2 SiC SiCxOy SiO2
(a) (b) (c)
Figure 2. Schematic diagram illustrating the trapping and de-trapping mechanisms for the three
classes of defects: (a) thermal emission and capture in the case of interface traps, (b) two-step process—
tunneling and thermal emission/capture—in the case of NITs below EC , and (c) tunneling in the case
of NITs above EC .
Energies 2023, 16, 1771 4 of 16

2.2. Near-Interface Traps with Energy Levels Aligned to the Energy Gap of SiC (NITs below EC )
The defects located near the SiC surface inside the gate dielectric, and with energy
levels aligned to the energy gap, will be referred to as NITs below EC . In Figure 1, these
defects are represented by the triangles. These type of defects also exist near the Si–SiO2
interface, where they are also called border traps. However, the density of defects near
the Si–SiO2 interface is very small—much smaller than the interface traps. In the case of
SiC, the transition between SiC and SiO2 is through a layer labeled as SiCx Oy [18–20]. This
layer is responsible for a high density of NITs. The NITs below EC exchange charge with
the energy bands by two-step processes, involving tunneling to and from the interface
traps and thermal emission/capture to/from the energy bands [21]. The two-step charge
trapping/detrapping by NITs below EC is shown in Figure 2b. In this paper, we will
use the symbol D N IT ( ET < EC ) for the density of these traps per unit area and unit
energy, although the symbol D IT is used in many papers and they are not always properly
distinguished from the interface traps.

2.3. Near-Interface Traps with Energy Levels Aligned to the Conduction Band of SiC (NITs
above EC )
The traps positioned near the SiC surface inside the gate dielectric and with energy
levels aligned to the conduction band (energy levels above EC ) will be referred to as NITs
above EC . These NITs are represented by squares in Figure 1. Having energy levels aligned
to the conduction band, these traps exchange electrons by tunneling to and from the SiC
when the Fermi level enters the conduction band at the SiC surface due to gate bias above
the threshold voltage (VT ), as shown in Figure 2c. This effect is due to the quantum-
confinement effect [22,23] and is ignored by the classical theory. It is also important to note
that the response times of trapping and de-trapping by the NITs depends on their distance
from the interface.

2.4. Impact on Performance and Reliability of MOSFETs

The reduced performance and sub-optimal reliability of SiC MOSFETs are attributed
to a high density of electrically active defects mentioned above [24–27]. The interface traps
increase the threshold voltage by capturing the electrons attracted to the surface by the
gate voltage (VG ). During device operation, NITs below EC can trap electrons, causing
threshold-voltage instability, which is a reliability issue [28–30]. However, at the operating
gate voltages (VG > VT ), NITs above EC become active and continuously capture and
release electrons from the MOSFET channel by tunneling [31]. This decreases the average
density of free inversion-layer electrons, which reduces the average channel-carrier mo-
bility from the trap-free value of above 200 cm2 V−1 s−1 down to around 40 cm2 V−1 s−1 in
commercial SiC MOSFETs. The reduction in the average channel-carrier mobility is respon-
sible for a proportional decrease in channel current and, therefore, reduced performance of
SiC MOSFETs.

3. Interface Traps
Numerous electrical characterization techniques, which were initially developed to
characterize the Si-base MOS capacitors and MOSFETs, have been adopted for electrical
characterization of the SiC devices. Since the interface traps are the dominant defects in
Si devices, these conventional techniques are suitable for the defects with energy levels
corresponding to the sub-threshold gate voltages (VG < VT ) in SiC devices [32–35].

3.1. Characterization by C—V Based Techniques

Several C–V-based techniques were developed to measure the density of D IT : high
frequency C–V technique or Terman technique [36], AC conductance technique [37,38],
quasi-static C–V method [39,40], high–low C–V method [41], Hill–Coleman technique [42],
Q–C method [43], and C–ψS method [44].
Energies 2023, 16, 1771 5 of 16

The AC conductance technique is one of the most prevalent techniques used to quantify
D IT in MOS capacitors due to its accuracy, sensitivity, and reliability. This method measures
the complex admittance of the device to extract the conductance G p (ω ) at a specific VG .
In addition to the D IT , the conductance curves obtained from the AC conductance technique
allow the calculation of the capture cross-section of the defects, and surface potential
fluctuations [45]. Figure 3 shows typical results obtained using the AC conductance
technique to determine the D IT .

Figure 3. Density of interface traps measured by AC conductance method (a) before post-oxidation
annealing in NO (data from [46]) and (b) after post-oxidation annealing in NO (data from [47]).

Figure 3a shows that temperatures from 150 K to 600 K were needed to provide
profiling from 0.05 eV to 0.8 eV below EC [46]. A wide range of temperatures was required
to see the energy distribution because the charge emission time from the interface traps to
EC is proportional to exp[(−( EC − ET ))/kT ], where k is the Boltzmann’s constant and T
is the absolute temperature [48–50]. The density of interface traps is quite high, but these
results are for gate oxides grown in dry O2 , which is inadequate for the proper operation of
SiC MOSFETs.
The gate-oxidation process used in all commercial SiC MOSFETs involves some form
of nitridation in nitric oxide, such as post-oxidation annealing in nitric oxide (NO). The first
conductance-based measurements of gate oxides nitrided in NO are shown in Figure 3b [47].
The distribution of trap density as a function of VG was obtained from the conductance
technique performed at room temperature. The results demonstrate a significant reduction
in interface-trap density due to the nitridation effect achieved by growing the gate oxide in
NO. The interface-trap densities are quite low, but it should be noted that these oxides are
very thin.
Energies 2023, 16, 1771 6 of 16

3.2. Characterization by I–V Based Techniques

MOS capacitors are used to profile the interface traps using C–V-based characterization
techniques. However, the fabrication process of MOSFETs is more complex than that of
the MOS capacitors, which may result in a different distribution of the interface traps
in MOSFETs [51,52]. The I–V-based measurement techniques can be used to profile the
D IT in both MOSFETs and MOS capacitors. Charge-pumping [53–56] and sub-threshold
characteristics [52,57,58] are the most popular I–V-based measurement techniques. Some
typical results for the distribution of D IT using the charge pumping method are shown
in Figure 4.

Figure 4. D IT in 4H-SiC MOSFET characterized using the charge-pumping method: (a) room
temperature (data from [59]), (b) temperature range from −60 ◦ C to 200 ◦ C (data from [60]).

The charge pumping technique used with MOSFETs can profile the trap density
in the whole energy gap. Figure 4a shows the distribution of interface traps in 4H-SiC
MOSFETs [59]. It is worth noting that the interface traps in the order of 1012 cm−2 eV−1
were also measured near the top of the valence band (EV ).
Charge-pumping measurements on lateral MOSFETs fabricated on the usual Si-face
(0001) and also on the a-face (112̄0) of 4H-SiC are shown in Figure 4b [60]. The results show
that the D IT near EC is lower in the case of a-face, which suggests that a MOSFET channel
along the a-face will exhibit higher channel-carrier mobility [61–64]. This relates to the
higher mobility in MOSFETs with trench gate structure, which utilize the a-face to form
the channel. Moreover, measurements were performed at a wide range of temperatures
ranging from −60 ◦ C to 200 ◦ C to obtain the distribution of trap density close to EV and EC .
Energies 2023, 16, 1771 7 of 16

4. NITs below EC
There is an emerging realization that electrically active defects are not only located
at the interface, but are also situated near the SiC surface within the SiCx Oy layer. In this
section, we will discuss the NITs energetically aligned with the energy gap.

4.1. Characterization by Measurements on MOS Capacitors

An investigation performed by Yoshika et al. on SiC MOS capacitors, using con-
ductance technique at low temperatures, suggested that the nitridation of the dry oxides
created very fast NITs, which they referred to as very fast NI traps. The D N IT of the dry
oxide sample and the samples nitrided at 1150–1350 ◦ C are shown in Figure 5a [65].

Figure 5. Density of near-interface traps obtained by (a) the conductance technique (data from [65])
and (b) the high–low C–V measurements (data from [66]).

It was considered that the electrons were trapped due to thermal emission, which
resulted in high density of traps, 0.06 eV below the conduction band edge, and an excep-
tionally wide-ranging electron capture cross-section area of 10−16 cm2 –10−9 cm2 . However,
recent studies show that the trapping of electrons by NITs is a two-step process with tun-
neling to and from the interface traps, and thermal emission/capture to/from the energy
bands as shown in Figure 2b [66,67]. Figure 5b shows the D N IT in SiC MOS capacitors
obtained using the high–low method [66]. All the curves show high density of both NITs
and interface traps near the bottom of EC and, consequently, the thermal emission times are
very short. This means that the overall time response is determined by the tunneling time
in the two-step process. However, the tunneling times are also very short for the majority
of NITs that are located within fractions of a nanomoter from the SiC surface. The tunneling
time constant as a function of the distance from the SiC surface is shown in Figure 6 [26].
It can be observed that the tunneling time constant is in the order of 10−9 s for the NITs
Energies 2023, 16, 1771 8 of 16

located 0.5 nm away from the interface. Hence, low temperatures are needed to measure
these traps, as measured in [66].

Tunneling time constant (s)

Distance of trap from SiC–SiO2 interface, x (nm)

Figure 6. The tunneling time constant for near-interface traps based on the data obtained from [26].

4.2. Characterization by Measurements on MOSFETs

To characterize NITs near the conduction band edge in SiC MOSFETs, Hatakeyama et al.
developed a method using Hall effect measurements and split C—V technique. Figure 7a
and b show comparisons of the D N IT and the field-effect mobility (µ FE ), respectively [68].
The highest mobility achieved by the sample NO 60 (post-oxidation annealing in nitric
oxide at 1250 ◦ C for 60 min) was ≈ 37 cm2 V−1 s−1 , which is much smaller than the bulk
mobility of 1000 cm2 V−1 s−1 . It is clear from the results shown in Figure 7 that the high
density of NITs is one of the main reasons for such low mobilities [68]. Moreover, similar to
the results discussed previously, the D N IT is high close to the bottom of the EC .

Figure 7. Comparison of (a) the density of near-interface traps and (b) the field-effect mobility in
MOSFETs with different gate dielectrics. Data are from [68].
Energies 2023, 16, 1771 9 of 16

5. NITs above EC
The operating gate voltage of the commercially available SiC MOSFETs ranges between
15 V and 20 V. Hence, it is important to characterize the effects of defects that are active at
the operating gate voltages.
At VG > VT , the Fermi level (EF ) is inside the conduction band at the SiC surface due
to the quantum-confinement effect. Modeling the quantum-confinement effect, Pennington
and Goldsman calculated the energy bands of P-type SiC as a function of the density of
electrons in strong inversion (Ninv ). The results for the position of the Fermi level in the
case of (0001) 4H-SiC are shown in Figure 8 [69]. Figure 9 shows that the positions of the
Fermi level (EF ) with respect to the bottom of the conduction band (EC ) are similar in the
following two cases: (a) an N-type SiC in accumulation and (b) a P-type SiC in strong
inversion as the P-type body of an N-channel MOSFET. The importance of this similarity is
that MOS capacitors on N-type SiC can be used as representative structures for N-channel
MOSFETs operating above VT .
EF – EC (eV)

Ninv ( )

Figure 8. The relationship between the position of the Fermi level at the surface of (0001) 4H-SiC and
the density of electrons in the inversion layer (Ninv ). Data points are from [69].

(a) (b)
EC
EC
EF EF
EV
EV

SiC SiO2 SiC SiO2

Accumulation layer in N-type SiC Inversion layer in P-type SiC

Figure 9. Energy-band diagrams for (a) MOS capacitor on N-type SiC in accumulation and (b) the
P-type body of a MOSFET in strong inversion, showing energy-band similarity at the SiC surface.

5.1. Characterization by Measurements on MOS Capacitors

Standard C–V techniques can characterize NITs only at the sub-threshold voltages
(VG < VT ) and are unable to detect the impact of NITs for VG > VT . For example, in the
standard high–low technique, the D N IT is calculated using the capacitance measurement at
high and low frequencies [41]. However, for MOS capacitors in the accumulation region,
the capacitance at low frequency is equal to the oxide capacitance (Cl f = Cox ), causing the
equation for the D N IT to be divided by Cox − Cl f = 0 [70]. Hence, the equation of the stan-
dard high–low technique cannot be used to calculate the D N IT in the accumulation region.
Recently, several techniques have been developed to profile the NITs with energy
levels aligned to the bottom of the conduction band. The transient-current method can
be used to characterize the NITs in MOS capacitors biased in accumulation by measuring
transient currents through the capacitor. To measure the transient currents shown in
Energies 2023, 16, 1771 10 of 16

Figure 10, the capacitor was first biased in accumulation for 30 s with the voltage high
enough to position the Fermi level at EC , and then the bias voltage was steeped-up to
position the Fermi level above EC . The tunneling of electrons to the NITs resulted in a
transient current that was measured and shown in Figure 10 for different samples [71].
However, this method can only detect slow NITs that were further from the SiC surface,
as the response times of the measured traps were longer than 20 ms (refer to Figure 6).

Dry oxide
Nitrided Oxide
Current (pA)

Time (s)
Figure 10. Transient currents due to electron trapping by NITs above EC , measured at room tempera-
ture. Data obtained from [71].

The density of NITs increases toward the SiC surface, and they have a stronger impact
on the performance and reliability of the device. Hence, with the aim of detecting fast
NITs, a direct measurement technique was developed. In this method, the distortions in
the output sinusoidal voltage measured across the MOS capacitor were attributed to the
NITs with response times of hundreds of nanoseconds [72]. Figure 11 shows the D N IT
above EC at different frequencies for the MOS capacitors with four different gate oxides: (a)
thermally grown in dry O2 at 1250 ◦ C for 1 h (O2 ), (b) thermally grown in dry O2 followed
by annealing in nitric oxide for 1 h each (O2 + NO), (c) annealed in 100% nitric oxide for 5 h
(NO), and (d) oxide deposited at low temperature and annealed in 100% nitric oxide for 5 h
(LTO + NO) [73].

(a) O2 (b) O2 + NO
)

)
Trap density,

Trap density,
DNIT (

DNIT (
ET –

ET –
E C(

E C(
eV)

eV)

Hz)
Frequency, f (M Frequency, f (M
Hz)

(c) NO (d) LTO + NO

)

)
Trap density,

Trap density,
DNIT (

DNIT (
ET –

ET –
E C(

E C(
eV)

eV)

Hz) Hz)
Frequency, f (M Frequency, f (M

Figure 11. Densities of near-interface traps measured by the direct measurement technique for (a) O2 ,
(b) NO + O2 , (c) NO, and (d) LTO + NO samples. Data obtained from [73].
Energies 2023, 16, 1771 11 of 16

5.2. Characterization by Measurements on MOSFETs

The complex structure of power MOSFETs makes it difficult to determine the reduc-
tion in channel-carrier mobility due to NITs. Since the NITs above EC impact the above
threshold I–V characteristics, one approach is to measure the transfer I–V characteristic and
then to use the mobility as a fitting parameter in a model for the transfer I–V characteristic.
Potbhare et al. proposed a physical model that could match the experimental results shown
in Figure 12 [74]. This model assumes near-interface traps spatially located few microm-
eters away from the interface. However, the model does not account for the quantum
confinement effect and, consequently, positions the traps below the conduction band.

Simulation 200 °C
Experiment
)
Drain Current, ID (

100 °C

25 °C

Gate Voltage, VGS (V)

Figure 12. Comparison of measured and simulated transfer characteristics of a SiC MOSFET at three
different temperatures. Data taken from [74].

An integrated-charge technique was developed recently to profile the NITs with

energy levels aligned with the conduction band [51,70]. This technique can be applied
to commercial MOSFETs as well as MOS capacitors. The integrated-charge method can
measure NITs active at the operating gate voltage with response times in the order of one
hundred nanoseconds. To explain this method, the C–V curves of the 1200-V SiC MOSFETs
measured using the integrated-charge technique for different response times are shown
in Figure 13 [75]. The commercial MOSFETs with planar and trench gate structures were
obtained from the same manufacturer.
The integrated-charge technique measures charge by integrating the current flowing
through the gate-capacitor of the SiC device. A trapped electron is unable to participate in
the current charging/discharging the gate capacitor for the duration it is trapped, resulting
in a smaller measured capacitance (CG ). It can be observed from Figure 13 that there is a
drop in CG with faster response times (τmin ), which corresponds to a higher density of NITs
with faster response times. Figure 14 compares the fraction of the total density of electrons
trapped for longer than τmin (γTOT ) in planar and trench SiC MOSFETs. The extrapolation
of the measured data indicates that the 80% and 60% electrons are trapped for the time
response of 10 ns in the planar and trench MOSFETs, respectively. Hence, the trench
MOSFET will have higher channel-carrier mobility and better performance compared
to the planar MOSFET at operating VG . These results are also in accordance with the
Hall measurements, which revealed that only 20% of electrons are free at the highest gate
voltages [76].
Energies 2023, 16, 1771 12 of 16

Figure 13. C–V curves measured using the integrated-charge technique for (a) planar MOSFET,
and (b) trench MOSFET. Data points are taken from [75].

Trench MOSFET
(%)
Fraction of electrons trapped for

Planar MOSFET
longer than ,

Minimum capture/release time, (s)

Figure 14. Comparison of the fraction of total density of electrons attracted to the SiC surface by
VG = 18 V and trapped for longer than τmin . Data obtained from [75].
Energies 2023, 16, 1771 13 of 16

For a given blocking voltage, there are many families of SiC MOSFETs fabricated by
various manufacturers available on the market. Hence, it is very challenging for power
engineers to select the family of MOSFETs that will deliver the best quality and reliability.
The integrated-charge technique also provides a figure of merit for the selection of the
family of SiC MOSFETs that ensures the best performance and reliability. This figure of
merit is obtained by multiplying R DS(on) given in the datasheet of the device and measured
value of gate capacitance at the manufacturer recommended operating gate voltage [77].
The integrated-charge method or standard AC measurements at low frequencies of up to
1kHz with any commercial instrument can be used to obtain the value of CG . The figure of
merit is proportional to the density of NITs on the device. Hence, the designer can select
the MOSFET family with the best figure of merit that will provide the highest quality due
to the minimum density of NITs.

6. Summary
This article classifies the electrically active defects in SiC MOS capacitors and SiC
MOSFETs into three categories: (1) interface traps, (2) near interface traps (NITs) with
energy levels aligned to the energy gap, and (3) near-interface traps with energy levels
aligned to the conduction band of SiC. The interface traps and NITs with energy levels
aligned to the energy gap capture electrons that are attracted to the SiC surface by the
gate voltage. Accordingly, their effect is observed as an increase in the effective threshold-
voltage value. The origin of the near-interface traps, irrespective of their energy levels, is
due to an SiCx Oy transition layer between SiC and SiO2 . Electron trapping at NITs located
further from the SiC surface is slow, but these NITs can trap electrons during the MOSFET
operation, resulting in a threshold-voltage drift that creates a reliability issue. At the
operating gate voltage (VG > VT ), owing to the quantum confinement effect, the Fermi
level is inside the conduction band at the SiC surface. Consequently, NITs with energy
levels aligned to the Fermi level capture and release electrons from and to the MOSFET
channel. This continuous capture and release of channel electrons reduces the density of
mobile electrons at any instant of time, which is observed as a reduced average value of
the channel-carrier mobility. Hence, the NITs with energy levels aligned to the conduction
band are responsible for the degraded performance of the SiC power MOSFETs.

Author Contributions: Conceptualization, M.C. and S.D.; methodology, M.C. and S. D.; software,
M.C.; validation, M.C., D.H. and S.D.; formal analysis, M.C., D.H., H.A.M. and S.D.; investigation,
M.C. and S.D.; resources, M.C. and S.D.; data curation, M.C.; writing—original draft preparation,
M.C. and S.D.; writing—review and editing, M.C., D.H., H.A.M. and S.D.; visualization, M.C. and
S.D.; supervision, S.D.; project administration, S.D.; funding acquisition, S.D. All authors have read
and agreed to the published version of the manuscript.
Funding: This research received no external funding.
Data Availability Statement: The data are contained within the article.
Acknowledgments: This work was performed at the Australia National Fabrication Facility (ANFF),
Queensland node, QLD, Australia, a company established under the National Collaboration Research
Infrastructure Strategy to provide nano- and microfabrication facilities to Australia’s researchers.
Conflicts of Interest: The authors declare no conflicts of interest.

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