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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2020.3040687, IEEE
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Hybrid Connected Unified Power Quality Conditioner

Integrating Distributed Generation with Reduced
Power Capacity and Enhanced Conversion Efficiency
Jiangfeng Wang, Member, IEEE, Kai Sun, Senior Member, IEEE, Hongfei Wu, Senior Member, IEEE,
Jianxin Zhu, Student Member, IEEE, Yan Xing, Member, IEEE and Yunwei Li, Fellow, IEEE

Abstract—A hybrid connected unified power quality vgx, vLx (x=a, b, c) Ac grid and load voltages
conditioner integrating distributed generation Vgx, VLx (x=a, b, c) RMS values of ac grid and load voltages
(HCUPQC-DG) is proposed. Two dc ports are created at the vgd, vgq Actual grid voltages in the dq frame
dc link of the HCUPQC-DG, in which one low-voltage (LV) vgd*, vgq* Rated grid voltages in the dq frame
dc port is directly connected to DG, and the other vsx (x=a, b, c), vsab Output ac phase and line voltages of the
high-voltage (HV) dc port is indirectly connected to DG
through the front-end dc-dc converter. With the hybrid
series converter
connected configuration, the HV is designed to ensure the vsan, vpan Midpoint voltages of the series and
dc-ac voltage conversion capability, while the LV, i.e., the parallel converters
voltage of DG, can be relatively low and vary in a wide Vac, Vacpk RMS and peak values of the output ac
range. Besides, most active power can be directly line voltages
transferred from DG to the ac load or grid through the isL, ipL LV port current of the series and parallel
direct power flow path. Hence, the conversion efficiency is converters
enhanced, and the power capacity of the front-end dc-dc igx, iLx (x=a, b, c) Ac grid and load currents
converter is significantly reduced. The operating principle Igx, ILx (x=a, b, c) RMS values of ac grid and load currents
and the control and modulation strategies of the proposed
HCUPQC-DG are discussed. Moreover, the power flow
isx, ipx (x=a, b, c) Output ac phase currents of the series
through the HCUPQC-DG is analyzed in detail to and parallel converters
understand the system operation. Experimental results ipd, ipq Actual output currents of the parallel
with a 3-kVA prototype are provided to verify the feasibility converter in the dq frame
and effectiveness of the proposed HCUPQC-DG. ipd*, ipq* Reference output currents of the parallel
converter in the dq frame
Index Terms—Distributed generation, efficiency, power Pdg, Pg, PL Active power of DG, grid and load
flow, power quality, unified power quality conditioner. Ps, Pp Active power flowing through the series
and parallel converters
NOMENCLATURE Ps_L, Ps_H Active power flowing through the LV
DG Distributed generation and HV ports of the series converter
UPQC Unified power quality conditioner Pp_L, Pp_H Active power flowing through the LV
UPQC-DG UPQC integrating DG and HV ports of the parallel converter
HCUPQC-DG Hybrid connected UPQC-DG Pdc-dc Active power flowing through the dc-dc
LV, HV Low-voltage and high-voltage converter
RMS Root-mean-square ΔPdc-dc Reduced active power flowing through
VL, VH Dc voltages of the LV and HV ports the dc-dc converter
s, p subscripts Parameters of the series and parallel
converters I. INTRODUCTION

Manuscript received June 5, 2020; revised September 11, 2020 and
October 25 2020; accepted November 16, 2020. This work was
supported in part by the National Natural Science Foundation of China
under Grants 52007098, 51811540405 and 51807104, in part by the
N owadays, due to energy scarcity and environmental issues,
distributed generation (DG) sources like photovoltaic (PV)
arrays have been significantly increasing [1, 2]. In distribution
China Postdoctoral Science Foundation (No. 2020M670326), and in
part by the Delta Power Electronics Research and Education power systems, grid voltage disturbances, e.g., voltage sags and
Development Program (DREM2019005). (Corresponding author: Kai swells, harmonics, and load current disturbances, e.g., current
Sun.) harmonics or unbalancing, are the most common power quality
J. Wang and K. Sun are with the State Key Lab of Power Systems,
Department of Electrical Engineering, Tsinghua University, Beijing
problems [3, 4]. A unified power quality conditioner (UPQC) is
100084, China (e-mail: [email protected], a versatile device as it mitigates voltage disturbances in the grid
[email protected]). side and current disturbances in the load side simultaneously [5,
H. Wu, J. Zhu and Y. Xing are with the Center for
More-Electric-Aircraft Power System, College of Automation
6]. With the ever-growing number of DG sources, the
Engineering, Nanjing University of Aeronautics and Astronautics, combination of a traditional UPQC with DG is an emerging
Nanjing 211106, China (e-mail: [email protected], trend in modern distribution power systems [7]. It integrates
[email protected], [email protected]).
DG, such as that facilitated by PV modules [8-11], at the dc link
Y. Li is with the Department of Electrical and Computer Engineering,
University of Alberta, Edmonton, AB, T6G 1H9, Canada (e-mail: of the UPQC. The so-called UPQC-DG features several
[email protected]).

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Series Parallel Load Series Parallel Load

ac Grid ac Grid
Converter Converter Converter Converter
Traditional solution one:
directly connected
Proposed solution:
DG hybrid connected
VDC
Source dc-dc
1 VH
DG Converter
Traditional solution two:
indirectly connected Source
VL
2
DG dc-dc
V VDC
Source L Converter Fig. 2. Proposed HCUPQC-DG.

Fig. 1. Traditional directly and indirectly connected UPQC-DG. However, these attractive approaches are still limited to being
applied in a single dc-dc or dc-ac converter, and have not yet
advantages over the traditional UPQC, such as compensation of been addressed in more complicated power equipment, like
voltage interruption and active power transfer capability from UPQC-DG.
DG to the load or grid [12, 13]. Until now, the existing architecture of UPQC-DG just
The existing typical architecture of UPQC-DG is shown in comprises the two configurations shown in Fig. 1, and the
Fig. 1, where DG is directly [8, 9, 14] or indirectly [10, 11, 15] power converter topologies used are also conventional. They
connected to the dc link of UPQC. For the directly connected still suffer from several problems that must be solved urgently,
UPQC-DG, DG sources are directly coupled to the dc link, e.g., high-rated power converter capacity and low conversion
which supplies active power required by the load through the efficiency. To address these issues, the major contribution of
parallel converter and also provides active power consumed by this paper is to propose a hybrid connected unified power
the series converter for grid voltage compensation. The direct quality conditioner integrating distributed generation
configuration features the advantages of simple architecture, (HCUPQC-DG). A comprehensive analysis for the topology,
low cost, and high efficiency, but suffers from the major control and modulation strategies, and active power flow is
drawbacks that the voltage of DG is limited by the common dc presented in detail to understand the nature of the proposed
bus of the UPQC. To meet the grid-connected requirement, the HCUPQC-DG. Major advantages of the proposed solution are
common dc-bus voltage is relatively high, which leads to more much lower power capacity of the dc-dc converter and higher
cascaded modules. In practical applications, the DG voltage overall conversion efficiency. The rest of this paper is
can be relatively low and vary in a wide range [16]. In these organized as follows. In Section II, the architecture and detailed
cases, the indirect configuration is preferred, where a front-end topology of the proposed HCUPQC-DG are presented. In
dc-dc converter is employed between DG and the UPQC to step Section III, the control and modulation strategies for the
up the DG voltage [17]. Although featuring flexible voltage HCUPQC-DG are derived. In Section IV, the active power flow
range of DG, the commonly used indirectly connected of the HCUPQC-DG is analyzed in detail, and the power rating
UPQC-DG still faces the following problems: (1) Part of active of the dc-dc converter is discussed. Experimental verifications
power from DG is used for voltage compensation, while the are given in Section V. Finally, conclusions are drawn in
other part of active power is transferred to the load or grid. Section VI.
However, all the active power from DG must be processed by
the dc-dc converter, which is very high-rated; and (2) all the II. PROPOSED HCUPQC-DG
active power supplied from DG should be processed twice,
leading to low conversion efficiency. A. Basic Idea of the Proposed HCUPQC-DG
As for the topology of UPQC-DG, the boost converter [10, As shown in Fig. 1, the major difference between traditional
11] is usually employed as the front-end dc-dc converter, and directly and indirectly connected UPQC-DG is the usage of the
the traditional two-level dc-ac converter [5, 9, 10] is used as the front-end dc-dc converter. For the indirect configuration, the
parallel and series converters. Multilevel converters are dc-dc converter is responsible for connecting different DGs
attractive solutions for UPQC-DG due to lower switching with wide voltage range to the common dc bus of the
UPQC-DG. However, it should be noted that, there is no need
power dissipation [8, 18]. However, the control and modulation
to use the dc-dc converter in all cases, especially for voltage
strategies become more complicated since capacitor voltage
compensation. For instance, during shallow voltage sags, the dc
balance is required [19]. In addition, the issues of multi-stage voltage of DG is capable to generate a relatively small ac
active power conversion and high power rating of the dc-dc voltage, without using the dc-dc converter. This means, in this
converter remain unsolved. Recently, the concept of partial case, the series converter can work well under a low dc voltage
power processing was proposed to reduce both power with direct configuration, and hence the power conversion
conversion stages and power converter ratings [20-24]. The stage and power losses can be reduced. This implies that, if one
concept was introduced as partial power converters in dc-dc combines the direct and indirect configuration and rebuilds a
applications [20, 21] and multi-port converters in dc-ac new hybrid configuration, it is possible to take advantage of
applications [22-24]. These new topologies effectively reduce each one. Inspired by this idea, a hybrid connected UPQC-DG
the conversion stage via creating a direct power flow path. (HCUPQC-DG) is proposed, as shown in Fig. 2. The proposed

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vga Lga iga Tsa vLa iLa Linear/

vLb Nonlinear
vgb Lgb igb Tsb iLb load
Lgc igc Tsc vLc i
vgc Tpa Tpb Tpc Lc

Csa vsa C2
isa Lsa VH L pa i pa i pb i pc
Csb vsb
isb Lsb S s _ Hx S p _ Hx L pb
Csc vsc
S s _ Lx1 S s _ Lx 2 isL i pL S p _ Lx 2 S p _ Lx1
isc Lsc L pc
C1
S s _ Zx VL S p _ Zx
Series Converter Parallel Converter
n

iH
L1 D1
Proposed hybrid
iin S1 connected method

Boost Converter
iL
Fig. 3. Typical topology of the proposed HCUPQC-DG.

HCUPQC-DG is a combination of traditional directly and

indirectly connected UPQC-DGs. The hybrid configuration
C2 C2
provides two dc ports, in which one low-voltage (LV) dc port VH VH
(marked in red), VL, is directly connected to DG, and the other S p _ Hx A S p _ Hx A
high-voltage (HV) dc port (marked in blue), VH, is indirectly S p _ Lx 2 S p _ Lx1 B S p _ Lx 2 S p _ Lx1 B
connected to DG through the front-end dc-dc converter. These C C
two dc ports are both interfaced with the common dc link of the C1 C1
VL S p _ Zx VL S p _ Zx
HCUPQC-DG.
With the hybrid connected configuration, numerous
remarkable features can be achieved.
(1) Voltage range of DG: The voltage VH is designed to (a) (b)
ensure the dc-ac voltage conversion capability, and the voltage Fig. 4. Equivalent circuits of the multi-port parallel converter related to
different switching states: (a) (Sp_Hx,Sp_Lx1,Sp_Lx2,Sp_Zx)=(1,1,0,0), (b)
VL, i.e., the DG voltage, can be relatively low and vary in a wide (Sp_Hx,Sp_Lx1,Sp_Lx2,Sp_Zx)=(0,1,1,0).
range.
(2) Active power conversion of DG: Since partial active Taking the multi-port parallel converter as an example, the
power can be transferred through the direct power flow path, equivalent circuits related to different switching states are
the power conversion efficiency is enhanced. illustrated in Fig. 4. As shown in Fig. 4(a), when Sp_Hx and Sp_Lx1
(3) Power capacity of the dc-dc converter: Since the dc-dc turn on, the current flows from the HV port to the ac side, which
converter only processes partial active power of DG, the power means part of the input power can be fed to the ac side after
capacity can be reduced. processed by the dc-dc converter. On the other hand, when
(4) Power quality: With the help of the parallel and series Sp_Lx1 and Sp_Lx2 turn on, the current is directly transferred from
converters, the function of power quality control still remains. the LV port to the ac side without processed by the dc-dc
converter, as shown in Fig. 4(b).
B. Typical Topology and Basic Operation
A typical topology of the proposed HCUPQC-DG is C. Brief Comparison with the Traditional Solution
illustrated in Fig. 3. A boost converter is employed as the For traditional solutions, the six-switch two-level converter
front-end dc-dc converter. The topology of the parallel and [15] and three-level converter [18] are most widely used as the
series converters can be derived from the conventional parallel and series converters. As is known, in terms of
three-level converter. Taking the T-type three-level converter conversion efficiency, the traditional solution with three-level
as an example, it is seen from Fig. 3 that one of the converters is more preferred. Hence, the traditional UPQC-DG,
voltage-dividing capacitors of the traditional T-type three-level in which the T-type three-level converter is used as the parallel
converter is separated to interface with the LV dc port, and the and series converters, is chosen for comparison in this paper,
original dc bus remains to interface with the HV dc port. and a brief comparison between the proposed HCUPQC-DG
Using the same method in different three-level circuits, a and traditional solution is summarized as follows.
family of multi-port parallel and series converters and the (1) Topology: The topology of the proposed HCUPQC-DG
related HCUPQC-DG topologies can be obtained. is similar to that of the traditional solution. The same number of

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power devices is used in the proposed and traditional solutions, vdc S1

VH* + dc-dc
and the voltage stresses of the devices S1, Ss_Hx, Ss_Zx, Sp_Hx, and PI PWM
 Converter
Sp_Zx are equal to VH. However, the circuit connection is VH
different, and the voltage stresses of the devices Ss_Lx1, Ss_Lx2, (a)
Sp_Lx1, and Sp_Lx2 in the traditional solution are always equal to
i pdf
VH/2, while those in the proposed solution are determined by iLd iLdf i*pdh+ + vdp
the voltage range of VL. The voltage stresses of the devices iLa dq LPF  PI
iLb +  SV- Parallel
Ss_Lx1, Sp_Lx1 are VL and the voltage stresses of the devices Ss_Lx2, abc i pd
iLc vqp PWM converter
Sp_Lx2 are (VH-VL). i pa 1 / Tpx PI
i pb dq iLq + 
(2) System control: The system control of the proposed i pc abc 1 / Tpx i pq
solution using multi-port converters as the parallel and series
(b)
converters would be different from that of the traditional
vsa
solution using two-port converters. vsb
dq
vsd
+ 
(3) Modulation: In traditional solutions, the modulation vsc abc v*gd + *
vsd isd* + vds
vga 1/ 3 PI PI
strategy of the three-level converter is used for realizing dq 
vgd 
vgb isd SV- Series
vsq
neutral-point voltage balance. However, in the proposed abc v *
+ 
vgc v*gq + gq vsq isq* + vqs PWM Converter
solution, the modulation strategy of the multi-port converter is isa
dq 1/ 3 PI

PI
isb isq
used to ensure that the active power from DG can be transferred isc abc
through the direct power flow path as much as possible, so that (c)
the system efficiency can be enhanced and the power capacity Fig. 5. System control of the proposed HCUPQC-DG. (a) control of the
of the dc-dc converter can be reduced. front-end dc-dc converter; (b) control of the multi-port parallel converter;
(c) control of the multi-port series converter.
III. CONTROL AND MODULATION STRATEGY the voltage VL. Therefore, the control of the proposed solution
A. System Control is simpler than that of traditional solutions.
The control targets of the proposed HCUPQC-DG include 3) Control of multi-port series converter
dc-bus voltage regulation, active power delivery, and power The control block diagram of the multi-port series converter
quality control. These control targets can be coordinated by the is shown in Fig. 5(c). In Fig. 5(c), vsx is the output voltage of the
front-end dc-dc converter, the multi-port parallel converter, and series converter, isx is the output current of the series converter,
the multi-port series converter. and vgx is the grid voltage, respectively. To compensate the grid
1) Control of front-end dc-dc converter voltage sag or swell, the series converter is controlled as a
voltage source. The injected ac voltage is regulated by using the
The front-end dc-dc converter can be used to regulate the
traditional in-phase compensation strategy. The control
dc-bus voltage. The control block diagram is shown in Fig. 5(a).
algorithm is also implemented in the synchronous rotating dq
It is seen that the dc-bus voltage VH is regulated by the dc-dc
frame, and the voltage reference can be calculated by
converter via a proportional-integral (PI) controller.
vsd
*
 1 v*gd  vgd 
2) Control of multi-port parallel converter  *   , (2)
The control block diagram of the multi-port parallel converter vsq  3 v*gq  vgq 
is shown in Fig. 5(b). In Fig. 5(b), iLx (x=a,b,c) is the load where vgd* and vgq* are rated grid voltages, and vgd and vgq are
current, and ipx is the output current of the parallel converter. To actual grid voltages in the dq frame, respectively. In this paper,
mitigate the load reactive and harmonic currents, the parallel vgd* is set to 220 2 , and vgq* is set to zero. The coefficient
converter is controlled as a current source. The control
1 3 is introduced since a Y-△ connection is used for the
algorithm is implemented in the synchronous rotating dq frame,
and the current reference is given by series transformer. To track the voltage reference, a dual-loop
control scheme with PI regulators is implemented.
i*pd  i*pdh  i*pdf 
*   (1) As mentioned above, the following conclusions can be drawn
i pq   iLq  for the system control of the proposed HCUPQC-DG.
(1) The overall control of the proposed solution is similar to
In the d axis, ipdh* is the ac component of the d-axis current
that of traditional solutions. The major difference is that, as for
reference. It is equal to the harmonic component of the load
the multi-port parallel converter, the control is much simpler due
currents, which can be extracted by a low pass filter (LPF). ipdf*
to the reduced voltage-balance control loop.
is the dc component of the d-axis current reference, which
(2) For each converter in the proposed solution, several
represents the output active currents of the parallel converter. In
simple control strategies are given here as examples to verify the
the q axis, the q-axis output signal of the load currents iLq is
basic function of the proposed HCUPQC-DG. Apart from them,
directly used as the current reference. To track the d- and q-axis
several other advanced control algorithms used in traditional
current reference, PI regulators are used in this paper due to its
solutions [8-10] can also be extended to the proposed
easy implementation.
HCUPQC-DG.
As shown in Fig. 5(b), for the proposed solution, there is no
need to realize the dc-bus capacitor voltage balance, because B. Modulation Strategy
one of the voltage-dividing capacitors is directly clamped by The modulation strategy is the key to realize that the active

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
(0,2,0) Sector II (l,2,0) (2,2,0)

(0,l,0) (l,l,0) (2,l,0)

Sector III Sector I VL  Vacpk

(0,2,l) (l,2,l) (2,2,l) Pdr

(0,2,2) (0,l,l) (l,2,2) (2,2,2) (2,l,l) (l,0,0) (2,0,0)

(l,l,l) (0,0,0)  VL  Vacpk
(0,l,2) (l,l,2) (2,l,2)

Sector IV Sector VI
VL VH Vac VH
(0,0,l) (l,0,l) (2,0,l)
Fig. 8. Curve of the direct power ratio Pdr.

(0,0,2) Sector V (l,0,2) (2,0,2) vector (2,l,l) is just opposite to that with the positive small
Fig. 6. Modified space vector diagram. vector (l,0,0), as shown in Fig. 7(b). Using the same analysis
method, it is easy to obtain that all the positive small vectors
make the current iL flow out of the VL port and hence increase
La (2, l , l ) : La the average value of iL, whereas all the negative small vectors
VH VH
C2 vA C2 iL  ib  ic vA just have an opposite effect. Therefore, to maximize the
ia  ia  0 ia average value of iL, the positive small vector can be selected
(l , 0, 0) : ib ic ib ic while all the negative small vector should be abandoned. After
vB vC vB vC selecting the voltage vectors, the vector dwell-time calculation
VL iL  ia  0 VL
C1 Lb Lc C1 Lb Lc and the duty-cycle calculation for each switch are similar to that
of traditional solutions and will not be repeated here. Above all,
(a) (b) it is also found that the modulation strategy of the multi-port
Fig. 7. Equivalent circuit of the multi-port converter with the examples converter is simpler than that of the three-level converter,
of positive and negative small vectors: (a) positive small vector (l,0,0); because it only must choose all the positive small vectors and
(b) negative small vector (2,l,l). discard all the negative small vectors for synthesis in the
power from DG can be transferred through the direct power proposed solution, instead of complicatedly arranging both
flow path as much as possible. To fulfill this target, it is positive and small vectors to realize voltage balance in
necessary to maximize the average value of the current iL, i.e., traditional solutions.
the sum of the currents ipL and isL, as shown in Fig. 3. With the modified modulation strategy, the direct power
According to the similarity of the topology between the ratio Pdr, which is defined as the active power transferred
multi-port converter and the traditional T-type three-level through the direct power flow path PL with respect to the total
converter, the space vector diagram of the multi-port parallel active power Ptotal, is given as
and series converters can be derived, as shown in Fig. 6. 1 2
iL  d
2 0
Different from the definition of the switching state in traditional VL 
PL
solutions, the switching state is defined as “l” (0<l≤2) instead Pdr (VL ,Vac )   , (3)
Ptotal 3  Vac  I
of “1” when the phase-leg is connected to the VL port in the
multi-port converter, since the voltage VL is variable. Therefore, where Vac is the root-mean-square (RMS) value of the ac line
the magnitude of positive small vectors (marked with red solid voltage, and I is the RMS value of the fundamental active
line in Fig. 6), e.g., (l,0,0), and negative small vectors (marked component of the phase current. The curve of the direct power
with blue solid line in Fig. 6), e.g., (2,l,l), change with the ratio Pdr in terms of the voltages VL and Vac is shown in Fig. 8. It
variation of l, i.e., the voltage VL. is seen that Pdr increases with the dc voltage VL but decreases
As is known, for the traditional three-level converter, the with the ac line voltage Vac. Once VL is larger than the peak
neutral point current, and capacitor voltage balance can be value of ac line voltage Vacpk, Pdr=1, which means that all the
controlled by adjusting positive and negative small vectors [11, active power can be transferred from DG to the load or grid
25]. This inspires the idea that the currents isL and ipL in the through the direct power flow path.
multi-port converter can also be regulated by these two kinds of For the parallel converter, the ac output is connected to the
voltage vectors. The equivalent circuit of the multi-port load through a transformer with a constant turn ratio, and hence
converter with the examples of positive and negative small the ac line voltage is constant. The worst case (i.e., the case in
vectors is shown in Fig. 7. As seen in Fig. 7(a), the current iL is which Pdr is minimum) for the parallel converter corresponds to
equal to the phase current ia with the function of the positive the minimum voltage of VL, and the minimum value of Pdr for
small vector (l,0,0). When considering the active component, the parallel converter is obtained as
the phase current ia is in phase with the voltage vA. Noting that Pp _ dr min  Pdr (VL min , V p _ ac ) , (4)
the positive small vector (l,0,0) is used to synthesize the where Vp_ac is the RMS value of the ac line output voltage of the
reference voltage vector in Sector I or VI, where the voltage vA parallel converter.
is a positive value. Accordingly, a positive current iL flows out For the series converter, the ac output is used for voltage
of the VL port. However, the current iL with the negative small compensation and the injected ac line voltage is variable with

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Pg Pg+Ps PL=Pg+Pdg TABLE I

Pdc-dc and △Pdc-dc RELATED TO DIFFERENT CASES
ac Grid Load
Ps_H Pp_H Assumption: VL<Vp_acpk, Vgx>VLx
Ps Pp=Pdg-Ps
Power Voltage
Case Pdc-dc △Pdc-dc
Relationship Relationship
Ps_L Pp_L
dc-dc I Pdg<PL VL<Vs_acpk Pdg-(Pp_L+Ps_L) Pp_L+Ps_L
DG Pdg
Converter II Pdg<PL VL≥Vs_acpk Pdg-(Pp_L+Ps_L) Pp_L+Ps_L
Source
III Pdg≥PL VL<Vs_acpk Pdg-(Pp_L-Ps_L) Pp_L-Ps_L
(a)
Pg Pg+Ps PL=Pg+Pdg IV Pdg≥PL VL≥Vs_acpk Pdg-(Pp_L-Ps_L) Pp_L-Ps_L

ac Grid Load
Pp_H simplify the analysis, the following assumptions are given in
Ps Pp=Pdg-Ps
this paper.
Ps_L (1) The dc voltage VL is relatively small, which is less than
Pp_L
dc-dc the peak value of ac line output voltage of the parallel converter
DG Pdg
Converter Vp_acpk.
Source
(2) For grid faults, only the condition of voltage sag is
(b) considered, and the condition of voltage swell can be studied in
Pg=Pdg-PL Pdg+Ps-PL PL a similar manner.
ac Grid Load The power flow diagrams of the proposed HCUPQC-DG are
Ps_H Pp_H
Ps Pp=Pdg+Ps
shown in Fig. 9, where Pg is the active power of the ac grid, Pdg
is the active power of DG, PL is the active power of load, Pp is
Ps_L Pp_L the active power flowing through the parallel converter, and Ps
Pdg
dc-dc is the active power flowing through the series converter; the
DG Converter
Source subscripts L and H represent the active power flowing through
the LV port and HV port, respectively. Besides, Vs_acpk
(c) represents the peak value of ac line voltage of the series
Pg=Pdg-PL Pdg+Ps-PL PL converter. With the assumptions above, the four following
ac Grid Load cases remain.
Pp_H
Ps Pp=Pdg+Ps Case I: When Pdg<PL, VL<Vs_acpk, the active power of DG is
delivered to the load through both the parallel and series
Ps_L Pp_L converters, and the ac grid provides the residual active power
DG Pdg
dc-dc required by the load, as shown in Fig. 9(a). Meanwhile, there
Converter
Source are two power flow paths for the parallel and series converters,
in which only part of the active power is fed to the load after
(d)
being processed by the dc-dc converter, while the other part of
Fig. 9. Power flow through the proposed HCUPQC-DG: (a) Case I,
Pdg<PL, VL<Vs_acpk; (b) Case II, Pdg<PL, VL≥Vs_acpk; (c) Case III, Pdg≥PL, the active power is transferred through the direct power flow
VL<Vs_acpk; (d) Case IV, Pdg≥PL, VL≥Vs_acpk. path.
Case II: When Pdg<PL, VL≥Vs_acpk, it is seen from Fig. 9(b)
the depth of the grid voltage sags/swells. The worst case for the that, for the series converter, all the active power can be directly
series converter corresponds to the minimum value of VL and transferred from DG to the ac side for voltage sag
maximum value of Vac, and the minimum value of Pdr for the compensation, without using the dc-dc converter, i.e., Ps_H=0.
series converter is obtained as Case III: When Pdg≥PL, VL<Vs_acpk, part of the active power
Ps _ dr min  Pdr (VL min ,Vs _ ac max ) , (5) from DG is delivered to the load, while the remainder is fed to
where Vs_acmax is the maximum RMS value of the ac line voltage the ac grid, as shown in Fig. 9(c). In this case, the active power
of the series converter. consumed by the series converter is transferred through the
parallel converter.
IV. POWER FLOW THROUGH THE PROPOSED Case IV: When Pdg≥PL, VL≥Vs_acpk, the active power Ps_H is
HCUPQC-DG equal to zero, and the other active power flow is similar to that
in Case III.
A. Power Flow Analysis
B. Reduced Active Power through the dc-dc Converter
Since more power flow paths exist in the proposed
HCUPQC-DG, the power flow through the proposed Based on the power flow analysis above, it can be
HCUPQC-DG is different from the traditional UPQC-DG. In summarized that the active power processed by the dc-dc
the proposed HCUPQC-DG, the active power flow is not only converter is related to different cases, as listed in Table I. In
determined by the active power relationship among DG, ac load, traditional UPQC-DG, due to the series connection, the active
and grid, but also related to the voltage relationship among the power processed by the dc-dc converter is always equal to the
dc voltage VL, the ac voltage of the parallel converter, vpx, and power supplied by DG, which satisfies
the ac voltage of the series converter, vsx. There are numerous Pdc  dc _ traditional  Pdg (6)
cases for the power flow of the proposed HCUPQC-DG. To As for the proposed HCUPQC-DG, the power processed by

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Oscilloscope Linear Load

vga (400V/div)
Power
Analyzer

i pa (20A/div)
dc-dc Parallel Series
dc Source Converter Converter Transformer

v pan (400V/div)
Nonlinear Load

Series Converter
ac Source v pab (1kV/div)
Fig. 10. Experimental prototype.
t (5ms/div)
TABLE II
TEST SETUP PARAMETERS Fig. 11. Reactive current compensation with active power injection.

System Parameters
VH (100V/div)
DG parameters Voltage: 200-308 V, Power: 0-6 kVA
vga (400V/div)
Rated voltage Vgx (RMS): 220 V,
Grid parameters Frequency: 50 Hz,
Voltage sags: 0.1-0.9 p.u.
Balanced: RLa=RLb=RLc=50 Ω iga (10A/div)
(220 V, 3 kW),
Linear load
Unbalanced: RLa=200 Ω,
RLb=RLc=50 Ω iLa (10A/div)
Load parameters
Three-phase half bridge rectifier
Non-linear
load feeding a L-R load of 10 t (10ms/div)
load
mH-100 Ω (PF: 0.976, THD: 24%)
Fig. 12. Steady-state waveform with harmonic current compensation.
Boost Converter
Parameters Values Parameters Values experimental prototype is shown in Fig. 10, and the test setup
dc voltage VH 400 V Capacitor C2 560 μF parameters are listed in Table II. The power devices used for
the boost converter is: S1: CMF20120D, D1: C2D20120D.
Inductor L1 2.5 mH Switching frequency f1 50 kHz
The high voltage VH is designed to be higher than the peak
Capacitor C1 350 μF value of ac line voltage. According to IEEE standard, the series
Parallel Converter converter is used to compensate voltage sags from 0.1 p.u. to
Parameters Values Parameters Values 0.9 p.u. [26]. Due to the Y-△ connection, the high voltage VH is
set as 400 V, and it is enough to realize this target. The low
Inductor Lpx 1.6 mH Switching frequency fp 20 kHz
voltage VL is determined by DG and should be lower than VH. In
Turn ratio of
transformers, Tpx
1.73:1 this paper, PV arrays are taken as examples for DG sources, and
the PV voltage at maximum power point is equal to 30.8 V per
Series Converter
panel [8]. With the series numbers of PV panels set as 10, the
Parameters Values Parameters Values maximum voltage of DG is 308 V. Besides, the minimum
Inductor Lsx 1.6 mH Capacitor Csx 4 μF voltage of DG is limited to 200 V. Hence, the voltage range of
Turn ratio of VL is 200-308 V.
1:1 Switching frequency fs 20 kHz
transformers, Tsx
B. Power Quality Control
the dc-dc converter is The waveform when the proposed HCUPQC-DG realizes
both reactive current compensation and active power injection
 Pdg  ( Pp _ L  Ps _ L ) Case I & II
Pdc  dc _ proposed   (7) is shown in Fig. 11. In the figure, vga is the grid voltage, ipa is the
 Pdg  ( Pp _ L  Ps _ L ) Case III & IV output current of the parallel converter, and vpan and vpab are the
Hence, the active power flowing through the dc-dc converter is midpoint voltage and midpoint line voltage of the parallel
reduced by converter, respectively. It can be seen that both reactive current
compensation and active power delivery are achieved, and the
 Pp _ L  Ps _ L Case I & II
Pdc  dc   (8) output current is controlled pretty well.
 Pp _ L  Ps _ L Case III & IV The steady-state waveform with harmonic current
It can be concluded that, since partial active power from DG compensation is given in Fig. 12, where iga and iLa are grid
can be delivered through the direct power flow path without current and load current, respectively. The harmonic spectra of
using the dc-dc converter, the power capacity of the dc-dc load and grid currents are shown in Fig. 13. It is seen that, the
converter can be reduced. THD value of load current is 26.3% while that of grid current is
4.87%. Therefore, the harmonic current produced by the
V. EXPERIMENTAL VERIFICATION nonlinear load can be compensated pretty well by the parallel
converter of the HCUPQC-DG.
A. Description of the Experimental Setup The steady-state performance parameters of the load side and
A 3-kVA laboratory prototype was constructed and tested to grid side, including total harmonic distortion (THD) and power
verify the effectiveness of the proposed HCUPQC-DG. The factor (PF), are measured by the power analyzer YOKOGAWA

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5 VL (200V/div)
unbalance compensation

iLa (A)
0 iga (10A/div)

5 igb (10A/div)
0 0.02 0.04 0.06 0.08 0.1
t (s)
Fundamental(50Hz)=5.299, THD=26.30% igc (10A/div)
25
H n H1 (%)

20
15 t (50ms/div)
10 Fig. 15. Experimental waveform under load unbalance.
5
0
0 1 2 3 4 5 Pdg  1kW
f (kHz) Pdg  2kW iin (10A/div)
(a) DG power variation VH (200V/div)
5
vga (400V/div)
iga (A)

0
iga (10A/div)
5
0 0.02 0.04 0.06 0.08 0.1
t (s) t (100ms/div)
Fundamental(50Hz)=5.124, THD=4.87%
Fig. 16. Experimental waveform under DG power variation.
2
H n H1 (%)

1.5
THDg is the THD value of load and grid currents, respectively.
1
It can be seen that, with the function of harmonic current
0.5
0
compensation, the PF in grid side can be corrected to 0.9949,
0 1 2 3 4 5 and the THD value of grid current is significantly improved.
f (kHz)
The experimental result under load unbalance is shown in
(b) Fig. 15, where igx (x=a, b, c) are grid currents. As seen, before
Fig. 13. The harmonic spectra of currents: (a) load current, (b) grid
current. the parallel converter operates, the grid currents are equal to the
load currents, which are unbalanced. After the parallel
converter is in action, the unbalanced load currents can be
(VLa ) (VLc ) compensated pretty well and the grid currents become balanced.
The experimental result under DG power variation is shown in
( I La ) ( I Lc )
Fig. 16, where iin is the output current of DG, VH is the dc-link
( PLa ) ( PLc ) voltage, vga is the grid voltage, and iga is the grid current. As
seen, the DG power changes from 1kW to 2kW, and hence the
(VLb ) ( PL ) grid currents increase accordingly. It is also seen from Figs. 15
and 16 that fast and smooth dynamic performance can be
( I Lb ) ( PFL ) achieved by the proposed system.
( PLb ) (THDL )
The waveform when the proposed HCUPQC-DG is used for
voltage sag compensation with active power injection is shown
(a)
in Fig. 17, where vga is the grid voltage, vLa is the load voltage,
(Vga ) (Vgc ) vsab is the ac line voltage of the series converter, and vsan is the
midpoint voltage of the series converter, respectively. As
( I ga ) ( I gc ) shown in Fig. 17(a), during shallow voltage sag, i.e., 0.5 p.u.,
which satisfies VL>Vs_acpk, the midpoint voltage of the series
( Pga ) ( Pgc )
converter changes between two levels. This indicates that all
(Vgb ) ( Pg )
the active power is transferred through the direct power flow
path, and the HV port as well as the dc-dc converter are not
( I gb ) ( PFg ) used for voltage-sag compensation. However, during deep
voltage sag, i.e., 0.9 p.u., which satisfies VL<Vs_acpk, the
( Pgb ) (THDg ) midpoint voltage of the series converter changes among three
(b) levels, as shown in Fig. 17(b). This indicates that the HV port is
Fig. 14. Steady-state performance parameters: (a) load side, (b) grid used, and partial active power must be processed by the dc-dc
side. converter in this case. The harmonic spectra of grid and load
WT1800, under the condition of load harmonic current voltages during 0.5 p.u. voltage sag are shown in Fig. 18. It is
compensation. The tested results are given in Fig. 14, where seen that, the magnitude of the load voltage can be
PFL and PFg is the power factor in load and grid side, THDL and compensated to the rated value, and the THD value of load

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vga (400V/ div) vga (400V/ div)

vLa (400V/ div)

vLa (400V/ div)

vsab (400V/ div)

vsab (400V/ div)
vsan (200V/ div)
isa (20A/ div)
t (10ms/div) t (1s/div)
(a) zoom-in zoom-in
vga (400V/ div)
vLa (400V/ div)

vsab (400V/ div)

vsan (200V/ div)

10ms/div 10ms/div
normal 0.5 p.u. sag 0.5 p.u. sag normal
(a)
t (10ms/div) vga (400V/ div)
(b)
Fig. 17. Voltage-sag compensation with active power injection: (a)
shallow voltage-sag (0.5 p.u.) compensation; (b) deep voltage-sag vLa (400V/ div)
(0.9 p.u.) compensation.

200 vsab (200V/ div)

vga (V)

0
isa (20A/ div)
200
t (1s/div)
0 0.02 0.04 0.06 0.08 0.1 zoom-in zoom-in
t (s)
Fundamental(50Hz)=152.8, THD=1.87%
1.5
H n H1 (%)

0.5
0
0 1 2 3 4 5 10ms/div 10ms/div
f (kHz) normal 1.2 p.u. swell 1.2 p.u. swell normal
(a) (b)
Fig. 19. Dynamic waveforms for voltage compensation: (a) voltage sag
200 compensation, (b) voltage swell compensation.
vLa (V)

0 the THD value of load voltage will be slightly higher after

200 compensation. However, the THD values are very close before
and after compensation, which indicates that the influence of
0 0.02 0.04 0.06 0.08 0.1
t (s) voltage compensation on THD performances is insignificantly.
Fundamental(50Hz)=310.3, THD=2.24% The dynamic waveforms when the system is undergoing
1.5 voltage sag (0.5 p.u. sag) and swell (1.2 p.u. swell) are given in
H n H1 (%)

Fig. 19. It can be seen that the voltage sag or swell can be
1
quickly compensated, which ensures the load voltage vLa free of
0.5 the fault. Besides, it is also seen that the system can return to the
0
normal state very fast when the fault is cleared. Therefore, the
0 1 2 3 4 5 fast and smooth transition between the fault and normal state
f (kHz)
can be achieved by the proposed system.
(b)
Fig. 18. The harmonic spectra of voltages: (a) grid voltage, (b) load C. Verification of Active Power Flow
voltage.
The experimental results of active power flow through the
voltage is 2.24% while that of grid voltage is 1.87%. Since only proposed HCUPQC-DG are shown in Fig. 20, where the four
the fundamental voltage of the grid is compensated by the cases correspond to that in Fig. 9. Taking the results shown in
series converter, while a small part of harmonics is introduced, Fig. 20(a) as an instance, the power and voltage relationship

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效率

Vga  0.8pu 98 98
98
Vga  0.1pu vga (400V/div) vga (400V/div)
96 96
96
94

Efficiency(%)
94

Efficiency(%)
94
iga (10A/div) iga (10A/div) 92
92
92
90 3LEVEL
90
90 TPTPC
v pan (400V/div) 88
v pan (400V/div) 88
88
86 Proposed HCUPQC-DG
Proposed HCUPQC-DG 86
86
84 Traditional UPQC-DG
Traditional UPQC-DG
vsan (400V/div) vsan (400V/div) 82 84
84
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 0 0.3
0.1 0.6
0.2 0.9
0.3 1.2
0.4 1.5
0.5 1.8
0.6 2.1
0.7 2.4
0.8 2.7
0.9 1
Pp (kW) Pp (kW)
t (5ms/div) t (5ms/div) (a) (b)
(a) (b) Fig. 22. Efficiency comparison with variable active power of the parallel
converter and constant active power of the series converter: the series
Vga  0.1pu Vga  0.8pu vga (400V/div)
vga (400V/div) converter compensates (a) 0.2 p.u.; and (b) 0.8 p.u. voltage sag.
效率 效率
iga (10A/div)
iga (10A/div) 98
98 98
98

96
96 96
96

v pan (400V/div)

Efficiency(%)

Efficiency(%)
v pan (400V/div) 94
94 94
94

92
92 92
92
3LEVEL 3LEVEL
vsan (400V/div) 90
90 90
90
TPTPC TPTPC
vsan (400V/div) 88
88 88
88
Proposed HCUPQC-DG Proposed HCUPQC-DG
86
86 86
86
Traditional UPQC-DG Traditional UPQC-DG
t (5ms/div) t (5ms/div) 84
84 84
84
0 0.1
0.1 0.2
0.2 0.3
0.3 0.4
0.4 0.5
0.5 0.6
0.6 0.7
0.7 0.8
0.8 0.9
0.9 1 0 0.1
0.1 0.2
0.2 0.3
0.3 0.4
0.4 0.5
0.5 0.6
0.6 0.7
0.7 0.8
0.8 0.9
0.9 1
(c) (d) voltage sag (pu) voltage sag (pu)
Fig. 20. Experimental results for active power flow through the (a) (b)
proposed HCUPQC-DG: (a) Case I, Pdg<PL, VL<Vs_acpk; (b) Case II, Fig. 23. Efficiency comparison with variable active power of series
Pdg<PL, VL≥Vs_acpk; (c) Case III, Pdg≥PL, VL<Vs_acpk; (d) Case IV, Pdg≥PL, converter and constant active power of parallel converter: parallel
VL≥Vs_acpk. converter outputs (a) 600 W; and (b) 2.4 kW active power.

S s _ Hx
S s _ Zx S s _ Hx
S s _ Zx 13.104W
25.356W 25.356W 16.5%
22.707W
23.1% 23.1% 1 1
28.6%
2 2
3 S s _ Lx1 & S s _ Lx 2 3
S s _ Lx1 & S s _ Lx 2
59.133W 43.674W
53.8% 54.9%

(a) (b)
Fig. 24. Loss breakdown of each power device: (a) three-level series
Fig. 21. Experimental result of the power through DG, load, grid and converter in the traditional solution, (b) multi-port series converter in
the direct power flow. the proposed solution.

satisfies Pdg<PL and VL<Vs_acpk. It is seen that the grid current iga D. Efficiency Comparison
is in phase with the grid voltage vga, which means that the active The efficiency of the proposed HCUPQC-DG is tested under
power of DG is not enough to provide the total active power different conditions and also compared with the traditional
required by the load, and the remainder is supplied by the ac indirectly connected UPQC-DG. The traditional indirectly
grid. Moreover, the midpoint voltage of the series converter connected UPQC-DG consists of the front-end dc-dc converter
changes among three levels, which indicates that partial active with the same topology as that in the proposed HCUPQC-DG,
power must be processed by the dc-dc converter for voltage-sag and the parallel and series converters with the T-type
compensation, i.e., Ps_H≠0. Similarly, it can be found that the three-level topology. The PCB, circuit parameters, and test
experimental results shown in Fig. 20 are all in accordance with conditions of the traditional UPQC-DG are the same as those of
the theoretical analysis in Section IV. the proposed HCUPQC-DG.
The experimental result of the power flow through DG, load, The comparison results when the parallel converter outputs
grid and the direct power flow is given in Fig. 21, which is variable active power and the series converter outputs constant
tested under different voltage sags. All the power is normalized active power are shown in Fig. 22. To compensate specific
by the load power. It is seen that, with the increase of grid voltage sag, e.g., 0.2 p.u. as shown in Fig. 22(a), the active
voltage sags, the grid power decreases while the DG power power consumed by the series converter is constant. The
used for voltage sag compensation increases. During shallow efficiency results are then tested with given different current
voltage sags, the direct power is equal to the DG power, which references for the parallel converter.
means that all the active power can be directly transferred. The comparison results when the series converter outputs
While during deep voltage sags, the direct power is lower than variable active power and the parallel converter outputs
the DG power, indicating that partial power of DG is directly constant active power are shown in Fig. 23, where the x-axis
transferred. represents the amount of sag in grid voltage Vgx. Given a

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TABLE III the HCUPQC-DG are discussed in detail. In addition, a

COMPARISON BETWEEN THE CONVENTIONAL UPQC-DG comprehensive analysis of the active power flow through the
AND PROPOSED HCUPQC-DG
proposed HCUPQC-DG is presented to understand the system
Conventional Proposed
Aspects operation. Both the analysis and experimental results indicate
UPQC-DG HCUPQC-DG
that the following advanced features are achieved by the
Low (almost 45%
Cost High reduction for the
proposed HCUPQC-DG.
dc-dc power rating) (1) The voltage of DG is not limited by the common dc bus
voltage of UPQC, and can be relatively low and vary in a wide
Hardware Almost the same
range.
Complexity
Software
Slightly
Slightly simple (2) The power capacity of the front-end dc-dc converter in
complex the proposed solution can be reduced since partial active power
Voltage
The same (200-308 V) from DG is transferred through the direct power flow path.
range of DG (3) Much higher overall efficiency is achieved by the
Performance
Overall
Low
High (1%-2% proposed HCUPQC-DG. With the specification of the
efficiency improvement) prototype, the efficiency improvement is almost 1%-2%.
constant current reference, the active power supplied by the
parallel converter is constant. The efficiency results are then REFERENCES
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transformerless dual-buck PV grid-connected inverters with high
As shown in Figs. 22 and 23, it is obvious that much higher efficiency,” Chin. J. Elect. Eng., vol. 4, no. 2, pp. 36–42, Jun. 2018.
efficiency is achieved by the proposed HCUPQC-DG. [2] H. Chen, H. Yi, B. Jiang, K. Zhang, and Z. Chen, “Data-driven detection
Compared with the traditional UPQC-DG, the efficiency of hot spots in photovoltaic energy systems,” IEEE Trans. Syst., Man,
improvement is almost 1%-2%. Cybern. Syst., vol. 49, no. 8, pp. 1731–1738, Aug. 2019.
[3] Y. W. Li, D. M. Vilathgamuwa and P. C. Loh, “A grid-interfacing power
The loss breakdown of each power device is shown in Fig. 24. quality compensator for three-phase three-wire microgrid applications,”
The series converter is taken as an example to illustrate the IEEE Trans. Power Electron., vol. 21, no. 4, pp. 1021-1031, Jul. 2006.
difference between the traditional and proposed solutions. As [4] F. Jiang, Y. Li, C. Tu, Q. Guo and H. Li, “A review of series voltage
source converter with fault current limiting function,” Chin. J. Elect. Eng.,
seen in Fig. 24(a), the power loss is symmetrically distributed vol. 4, no. 1, pp. 36–44, Mar. 2018.
on the high-side device Ss_Hx and low-side device Ss_Zx. [5] I. Axente, J. N. Ganesh,M. Basu, M. F. Conlon, and K. Gaughan, “A
However, this is not the case for the proposed solution. As seen 12-kVA DSP-controlled laboratory prototype UPQC capable of
in Fig. 24(b), the power loss on the low-side device Ss_Zx is mitigating unbalance in source voltage and load current,” IEEE Trans.
higher than that on the high-side device Ss_Hx. This is because Power Electron., vol. 25, no. 6, pp. 1471–1479, Jun. 2010.
[6] R. A. Modesto, S. A. O. da Silva, A. A. de Oliveira and V. D. Bacon, “A
most active power is directly transferred through the direct Versatile Unified Power Quality Conditioner Applied to Three-Phase
power flow path (i.e., low-side device Ss_Zx) for the proposed Four-Wire Distribution Systems Using a Dual Control Strategy,” IEEE
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[7] V. Khadkikar, “Enhancing electric power quality using UPQC: A
converter and overall efficiency improvement. comprehensive overview,” IEEE Trans. Power Electron., vol. 27, no. 5,
A point to point comparison between the conventional pp. 2284-2297, May 2012.
UPQC-DG and proposed HCUPQC-DG with respect to cost, [8] L. B. G. Campanhol, S. A. O. da Silva, A. A. de Oliveira and V. D. Bacon,
performance, and complexity, is given in Table III, where it is “Single-stage three-phase grid-tied PV system with universal filtering
capability applied to DG systems and AC microgrids,” IEEE Trans.
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overall efficiency and easy implementation. [9] S. Devassy and B. Singh, “Design and performance analysis of
three-phase solar PV integrated UPQC,” IEEE Trans. Ind. Appl., vol. 54,
E. Discussions for Practical Applications no. 1, pp. 73-81, Jan./Feb. 2018.
In a distributed system, the UPQC-DG has both functions of [10] S. Devassy and B. Singh, “Implementation of Solar Photovoltaic System
With Universal Active Filtering Capability,” IEEE Trans. Ind. Appl., vol.
power quality improvement and active power delivery from 55, no. 4, pp. 3926-3934, Jul./Aug. 2019.
DG to the grid or load. A comprehensive overview for UPQC is [11] J. Wang, H. Wu, K. Sun and L. Zhang, “A High Efficiency
presented in [7], and it states that, among all the configurations Quasi-Single-Stage Unified Power Quality Conditioner Integrating
Distributed Generation,” in Proc. Int. Symp. Power Electron. Distrib.
of UPQC, UPQC-DG could be the most interesting topology Gener. Syst., Xi'an, China, 2019, pp. 1099-1104.
for a renewable-energy-based power system. Also, numerous [12] B. Han, B. Bae, H. Kim, and S. Baek, “Combined operation of unified
valuable researches for this interesting topic have been power-quality conditioner with distributed generation,” IEEE Trans.
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[13] S. K. Khadem, M. Basu and M. F. Conlon, “Intelligent Islanding and
researches, a hybrid connected UPQC-DG (HCUPQC-DG) is Seamless Reconnection Technique for Microgrid With UPQC,” IEEE J.
proposed in this paper, featuring much lower power capacity of Emerg. Sel. Topics Power Electron., vol. 3, no. 2, pp. 483-492, Jun. 2015.
the dc-dc converter and higher overall conversion efficiency. [14] F. Wang, J. L. Duarte and M. A. M. Hendrix, “Grid-Interfacing Converter
Systems With Enhanced Voltage Quality for Microgrid
Therefore, the proposed HCUPQC-DG is a promising power Application—Concept and Implementation,” IEEE Trans. Power
device used for a distributed system. Electron., vol. 26, no. 12, pp. 3501-3513, Dec. 2011.
[15] D. Somayajula and M. L. Crow, “An ultracapacitor integrated power
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2020.3040687, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

[17] M. H. de Freitas Takami, S. A. Oliveira da Silva and L. P. Sampaio, Electronics, and Journal of Power Electronics. Dr. Sun served as the TPC Vice
“Dynamic performance comparison involving grid-connected PV Chair of IEEE ECCE2017 and IEEE ECCE-Asia2017, the Organization
systems operating with active power-line conditioning and subjected to Committee Chair of IEEE eGrid2019, and the Publicity Chair of IEEE
sudden solar irradiation changes,” IET Renew. Power Gener., vol. 13, no. ECCE2020. He also served as the General Co-Chair of 2018 International
4, pp. 587-597, 18 3 2019. Future Energy Challenge (IFEC2018). He was a recipient of Delta Young
[18] L. B. G. Campanhol, S. A. O. da Silva, A. A. de Oliveira and V. D. Bacon, Scholar Award in 2013, and Youth Award of China Power Supply Society
“Power Flow and Stability Analyses of a Multifunctional Distributed (CPSS) in 2017, and IEEE Transactions on Power Electronics' Outstanding
Generation System Integrating a Photovoltaic System With Unified Reviewers Award in 2019.
Power Quality Conditioner,” IEEE Trans. Power Electron., vol. 34, no. 7,
pp. 6241-6256, Jul. 2019.
[19] K. Wang, Z. Zheng, L. Xu and Y. Li, “A Generalized Carrier-Overlapped
PWM Method for Neutral-Point-Clamped Multilevel Converters,” IEEE
Trans. Power Electron., vol. 35, no. 9, pp. 9095-9106, Sept. 2020. Hongfei Wu (S’11-M’13-SM’18) received the
[20] M. S. Agamy et al., “An Efficient Partial Power Processing DC/DC B.S. and Ph. D degrees in electrical engineering
Converter for Distributed PV Architectures,” IEEE Trans. Power and power electronics and power drives from
Electron., vol. 29, no. 2, pp. 674-686, Feb. 2014. Nanjing University of Aeronautics and
[21] J. R. R. Zientarski, M. L. d. S. Martins, J. R. Pinheiro and H. L. Hey, Astronautics (NUAA), Nanjing, China, in 2008
“Series-Connected Partial-Power Converters Applied to PV Systems: A and 2013, respectively.
Design Approach Based on Step-Up/Down Voltage Regulation Range,” Since 2013, he has been with the Faculty of
IEEE Trans. Power Electron., vol. 33, no. 9, pp. 7622-7633, Sept. 2018. Electrical Engineering, NUAA, and is currently a
[22] L. Dorn-Gomba, P. Magne, B. Danen and A. Emadi, “On the Concept of Professor with College of Automation
the Multi-Source Inverter for Hybrid Electric Vehicle Powertrains,” IEEE Engineering, NUAA. He has authored and
Trans. Power Electron., vol. 33, no. 9, pp. 7376-7386, Sept. 2018. co-authored more than 200 peer-reviewed papers
[23] J. Wang, H. Wu, T. Yang, L. Zhang and Y. Xing, “Bidirectional published in journals and conference proceedings.
Three-Phase DC–AC Converter With Embedded DC–DC Converter and He is the holder of more than 40 Patents. His
Carrier-Based PWM Strategy for Wide Voltage Range Applications,” research interests are high performance power converters, wide-band-gap
IEEE Trans. Ind. Electron., vol. 66, no. 6, pp. 4144-4155, Jun. 2019. devices applications and magnetic integration.
[24] J. Wang, K. Sun, H. Wu, L. Zhang, J. Zhu and Y. Xing, Dr. Wu was the recipient of the Best Associate Editor of Journal of Power
“Quasi-Two-Stage Multifunctional Photovoltaic Inverter With Power Electronics (2018), the Outstanding Reviewer of IEEE Transactions on Power
Quality Control and Enhanced Conversion Efficiency,” IEEE Trans. Electronics (2013), the Changkong Scholar Award and Young Scholar
Power Electron., vol. 35, no. 7, pp. 7073-7085, Jul. 2020. Innovation Award of NUAA (2017). He serves as an Associate Editor of
[25] A. H. Bhat and N. Langer, “Capacitor Voltage Balancing of Three-Phase Journal of Power Electronics, CPSS Transactions on Power Electronics and
Neutral-Point-Clamped Rectifier Using Modified Reference Vector,” Applications and Chinese Journal of Electrical Engineering.
IEEE Trans. Power Electron., vol. 29, no. 2, pp. 561-568, Feb. 2014.
[26] Y. Lu, G. Xiao, B. Lei, X. Wu and S. Zhu, “A Transformerless Active
Voltage Quality Regulator With the Parasitic Boost Circuit,” IEEE Trans.
Power Electron., vol. 29, no. 4, pp. 1746-1756, Apr. 2014.
Jianxin Zhu (S’16) received the B.S. and Ph.D
degree in electrical engineering and power
electronics and power drives from Nanjing
University of Aeronautics and Astronautics
Jiangfeng Wang (S’15-M’19) received the B.S. (NUAA), Nanjing, China, in 2014 and 2020,
and Ph. D degrees in electrical engineering and respectively. Since 2020, he has been with the
power electronics and power drives from Nanjing Faculty of Electrical Engineering, Nanjing
University of Aeronautics and Astronautics University of Posts and Communications
(NUAA), Nanjing, China, in 2012 and 2018, (NJUPT), and is currently a Lecturer with
respectively. Since Mar 2019, he has been a College of Automation Engineering, NJUPT.
Post-Doctoral Research Fellow with the His research interests include the power
Department of Electrical Engineering, Tsinghua quality, modulation and control of power
University, Beijing, China. Since Dec 2019, he converters, and hardware-in-the-loop simulation
has been a Visiting Scholar at Department of system.
Electrical and Computer Engineering, University
of Alberta, Edmonton, Canada.
His research interests include high performance
converters for hybrid AC/DC microgrids, power quality and distributed power
generation system. Yan Xing (M’03) received the B.S. and M.S.
degrees in automation and electrical engineering
from Tsinghua University, Beijing, China, in
1985 and 1988, respectively, and the Ph.D.
degree in electrical engineering from Nanjing
Kai Sun (M’12-SM’16) received the B.E., M.E., University of Aeronautics and Astronautics
and Ph.D. degrees in electrical engineering from (NUAA), Nanjing, China, in 2000.
Tsinghua University, in 2000, 2002, and 2006, Since 1988, she has been with the Faculty of
respectively. He joined the faculty of Electrical Electrical Engineering, NUAA, and is currently a
Engineering, Tsinghua University, in 2006, where Professor with the College of Automation
he is currently an Associate Professor. From Sep Engineering, NUAA. She has authored more than
2009 to Aug 2010, he was a Visiting Scholar at 200 technical papers published in journals and
Department of Energy Technology, Aalborg conference proceedings and has also published
University, Aalborg, Denmark. From Jan to Aug three books. Her research interests include topology and control for dc–dc and
2017, he was a Visiting Professor at Department dc–ac converters.
of Electrical and Computer Engineering, Dr. Xing is an Associate Editor of the IEEE Transactions on Power
University of Alberta, Edmonton, Canada. His Electronics. She is a member of the Committee on Renewable Energy Systems
current research interests include power of the IEEE Industrial Electronics Society.
electronics for renewable generation systems, microgrids, and energy internet.
Dr. Sun serves as an Associate Editor for IEEE Transactions on Power
Electronics, IEEE Journal of Emerging and Selected Topics in Power

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2020.3040687, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Yunwei Li (S'04-M'05-SM'11-F'20) received

the B.Sc. in Engineering degree in electrical
engineering from Tianjin University, Tianjin,
China, in 2002, and the Ph.D. degree from
Nanyang Technological University, Singapore, in
2006.
In 2005, Dr. Li was a Visiting Scholar with
Aalborg University, Denmark. From 2006 to
2007, he was a Postdoctoral Research Fellow at
Ryerson University, Canada. In 2007, he also
worked at Rockwell Automation Canada before
he joined University of Alberta, Canada in the
same year. Since then, Dr. Li has been with
University of Alberta, where he is a Professor now. His research interests
include distributed generation, microgrid, renewable energy, high power
converters and electric motor drives.
Dr. Li serves as Editor-in-Chief for IEEE Transactions on Power Electronics
Letters. Prior to that, he was Associate Editor for IEEE Transactions on Power
Electronics, IEEE Transactions on Industrial Electronics, IEEE Transactions on
Smart Grid, and IEEE Journal of Emerging and Selected Topics in Power
Electronics. Dr. Li received the Richard M. Bass Outstanding Young Power
Electronics Engineer Award from IEEE Power Electronics Society in 2013 and
the second prize paper award of IEEE Transactions on Power Electronics in
2014. He is listed as a Highly Cited Researcher by the Web of Science Group.

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Authorized licensed use limited to: University of Prince Edward Island. Downloaded on June 08,2021 at 07:54:17 UTC from IEEE Xplore. Restrictions apply.