A Hybrid Switched-Capacitor/Inductor Converter for Small

Conversion Ratios

by

Norah Elena Nakibuuka

B.S., Massachusetts Institute of Technology (2013)

Submitted to the Department of Electrical Engineering and Computer Science

in Partial Fulfillment of the Requirements for the Degree of

Master of Engineering in Electrical Engineering and Computer Science

at the A;1x

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

May 2013 1
©Massachusetts Insurute of Technology. All rights reserved.

Author
Department of Electrical Engineering and Computer Science
May 241 2013

Certified by
David J. Perreault
Associate Professor, Department of Electrical Engineering and Computer Science
Thesis Supervisor May 24 th, 2013

Certified by e
Shea Petricek
Intersil Corporation
Thesis Co-Supervisor May 241, 2013

Accepted by
Prof. Dennis Freeman
Chairman, Masters of Engineering Thesis Committee
 A Hybrid Switched-Capacitor/Inductor Converter for Small Conversion Ratios

by

Norah Elena Nakibuuka

Submitted to the Department of Electrical Engineering and Computer Science

on May 24th, 2013 in Partial Fulfillment of the
Requirements for the Degree of

Master of Engineering in Electrical Engineering and Computer Science

Abstract

A hybrid three-switch DC-DC step-up power converter for on chip applications is

proposed. It is shown that the hybrid-three switch step-up converter can offer
advantages such as reduced size of magnetic components, reduced MOSFET voltage
stresses, improved closed loop control and can offer high efficiency compared to a
standard boost converter of the same IC package size. These improvements are made
possible by adding a flying capacitor that reduces the voltage stresses on the switches
and decreases the inductor size by reducing the volt-second across the inductor. The
converter is implemented as an integrated circuit built in a 0.25pm 5V CMOS process.
Experimental verification shows the gains.

Thesis Supervisor: David J. Perreault

Title: Associate Professor, Department of Electrical Engineering and Computer Science
iv
Acknowledgements

I would like to thank Professor David Perrault for agreeing to be the on campus
supervisor for this thesis, as well as for his guidance on this project. Most important, my
interest in power electronics sparked after taking 6.334. Professor Perrault's teaching
style made me enthusiastic about the subject content.

I would like to express my gratitude to the MIT VI-A program coordinators for giving
me the opportunity to participate in the program. Kathy Sullivan and Professor Mark
Zahn were very helpful in ensuring that the program run smoothly.

I would like to thank Shea Petricek, my VI-A Intersil supervisor, for his support and
guidance throughout my assignment at Intersil. I learned so much about power from
him. I would also like to thank Shea for giving me career advice, and for making me feel
welcome in Dallas.

Lastly, I would like to thank my family. My parents, Regina and Jonathan Kityo, who
have made so many sacrifices so that their children are who they are today. My mother,
whom I love dearly and is a true inspiration for her children. My father, for always
believing in me and encouraging me to reach my full potential. My siblings David,
Patrick, Diana, Grace and Ivan, who I can always count on for support.

v
vi
Contents
Abstract ......................................................................................................................................... iv

List of Tables.................................................................................................................................ix

List of Figures............................................................................................................................ xiii

1. Introduction ............................................................................................................................. 15

1.1 Research Background................................................................................................ 16

1.1.1 Current switched capacitor/inductor DC-DC converters............................... 16

1.1.2 Proposed class of circuits ..................................................................................... 17

1.2 Thesis Objectives, Contributions and Organization..............................................18

2. Proposed Hybrid 3-switch Step-Up Power Converter .................................................. 21

2.1 Power Stage A rchitecture........................................................................................ 21

2.2 Operating Principles ................................................................................................. 22

2.3 Comparison with a conventional boost converter................................................ 26

2.3.1 Inductance Benefit................................................................................................ 26

2.3.2 Voltage Stresses on Devices................................................................................. 27

2.3.3 A verage Inductor Current Benefit .................................................................... 28

2.4 Sim ulated Converter Perform ance.......................................................................... 29

2.4.1 Converter W aveform s........................................................................................... 30

3. Power Loss M odeling......................................................................................................... 27

3.1 O utput Inductor......................................................................................................... 31

3.2 Flying capacitor ......................................................................................................... 32

vii
 3.3 Sw itches ........................................................................................................................... 34

3.3.1 Switch Q1.....................................................................................................................34

3.3.2 Switch Q2.....................................................................................................................35

3.3.3 Switch Q3.....................................................................................................................37

3.4 M odeled pow er loss results ...................................................................................... 38

3.4.1 A ccuracy of m odeled results ............................................................................... 41

4. Device Selection and Sizing of Power Stage Components........................................... 41

4.1 Device Selection and Sizing ...................................................................................... 41

4.1.1 Switch on-resistance.............................................................................................. 41

4.1.2 Size of the flying capacitor .................................... 42

5. Design and Layout ...... ....................................................................................... 45

5.1 Pow er Stage..................................................................................................................45

5.1.1 Test Chip Layout............................................................ ........................................... 45

5.1.2 Power Stage Board Layout.............................................................................. ... 46

5.1.3 Pow er Stage Com ponents ................................................................................... 48

5.2 Control Circuitry ............................................................................................ 49

6. Experim ental Results ............................................................................................................ 51

6.1 M easurem ent Setup.............................................................................................. ... 51

6.2 C easerementvefop ................................................................................................. .52

6.2.1 Steady State W aveform s........................................................................................... 52

6.2.2 Startup w aveform ................................................................................................ 54

6.3 Closed Loop Efficiency ............................................................................................. 55

Viii
 6.4 Transient Perform ance............................................................................................. 58

6.4.1 Load Step and Step Down.................................................................................... 58

7. Summary and Conclusions................................................................................................ 61

7.1 Thesis Sum mary and Contributions........................................................................ 61

7.2 Future W ork .................................................................................................................... 62

Appendix A: Efficiency Comparison with a Conventional Boost Converter.................63

Appendix B: Inductor Conduction Loss Comparison.......................................................65

Bibliography ................................................................................................................................ 67

ix
X
List of Tables
Table 2.1: Comparison of the inductor size required in a conventional boost converter
versus the proposed cicruit ................................................................................................. 27

Table 3.1: Component loss disctributions predicted by the loss model..........................39

Table 4.1: Designed values for switch on resistance and area........................................42

Table 5.1: A description of the pin functions of the test chip...........................................46

Table 5.2: Component values for the power stage ........................................................... 48

Table 6.1: Key component values for efficiency and power loss measurements..........55

xi
xii
List of Figures

Figure 1.1: Three switch plus inductor unit of the proposed class of circuits .................... 17

Figure 2.1: Schematic of the 3-switch hybrid step-up power converter......................... 22

Figure 2.2: Timing Diagram for D<0.5 ..................................................................................... 23

Figure 2.3: Charging phase of the flying capacitior .......................................................... 24

Figure 2.4: Disharging phase of the flying capacitor ......................................................... 24

Figure 2.5: Inductance comparison and inductance benefit ............................................. 29

Figure 2.6: Inductor Average Current Benefit .................................................................. 28

Figure 2.7: Converter Waveforms ....................................................................................... 30

Figure 3.1: Inductor current in steady state........................................................................ 32

Figure 3.2: The current through the flying capcitor in steady state ................................ 33

Figure 3.3: The current through switch Q1 in steady state ............................................... 35

Figure 3.4: The current through switch Q2 in steady state ............................................... 36

Figure 3.5: The current through siwth Q3in steady state ................................. 37

Figure 3.6: Predicted power loss distribution by component .......................................... 39

Figure 3.7: Modeled versus mesured efficiency ................................................................ 40

Figure 4.1: A schematic showing the charging phase of the flying capacitor ............... 43

Figure 5.1: Test chip layout.................................................................................................. 45

Figure 5.2: Photograph of top and bottom sides of the converter evaluation board ........ 47

Figure 5.3: Photograph of the converter with power stage components labeled .......... 48

xiii
Figure 5.4: Photograph of the evaluation board with control circuits boxed out .......... 49

Figure 5.5: Schematic of control circuitry ............................................................................ 50

Figure 6.1: Measurement setup used to obtain efficiency measurements ...................... 52

Figure 6.2: Steady state waveforms......................................................................................53

Figure 6.3: Startup waveforms showing the output and flying capacitor voltage ..... 54

Figure 6.4: Efficiency measurements at Vout= 5V.............................................................. 56

Figure 6.5: Efficiency measurements at Vout= 3.3V............................................................ 56

Figure 6.6: Power loss measurements at Vout = 5V...............................................................57

Figure 6.7: Power loss measurements at Vout = 3V ........................................................... 57

Figure 6.8: Effect of number of flying capacitors used on power loss............................ 58

Figure 6.9: Load step up waveform.................................................................................... 59

Figure 6.10: Load step down waveform............................................................................ 59

Figure A.1: Power loss comparison of the conventional boost converter and the 3 switch
hybrid step-up power converter ............................................................................................... 64

Figure B.1: Comparison of inductor conduction loss of the proposed converter and the
conventional boost converter ............................................................................................... 65

xiv
1. Introduction
Conventional boost converters have been used almost exclusively to provide DC-

DC conversion for integrated switching regulators. However, existing boost converters

have some constraints including 1: Large inductor size, 2. High voltage stresses on

MOSFETs, and 3. Right-half-plane zero that easily causes instability. Further, the

efficiency of the conventional boost converter can be improved. Large inductor size is a

barrier to integration, especially for SOC (System on a Chip) applications. Increasing the

switching frequency reduces the inductor size, but results in higher switching losses that

reduce overall converter efficiency.

For applications that require small conversion ratios such that the output voltage

need not be greater than twice the input voltage, the converter proposed in this thesis

can: 1. Reduce the required inductor size, 2. Reduce the voltage stresses on the switches,

3. Reduce the average inductor current, 4. Provide improved dosed loop control, 5.

Maintain or offer improved efficiency over that of the traditional boost converter by

reducing inductor losses. This topology may be used to generate a 5V rail from low

voltages such as a single lithium-ion cell.

15
1.1 Research Background
1.1.1 Current switched capacitor/inductor DC-DC converters
As applications that require power converters move more and more towards

miniaturization, it becomes important to integrate the power stage components of the

converter. Various methods are currently adopted to realize dc-dc conversion for such

integrated solutions. These include topologies that utilize magnetic components, and

are discussed in [1]-[9]. Other power converters such as switched capacitor circuits

require no magnetics and are discussed in [11]-[17].

Switched capacitor circuits contain primarily semiconductor switches and

capacitors. They are used to convert or invert dc voltages. The capacitors in the switched

capacitor stages are charged when they are connected across the input. The switched

capacitor circuits are attractive as they require no magnetic components and therefore

are small and can be used for integration ([12], [14], [21]). Moreover, high efficiency can

be realized. However, when using switched capacitor circuits, it is difficult to realize

output regulation with a wide range of input variations, as discussed in [20]. Moreover,

good output regulation is achieved at the expense of high efficiency.

Due to the limitations of the switched capacitor circuits, these circuits are often

integrated with a regulation stage to allow for output voltage regulation. An example of

a two stage architecture that utilizes a switched capacitor stage and a buck converter

stage for regulation is discussed in [1]. Another circuit integrates a switched capacitor

16
circuit within a boost converter and is discussed in [18]. Similarly, a two stage

architecture that uses a switched capacitor voltage divider as the first stage and a

regulation stage is discussed in [2].

1.1.2 Proposed class of circuits

While the converters discussed in the section above have various merits, we

would like to investigate circuits that improve on performance of the conventional

converters. To have commercial value, we must produce a circuit having some

improved combination of size, cost and efficiency. The class of circuits proposed consists

of a three switch plus inductor unit and is shown in Figure 1.1.

Figure 1.1: Three switch plus inductor unit of the proposed class of circuits.

A flying capacitor is added to act as a floating voltage source. The unit has six different

variants: the step up, step down and inverting configurations. Each configuration has a

17
constraint on the output. This work focuses on one of the step up configurations whose

operation is detailed in the next chapter.

1.2 Thesis Objectives, Contributionsand Organization

The goal of this thesis is to analyze and design a hybrid switched

capacitor/inductor step-up power converter in order to understand the value and

limitation of this class of circuits. An experimental prototype is built with the following

specifications:

* Input voltage: 2.54.2V

* Output voltage: 3.3-5V

" Switching frequency: 1MHz

" Output current: 3A

Chapter 2 introduces the hybrid 3-switch step-up power converter that is

analyzed in this thesis. The operating principles of the circuit are discussed, and its

merits over the conventional boost converter are illustrated by showing the circuit's

inductance benefit, reduced voltage stresses and average inductor benefit. This chapter

also illustrates the simulated converter performance.

Chapter 3 discusses the power loss mechanisms of the proposed power

converter. A detailed model of the loss contribution of each of the converter components

18
is presented. Lastly, the efficiency results obtained from the power loss model are

compared with those from experimental verification to determine the model's accuracy.

Chapter 4 details the methods used to select and size the power stage

components. The flying capacitor and the switch on resistance are of special interest.

Chapter 5 discusses the design and layout of the power stage components,

control circuit and the PCB board used for experimental verification.

Chapter 6 provides experimental verification of the IC implementation of the

proposed converter. Important characteristics such as power loss, efficiency, response to

load steps, startup and shutdown waveforms are evaluated at different conditions. The

gains provided by the IC implementation are shown.

Finally, Chapter 7 summarizes the contribution of the thesis, and also suggests

areas for future work.

19
20
2. Proposed Hybrid 3-switch Step-Up Power Converter
The previous chapter discussed the limitations of existing hybrid switched

capacitor/inductor power converters. Chapter 2 discusses the proposed architecture of

the hybrid step up power converter. To have commercial value, the circuit must have

some improved combination of size, cost and efficiency. In addition, the circuit must not

be so complex that it becomes impractical for widespread use. Section 2.1 discusses the

proposed architecture, followed by the operating principles in Sections 2.2. The

proposed circuit is compared with the conventional boost converter in Section 2.3 and

the simulated performance of the proposed converter is discussed in Section 2.4.

2.1 Power Stage Architecture

The power stage is shown in Figure 2.1 and it consists of three switches Q1, Q2

and Q3. An external flying capacitor Cy is added that acts as a floating voltage source

and is balanced so that it holds the input voltage. Finally, a low pass filter consisting of

an inductor and output capacitor is connected to the high frequency phase node. A key

feature to note is that the architecture looks like that of the conventional buck converter,

with a third switch and flying capacitor added to provide a boosting benefit. This

architecture offers the simplicity to be used in a commercial application.

21
 Q1 3
o

LOUT VOUr

2'
CFLY
VIN
VPHASE COUT

Q2 j

Figure 2.1: Schematic of the 3-switch hybrid step-up power converter, consisting of
three switches Q1, Q2 and Q3, a flying capacitor Cny, and an output filter consisting of
an inductor Lot and output capacitor Cout.

The size of the flying capacitor must be chosen so that it is large enough to hold the

input voltage but at the same time should not increase the size of the desired

application. Chapter 4 discusses the sizing of the flying capacitor in more detail.

2.2 Operating Principles

The operation of the proposed circuit is as follows:

DT-T: Switches Q2and Q3are turned on while Qi remains off. The flying capacitor is

charged and the input voltage appears across it. The voltage across the inductor is
22
reversed and the inductor current ramps down. Figure 2.3 shows the charging phase of

the flying capacitor.

0-DT: Switch Q1 is turned on while Q2and Q3 are off. The flying capacitor is discharged.

A positive voltage appears across the inductor and the inductor current ramps up.

Figure 2.4 shows the discharging phase of the flying capacitor, and Figure 2.2 below

illustrates the timing diagram when the duty ratio is less than 0.5.

Qi

hril:2Vr
VIN

1L 10

u I

Figure 2.2: Timing diagram for D<0.5.

23
 Q3_Rdson

LOUT1 VOUT

* I--
COU
CFLY1
VIN1 "GO
VPHASE
Q2_Rdson

Figure 2.3: Charging phase of the flying capacitor.

Q1_Rdson

LOUT VOUT

CFLY
VIN
VPHASE
OU1

I
Figure 2.4: Discharging phase of the flying capacitor.

24
During one complete cycle, the phase node moves between Vi, and 2V,,. From inductor

volt-second balance, it follows that:

(2Vin-Vout)D+ (1-D) (Vin-Vout) =0 (2.1)

Vout (2.2)
Vin

where Vi. is the input voltage, Vout is the output voltage, and DT is the on-time of switch

Qi. The inductor current ramps up during time 0-DT, which results in an inductor ripple

current given by

A1k-pk -(2Vn-Vout)D (2.3)

wherefiwis the switching frequency and L is the value of the output inductor. Using

state equations, the small signal gain of the converter is derived and has a transfer

function given by

Vout -1 (2.4)
Vi" s2LC+ +1

where C is the output capacitor and R is the load. This converter has two left half-plane

poles, and no zeros. Given the operating principle explained above, it can be seen that

since the phase node moves between the input voltage and twice the input voltage, the

output voltage can only rise to twice the input voltage. Hence, the proposed circuit can

only be used in applications that require boost conversion ratios of up to two.

25
2.3 Comparison with a conventional boost converter
Compared with the conventional boost converter, the proposed circuit offers

advantages such as reduced inductor size, lower voltage stresses on the switches, and

reduced average inductor current. Each of these gains is explained in detail in the

following subsections.

2.3.1 Inductance Benefit

The hybrid three switch step up converter is attractive for small boost conversion

ratios as it eliminates the use of bulky magnetic components. The sizes of the inductors

required in the hybrid three switch and conventional boost converter are as follows:

(2Vn-V Vout -1) (2.5)

L3switch'- u) 7
L =
AIpk-pk sw

(2.6)
Vout-Vin
Ltraditionalboost 1 Vp v0out
ALk-pkfSW

When the switching frequency and ripple current are kept constant, a comparison of the

inductor size needed in the hybrid versus the conventional boost converter is illustrated

in Figure 2.5. As shown in the figure, the hybrid always utilizes a smaller inductor for

conversion ratios greater than 1.2.

26
 Inductance Comparison Inductance Benefit
-Hybrid 3 Swt3ch - Traditiorwl boost 16

Isresa h 1h,
0-7

- IIndco siz 1 H 640H

2.3 Votg=4,_s_1_zIu
tesso =3A.
eie

(a). ndutance Comrsson (b)Inucanecensi

vessthe hrid switch ithybre switchinrqec nderiperny cundt ke cstdt.

volage nthne CmSETare as) follows:Benfi

atansa fty npet rae.dutiong in hs e h inductor siewhncopret thep convethona

Thetaresut n the tableT' were obaindfoms: n aS tiSMLSsiuain

27
 Vdsq1=O (2.7)

VdsQ2=Vm (2.8)

VdsQ3=(Vm+VCfly-Vm)=Vn (2.9)

where VdsQ1, Vds2, and VdsQ are the drain to source voltages across Qi, Q2 and Q3

respectively. As the inductor current ramps down and the flying capacitor is charged,

the voltages seen across the devices are:

VdsQi=Vm (2.10)

Vds2=0 (2.11)

Vds=0 (2.12)

where Vcfy is the voltage across the flying capacitor and is balanced to equal the input

voltage.

Hence, all the switches need only be sized to handle the input voltage as

compared to the conventional boost converter where the switches must handle the full

output voltage.

2.3.3 Average Inductor Current Benefit

In the hybrid three switch converter, the inductor carries the load current,

whereas the inductor in the conventional boost carries a multiple of the load current, as

seen in the equations 2.13 and 2.14.

28
 ILswitch=I0 (2.13)

Ltraditional-boost Vout
in
0(2.14)

where Iis the load current. This allows for the inductor in the hybrid converter to be

sized for lower peak currents. Figure 2.1 below illustrates the average inductor current

benefit of the proposed circuit versus the conventional boost converter.

Inductor Average Current

2

1.9 - -
2.7

1.4

1.
-. 1.2

1.1

1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2

Vout/Vin

Figure 2.1: The conventional boost converter carries more average current than the
hybrid 3-switch by a factor of the conversion ratio.

2.4 Simulated Converter Performance

The SIMetrix/SIMPLIS simulator was used to optimize the performance of the

proposed circuit before an experimental prototype was built. A piecewise linear model

for the flying capacitor used in the simulator was obtained by taking laboratory

measurements of the capacitance at various voltages and then calculating the stored

charge. The on-resistance of the switches used in the simulator was chosen to minimize

conduction losses, as will be discussed in Chapter 3.

29
2.4.1 Converter Waveforms
Figure 2.6 below shows the switch, inductor and flying capacitor current waveforms

when the load current is 3A. Switch Qi carries the inductor current during its on time,

whereas the load current is split between switches Q2 and Q3 during their on time. The

flying capacitor carries high frequency currents, and hence its EsR should be low to

reduce conduction losses.

I] ~II~ fII~I I~I~

4
3
2
1*
-0

iii i Ii Ile U ~
11 4 I

C57 41

= I-

2,L2J2233
Time [gs]

Figure 2.6: Converter waveforms obtained from a SIMetrix/SIMPLIS simulator when

the load current is 3A. The flying capacitor carries high frequency current.

30
3. Power Loss Modeling
For circuit evaluation, much emphasis was placed on fully understanding the

actual power conversion losses and limitations. The converter performance is highly

dependent on the loss mechanism of each of the components used. When operating the

converter in the 1OW power range, Ims 2R losses are high and must be minimized. A

power loss model was built in excel to calculate the losses due to the output inductor

(Section 3.1), flying capacitor (Section 3.2), and switches (Section 3.3). Section 3.4

illustrates the accuracy of the modeled results.

3.1 Output Inductor

The main loss mechanism for the inductor was the conduction loss. Figure 3.1

below shows the inductor current waveform in steady state. The Imsvalues of the

currents were calculated by taking the integral of the square of current over one

switching cycle and then simplifying the resulting equations using Mathcad.

31
 Ia

ta T t
Figure 3.1: Inductor current in steady state.

The ripple current I was calculated as follows:

t- )x (3.1)
ir = (2ViVout) -V
k L )(Vin fsw

The In-, current in the inductor is calculated as follows:

(3.2)
Irms (Ia2+2)

The conduction loss in the inductor is calculated as follows:

Pconduction=rms 2 xLDCR (3-3)

3.2 Flying capacitor

Figure 3.2 shows the waveform for the current through the flying capacitor.

32
 ICfIy
AL

. t.......
..
I jIla Iba

lb t
ta T
Figure 3.2: The current through the flying capacitor Cfly in steady state.

The Im current through the flying capacitor is estimated as follows:

(3.4)
Irms=(Ib2(1-k)+k(Ia2 - IaIr+ ))

Using capacitor charge balance, the current Ibis obtained as:

-k(Ia-L;) (3.5)
Ib 1-k

where

t
k=h (3.6)
T

The conduction loss was then calculated by:

Ponnduction=Irms2 XCflyESR (3.7)

Similarly, the output capacitor conduction loss is given by:

Pconduction=rms 2 xCOUT_ESR (3.8)

33
3.3 Switches
The main loss mechanism for the switches Q1, Q2, and Q3 were the conduction

loss, switching loss, body diode deadtime loss and output capacitance loss.

3.3.1 Switch 01
Figure 3.3 below shows the current through switch Q1 in steady state. The switch

turns on when the flying capacitor is discharging. During this phase, Qi carries the

inductor current. The I.,s current was derived as follows:

(3.9)
Ins (Ia2a

The conduction loss was then calculated by:

Pconductior=Irns 2XRdson (3.10)

The switching losses were calculated by:

Pswitching=0.5*Vin 2 IQ1(trise+tfall)fsw (3.11)

The average current IQi was calculated by:

IQi= (Ia -L) (3.12)

34
 AL

ta T t
Figure 3.3: The current through switch Qi in steady state.

Finally, the output capacitance loss was calculated as follows:

PIo~s-cap=Cn-sxVifs. x 0.5 (3.13)

The loss due to driving Qi is determined by:

Pdriver--VgsfswQg (3.14)

where Qgis the gate charge.

3.3.2 Switch 02
Figure 3.4 below shows the current through switch Q2in steady state. The main

losses in this switch were conduction loss, switching loss, body diode dead time loss,

and output capacitance loss.

35
 'Q2I

ta T t

Figure 3.4: The current through switch Q2 in steady state.

The Ims current through this switch was calculated by:

It=Ib (3.15)

IQ2=Irms (3.16)

Then the body diode deadtime loss was calculated as follows:

Pdeadtime=Vd fsw(IbTd+IbTd) (3.17)

The conduction loss was determined as follows:

Pconduction=Ins 2xRdson (3.18)

The output capacitance loss was calculated by:

Pioss.caP=CossxVin2fSW x 0.5 (3.19)

The switching loss was calculated as follows:

Pswitching=0.5*Vin 2 IQ2(trnse+tfaI)fsw (3.20)

36
The loss due to driving Q2 is determined by:

Pdriver=Vgs2fswQg (3.21)

3.3.3 Switch Q3
Figure 3.5 below shows the current through switch Q3in steady state.

Iq3

Ir
'a3

Ioffset
F
.0

ta T

Ts t2

Figure 3.5: The current through switch Q3 in steady state.

The Lns current was calculated as follows:

(3.22)
Irms= (Ioffset2 +IofrsetxIr+ )

Then the switch conduction loss was determined as follows:

PconductionIrms2xRdson (3.23)

The switching loss was then calculated as:

Pswitching=O.5*Vin2 IQ3(trise+tfall)fsw (3.24)

37
Finally, the output capacitance loss was determined as follows:

POss-cap=CossxVin fSW x 0.5 (3.25)

In addition, there is loss due to driving the gate of Q3. The driver loss is given by:

Pdriver=Vgs3fswQg (3.26)

3.4 Modeled power lossresults

Figure 3.6 illustrates the predicted power loss distribution by component at an

output power of 8.25W. These results were obtained from the excel power loss model.

Table 3.1 shows the percent contribution to the loss by each component. At this

operating condition, switch Q3 contributes to the majority of the losses (36.9%), followed

by Q2(26.9%), and Low (16.1%). The gate driver has the least amount of loss.

3.4.1 Accuracy of modeled results

Figure 3.7 compares the predicted power loss to experimental results. The model

is more accurate at lighter loads than it is at full loads. As shown in the figure, the

modeled efficiency at full load is slightly higher than the measured result. At such large

loads, lm- 2R losses due to the parasitics on the PCB board are more difficult to predict,

which could explain the discrepancy in measured and modeled efficiency at full load.

38
 GATE DRIVER Q

LU

Figure 3.6: Predicted power loss distribution by component when the output power is
8.25W.

Component Power Loss %of total

[W] power loss
0.078 9.4
Q2 0.223 26.9
Q3 0.304 36.9
Lour 0.113 16.1
Cny 0.089 10.7

Table 3.1: Component loss distributions predicted by the loss model.

39
 Modeled vs. Measured EffidencyatVo- 5V
100% 1~

98%
-~
_ _ __
96%
94% I-I- -*~-

92% i-v- _____ __________

I I
Efficiency 90%
88% 4
I __
____
-U-Measured
-*r-Modeled
86%
.1-. _______ _______

84%
II _____ __
82% 4-4 I
80%
I _ ___ ___

0 1 2
Iload [Al

Figure 3.7: Modeled versus measured efficiency.

40
4. Device Selection and Sizing of Power Stage
Components
In order to achieve high performance, care must be taken when selecting the

components used in the power converter. The on-chip devices are sized to achieve the

maximum power for a given die area with minimum loss. The off-chip components are

sized to minimize loss and size for a given PCB area, as well as to achieve high

performance at a given switching frequency. Section 4.1.1 details the sizing of switch on-

resistance, and Section 4.1.2 discusses how the flying capacitor should be sized.

4.1 Device Selection and Sizing

4.1.1 Switch on-resistance
The experimental prototype of the 3-switch hybrid step-up power converter was

designed to carry a 3A load current. The switches used were 5V/5V Vgs/Vds isolated

nmos devices. Detailed calculations were performed to determine the Ims current that

each of the three switches carries. Thereafter, a simulation was run to better estimate the

ratios of Im current in the three switches. It was found that the switches Q1 and Q2 carry

about the same current, whereas Q3 carries twice the amount of current as the other two

switches. Hence, the switch that carries the largest root mean square current is designed

to have the smallest on-resistance, and vice versa. Once the switch current was

determined, the switch on resistance was determined by the following equations:

41
 Rsp=Rd..xArea (4.1)

Lmn 1~ Ir-ms2 (4.2)

Lrn6Q3~ 2 IrnsQl (4.3)

Irms ~ 1 (4.4)
Rcison

RdsonQ1 = Rasor2 (4.5)

RdoQ3 = 1 R(4.6)
2

Table 4.1 below summarizes the designed values of the switch on-resistance for the

experimental prototype of the 3-switch step- up power converter.

Irms Rdson Area

Q1 ImS1 40mQ 0.22mm 2
Q2 I.msi 40m(Q 0.22mm 2
Q3 2Irms1 20mQ 0.44mm 2
Total 0.88mm 2
Table 4.1: Designed values for switch on-resistance and area.

As shown in the table, the total area ocuupied by the switches is 0.88mm 2 for an Rsp of

~4*2.2 mQ*mm 2.

4.1.2 Size of the flying capacitor

The flying capacitor should be sized so that it is large enough to hold the input

voltage. However, it must not be too large so as not to have a practical application. At

the same time, the capacitor ESR should be small enough so as to minimize conduction

losses. During the phase when the capacitor charges, the on time of switches Q2and Q3

42
must be long enough so that the capacitor is charged to the input voltage. If Req is the

resistor combination of the on-resistance of switches Q2 and Q3, then the on time of these

two switches should be in the neighborhood of the ReqCfy time constant. Figure 4.1 below

shows the schematic of the converter during the charging phase of the capacitor.

RdsonQ3 _

LL-

Rdson02

Figure 4.1: A schematic showing the charging phase of the flying capacitor. The on
time of switches Q2and Q3 should be in the neighborhood of the RC time constant of
Rdws and RaoQ2.

Unfortunately, the actual capacitance values often differ from those stated in the

capacitor datasheet. In addition to allowing for enough charging time for the flying

capacitor, the size of the capacitor required for the experimental prototype was

determined by using the AP Instruments network analyzer and experimentally

measuring the capacitance at different bias voltages. The test chip application used a

single 10iF flying capacitor.

43
44
5. Design and Layout
Chapters 1- 3 discussed the theory, architecture, and power loss model of the

proposed hybrid power converter. Chapter 4 then presented ways to select the

components used in the power stage. This chapter presents the design and layout of the

experimental prototype. Section 5.1 explains the layout of the power stage, followed by a

discussion of the control circuitry layout in Section 5.2.

5.1 Power Stage

5.1.1 Test Chip Layout
Figure 6.1 illustrates the pin out of the test chip and the schematic of the converter is also

shown for reference.

VIN

I I I I
BOOT1
1
0 01] 03
"3 VSW
vSw
vSw
PHASE LOUT
PWM PHASE
VSW &-
FLY
o 0 PHASE
M z z VPHASE COUl
0 PHASE

02 j

PGND

Figure 5.1: Left is the 3 switch hybrid test chip. To the right is the converter schematic.

45
The test chip of the 3 switch hybrid step-up power converter was designed in a 0.25pm

5V CMOS process. Design help from Intersil Corporation was utilized. The test chip

package consists of 7 pins namely BOOT1, VIN, VSW, PHASE, GND, PWM and BOOT3.

The description of the pins is detailed in Table 5.1.

NAME I/0 DESCRIPTION

BOOT1 I Bootstrapped supply to the Qi gate for PWM enabling. A boot capacitor
is connected between this pin and VSW.
BOOT3 I Bootstrapped supply to the Q3 gate for PWM enabling. A boot capacitor
is connected between this node and VIN.
VIN I Power input to the device. This pin is bypassed to ground in the board
layout.
VSW 0 This pin connects to the switch node of the controller. It connects the Q1
source to the Q2drain.
VPHASE 0 Connects to the phase node of the converter. Connect the flying
capacitor between this pin and VSW. The inductor is also connected to
this pin.
PWM - This pin supplies the control for the switches. It is connected to an
external controller for dosed loop control. It can also be connected to a
signal generator for open loop control.
GND - Ground connection to the device.
Table 5.1: A description of the pin functions of the test chip.

5.1.2 Power Stage Board Layout

The evaluation board for the test chip was designed and laid out by utilizing the

Cadence Allegro PCB design software. Figure 5.2 shows a photograph of the PC3 board.

Majority of the power stage components were placed on the top side of the board using

a tight layout. Care was taken to minimize stray inductance due to the PCB traces. For

instance, components such as the input and boot capacitors were placed as dose to the

IC as possible. In addition, the Vin, Vow and Gnd traces were wide and placed on multiple

46
layers to minimize PCB losses. Multiple layers were used for the Gnd plane to improve

thermal performance. The sensitive analog pins of the controller were placed far from

the converter. As shown in Figure 5.3, the converter was implemented using very small

components. All capacitors and resistors used were of the 0603 package size, apart from

the large electrolytic input capacitor that was placed in parallel with a smaller ceramic

input capacitor. Moreover, a single 10pF ceramic capacitor was used as the flying

capacitor and a small 0.56il-H output inductor achieved minimal ripple current.

(a) Photograph of top side of the converter (b) Photograph of bottom side of the
evaluation board with dime shown for converter evaluation board with dime
scale. shown for scale.

Figure 5.2: Photograph of top and bottom sides of the converter evaluation board.

47
 COUT

- CFY

-CmN

TEST CHIP

Figure 5.3: Photograph of the converter with power stage components labeled.

5.1.3 Power Stage Components

Table 5.2 shows the component values for the power stage. Ceramic capacitors
are used for the flying capacitor due to their relatively low Esr.

Component Value Package Manufacturer

LouT 0.56 H 4020 Wurth Elektronik
CnY 10 tF 0603 TDK
CIN 22[iF 0603 TDK
220 FSanyo
CoUT 22g 0603 TDK

48
Table 5.2: Component values for the power stage.

5.2 Control Circuitry

The ISL6840 current mode controller provided the PWM input to the test chip

and completed the feedback loop. This converter has a maximum duty cycle of 100%,

which enabled its use for a wide range of conversion ratios. The control circuitry was

placed on both the bottom and top sides of the board.

ISL.840 Controller Circuitry Controier Circuitry

(a) Front of evaluation board with control (b) Back of evaluation board with
circuitry boxed out. control circuitry boxed out.

Figure 5.4: Photograph of the evaluation board with control circuits boxed out.

49
Figure 5.5 shows a layout schematic of the components of the PCB board used to

evaluate the test chip. The values of the various components are displayed on the

schematic.

Js It N R12
D0T3 + 50M
U JU
(MVD 9.s5
RI I C5 C13 9OTI
7 open 7in
R3 02uC t -l22v *
221
WIC1 2
Ca R4 COMP -U2
z zZOOT1 J4
-7r COMP WRf - CID
in B01 82C3 2
Ri 2D 2 S D A2

R2
li RJM1 4 5 R9 C1 C
A1 W M Y

(ff PHASE ii

PHASE
0 0 PHASE
o w 14

*O SOOP

RS
J5

27n
C16

L 1

R14

Figure 5.5: Layout schematic of the PCB board components.

50
6. Experimental Results

This chapter presents experimental results obtained by taking data on the test

chip of the proposed hybrid 3 switch step-up power converter. The chapter begins with

an overview of the measurement setup that was used when taking the data in Section

6.1. Section 6.2 discusses the test chip converter waveforms, followed by the power stage

efficiency (Section 6.3) and transient performance (Section 6.4). Finally, the chapter

condudes by showing experimental results of the efficiency gains obtained by the 3

switch hybrid test chip.

6.1 Measurement Setup

Figure 6.1 shows the measurement setup used when taking efficiency

measurements. A 220 F electrolytic capacitor and a 22 IF ceramic capacitor were placed

at the input of the test chip to stabilize the input voltage. The 22pF capacitor was placed

as close as possible to the input of the chip. The input voltage is provided by an Agilent

E3631A dc power supply. To measure the input voltage, an Agilent 34401A digital

multimeter in voltage mode was connected across the 22 F input capacitor. The input

current was measured by connecting an Agilent 34401A digital multimeter in current

mode between the power supply and the input to the evaluation board. A similar setup

of two multimeters in voltage mode and current mode were used to measure the output

51
voltage and the output current respectively. A BK Precision electronic load was

connected to the current measuring multimeter to supply a variable load.

AGILENT AGILENT 34401A

34401A DIGITAL
DIGITAL MULTIMETER
MULTIMETER IDC
IDIC

BK PRECISION
ELECTRONIC
VOUT LOAD
VIN
AGILENT
E3631A TEST CHIP AGILENT
DCPOWER EVALUATION 4
SUPPLY BOARD 34G0TA
-- GND GND MULTIMETER
D

AGILENT 34401A
DIGITAL
MULTnMaEE
VDC

Figure 6.1: Measurement setup used to obtain efficiency measurements.

Care was taken to minimize losses caused by parasitics on the evaluation board

by minimizing the use of probe wires. The converter voltage waveforms were obtained

using the Lecroy WavePro %0 oscilloscope with 4 channels.

6.2 Converter Waveforms

6.2.1 Steady State Waveforms
Figure 6.2 shows the steady state voltage waveforms of the flying capacitor

voltage, the phase node voltage, switch node voltage and inductor current. As seen in

52
 NAy

Vphase

-- -
pm - - -wqr-w- - -- 1

\/SW

1Lt

N/fly

m
- N/phase
7t

IL
4
II
Figure 6.2: Steady state waveforms showing the flying capacitor voltage Vfly, phase
node voltage Vp.a, switch voltage V.s, and inductor current IL The results in the top
graph were obtained at no load, whereas those in the bottom graph were obtained at a
2.5A load.

53
in the two graphs, at no load, there is hardly any ripple in the flying capacitor voltage.

As the load current increases as shown in the bottom graph of Figure 6.2, the current

through the flying capacitor increases and results in a higher AV across the capacitor.

Moreover, the higher load current causes the phase node to dip as more current is forced

out of the node. The downward dip in the phase node voltage can be reduced by either

using a larger size of the flying capacitor, or utilizing a capacitor with a higher voltage

rating.

6.2.2 Startup waveform

Figure 6.3 below shows the output voltage and flying capacitor voltage

waveforms at start up.

Figure 6.3: Startup waveforms showing the output voltage and flying capacitor
voltage at startup.

54
6.3 Closed Loop Efficiency
All efficiency and power loss measurements were obtained at a switching

frequency of 1.25MHz. Table 6.1 below shows key component values used when taking

the efficiency data.

Component Value Package Manufacturer

Low 0.56 iH 4020 Wurth Elektronik
LDCR 16m0 -

Cfly I 10&F 0603 TDK

Table 6.1: Key Component values for efficiency and power loss measurements.

As shown in Figure 6.6, losses increase with an increase in load current due to the rise in

the Ims 2R conduction losses. As Figure 6.4 illustrates, the 3 switch hybrid step-up power

converter exhibits high efficiency even at light loads. Moreover, the converter has a peak

efficiency of 97.7%. The converter's efficiency decreases following a reduction in input

voltage due to the higher conversion ratio at low input voltages.

55
 Converter Efficiency vs. Load at V, = 5V
100%

98%

96% _n_ I _-

94%

92%
-- 3.3 Vin
90%
-U-3 Vin
Efficiency ____________ ____________I____________[____-______
88% - 3.6 Vin
86% -.- 4.2 Vin

84%

82%

80%
0 0.5 I Iload [A.- 5 2 2.5

Figure 6.4: Efficiency measurements at Vout= 5V.

Converter Efficiency vs. Load at V., =3.3V

100%

98%

96%

94%

92%

Efficiency 90%
+- 2.5Vin
-=--3V n
88%

86%

84%

82%

80%
0 0.5 I 1.5 2 2.5
Iload [A]

Figure 6.5: Efficiency measurements at Vout= 3.3V.

56
 Converter Power Loss vs. Load at V. =5V
1
0.9
0.8
0.7
O.6
--.- 3.3Vin

0.5 -m-3Vin

0.4 -.- 3.6Vin

o 0.3 --- 4.2Vin
0.2
0.1 o- - - - - -
0
0 0.5 1 1.5 2 2.5
load [A]

Figure 6.6: Power loss measurements at Vout= 5V.

Converter Power Loss vs. Load at V.t= 3V

1

0.9
0.8
0.7
0.6

0 0.5
I-
-u-2.5Vin
0.4
w --- 3Vin
0 0.3
0.2
0.1
0 . . .
0 I I
0 0.5 1 L.5 2 2.5
Iload [A]

Figure 6.7: Power loss measurements at Vout= 3.3V.

We investigated the effect of the number of flying capacitors used on the power loss of

the converter. This relation is shown in Figure 6.8. Adding a second flying capacitor in

57
parallel with the first has no noticeable effect on light load power loss. As the load

current increased, the power loss reduced by less than 9 % at full load.

Effect of Number of Flying Capacitors on Power Loss at V..t=5V

0.7

U.0

0.5

0.4
3.6 Vin, 1*10uF Cfly
--- 3.6 Vin, 2*10uF Cfly
0.3

0 2

n
0 0.5 1 L5 2 2.5
Iload [A]

Figure 6.8: Effect of number of flying capacitors used on power loss.

6.4 Transient Performance

6.4.1 Load step and step down
Figure 6.9 and 6.10 show the transient performance of the converter when the

load is changed from low to high and vice versa.

58
 W11201 3 0:40:00 PN#

Figure 6.9: Load step up waveform.

-J
1...

I.71.

Figure 6.10: Load step down waveform.

59
60
7. Summary and Conclusions
This chapter provides a summary of the thesis. Ideas for areas of improvement

and future work are discussed in Section 7.2.

7.1 Thesis Summary and Contributions

This thesis presents a switched capacitor/inductor step-up power converter for

small conversion ratios. The circuit offers some gains compared with the conventional

boost converter. These benefits include reduced inductor size, reduced switch voltage

stress and improved dosed loop control while maintaining the efficiency of a boost

converter of a similar IC package size. Adding a flying capacitor between the three

switches reduces the voltage stress on the switches. Moreover, adding the flying

capacitor reduces the required inductor size by reducing the volt-second across the

inductor. A power loss model for the converter is constructed to better understand the

loss mechanisms of the circuit as discussed in Chapter 3.

After an understanding of the operation and loss mechanisms, an experimental

prototype of the power converter is implemented as an integrated circuit and is built in a

0.25[im 5V CMOS process. The converter has a peak efficiency of 97.7%. Moreover, it

displays high efficiency at light load even without using light load efficiency

enhancements schemes. A side by side comparison with the conventional boost

converter shows the efficiency gains of the converter at high voltages.

61
7.2 Future Work
This work has detailed the analysis of a switched capacitor/inductor step-up

power converter and demonstrated its gains through experimental verification. Further

improvements on the converter can be realized by enhancing the efficiency further. For

instance, techniques such as low load enhancements may be applied to the converter to

increase its efficiency. The proposed converter of this thesis belongs to a class of circuits

that comprises of a three switch plus inductor unit that can be arranged to form step-up,

step-down and inverting configurations. Further work will investigate the step-down

and inverting configurations of the class of circuits.

62
Appendix A: Efficiency Comparison with a Conventional

Boost Converter
Earlier work showed a side by side efficiency comparison of the three switch

hybrid step-up converter and the conventional boost converter. An experimental

prototype of the hybrid three switch converter was constructed to demonstrate its gains

over the conventional boost converter. It was built using the ISL85400 buck converter IC

made by Intersil Corp. The third switch, Q3 was implemented using a B340B shottky

diode manufactured by Diodes Incorporated that has a forward voltage drop of 0.6V.

Similarly, the boost converter was implemented using the ISL86401 boost converter IC

made by Intersil Corp. The ISL85400 and ISL86401 IC's have the same switch on

resistance for the high side and low side MOSFET's (450m[2 and 250mQ respectively).

These two IC's were used to ensure that a side by side comparison of the hybrid three

switch and conventional boost converter was achieved.

The efficiency of the two converters was observed with the inductor ripple

current kept constant, and the results are compared in Figure A.1. It is observed that the

hybrid converter has higher efficiency than the conventional boost converter.

63
 Efficiency comparison of conventional boost and 3-switch Power loss comparison of conventional boost and 3-switch
hybrid step-up converter hybrid step-up converter
V. -36V, Vs -24V V , -36V, V, -24V

-Cawertoa boapt -.- 3sitchbost -4-ceveo boost -4-3wtr st

100%-
0.9
95%
08
90%

85%
10-1 07

80%
I _ ___
06 '00,
I 75%

.3 045
TO%

0.3
60%

55% 0.2

509A 0I
0 100 200 300 40 5M0 SW0 0 100 200 300 400 500 600
OapWCbWnut(mA)

Figure A.l: Power loss comparison of the conventional boost converter and the 3
switch hybrid step-up power converter

64
Appendix B: Inductor Conduction Loss Comparison
In Figure B.1, the inductor and switching frequency were kept constant and the

conduction loss in the hybrid three switch and conventional boost converter were

compared. When the converters operate at the same frequency, the inductor in the

conventional boost carries higher average current, as well as higher ripple current,

which results in higher losses.

Comparison of Inductor Conduction Loss

Vo =3.3V, fw = 1.25MHz

0.7

0.6

0.5
--- Hybrid 3 switch
0.4
-+-Conventional
0
-j 0.3 --"00/ -0001,boost
0.2

0.1

0
0 0.5 1 1.5 2 2.5 3
Iload [A]

Figure B.1: Comparison of inductor conduction loss of the proposed converter and the
conventional boost converter.

65
66
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