ARTICLE

https://doi.org/10.1038/s41467-020-20280-3 OPEN

Single-electron operations in a foundry-fabricated

array of quantum dots
Fabio Ansaloni1,3, Anasua Chatterjee1,3, Heorhii Bohuslavskyi1, Benoit Bertrand2, Louis Hutin2, Maud Vinet2 &
Ferdinand Kuemmeth 1 ✉
1234567890():,;

Silicon quantum dots are attractive for the implementation of large spin-based quantum
processors in part due to prospects of industrial foundry fabrication. However, the large
effective mass associated with electrons in silicon traditionally limits single-electron opera-
tions to devices fabricated in customized academic clean rooms. Here, we demonstrate
single-electron occupations in all four quantum dots of a 2 x 2 split-gate silicon device
fabricated entirely by 300-mm-wafer foundry processes. By applying gate-voltage pulses
while performing high-frequency reflectometry off one gate electrode, we perform single-
electron operations within the array that demonstrate single-shot detection of electron
tunneling and an overall adjustability of tunneling times by a global top gate electrode. Lastly,
we use the two-dimensional aspect of the quantum dot array to exchange two electrons by
spatial permutation, which may find applications in permutation-based quantum algorithms.

1 Center for Quantum Devices, Niels Bohr Institute, University of Copenhagen, 2100 Copenhagen, Denmark. 2 CEA, LETI, Minatec Campus, Grenoble, France.
3
These authors contributed equally: Fabio Ansaloni, Anasua Chatterjee. ✉email: [email protected]

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S
ilicon spin qubits have achieved high-fidelity one- and two- capable of inducing one quantum dot with a controllable number
qubit gates1–5, above error-correction thresholds6, promis- of electrons16,17.
ing an industrial route to fault-tolerant quantum compu- While devices with a larger number of split-gate pairs are
tation. A significant next step for the development of scalable possible (see Supplementary Fig. S1 and refs. 17,18), we focus on a
multi-qubit processors is the operation of foundry-fabricated, 2 × 2 quantum-dot array as the smallest two-dimensional unit cell
extendable two-dimensional (2D) quantum-dot arrays. In gallium in this architecture, that is, a device with two pairs of split-gate
arsenide, 2D arrays recently allowed coherent spin operations and electrodes, labeled Gi with corresponding control voltages Vi. The
quantum simulations7,8. In silicon, 2D arrays have been limited to device studied is similar to the one shown in Fig. 1a, but
transport measurements in the many-electron regime9. additionally has a common top gate 300 nm above the channel,
Here, we operate a foundry-fabricated 2 × 2 array of silicon and was encapsulated at the foundry by a backend that includes
quantum dots in the few-electron regime, achieving single- routing to wirebonding pads. Quantum dots are induced in the 7-
electron occupation in each of the four gate-defined dots, as well nm-thick channel by 32-nm-long gates, separated from each
as reconfigurable single, double, and triple dots with tunable other by 32-nm silicon nitride (see “Methods”). The handle of the
tunnel couplings. Pulsed-gate and gate-reflectometry techniques silicon-on-insulator wafer is grounded during measurements, but
permit single-electron manipulation and single-shot charge can in principle be utilized as a back gate. Figure 1b shows a
readout, while the two-dimensionality allows the spatial exchange schematic of the device with Vi tuned to induce a few-electron
of electron pairs. The compact form factor of such arrays, double quantum dot underneath G1 and G4. Source and drain
whose foundry fabrication can be extended to larger 2 × N arrays, contacts allow conventional I(V) transport characterization, while
along with the recent demonstration of spin control10–12 and spin an inductor (wirebonded to G4) allows gate-based reflectometry,
readout13,14, paves the way for dense qubit arrays for quantum in which the combination of a radio-frequency (RF) carrier (VRF)
computation and simulation15. and a homodyne detection circuit yields a demodulated voltage
VH19. Bias tees connected to G1−3 (not shown) allow the
application of high-bandwidth voltage signals.
Results Measurement of the source–drain current I as a function of V1
Device and gate reflectometry. Our device architecture consists and V4 reveals a conventional double-dot stability diagram
of an undoped silicon channel (Fig. 1a, dark gray) connected to a (Fig. 1c), with bias triangles arising from a finite source bias
highly doped source (S) and drain (D) reservoir. Metallic poly- V = −3 mV and co-tunneling ridges indicating substantial tunnel
silicon gates (light gray) partially overlap the channel, each couplings in this few-electron regime (each dot is occupied by 6–9
electrons). The characteristic honeycomb pattern is also observed
a
G3
b V2 V3 in the demodulated voltage VH (Fig. 1d, acquired simultaneously
with Fig. 1c), and suggests the potential use of G4 for
(dispersively) sensing charge rearrangements (quantum capaci-
G2 S I V
tance) anywhere within the 2D array. In the following, we keep
D VRF dot 4 in the few-electron regime (6–9 electrons, serving as a
G4
C sensor dot), resulting in an enhancement of VH whenever dot 4
G1 V1 V4
L R exchanges electrons with its reservoir, and reduce the occupation
log10(I) -13.5 -9.5 V H (mV) -760 -730
numbers of the other three dots (which in the single-electron
c d regime we refer to as qubit dots). In fact, the large capacitive shift
of the dot-4 transition by nearby electrons (evident in Fig. 1c for
c
550 550 V1 dot 1) was used to count the absolute number of electrons within
each of the three qubit dots (see “Methods”).

Single-electron control. It is convenient to control the chemical

V1 (mV)
V1 (mV)

potential of the three qubit dots without affecting the chemical

potential of the sensor dot, as illustrated for dot 1 by the com-
pensated control parameter V c1 (Fig. 1d). This is done experi-
mentally by calibrating the capacitive matrix elements αi4
such that V4 compensates for electrostatic cross-coupling between
470 470 V1−3 and dot 4, that is, by updating voltage V 4 ¼ V o4 
480 V4 (mV) 580 480 V4 (mV) 580 P3
i¼1 α4i ðV i  V i Þ whenever V1−3 is changed relative to a chosen
o

Fig. 1 Compensated control voltages within a two-dimensional silicon reference point ðV o1 ; V o2 ; V o3 Þ. The presence of this compensation
quantum-dot array. a Foundry-fabricated undoped silicon channel is indicated by adding a superscript “c” to the respective control
connected to reservoirs (dark gray), with four gate electrodes (light gray). parameters. Using this compensation, and setting the operating
This SEM image shows a device from a different fabrication run without point of dot 4 with V o4 , the associated reflectometry signal VH can
backend16. b Device schematic for the example of a few-electron double dot be used to detect charge movements between the three qubit dots.
underneath gates G1 and G4, induced by appropriate control voltages V1–4. The compensated voltages are used to map out ground-state
Each of the three qubit dots (dot 1 indicated in red) capacitively couples to regions of various desired charge configurations of the qubit dots.
the sensor dot (black), which can be monitored using RF reflectometry off For example, Fig. 2a was acquired by first parking V1 and V2 in
an inductor (L) wirebonded to G4. c, d Charge stability diagram of the the first Coulomb valley of dot 1 and dot 2 (keeping dot 3 empty
double quantum dot in b, acquired at fixed source–drain bias V = −3 mV. by setting V3 = 0), then tuning V4 to the degeneracy point of dot
Source–drain current I and demodulated reflectometry voltage VH 4 (maximum of VH), before sweeping V c2 vs. V c1 . The
measured simultaneously as a function of V1 and V4. The dotted white line enhancement of VH clearly shows the extent of the 110 ground-
defines a compensated voltage V c1 that controls the chemical potential of state region. (Here, numbers indicate the occupation of the three
dot 1 without affecting the chemical potential of dot 4. Control voltages qubit dots, as illustrated in the schematics of Fig. 2.) Due to the
V c1;2;3 for other dot configurations are established analogously. relatively large capacitive coupling of the sensor dot to the qubit

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a V H (mV) 10 22 b V H (mV) 10 22 c V H (mV) 12 24 d V H (mV) 10 26

300
320 300 280
111
V2 (mV)

V3 (mV)

V3 (mV)

V3 (mV)
101
110
011
c

c
180 160
180 180
c c c c
60 V1 (mV) 160 120 V2 (mV) 260 60 V1 (mV) 180 60 V1 (mV) 140

Fig. 2 Various single-electron configurations within the array. a–c Three different double-dot configurations, controlled by compensated voltages V c1;2;3 .
Numbers indicate the occupation of the three qubit dots (each red dot represents one electron). d Similar to c, but with V c2 fixed at a larger positive voltage,
revealing the triple-dot ground-state region. In a–d the top gate is fixed at 6 V.

dots, dot 4 is in Coulomb blockade outside the 110 region; there While the compact one-gate-per-qubit architecture in accu-
VH reduces to its approximately constant background. (The gain rately dimensioned silicon devices10,12 may ultimately facilitate
of the reflectometry circuit had been changed relative to the the wiring fanout of a large-scale quantum computer23, an overall
acquisition in Fig. 1d.) tunability of certain array parameters may initially be essential.
In addition to the transverse double dot in Fig. 2a, we also Figure 3d demonstrates phenomenologically that all transition
demonstrate the longitudinal (Fig. 2b, with V1 = 0) and diagonal times studied can be decreased significantly by increasing the top-
(Fig. 2c, with V2 = 0) double dots. While such a degree of single- gate voltage. (The specific gate voltages associated with each data
electron charge control is impressive for a reconfigurable, silicon- point are listed in Supplementary Table S1.)
based multi-dot circuit, it is not obvious how coherent single-spin
control (e.g., via micromagnetic field gradients20 or spin–orbit Electron shuttling in two dimensions. An important resource
coupling12) can most easily be implemented in these foundry- for tunnel-coupled two-dimensional qubit arrays is the ability to
fabricated structures. One option is to encode qubits in suitable move or even exchange individual electrons (and their associated
spin states of 111 triple dots, and operate these as voltage- spin states) in real space24. In fact, a two-dimensional triple dot,
controlled exchange-only qubits21,22. To this end, we demonstrate as in our device, is the smallest array that allows the exchange of
in Fig. 2d the tune-up of a triple dot (in order to populate also dot two isolated electrons (Heisenberg spin exchange, as demon-
2, V2 = 197 mV was chosen more positive relative to Fig. 2c), strated in linear arrays25, requires precisely timed wavefunction
revealing the pentagonal cross-section expected for the 111 overlap).
charge state. To demonstrate the spatial exchange of two electrons, we first
follow the 111 ground-state region of Fig. 2d towards lower
voltages on G1−3. In Fig. 4a, this is accomplished by reducing the
Tuning of tunneling times. To demonstrate fast single-shot common-mode voltage ϵc1 , such that the 111 region only borders
charge readout of the qubit dots, we apply voltage pulses to with two-electron ground states. In this gate-voltage region, the
G1–G3 while digitizing VH19. Specifically, two-level voltage pulses charge configuration of the qubit dots is most intuitively
V1,2,3(t) are designed to induce one-electron tunneling events into controlled using a symmetry-adopted coordinate system defined
the quantum-dot array or within the array, as illustrated by color- by
coded arrows in Fig. 3a. One such pulse is exemplified in Fig. 3b, 0 1 0 pffiffiffi pffiffiffi pffiffiffi 10 c 1
ϵc1 1= 3 1= 3 1= 3 V1
preparing one electron in dot 1 (P) before moving it to dot 2 for B cC B pffiffiffi pffiffiffi CB c C
ϵ ¼
@ 2A @ 0 1= 2 1= 2 A@ V 2 A: ð1Þ
measurement (M). P and M are chosen such that the ground-state pffiffiffi pffiffiffi pffiffiffi
transition of interest (in this case the interdot transition) is ϵc3 2= 6 1= 6 1= 6 V c3
expected halfway between P and M, using a pulse amplitude of
2 mV. This pulse is repeated many times, with V4 fixed at a Physically, ϵc1 induces overall gate charge in the qubit-dot
voltage that gives good visibility of the transition of interest in array, whereas detuning ϵc2 (ϵc3 ) relocates gate charge within the
VH(τM). Here, VH(τM) serves as a single-shot readout trace that array along (across) the silicon channel (cf. Fig. 1b). As expected
probes for a tunneling event at time τM after the gate voltages are from symmetry, the 111 region within the ϵc2 –ϵc3 control plane
pulsed to the measurement point (Fig. 3). appears as a triangular region, surrounded by the three two-
Figure 3c shows the repetition of 100 such readout traces electron configurations 011, 101, and 110, as indicated by guides
obtained at a top-gate voltage of 6 V, revealing the stochastic to the eye in Fig. 4b. Importantly, due to the finite mutual
nature of tunneling events, in this case with an averaged charging energies within the array (set by interdot capacitances),
tunneling time of 300 μs. This time is obtained by averaging all these three two-electron regions are connected to each other,
single-shot traces and fitting an exponential decay. In the lower allowing the cyclic permutation of two electrons without
panel of Fig. 3c, V
H indicates that the average (triangles) has been invoking doubly occupied dots (wavefunction overlap) or
normalized according to the offset and amplitude fit parameters, exchange with a reservoir.
which allows comparison with similar data (stars) obtained at a In principle, any closed control loop traversing
top-gate voltage of 10 V (see “Methods”). The deviation of the 011 → 101 → 110 → 011 should exchange the two electrons,
data from the fitted exponential decay (solid line) may indicate which are isolated at all times by Coulomb blockade, making this
the presence of multiple relaxation processes, and the reported a topological operation that may find use in permutational
decay times should therefore be understood as an approximate quantum computing26. In practice, leakage into unwanted qubit
quantification of characteristic tunneling times within the array. configurations (such as 111, 200, 020, etc.) can be avoided by

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V H (mV) -13 0 sensor dot can simultaneously serve as a qubit dot. Our choice of
a c
utilizing dot 4 as a charge sensor (read out dispersively from its
D 32 nm S 80
gate) realizes a compact architecture for spin-qubit imple-
mentations where each gate in principle controls one qubit. This

repetitions
technique also alleviates drawbacks associated with the pure
64 nm dispersive sensing of quantum capacitance, such as tunneling
VH (mV) 428 438 rates constraining the choice of RF carrier frequencies or sig-
b
nificantly limiting the visibility of transitions of interest. For
15 100 110 0
example, the honeycomb pattern in Fig. 1d with a clear visibility
P 1 top gate = 6V of dot-4 and dot-1 transitions is unusual for gate-based dispersive
top gate = 10V sensing in the few-electron regime, where small tunneling rates
M
VH typically limit the visibility of dot-to-lead or interdot transi-
V1 (mV)

000 010 tions29. This is a consequence of the strong cross-capacitance

0
between the reflectometry gate G4 and dot 1, allowing the RF
excitation to probe also the quantum capacitances arising from
0 τM (µs) 1000 dot 1. This also explains the visibility of discrete features within
d the bias triangles of Fig. 1d and shows the potential of gate-based
-10
60 V2 (mV) 120 3 reflectometry for directly revealing excited quantum-dot states.
10
The binary nature of the high-bandwidth charge signal (evident
τ (µs)

V1(τM) in Fig. 2) may also simplify the algorithmic tuning of qubit

arrays30.
V2(τM) 10
1
While all data presented were obtained at zero magnetic field,
τM
application of finite magnetic fields to explore spin dynamics
prepare 0 measure VH 0 top gate (V) 16 and to characterize spin-qubit functionalities should also be
possible. In LETI’s silicon-on-insulator technology, coherent
Fig. 3 Pulsed-gate charge manipulation, single-shot readout, and spin control was demonstrated for holes in double dots using
tunability of tunnel couplings. a Device schematic indicating the lead-to- spin–orbit coupling10,12, and electrically driven spin resonance
dot (green and blue) and interdot (orange and magenta) transitions for the was observed for electrons in double dots using the interplay of
first electron. The arrows indicate the directions of the tunneling events spin–orbit coupling and valley mixing11. Readout of spin using
studied. b Illustration of a V1–V2 gate-voltage pulse (orange) that moves an reflectometry has been demonstrated both for holes10,12 and
electron from dot 1 to dot 2, with V4 fixed such that a tunneling event electrons13,14.
causes a change in the sensor signal VH (color scale). For each pulse, Another important next step is the application of our findings
digitization of VH(τM) begins when the gate-voltage switches from to larger 2 × N devices (see Supplementary Fig. S1 for a 2 × 4 and
preparation point P to measurement point M. c Single-shot traces VH(τM) 2 × 8 device). Unlike linear arrays of qubits31, which do not tol-
for 100 pulse repetitions, with top gate fixed at 6 V. An exponential decay erate defective qubit sites, the development of 2 × N qubit arrays
(orange), fitted to the normalized average of all traces (◂), yields a may prove useful for the realization of fault-tolerant spin-qubit
characteristic tunneling time of 300 μs, and is compared with data obtained quantum computers, trading topological constraints against lower
with the top gate fixed at 10 V (⋆). Analogous data for the other transitions error thresholds32. The systematic loading of such extended
in a are shown in Supplementary Fig. S2. d Tunneling times for the arrays with individual electrons, as well as the controlled move-
transitions indicated in a, as a function of the top-gate voltage. ment of electrons along the array, can be facilitated by virtual
control channels similar to those used in linear arrays24,33. Recent
mapping out their ground-state regions, as demonstrated in experiments even suggest that the capacitive coupling of multiple
Fig. 4c by slightly adjusting the operating point V o4 of the sensor 2 × N arrays on one chip may be possible34,35, opening further
dot. This sensor tuning also allows us to verify the sequence of opportunities for functionalizations and extensions.
traversed charge configurations while sweeping gate voltages Further development of a spin-qubit architecture employing
along the circular shuttling path C, by simultaneously digitizing this platform will rely on array initialization33, coherent spin
VH. The time trace of one shuttling cycle, starting and ending in manipulation36, and high-fidelity operations37, as well as readout
011, is plotted in Fig. 4d, and clearly shows the three charge protocols14,38.
transitions associated with the two-dimensional exchange (i.e., In conclusion, we demonstrate a two-dimensional array of
spatial permutation) of two electrons. quantum dots implemented in a foundry-fabricated silicon
nanowire device. Each dot can be depleted to the last electron,
and pulsed-gate measurements and single-shot charge readout via
Discussion gate-based reflectometry allow manipulation of individual elec-
In this experiment, only gates G1, G2, and G3 can be pulsed trons within the array, while a common top gate provides an
quickly, due to our choice of wirebonding G4 as a reflectometry overall tunability of tunnel couplings. We demonstrate that the
sensor. Therefore, the acquisition in Fig. 4d took much longer array is reconfigurable in situ to realize various multi-dot con-
(51 s) than the intrinsic speed expected from the characteristic figurations, and utilize the two-dimensional nature of the array to
tunneling times in Fig. 3. We did not observe any effects indi- physically permute the position of two electrons. We have also
cating alternative tunneling channels27, but verified by inten- tested device stability, including charge noise (see “Methods”
tionally changing the radius of C and inspecting VH(C) that section) and reproducibility upon multiple thermal cycles from
leakage into undesired charge configurations does indeed now room temperature to base temperature (see Supplementary Table
occur. In future experiments, a faster execution of C combined S2). In conjunction with complementary experiments in various
with spin-selective readout28 may allow a more direct confirma- other laboratories using similar LETI devices from the same
tion of the electrons’ shuttling paths within the array. fabrication run14,18,34,35, these results constitute key steps
We verified that dot 4 can also be depleted to the last electron towards fault-tolerant quantum computing based on scalable,
(see “Methods”) and future work will investigate whether the gate-defined quantum dots.

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c
a
ε c1 b
o
V H (mV) 12 24
o
V H (mV) 28 40
V4 = 595 mV V4 = 592 mV 011
15 011 020
170 15

111

ε c3 (mV)

ε 3c (mV)
111
101 110
c 101
V2 (mV) 110

130 200
200
-20 -10
-20 ε c
2 (mV)
30 -10 ε 2c (mV) 20
300 d
ε c

ε c3 2
38

c
V3 (mV)

V H (mV)
60 c
150
V1 (mV) 28
140
0 C 360 degrees

Fig. 4 Exchange of two electrons by permutation within a 2D array. a Ground-state region of the 111 triple dot from Fig. 2d ¼constant), plotted in (V c2
three-dimensional control-voltage space, along measurements within a plane of fixed common-mode voltage (ϵc1 ¼constant). Physically, ϵc1 induces overall
gate charge in the array, whereas detuning ϵc2 (ϵc3 ) relocates gate charge within the array along (across) the silicon channel. b Guides to the eye indicating
different ground states within the detuning plane in a. For this choice of sensor operating point, V o4 ¼ 595 mV, VH does not discriminate between different
two-electron configurations. c Same detuning plane as in b, but with slightly different sensor operating point, V o4 ¼ 592 mV. The control-voltage path C
traverses three two-electron ground states in such a way that the two isolated electrons are exchanged within the array. d Sensor signal VH acquired during
one cycle of the shuttling path C. Changes in VH reflect single-electron movements within the array, as illustrated by red arrows. After completion of one
cycle C, the position of the two electrons in the array has been permuted.

Methods Voltage control. Low-frequency control voltages are generated by a multi-channel

Sample fabrication. Our quantum-dot arrays are fabricated at CEA-LETI using a digital-to-analog converter (QDevil QDAC) (https://www.qdevil.com), whereas
top-down fabrication process on 300-mm silicon-on-insulator (SOI) wafers, high-frequency control voltages are generated using a Tektronix AWG5014C
adapted from a commercial fully-depleted SOI (FD-SOI) transistor technology16. arbitrary waveform generator. To acquire voltage scans that involve compensated
Compared to single-gate transistors (in which a single-gate electrode wraps across a control voltages, we use appropriately programmed QDevil QDACs.
silicon nanowire) two main changes in regards to gate patterning are needed in
order to realize 2 × N arrays. First, N gate electrodes are patterned, in series along
RF reflectometry. The reflectometry technique is similar to that described in
one silicon channel. Second, a dedicated etching process is introduced that creates a
ref. 19, in which a sensor dot tunnel-coupled to two reservoirs was monitored via a
narrow trench through the gate electrodes, along the nanowire, thereby splitting
SMD-based tank circuit wirebonded to the accumulation gate of the sensor. In this
each gate electrode into one split-gate pair17. The main fabrication steps are
work, the sensor dot (located underneath G4) is tunnel coupled only to one
described below. For illustrative purposes, the device shown in Fig. 1a was imaged
reservoir (source in Fig. 1a), and the increased cross-capacitance to the three qubit
after gate patterning and first spacer deposition16, and does not represent the top
dots results in much larger electrostatic shifts of dot 4 whenever the occupation of
gate and backend.
the qubit dots changes. For example, each pair of triple points in Fig. 1d is spaced
Starting with a blank SOI wafer (12 nm Si/145 nm SiO2), the active mesa
significantly larger than the peak width associated with the sensor-dot transition.
patterning is performed in order to define a thin, undoped nanowire via a
In order to increase the signal intensity as well as to allow for inaccuracies in α4i,
combination of deep-ultra-violet (DUV) lithography and chemical etching. The
we find it useful to occupy the sensor dot with several electrons (6–9 in Fig. 2), and
silicon nanowire is 7-nm thin after oxidation, and has a width of ~70 nm for the
to intentionally power-broaden the Coulomb peaks of dot 4 (with −70 dBm
device studied in this work. Then, a high-quality 6-nm-thick SiO2 gate oxide is
applied to the inductor) for all acquisitions in Fig. 2. The SMD inductance used is
deposited via thermal oxidation. To define the metal gate, a 5-nm-thick layer of
820 nH, and the RF carrier has a frequency of 191.3 MHz. A voltage-controlled
TiN followed by 50 nm of n+-doped polysilicon is used from the standard FD-
phase shifter is used to adjust the phase of the reflected reflectometry carrier
SOI processing. The gate is patterned using a combination of conventional DUV
relative to the local-oscillator signal powering the mixer. The output of the mixer is
lithography combined with an electron-beam lithography process, allowing to
low-pass filtered to generate the demodulated voltage VH. For the data presented
achieve an aggressive intergate pitch down to 64 nm (gate length, longitudinal
here, the phase shifter was adjusted to remove a large background signal in the
gate spacing, and transverse gate spacing as small as 32 nm) without the need for
demodulated voltage, making VH sensitive to phase changes in the reflected
extreme ultraviolet technology. Then, 32-nm-thick SiN spacers between gates
reflectometry carrier.
and between gates and source/drain regions are formed, which serve two roles:
For the real-time detection of interdot tunneling events in Fig. 3c, an Alazar
they protect the intergate regions from self-aligned doping (therefore keeping
digitizing card (ATS9360) is used with a sample rate set to 500 kS/s. The
the channel undoped), and they define tunnel barriers within the array.
integration time per pixel is set by a 30 kHz low-pass filter (SR560), yielding a
Afterwards, raised source/drain regions are regrown to 18 nm to increase the
signal-to-noise ratio as high as 1.4 in this device.
cross-section of source and drain access. Then, to obtain low access resistances,
source/drain are doped in two steps: first with lightly doped drain implant
(using As at moderate doping conditions) and consecutive annealing to activate Determination of electron number. For a given tuning of the quantum-dot array,
dopants, and then with highly doped drain implant (As and P at heavy doping the occupation number of each qubit dot is determined by counting the number of
conditions). To complete the device fabrication, the gate and lead contact discrete electrostatic shifts of the sensor dot (i.e., shifts of a dot-4 Coulomb peak in
surfaces are metallized to form NiPtSi (salicidation), in preparation for metal VH along V4) as the qubit dots are emptied by continuously reducing the control
lines to be routed to bonding pads on the surface of the wafer. Finally, a voltage of the dot of interest. If the total number of electrons within the qubit-dot
standard copper-based back-end-of-line process is used to define an optional array is desired, voltages V1,2,3 can be reduced simultaneously, while sweeping V4
metallic top gate 300 nm above the nanowire, to make interconnections over one or more Coulomb peaks of dot 4, which serves as an electrometer. An
to bonding pads, as well as to encapsulate the device in a protective glass example of such a diagnostic scan, for the case of a 111-occupied triple dot, is
of silicon oxide. Using the powerful parallelism of foundry fabrication, we shown in Supplementary Fig. S3. To determine the number of electrons in the
obtain dozens of dies on a single 300-mm-diameter wafer, each of them sensor (dot 4), we utilized Coulomb peaks associated with dot 3 as an electrometer
containing hundreds of quantum-dot devices buried 2–3 μm below the for dot 4, while continuously reducing V4. This works because the strong dispersive
chip surface. signal associated with the dot-3-to-lead transition shows discrete shifts (along V3)

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6 NATURE COMMUNICATIONS | (2020)11:6399 | https://doi.org/10.1038/s41467-020-20280-3 | www.nature.com/naturecommunications

NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-20280-3 ARTICLE

39. Connors, E. J., Nelson, J. J., Qiao, H., Edge, L. F. & Nichol, J. M. Low- Correspondence and requests for materials should be addressed to F.K.
frequency charge noise in Si/SiGe quantum dots. Phys. Rev. B 100, 165305
(2019). Peer review information Nature Communications thanks the anonymous reviewer(s) for
their contribution to the peer review of this work.

Acknowledgements Reprints and permission information is available at http://www.nature.com/reprints

We thank Silvano De Franceschi for technical help and the coordination of samples. This
project received funding from the European Union’s Horizon 2020 research and inno- Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in
vation program under grant agreements 688539 and 951852. F.A. acknowledges support published maps and institutional affiliations.
from the Marie Sklodowska-Curie Action Spin-NANO (Grant Agreement No. 676108).
A.C. acknowledges support from the EPSRC Doctoral Prize Fellowship. F.K. acknowl-
edges support from the Independent Research Fund Denmark.
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