MIPS Reference Data Card (Green Card) 1. Pull along perforation to separate card 2.

Fold bottom side (columns 3 and 4) together

M I P S Reference Data
Add Immediate Add Unsigned And And Immediate Branch On Equal
addi

CORE INSTRUCTION SET FORNAME, MNEMONIC MAT OPERATION (in Verilog) add Add R R[rd] = R[rs] + R[rt] I I R[rt] = R[rs] + SignExtImm R[rt] = R[rs] + SignExtImm Add Imm. Unsigned addiu
addu and andi beq

OPCODE / FUNCT (Hex) (1) 0 / 20hex (1,2) (2) 8hex 9hex 0 / 21hex 0 / 24hex (3) (4) (4) (5) (5) chex 4hex 5hex 2hex 3hex 0 / 08hex (2) (2) (2,7) (2) 24hex 25hex 30hex fhex 23hex 0 / 27hex 0 / 25hex (3) dhex 0 / 2ahex

R R[rd] = R[rs] + R[rt] R R[rd] = R[rs] & R[rt] I I I J J R[rt] = R[rs] & ZeroExtImm if(R[rs]==R[rt]) PC=PC+4+BranchAddr if(R[rs]!=R[rt]) PC=PC+4+BranchAddr PC=JumpAddr R[31]=PC+8;PC=JumpAddr

Branch On Not Equal bne Jump Jump And Link Jump Register
j jal jr

Load Byte Unsigned lbu Load Halfword Unsigned Load Linked Load Upper Imm. Load Word Nor Or Or Immediate Set Less Than
lhu ll lui lw nor or ori slt

R PC=R[rs] R[rt]={24b0,M[R[rs] I +SignExtImm](7:0)} R[rt]={16b0,M[R[rs] I +SignExtImm](15:0)} I R[rt] = M[R[rs]+SignExtImm] I I R[rt] = {imm, 16b0} R[rt] = M[R[rs]+SignExtImm]

R R[rd] = ~ (R[rs] | R[rt]) R R[rd] = R[rs] | R[rt] I I R[rt] = R[rs] | ZeroExtImm R R[rd] = (R[rs] < R[rt]) ? 1 : 0

OPCODE / FMT /FT FOR/ FUNCT NAME, MNEMONIC MAT OPERATION (Hex) bc1t FI if(FPcond)PC=PC+4+BranchAddr (4) 11/8/1/-Branch On FP True Branch On FP False bc1f FI if(!FPcond)PC=PC+4+BranchAddr(4) 11/8/0/-div R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] 0/--/--/1a Divide divu Divide Unsigned R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] (6) 0/--/--/1b add.s FR F[fd ]= F[fs] + F[ft] 11/10/--/0 FP Add Single FP Add {F[fd],F[fd+1]} = {F[fs],F[fs+1]} + add.d FR 11/11/--/0 Double {F[ft],F[ft+1]} 11/10/--/y FP Compare Single c.x.s* FR FPcond = (F[fs] op F[ft]) ? 1 : 0 FP Compare FPcond = ({F[fs],F[fs+1]} op c.x.d* FR 11/11/--/y Double {F[ft],F[ft+1]}) ? 1 : 0 * (x is eq, lt, or le) (op is ==, <, or <=) ( y is 32, 3c, or 3e) FP Divide Single div.s FR F[fd] = F[fs] / F[ft] 11/10/--/3 FP Divide {F[fd],F[fd+1]} = {F[fs],F[fs+1]} / div.d FR 11/11/--/3 Double {F[ft],F[ft+1]} mul.s FR F[fd] = F[fs] * F[ft] 11/10/--/2 FP Multiply Single FP Multiply {F[fd],F[fd+1]} = {F[fs],F[fs+1]} * mul.d FR 11/11/--/2 Double {F[ft],F[ft+1]} 11/10/--/1 FP Subtract Single sub.s FR F[fd]=F[fs] - F[ft] FP Subtract {F[fd],F[fd+1]} = {F[fs],F[fs+1]} sub.d FR 11/11/--/1 Double {F[ft],F[ft+1]} lwc1 I F[rt]=M[R[rs]+SignExtImm] Load FP Single (2) 31/--/--/-Load FP F[rt]=M[R[rs]+SignExtImm]; (2) ldc1 I 35/--/--/-Double F[rt+1]=M[R[rs]+SignExtImm+4] mfhi R R[rd] = Hi 0 /--/--/10 Move From Hi mflo R R[rd] = Lo 0 /--/--/12 Move From Lo 10 /0/--/0 Move From Control mfc0 R R[rd] = CR[rs] mult R {Hi,Lo} = R[rs] * R[rt] 0/--/--/18 Multiply Multiply Unsigned multu R {Hi,Lo} = R[rs] * R[rt] (6) 0/--/--/19 sra R R[rd] = R[rt] >>> shamt 0/--/--/3 Shift Right Arith. swc1 I M[R[rs]+SignExtImm] = F[rt] Store FP Single (2) 39/--/--/-Store FP M[R[rs]+SignExtImm] = F[rt]; (2) sdc1 I 3d/--/--/-Double M[R[rs]+SignExtImm+4] = F[rt+1]

ARITHMETIC CORE INSTRUCTION SET

Set Less Than Imm. slti Set Less Than Imm. sltiu Unsigned Set Less Than Unsig. sltu Shift Left Logical Shift Right Logical Store Byte Store Conditional Store Halfword Store Word Subtract Subtract Unsigned
sll srl sb sc sh sw sub subu

R[rt] = (R[rs] < SignExtImm)? 1 : 0 (2) ahex R[rt] = (R[rs] < SignExtImm) bhex I ?1:0 (2,6) R R[rd] = (R[rs] < R[rt]) ? 1 : 0 (6) 0 / 2bhex 0 / 00hex R R[rd] = R[rt] << shamt R R[rd] = R[rt] >> shamt M[R[rs]+SignExtImm](7:0) = I R[rt](7:0) M[R[rs]+SignExtImm] = R[rt]; I R[rt] = (atomic) ? 1 : 0 M[R[rs]+SignExtImm](15:0) = I R[rt](15:0) I M[R[rs]+SignExtImm] = R[rt] R R[rd] = R[rs] - R[rt] 0 / 02hex (2) (2,7) (2) (2) 28hex 38hex 29hex 2bhex

FLOATING-POINT INSTRUCTION FORMATS FR

31

opcode
26 25

fmt
21 20

ft
16 15

fs
11 10

fd
6 5

funct
0

FI
31

opcode
26 25

fmt
21 20

ft
16 15

immediate
0

PSEUDOINSTRUCTION SET NAME MNEMONIC OPERATION blt if(R[rs]<R[rt]) PC = Label Branch Less Than bgt if(R[rs]>R[rt]) PC = Label Branch Greater Than ble if(R[rs]<=R[rt]) PC = Label Branch Less Than or Equal bge if(R[rs]>=R[rt]) PC = Label Branch Greater Than or Equal li R[rd] = immediate Load Immediate move R[rd] = R[rs] Move REGISTER NAME, NUMBER, USE, CALL CONVENTION PRESERVED ACROSS NAME NUMBER USE A CALL? $zero 0 The Constant Value 0 N.A. $at 1 Assembler Temporary No Values for Function Results $v0-$v1 2-3 No and Expression Evaluation $a0-$a3 4-7 Arguments No $t0-$t7 8-15 Temporaries No $s0-$s7 16-23 Saved Temporaries Yes $t8-$t9 24-25 Temporaries No $k0-$k1 26-27 Reserved for OS Kernel No $gp 28 Global Pointer Yes $sp 29 Stack Pointer Yes $fp 30 Frame Pointer Yes $ra 31 Return Address Yes

R R[rd] = R[rs] - R[rt] (1) May cause overflow exception (2) SignExtImm = { 16{immediate[15]}, immediate } (3) ZeroExtImm = { 16{1b0}, immediate } (4) BranchAddr = { 14{immediate[15]}, immediate, 2b0 } (5) JumpAddr = { PC+4[31:28], address, 2b0 } (6) Operands considered unsigned numbers (vs. 2s comp.) (7) Atomic test&set pair; R[rt] = 1 if pair atomic, 0 if not atomic rs
26 25 21 20

(1) 0 / 22hex 0 / 23hex

BASIC INSTRUCTION FORMATS R

31

opcode opcode
31 26 25

rt
16 15

rd
11 10

shamt
6 5

funct
0

I J
31

rs
21 20

rt
16 15

immediate
0

opcode
26 25

address
0

Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed.

(-1)S (1 + Fraction) 2(Exponent - Bias) where Single Precision Bias = 127, Double Precision Bias = 1023. IEEE Single Precision and Double Precision Formats: S
31 30

Exponent
23 22

Fraction
0

S
63 62

Exponent
52 51

Fraction
0

MEMORY ALLOCATION $sp 7fff fffchex Stack

STACK FRAME ... Argument 6 Argument 5 $fp Saved Registers

Higher Memory Addresses

$gp

1000 8000hex 1000 0000hex

Dynamic Data Static Data Text Reserved Local Variables

Stack Grows

$sp Lower Memory Addresses

pc

0040 0000hex 0hex

DATA ALIGNMENT

Double Word Word Word Halfword Halfword Halfword Halfword Byte Byte Byte Byte Byte Byte Byte Byte
0 1 2 3 4 5 6 7

Value of three least significant bits of byte address (Big Endian) EXCEPTION CONTROL REGISTERS: CAUSE AND STATUS B Interrupt Exception D Mask Code
31 15 8 6 2

Pending Interrupt
15 8

U M
4

E I L E
1 0

BD = Branch Delay, UM = User Mode, EL = Exception Level, IE =Interrupt Enable EXCEPTION CODES Number Name Cause of Exception Number Name Cause of Exception 0 Int Interrupt (hardware) 9 Bp Breakpoint Exception Address Error Exception Reserved Instruction 4 AdEL 10 RI (load or instruction fetch) Exception Address Error Exception Coprocessor 5 AdES 11 CpU (store) Unimplemented Bus Error on Arithmetic Overflow 6 IBE 12 Ov Instruction Fetch Exception Bus Error on 7 DBE 13 Tr Trap Load or Store 8 Sys Syscall Exception 15 FPE Floating Point Exception SIZE PREFIXES (10x for Disk, Communication; 2x for Memory) PREPREPREPRESIZE FIX SIZE FIX SIZE FIX SIZE FIX 3 10 15 50 -3 -15 Kilo- 10 , 2 Peta10 milli- 10 femto10 , 2 10-6 micro- 10-18 atto106, 220 Mega- 1018, 260 Exa109, 230 Giga- 1021, 270 Zetta- 10-9 nano- 10-21 zepto1012, 240 Tera- 1024, 280 Yotta- 10-12 pico- 10-24 yoctoThe symbol for each prefix is just its first letter, except is used for micro.

Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed.

MIPS Reference Data Card (Green Card) 1. Pull along perforation to separate card 2. Fold bottom side (columns 3 and 4) together

3 OPCODES, BASE CONVERSION, ASCII SYMBOLS MIPS (1) MIPS (2) MIPS Hexa- ASCII Hexa- ASCII DeciDeciopcode funct funct Binary deci- Chardeci- Charmal mal (31:26) (5:0) (5:0) mal acter mal acter sll 00 0000 0 0 NUL 64 40 @ add.f (1) sub.f 00 0001 1 1 SOH 65 41 A j srl mul.f 00 0010 2 2 STX 66 42 B jal sra div.f 00 0011 3 3 ETX 67 43 C beq sllv sqrt.f 00 0100 4 4 EOT 68 44 D bne abs.f 00 0101 5 5 ENQ 69 45 E blez srlv mov.f 00 0110 6 6 ACK 70 46 F bgtz srav neg.f 00 0111 7 7 BEL 71 47 G addi jr 00 1000 8 8 BS 72 48 H addiu jalr 00 1001 9 9 HT 73 49 I slti movz 00 1010 10 a LF 74 4a J sltiu movn 00 1011 11 b VT 75 4b K andi syscall round.w.f 00 1100 12 c FF 76 4c L ori break trunc.w.f 00 1101 13 d CR 77 4d M xori ceil.w.f 00 1110 14 e SO 78 4e N lui sync floor.w.f 00 1111 15 f SI 79 4f O mfhi 01 0000 16 10 DLE 80 50 P mthi (2) 01 0001 17 11 DC1 81 51 Q mflo movz.f 01 0010 18 12 DC2 82 52 R mtlo movn.f 01 0011 19 13 DC3 83 53 S 01 0100 20 14 DC4 84 54 T 01 0101 21 15 NAK 85 55 U 01 0110 22 16 SYN 86 56 V 01 0111 23 17 ETB 87 57 W mult 01 1000 24 18 CAN 88 58 X multu 01 1001 25 19 EM 89 59 Y div 01 1010 26 1a SUB 90 5a Z divu 01 1011 27 1b ESC 91 5b [ 01 1100 28 1c FS 92 5c \ 01 1101 29 1d GS 93 5d ] 01 1110 30 1e RS 94 5e ^ 01 1111 31 1f US 95 5f _ lb add cvt.s.f 10 0000 32 20 Space 96 60 lh addu cvt.d.f 10 0001 33 21 ! 97 61 a lwl sub 10 0010 34 22 " 98 62 b lw subu 10 0011 35 23 # 99 63 c lbu and cvt.w.f 10 0100 36 24 $ 100 64 d lhu or 10 0101 37 25 % 101 65 e lwr xor 10 0110 38 26 & 102 66 f nor 10 0111 39 27 103 67 g sb 10 1000 40 28 ( 104 68 h sh 10 1001 41 29 ) 105 69 i swl slt 10 1010 42 2a * 106 6a j sw sltu 10 1011 43 2b + 107 6b k 10 1100 44 2c , 108 6c l 10 1101 45 2d 109 6d m swr 10 1110 46 2e . 110 6e n cache 10 1111 47 2f / 111 6f o ll tge c.f.f 11 0000 48 30 0 112 70 p lwc1 tgeu c.un.f 11 0001 49 31 1 113 71 q lwc2 tlt c.eq.f 11 0010 50 32 2 114 72 r pref tltu c.ueq.f 11 0011 51 33 3 115 73 s teq c.olt.f 11 0100 52 34 4 116 74 t ldc1 c.ult.f 11 0101 53 35 5 117 75 u ldc2 tne 11 0110 54 36 6 118 76 v c.ole.f c.ule.f 11 0111 55 37 7 119 77 w sc 11 1000 56 38 8 120 78 x c.sf.f swc1 57 39 9 121 79 y c.ngle.f 11 1001 swc2 11 1010 58 3a : 122 7a z c.seq.f c.ngl.f 11 1011 59 3b ; 123 7b { c.lt.f 11 1100 60 3c < 124 7c | sdc1 11 1101 61 3d = 125 7d } c.nge.f sdc2 11 1110 62 3e > 126 7e ~ c.le.f c.ngt.f 11 1111 63 3f ? 127 7f DEL (1) opcode(31:26) == 0 (2) opcode(31:26) == 17ten (11hex); if fmt(25:21)==16ten (10hex) f = s (single); if fmt(25:21)==17ten (11hex) f = d (double)

IEEE 754 FLOATING-POINT STANDARD

4 IEEE 754 Symbols Exponent Fraction Object 0 0 0 0 0 Denorm 1 to MAX - 1 anything Fl. Pt. Num. MAX 0 MAX 0 NaN S.P. MAX = 255, D.P. MAX = 2047

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MIPS R-format Instructions

Instruction fields
op: operation code (opcode) rs: first source register number rt: second source register number rd: destination register number shamt: shift amount (00000 for now) funct: function code (extends opcode)
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R-format Example

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MIPS I-format Instructions

Immediate arithmetic and load/store instructions

rt: destination or source register number Constant: 215to +2151 Address: offset added to base address in rs

Near branch instructions

PC-relative addressing
Target address = PC + offset 4 PC already incremented by 4 by this time

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MIPS J-format Instructions

Jump Addressing
Jump (j and jal) targets could be anywhere in text segment

Direct jump addressing

Target address = PC3128: (address 4)

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Shift Operations (cont)

op
6 bits

rs
5 bits

rt
5 bits

rd
5 bits

shamt
5 bits

funct
6 bits

shamt: how many positions to shift Shift left logical

Shift left and fill with 0 bits sll by i bits multiplies by 2i

Shift right logical

Shift right and fill with 0 bits srl by i bits divides by 2i (unsigned only)
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Review: MIPS Instructions, so far

Category add subtract add immediate shift left logical shift right logical Arithmetic (R & I format) shift right arithmetic and or nor and immediate or immediate load upper immediate
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Instr

OpC 0 & 20 0 & 22 8 0 & 00 0 & 02 0 & 03 0 & 24 0 & 25 0 & 27 c d f add sub

Example $s1, $s2, $s3 $s1, $s2, $s3

Meaning $s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2 + 4 $s1 = $s2 << 4 $s1 = $s2 >> 4 (fill with zeros) $s1 = $s2 >> 4 (fill with sign bit) $s1 = $s2 & $s3 $s1 = $s2 | $s3 $s1 = not ($s2 | $s3) $s1 = $s2 & 0xff00 $s1 = $s2 | 0xff00 $s1 = 0xffff0000
2011, Dr. Dinh Duc Anh Vu 38

addi $s1, $s2, 4 sll srl sra and or nor and or lui $s1, $s2, 4 $s1, $s2, 4 $s1, $s2, 4 $s1, $s2, $s3 $s1, $s2, $s3 $s1, $s2, $s3 $s1, $s2, ff00 $s1, $s2, ff00 $s1, 0xffff

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Review: MIPS Instructions, so far

Category Instr load word store word Data transfer (I format) load byte store byte load half store half br on equal Cond. branch (I & R format) br on not equal set on less than immediate set on less than Uncond. jump jump jump register OpC 23 2b 20 28 21 29 4 5 a 0 & 2a 2 0 & 08 lw sw lb sb lh sh beq bne Example $s1, 100($s2) $s1, 100($s2) $s1, 101($s2) $s1, 101($s2) $s1, 101($s2) $s1, 101($s2) $s1, $s2, L $s1, $s2, L Meaning $s1 = Memory($s2+100) Memory($s2+100) = $s1 $s1 = Memory($s2+101) Memory($s2+101) = $s1 $s1 = Memory($s2+102) Memory($s2+102) = $s1 if ($s1==$s2) go to L if ($s1 !=$s2) go to L if ($s2<100) $s1=1; else $s1=0 if ($s2<$s3) $s1=1; else $s1=0 go to 10000 go to $t1

slti $s1, $s2, 100 slt j jr $s1, $s2, $s3 2500 $t1

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Instructions for Accessing Procedures

MIPS procedure call instruction:
jal ProcedureAddress #jump and link Saves PC+4 in register $ra to have a link to the next instruction for the procedure return Jumps to target address

Machine format (J format):

0x03 26 bit address

Then can do procedure return with a jump register jr $ra # return

Copies $ra to program counter Can also be used for computed jumps (e.g., for case/switch statements)

Instruction format (R format):

0 31 0x08
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Register Usage
$a0 $a3: arguments (regs 4 7) $v0, $v1: result values (regs 2 and 3) $t0 $t9: temporaries
Can be overwritten by callee

$s0 $s7: saved

Must be saved/restored by callee

$gp: global pointer for static data (reg 28) $sp: stack pointer (reg 29) $fp: frame pointer (reg 30) $ra: return address (reg 31)

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Preserved/Not preserved Registers

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Review: MIPS Instructions, so far

Category add subtract add immediate shift left logical shift right logical Arithmetic (R & I format) shift right arithmetic and or nor and immediate or immediate load upper immediate
Computer Architecture, Chapter 2

Instr

OpC 0 & 20 0 & 22 8 0 & 00 0 & 02 0 & 03 0 & 24 0 & 25 0 & 27 c d f add sub

Example $s1, $s2, $s3 $s1, $s2, $s3

Meaning $s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2 + 4 $s1 = $s2 << 4 $s1 = $s2 >> 4 (fill with zeros) $s1 = $s2 >> 4 (fill with sign bit) $s1 = $s2 & $s3 $s1 = $s2 | $s3 $s1 = not ($s2 | $s3) $s1 = $s2 & 0xff00 $s1 = $s2 | 0xff00 $s1 = 0xffff0000
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addi $s1, $s2, 4 sll srl sra and or nor and or lui $s1, $s2, 4 $s1, $s2, 4 $s1, $s2, 4 $s1, $s2, $s3 $s1, $s2, $s3 $s1, $s2, $s3 $s1, $s2, ff00 $s1, $s2, ff00 $s1, 0xffff

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Review: MIPS Instructions, so far

Category Instr load word store word Data transfer (I format) load byte store byte load half store half br on equal Cond. branch (I & R format) br on not equal set on less than immediate set on less than Uncond. jump jump jump register jump and link OpC 23 2b 20 28 21 29 4 5 a 0 & 2a 2 0 & 08 3 lw sw lb sb lh sh beq bne Example $s1, 100($s2) $s1, 100($s2) $s1, 101($s2) $s1, 101($s2) $s1, 101($s2) $s1, 101($s2) $s1, $s2, L $s1, $s2, L Meaning $s1 = Memory($s2+100) Memory($s2+100) = $s1 $s1 = Memory($s2+101) Memory($s2+101) = $s1 $s1 = Memory($s2+102) Memory($s2+102) = $s1 if ($s1==$s2) go to L if ($s1 !=$s2) go to L if ($s2<100) $s1=1; else $s1=0 if ($s2<$s3) $s1=1; else $s1=0 go to 10000 go to $t1 go to 10000; $ra=PC+4
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slti $s1, $s2, 100 slt j jr jal $s1, $s2, $s3 2500 $t1 2500

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Aside: MIPS Register Convention

Name $zero $at $v0 - $v1 $a0 - $a3 $t0 - $t7 $s0 - $s7 $t8 - $t9 $k0 - $k1 $gp $sp $fp $ra Register Number 0 1 2-3 4-7 8-15 16-23 24-25 26-27 28 29 30 31 Usage constant 0 (hardware) reserved for assembler returned values arguments temporaries saved values temporaries reserved for operating system global pointer stack pointer frame pointer return addr (hardware) Preserve on call? n.a. n.a. no yes no yes no n.a yes yes yes yes
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