Dec50143 - PW3 (M.adam F1126)

ELECTRICAL ENGINEERING DEPARTMENT
ACADEMIC SESSION: 2023/2024

DEC50143 - CMOS IC DESIGN & FABRICATION
PRACTICAL Layout Design and Simulation of Basic Logic
WORK 3 : Gates.
PRACTICAL
-
WORK DATE :
LECTURER’S WAN ZAIMI BIN WAN YUSOF
NAME:
GROUP NO. : -
TOTAL
STUDENT ID & NAME : MARKS
(100%)
(1)MUHAMMAD ADAM BIN ABDULLAH (13DTK21F1126)
(2)
(3)
(4)
(5)
DATE SUBMIT : - DATE RETURN : -

6 RESULT
Part A: 2-input NAND gate
S
OPTIMIZED LAYOUT AREA = 50 λ x 80 λ
=4000 λ^2
Part B: 2-input AND gate

=9384 λ^2
Part E: Layout of IC 4011 (NAND Gate)

=30600 λ^2
7 DISCUSSION
1. What is the function of stick diagram in integrated circuit layout design?
Understanding Connectivity: Stick diagrams help designers understand the connectivity between
different components in the IC. By representing transistors, gates, and interconnections as simple
geometric shapes and lines, designers can easily grasp the flow of signals within the circuit.
(2 marks)
2. State the color codes for stick diagram.
I)Black or Solid Lines: Denote active areas, which represent regions where
transistors are located.
II)Red Lines: Represent N-well regions, which are used in CMOS technology to
create the P-channel transistors.
III)Blue Lines: Represent P-well regions, used in CMOS technology for N-

channel transistors.
IV)Green Lines: Indicate polysilicon layers, which are used for gate electrodes.
V)Yellow Lines: Denote metal layers, which are used for interconnecting
different components in the IC.
VI)Brown Lines: Represent the substrate, usually the bulk silicon material.
3. Explain the use of metal2 layer in designing the layout of logic gates IC in Part E.
Interconnecting Components: The Metal2 layer provides a means to connect different
components of the IC, including transistors, resistors, and capacitors. Logic gates consist of
multiple transistors arranged in a specific configuration. The Metal2 layer facilitates the
interconnection of these transistors to create functional logic gates.
8 CONCLUSION
In conclusion, I able to designed the layout of the following logic gates such 2-input NAND
gate and 2-input AND gate with no error. After that, I got the correct output by simulated
(Voltage vs Time) the layout of each gate. Then, I measured the optimized area of the layout
(the unit is λ 2 ) by got the answer for (Length x Width). Lastly, I designed the layout for IC
4011/ IC 4081/ IC 4001 / IC 4071. I also did the same thing by collect it is output timing
diagram and area of the layout. Overall, I successfully finish my task for Practical Work 3
title Layout Design and Simulation of Basic Logic Gates.
(4 marks)
Appendix
CMOS Logic Gates

PRACTICAL SKILL ASSESSMENT RUBRIC
DEC50143 CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 3
Student Name : MUHAMMAD ADAM BIN ABDULLAH Class : DTK5C
Date :
Student ID# : 13DTK21F1126
SCORE DESCRIPTION …………….…………………….
ASPECTS EXCELLENT MODERATE Supervisor Name & SCALE SignatureSCORE

POOR
4-5 2-3 1
Use correct technology Use correct technology
Technology
A. feature for ALL parts of feature for parts of the Use other technology feature. x1
feature
the layout. layout.
Follow lambda design rule
Follow lambda design rule Follow lambda design rule for
B. Design rule for minimum width and x1
for MANY of the polygons. ONLY a few of the polygons.
spacing for ALL polygons.
Use correct PMOS and Use acceptable PMOS and Use incorrect PMOS and
C. Transistor size x2
NMOS transistor size. NMOS transistor size. NMOS transistor size.
Use correct number of Use correct metal layers but Use incorrect metal layers and
D. Metal layers x2
metal layers and width. incorrect width. width.
‘No DRC error’ Able to produce ‘No DRC Able to produce ‘No DRC Not able to produce ‘No DRC
E. display error’ display for ALL error’ display for some of error’ display at ALL. x2
layouts. the layouts.
Layout Design Produce good floorplan Produce appropriate Produce acceptable floorplan
F. – input / and input / output layout floorplan and input / and input / output layout x2
design. output layout design. design.
output /
floorplan
Able to produce the Able to produce the Not able to produce any
G Layout simulation simulation of ALL layouts simulation for some of the simulation for ALL of the x2
correctly. layouts correctly. layouts.
Layout size (end Produce small layout size Produce acceptable layout Produce large layout size (end
H. x2
product) (end product). size (end product). product).
TOTAL / 70

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ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION: 2023/2024

(1)MUHAMMAD ADAM BIN ABDULLAH (13DTK21F1126)

DATE SUBMIT : - DATE RETURN : -

OPTIMIZED LAYOUT AREA = 92 λ x 102 λ

OPTIMIZED LAYOUT AREA = 170 λ x 180 λ

III)Blue Lines: Represent P-well regions, used in CMOS technology for N-

CMOS Logic Gates

SCORE DESCRIPTION …………….…………………….

ASPECTS EXCELLENT MODERATE Supervisor Name & SCALE SignatureSCORE

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