Chapter1 4 - Amplifier MOSFET

APLLIED ELECTRONICS
(EE3129)
Chapter 1-4: MOSFET Amplifier Circuits
HIEU NGUYEN
Department of Electronics
Ho Chi Minh City University of Technology
HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 1 / 90

Table of Contents
1 Voltage Transfer Characteristic - VTC
2 Biasing Problems
3 Biasing in MOSFET Amplifier Circuits
4 Small-signal Models
5 Basic Amplifier Circuits
6 Cascaded Amplifiers
7 Reference

Table of Contents
2 Biasing Problems
7 Reference

Voltage Transfer Characteristic - VTC
Consider a simple MOSFET circuit as shown in (a)
The plot of vDS versus vGS is shown in (b) - Voltage

Transfer Characteristic (VTC)
Explain the VTC:
When vGS < VTN : MOSFET is cut off
iD = 0 → vDS = VDD
When vGS increases from VTN : since vDS will still be
high, the MOSFET will be operating in the
saturation mode. The vDS vs vGS relationship:
1
vDS = VDD − RD Kn (vGS − VTN )2
2
(Neglected channel-length modulation)
When vGS reaches VGS|B (point B) and continues
increasing: vDS decreases to VDS|B = VDSsat
→ MOSFET operates in the triode mode
The vDS vs vGS relationship in triode mode:

2
vDS
vDS = VDD − RD Kn ((vGS − VTN )vDS − )
2
The value of VGS|B be obtained by substituting
vGS = VGS|B and vDS = VDSsat = VGS|B − VTN into
one of two relations above:
√
2Kn RD VDD + 1 − 1
VGS|B = VTN +
Kn RD

In saturation region, the relationship between vDS and

vGS is is quadratic. Nevertheless, by using the technique
of biasing the MOSFET, we can obtain the linear (or
almost-linear) amplification
Obtaining Linear Amplification
A DC voltage VGS is selected to obtain operation at a
point Q on the segment AB of the VTC
Biasing the MOSFET amplifier at a point Q located on

the saturation mode segment of the VTC
Point Q is known as the bias point or the DC

operating point or quiescent point
Since MOSFET is in saturation mode, point Q is
determined by:
The relation between VDS and VGS :
1
VDSQ = VDD − RD Kn (VGSQ − VTN )2
2
1
Current: IDQ = Kn (VGSQ − VTN )2
2


The signal to be amplified vgs (t) a function of time is
superimposed on the bias voltage VGSQ
→ the total voltage at G of MOSFET
vGS (t) = VGSQ + vgs (t)
The resulting output signal vds appears superimposed on
the DC collector voltage VDSQ
→ the total voltage at D of MOSFET
vDS (t) = VDSQ + vds (t)
The relation between vds and vgs :
vds
Av =
vgs
The Small-Signal Voltage Gain
If the input signal vgs is kept small, the corresponding
signal at the output vds will be nearly proportional to vgs
with the constant of proportionality Av being the slope
of the almost-linear segment of the VTC around Q
dvds
Av =
dvgs
vGS =VGSQ
1
By using the relation: vDD = VCC − RD Kn (vGS − VTN )2
2
dvds
→ = −RD Kn (vGS − VTN ) =
dvgs
vGS =VGSQ vGS =VGSQ
−RD Kn (VGSQ − VTN ) = Kn VOV
The Small-Signal Voltage Gain
Assign gm = Kn VOV → Av = −gm RD

→ Av < 0 → the amplifier is inverting → 180o phase
shift between the input and the output
There are 2 conditions to achieve linear amplification:
MOSFET is biased at a point Q in saturation region
The amplitude of vgs (t) is small enough to restrict
the excursion of the instantaneous operating point
to a short almost linear segment of the VTC around
the bias point Q

Example 1
Example 1:
Consider the amplifier circuit shown below. The
transistor is specified to have VTN = 0, 4V ,
Kn = 4mA/V 2 and VA = ∞. Also, let VDD = 1, 8V ,
RD = 17, 5K Ω and VGSQ = 0, 6V
(a) For vgs = 0, find VOV , IDQ , VDSQ and Av

Example 1
With VGSQ = 0, 6V then

VOV = VGSQ − VTN = 0, 6 − 0, 4 = 0, 2(V )
1 2 1
Drain current: IDQ = Kn VOV = .10.0, 22 = 0, 08(mA)
2 2
Drain to source voltage:
VDSQ = VDD − RD IDQ = 1, 8 − 17, 5.0, 08 = 0, 4(V )
Since VDSQ > VOV , the MOSFET operates in saturation
mode
The voltage gain:
Av = −Kn VOV RD = −10.0, 2.17, 5 = −14V /V

Example 1
Example 1:
Consider the amplifier circuit shown below. The
transistor is specified to have VTN = 0, 4V ,
Kn = 4mA/V 2 and VA = ∞. Also, let VDD = 1, 8V ,
RD = 17, 5K Ω and VGSQ = 0, 6V
(b) What is the maximum symmetrical signal swing
allowed at the drain? Hence find the maximum allowable
amplitude of a sinusoidal vgs

Example 1
Sketch the VTC:

Example 1
From VTC, we see that the maximum allowable negative

signal swing at the drain is 0, 2V . In the positive
direction, a swing of 0, 2V would not cause the transistor
to cut off and thus is allowed
→ avdsMax = 0, 2V
The corresponding amplitude of vgs can be found:
av 0, 2
avgsMax = dsMax = = 14, 2mV
|Av | 14
Since avgsMax << VOV , the operation will be reasonably
linear

Example 1
Another solution: vDSmin ≥ vGSmax − VTN

→ 0, 4 − |Av |avgs ≥ 0, 6 + avgs − 0, 4
→ avgs ≤ 0, 2/(|Av | + 1) = 13, 3mV
Table of Contents
2 Biasing Problems
7 Reference

Graphical Analysis
The graphical analysis is based on the observation that
for each value of vGS , the circuit will be operating at the
point of intersection of the corresponding iD vs vDS
graph and the straight line representing for the circuit
In the previous circuit, using KVL:
VDD 1
iD = − vDS
RD RD
The plot of iD vs vDS is a straight line (called DCLL -
DC loadline). It intersects the horizontal axis at VDS and
1
has a slope of −
RD
Graphical Analysis
The DCLL is superimposed on the iD vs vDS
characteristics of MOSFET (output characteristics)

Locating the Point Q
Four important points is labeled:

point A at which vGS = VTN : the region under point
A is cut off region
point Q at which the MOSFET can be biased for
amplifier operation (saturation region)
point B at which the MOSFET leaves saturation
and enters the triode region
point C at which the MOSFET is deep into the
triode region and for which vGS = VDD

Two important considerations in deciding on the location
of Q are the gain and the allowable signal swing at the
output

Load line (1) results in bias point Q1 with a

corresponding VDS that is too close to VDD and thus
limits the positive swing of vDS
Load line (2) results in an operating point, Q2 , too close

to the saturation region, thus limiting the negative swing
of vDS
The exponential relationship iD –vGS means that any

small and inevitable differences in VGS from the desired
value will result in large differences in ID and in VDS
The bias circuit must keep VGSQ from being affected

much by input signal vgs or sometimes by the noise of
the input source
Dependence of VTN on ID and Temp
When MOSFET operates, increasing temperature (by

power dissipation) leads to decrease VTN and increase ID
and changes the position of Q
Table of Contents
2 Biasing Problems
7 Reference

Biasing by Fixing VGS
When MOSFET is bias in saturation region:
1
iD = Kn (vGS − VTN )2
2
The values of the threshold voltage VTN and
coefficient Kn vary widely among devices of
supposedly the same size and type
Both VTN and Kn depend on temperature, with the
result that if we fix the value of vGS , the drain
current iD becomes very much temperature
dependent
The figure in the next slide shows two iD vs vGS
characteristic curves representing MOSFETs of the
same type at two different temperatures
Biasing by Fixing VGS

Biasing by Fixing VG and Rs
An excellent biasing technique for discrete MOSFET
circuits consists of fixing the DC voltage at the gate, VG ,
and connecting a resistance Rs in the Source lead. For
this circuit, we have:
VG = VGS + ID Rs

Resistor Rs provides negative feedback, which

acts to stabilize the value of the bias current ID :
When ID increases for whatever reason, VGS will
have to decrease because VG is constant. This in
turn results in a decrease in ID
The graph on the right provides a graphical
illustration of the effectiveness of this biasing
scheme. The Q point moves from point on T2 to T1
characteristics through a line with slope −1/Rs

The possible practical discrete implementation of this
bias scheme is shown:
RG 2
Since IG = 0, using voltage divider: VG = VDD
RG 1 + RG 2
The Two-Power-Supply Bias
Resistor RG presents a high input resistance to a signal
source that may be connected to the Gate through a
coupling capacitor

Using a CG Feedback Resistor
If ID for some reason increases, the formula show that

VGS must decrease, and vice versa
→ RG provides negative feedback
Biasing Using a Constant-Current Source
Using the current source, the ID is independent of the
values of temperature
RG establishes a DC ground and presents high input
resistance
A simple implementation of the constant-current source I
is shown: current mirror

Table of Contents
2 Biasing Problems
7 Reference

The Signal and the DC Quantities
The analysis indicates that every current and
voltage in the amplifier circuit of is composed of
two components: a dc component and a signal
component
For example: iD = IDQ + id ; vgs = VGSQ + vgs ; ...
The DC components are determined from the bias
circuit (analyzed in the previous part)
Using the superposition theorem, a
representation of the signal operation of the
MOSFET can be obtained by eliminating the DC
sources
The Signal and the DC Quantities
Using the superposition theorem, that a circuit with DC

and signal sources can be analyzed by evaluating only
one source at a time
The small-signal models
One method used to analyze the signal amplification

is small-signal models (or approximation)
The small-signal approximation implies keeping the
signal amplitude sufficiently small that operation is
restricted to an almost-linear segment of the iD ˘vGS
quadratic curve
Increasing the signal amplitude vgs will result in the
ID having components nonlinearly
This approximation requires vgs << 2(VGSQ − VTN )

The small-signal models
The input signal vgs should be keep small:

vgs << 2(VGSQ − VTN ) = VOV
The Hybrid-π models
Using the Y-parameters
i1
y11 =
v1 v2 =0
i2 i2
y21 = and y22 =
v1 v2 =0 v2 v1 =0

i1 ∂iG
The first parameter: y11 = = ∂vGS v =V
v1 v2 =0 DS DSQ
∂iG
Since iG = 0 → ∂vGS v =V =0
DS DSQ
This means the input port is open circuit
i2 ∂iD
The second parameter: y21 = = ∂v
v1 v2 =0 GS vDS =VDSQ
1
Using iD = Kn (vGS − VTN )2 (1 + λvDS )
2
∂iD
⇒ ∂vGS = Kn (vGS − VTN )(1 + λvDS )
vDS =VDSQ vDS =VDSQ
2IDQ 2IDQ
= = = gm
VGSQ − VTN VOV
This parameter is a voltage-controlled current source
i2 ∂iD
The third parameter: y22 = = ∂vDS v =V
v2 v1 =0 GS GSQ
∂iD 1
∂vDS v =V = λ Kn (vGS − VTN )2 (1 + λvDS )
GS GSQ 2 vGS =VGSQ
IDQ
= λIDQ =
VA
This parameter is the conductor seen from the output
port, we often use this parameter as a resistor, named
ro
1 VA 1
ro = = =
y22 IDQ λIDQ

This model is shown in (a). If we neglect ro or VA = ∞,

the model is shown in (b)

The T models
Using some basic circuit transformations:

The T models
The T model is shown in (a) and (b). If we neglect ro or
VA = ∞, the model is shown in (c)

Example 2
Example 2a:
The transistor has VTN = 1, 5V , Kn = 0.25mA/V 2 , and
VA = 50V . Assume the coupling capacitors to be
sufficiently large to act as short circuits at the signal
frequencies of interest
(a) Calculate the overall voltage gain vo /vi

Determining the Q point
Since IG = 0 → VRG = 0
Then:
VGSQ = VDSQ = VDD − RD IDQ
With VDS = VGS , N-MOSFET
operates in saturation mode
1
→ IDQ = Kn (VGSQ − VTN )2
2
(Neglect Early effect)
Solving two equations:
IDQ = 1, 06mA
VGSQ = VDSQ = 4, 4V
VOV = 2, 9V

Calculating the amplifying model
The small-signal model parameters:

2IDQ 2.1, 06 mA
gm = = = 0, 725
VOV 2, 9 V
VA 50
ro = = = 47kΩ
IDQ 1, 06
Carrying out the small-signal analysis
Simplifying the circuit by combining the three parallel

resistances: RL0 = RL ||RD ||ro = 4, 52kΩ
From the new circuit, we have: vo = (ii − gm vgs )RL0 (1)
vgs − vo
and ii = (2)
RG
Carrying out the small-signal analysis
Substituting for ii from (2) into (1) results in the

following expression for the voltage gain:
1
1−
vo vo gm RG
Av = = = −gm RL0 0 ≈ −gm RL0
vi vgs R
1+ L
RG
R0
(Since RG is very large, gm RL0 >> 1 and L << 1)
RG
Substituting, gm = 0, 725mA/V and RL0 = 4, 52kΩ
yields: Av = −3, 3V /V

Example 2b
Example 2b:
(b) Calculate the input resistor seen from the source (in
vi
case of including load RL ): Ri =
ii
To obtain the input resistance, we substitute in (2) for
vo = Av vgs = −gm RL0 vgs :
vgs + gm RL0 vgs 1 + gm RL0
ii = = vgs
RG RG
vi vgs RG RG
⇒ Rin = = = =
ii ii 1 + gm RL0 1 − Av

Example 2b
Substituting, gm = 0, 725mA/V , RL0 = 4, 52kΩ and

RG = 10MΩ yields: Rin = 2, 33MΩ
Note: The input resistance decreases as the gain
(gm RL0 ) is increased
Similarly, calculating the input seen from the source in
case of not including load RL :
vi RG RG
Rin = = =
ii RL =∞ 1 − Avo 1 + gm (ro //RD )
where: Avo = −gm (ro //RD ) is the open-circuit voltage
gain

Example 2
Example 2c:
(c) Assume that vi has a sine waveform. Determine the
maximum amplitude that vi is allowed to have
The largest allowable input signal vi is constrained by the
need to keep the transistor in saturation at all times:
vDSmin ≥ vGSmax − VTN
→ VDSQ − |Av |avgs ≥ VGSQ + avgs − VTN
Since VDSQ = VGSQ :
VTN
avgs ≤ = 0, 35V
|Av | + 1

Table of Contents
2 Biasing Problems
7 Reference

Characterizing Amplifiers
Any amplifier circuit can be modeled using the amplifier
model

Characterizing Amplifiers
vi
The input resistance: Rin =
ii vo =0
vo
The output resistance: Rout =
io ii =0
vo vo
The open-circuit voltage gain: Avo = =
vi vo =0 vi RL =∞
vo RL
The voltage gain: Av = = Avo
vi RL + Ro
vo Rin
The overall voltage gain: Gv = = Av
vsig Rin + Rsig
vo
io RL Rin + Rsig
The current gain: Ai = = vsig = G v
ii RL
Rin + Rsig
The Common-Source (CS) Amplifier
Using π model:

Using T model:

The input resistance: Rin = ∞
The output resistance: Rout = RD
The open-circuit voltage gain: Avo = −gm RD
Since there are no loads, the voltage gain:
Av = Avo = −gm RD
The overall voltage gain:

Rin
Gv = Av = −gm RD
Rin + Rsig

The CS Amplifier with Rs
Using π model:

The CE Amplifier with Re
Using T model:

The CS Amplifier with Rs
Since there are no load RL , the open-circuit voltage gain
and the voltage gain:
RD
Av = Avo = −gm
1 + gm Rs
Rin RD
Gv = Av = −gm RD = −gm
Rin + Rsig 1 + gm Rs

Example 3
Example 3:
The capacitor CC 1 and CC 2 are the coupling capacitors.
The capacitor CS is the bypass capacitor
Calculate the Ri , Ro , Avo , Av , Gv , Ai , and Ap

Coupling Capacitors
The capacitor CC 1 is a coupling capacitor whose
purpose is to couple the signal vsig to the input of
the amplifiers while blocking DC
Similarly, the capacitor CC 2 is used to couple the
output signal vo to other parts of the system
In this way, the DC bias established by VCC and VEE
together with RS and RC will not be disturbed when
the signal vsig is connected
In exercise, they are assumed to be very large so as
to act as a perfect short circuit at signal frequencies
of interest
Bypass Capacitors
A large capacitor CS , usually in the range of (µF or

tens of µF ) is connected between Source and
ground
This capacitor provides a very low impedance to
ground (ideally, zero impedance, in effect, a short
circuit) at all signal frequencies of interest
The Source signal current passes through CS to
ground and thus bypasses the output resistance of
the current source I (and any other circuit
component that might be connected to the Source)

Example 3
The input resistance: Rin = RG

The output resistance: Ro = RD
The open-circuit voltage gain: Avo = −gm RD
Example 3
RL RL
The voltage gain: Av = Avo = −gm RD
Ro + RL RD + RL
Rin RL RG
Gv = Av = −gm RD
Rin + Rsig RD + RL RG + Rsig
The current gain:

Rin + Rsig RG
Ai = Gv = −gm RD
RL RD + RL
The power gain: Ap = Ai Av
Example 4
Example 4:
The capacitor CE is the bypass capacitor

Example 4

Example 4
RD
The open-circuit voltage gain: Avo = −gm
1 + g m Rs
The voltage gain:
RL RD RL
Av = Avo = −gm
Ro + RL 1 + g m Rs RD + RL
Rin RD RL Rin
Gv = Av = −gm
Rin + Rsig 1 + gm Rs RD + RL RG + Rsig
The current gain:
Rin + Rsig RD RG
Ai = Gv = −gm
RL 1 + g m Rs RD + RL
The Common-Drain (CD) Amplifier
Using π model:

Using T model:

1
The output resistance: Rout = ||Rs
gm
Rs
Av = Avo =
1
Rs +
gm
Rin Rs
Gv = Av =
Rin + Rsig 1
Rs +
gm
Example 5
Example 5:

Example 5

The output resistance: Ro = g1m
Example 5
The open-circuit voltage gain: Avo = 1
RL RL
The voltage gain: Av = Avo =
Ro + RL Ro + RL
Rin RL Rin
Gv = Av =
Rin + Rsig Ro + RL Rin + Rsig
The current gain:

Rin + Rsig Rin
Ai = Gv =
RL Ro + RL

The Common-Gate (CG) Amplifier
Using T model:

The Common-Gate (CG) Amplifier
1
The input resistance: Rin =
gm
Av = Avo = gm RD
1
Rin gm
Gv = Av = g m RD
Rin + Rsig 1
+ Rsig
gm
Example 6
Example 6:

Example 6
The input resistance: Rin = g1m

Example 6
The open-circuit voltage gain: Avo = gm RD
RL RL
The voltage gain: Av = Avo = g m RD
Ro + RL Ro + RL
Rin RL Rin
Gv = Av = gm RD
Rin + Rsig Ro + RL Rin + Rsig
The current gain:

Rin + Rsig Rin
Ai = Gv = gm RD
RL Ro + RL

Characteristics of MOSFET Amplifiers

Table of Contents
2 Biasing Problems
7 Reference

Cascaded Amplifiers
To meet given amplifier specifications, we often need to
design the amplifier as a cascade of two or more stages.
Each is designed to serve a specific purpose:
The first stage is usually required to have a large
input resistance
The middle stages are used to amplify the signal
The final stage in the cascade is usually designed to
have a low output resistance

Table of Contents
2 Biasing Problems
7 Reference

Textbooks
1 Microelectronic Circuit (6th edition) - Sedra Smith

2 Giáo trình Điện tử tương tự - Lưu Phú
3 Giáo trình Kỹ thuật xung - Lưu Phú
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APLLIED ELECTRONICS

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 1 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 2 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 3 / 90

The plot of vDS versus vGS is shown in (b) - Voltage

The vDS vs vGS relationship in triode mode:

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 6 / 90

In saturation region, the relationship between vDS and

Biasing the MOSFET amplifier at a point Q located on

Point Q is known as the bias point or the DC

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 9 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 10 / 90

Assign gm = Kn VOV → Av = −gm RD

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 13 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 14 / 90

With VGSQ = 0, 6V then

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 15 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 16 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 17 / 90

From VTC, we see that the maximum allowable negative

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 18 / 90

Another solution: vDSmin ≥ vGSmax − VTN

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 20 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 22 / 90

Four important points is labeled:

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 23 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 24 / 90

Load line (1) results in bias point Q1 with a

Load line (2) results in an operating point, Q2 , too close

The exponential relationship iD –vGS means that any

The bias circuit must keep VGSQ from being affected

When MOSFET operates, increasing temperature (by

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 30 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 32 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 33 / 90

Resistor Rs provides negative feedback, which

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 34 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 36 / 90

If ID for some reason increases, the formula show that

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 38 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 39 / 90

Using the superposition theorem, that a circuit with DC

One method used to analyze the signal amplification

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 42 / 90

The input signal vgs should be keep small:

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 44 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 46 / 90

This model is shown in (a). If we neglect ro or VA = ∞,

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 47 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 48 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 49 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 50 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 51 / 90

The small-signal model parameters:

Simplifying the circuit by combining the three parallel

Substituting for ii from (2) into (1) results in the

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 54 / 90

HIEU NGUYEN (HCMUT) APLLIED ELECTRONICS Chapter 1-4 55 / 90

Substituting, gm = 0, 725mA/V , RL0 = 4, 52kΩ and