Microelectronic Circuits, 8e Sedra, Smith, Carusone, Gaudet

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EE 315 Homework 8

Due Thursday, April 21, 2022


Submit your solutions as a pdf file in Canvas.

Problems 1-4 are based on this amplifier:

1. For the MOS amplifier above, with VDD = 3 V, Vt = 0.5 V, kn = 10 mA/V2 , and RD = 15 kΩ,
determine the coordinates of the active-region segment (AB) of the VTC.
2. We want to bias the MOS amplifier shown above at point Q for which VOV = 0.2 V and VDS = 1 V.
Find the required value of RD when VDD = 3 V, Vt = 0.5 V, and kn = 10 mA/V2 . Also specify the
coordinates of the VTC end point B. What is the small-signal voltage gain of this amplifier? Assuming
linear operation, what is the maximum allowable negative signal swing at the output? What is the
corresponding peak input signal?
3. Design the MOS amplifier above to obtain maximum gain while allowing for an output voltage swing
of at least ±0.2 V. Let VDD = 2 V, and use an overdrive voltage of approximately 0.2 V.

(a) Specify VDS at the bias point.


(b) What is the gain achieved? What is the signal amplitude v̂gs that results in the 0.2 V signal
amplitude at the output?
(c) If the dc bias current in the drain is to be 100 µA, what value of RD is needed?
(d) If kn′ = 400 µA/V2 , what W/L ratio is required for the MOSFET?

4. Consider the MOSFET amplifier above for the case Vt = 0.4 V, kn = 10 mA/V2 , VGS = 0.6 V,
VDD = 1.8 V and RD = 6.8 kΩ
(a) Find the dc quantities ID and VDS
(b) Calculate the value of gm at the bias point.
(c) Calculate the value of the voltage gain.
(d) If the MOSFET has λ = 0.2 V−1 , find rO at the bias point and calculate the voltage gain.
5. For the NMOS amplifier below, replace the transistor with its T equivalent circuit, assuming λ = 0.
Derive the expressions for the voltage gains vs /vi and vd /vi .

Microelectronic Circuits, 8e Sedra, Smith, Carusone, Gaudet Cop


6. Below is a discrete-circuit amplifier. The input signal vsig is coupled to the gate through a very large
capacitor (shown as infinite). The transistor source is connected to ground at signal frequencies via
a very large capacitor (shown as infinite). The output voltage signal that develops at the drain is
coupled to a load resistance via a very large capacitor (shown as infinite). All capacitors behave as
short circuits for signals and as open circuits for dc.
(a) If the transistor has Vt = 1 V, and kn = 4 mA/V2 , verify that the bias circuit establishes
VGS = 1.5 V, ID = 0.5 mA, and VD = +7.0 V. That is, assume these values and verify that they
are consistent with the values of the circuit components and device parameters.
(b) Find gm and rO if VA = 100 V.
(c) Draw a complete small-signal equivalent circuit for the amplifier, assuming all capacitors behave
as short circuits at signal frequencies.
(d) Find Rin , vgs /vsig , vo /vgs , and vo /vsig

Circuits, 8e Sedra, Smith, Carusone, Gaudet Copyright

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