Microelectronic Circuits, 8e Sedra, Smith, Carusone, Gaudet
Microelectronic Circuits, 8e Sedra, Smith, Carusone, Gaudet
Microelectronic Circuits, 8e Sedra, Smith, Carusone, Gaudet
1. For the MOS amplifier above, with VDD = 3 V, Vt = 0.5 V, kn = 10 mA/V2 , and RD = 15 kΩ,
determine the coordinates of the active-region segment (AB) of the VTC.
2. We want to bias the MOS amplifier shown above at point Q for which VOV = 0.2 V and VDS = 1 V.
Find the required value of RD when VDD = 3 V, Vt = 0.5 V, and kn = 10 mA/V2 . Also specify the
coordinates of the VTC end point B. What is the small-signal voltage gain of this amplifier? Assuming
linear operation, what is the maximum allowable negative signal swing at the output? What is the
corresponding peak input signal?
3. Design the MOS amplifier above to obtain maximum gain while allowing for an output voltage swing
of at least ±0.2 V. Let VDD = 2 V, and use an overdrive voltage of approximately 0.2 V.
4. Consider the MOSFET amplifier above for the case Vt = 0.4 V, kn = 10 mA/V2 , VGS = 0.6 V,
VDD = 1.8 V and RD = 6.8 kΩ
(a) Find the dc quantities ID and VDS
(b) Calculate the value of gm at the bias point.
(c) Calculate the value of the voltage gain.
(d) If the MOSFET has λ = 0.2 V−1 , find rO at the bias point and calculate the voltage gain.
5. For the NMOS amplifier below, replace the transistor with its T equivalent circuit, assuming λ = 0.
Derive the expressions for the voltage gains vs /vi and vd /vi .