C UK and Sepic Converter
C UK and Sepic Converter
C UK and Sepic Converter
3
DC to DC Converters
Version 2 EE IIT, Kharagpur 1
Lesson
24
C uK and Sepic Converter
n
• l and Sepic
Draw the circuit diagrams and identify the operating modes of CuK
converters.
• l converter.
Calculate the capacitor voltage ripples and inductor current ripples in CuK
The Canonical Cell forms the basis of analyzing switching circuits, but the energy
transport mechanism forms the foundation of the building blocks of such converters. The Buck
converter may consequently be seen as a Voltage to Current converter, the Boost as a Current to
Voltage converter, the Buck-Boost as a Voltage-Current-Voltage and the CUK as a Current-
Voltage-Current converter. All other switching converter MUST fall into one of these
configurations if it does not increase the switching stages further for example into a V-I-V-I
converter which is difficult to realize through a single controlled switch. It does not require an
explanation that a current source must be made to deliver its energy into a voltage sink and vice-
versa. A voltage source cannot discharge into a voltage sink and neither can a current source
discharge into a current sink. The first would cause current stresses while the latter results in
voltage surges. This rule is analogous to the energy exchange between a source of Potential
Energy (Voltage of a Capacitor) and a sink of Kinetic Energy (Current in an Inductor) and vice-
versa. Both can however discharge into a dissipative load, without causing any voltage or current
amplification. The resonant converters also have to agree to some of these basic rules.
l
24.2 Analysis of C uK converter
The advantages and disadvantages of three basic non-isolated converters can be summerised as
given below.
L R
Vin
C
S1
1 + +
R
Vin C - C2 -
2'
S2
1'
Fig. 24.4: Circuit schematic of a boost-buck converter
Version 2 EE IIT, Kharagpur 5
S1 and S2 operate synchronously with same duty ratio. Therefore there are only two switching
states.
(i) 0 < t ≤ DT
S1 to (1)
& S2 to (1')
R R
Vin C1 C2 C2
(a)
R R
Vin C2 C2
(b)
Fig. 24.5: Circuit topology of a boost-buck converter during different
switching intervals
(a) 0 ≤ t < DT, (b) DT ≤ t < T
These two topologies can also be obtained from the following circuit which is the so called
l converter.
CuK
1 2
S
R
Vin C2
(a)
vc1
L1 C1 L2
+ -
ic2 i0
iL1 iL2
1 2 +
Vin R V0
iB C2 -
(b)
Fig. 24.6: Schematic and Circuit representation of ĈuK converter.
(a) Schematic diagram, (b) Circuit diagram
∴ Vin (1 − D ) VC 1 = 0
Vin
or VC1 = (24.2)
1− D
or V0 + DVC1 = 0 (24.4)
DVin
or V0 = − DVC1 = − (24.5)
1− D
Expression for average inductor current can be obtained from charge balance of C2
I L 2 + I0 = 0 (24.6)
V0 V
∴ I L 2 = − I0 = − = D in (24.7)
R 1− D R
v02 D 2 Vin2
Vin I L1 = V0 I 0 = = (24.8)
R (1 − D )2 R
∴ I L1 = D 2 Vin (24.9)
(1 − D ) R
2
DT T
IL1 MAX
IL1
iL1
IL1 MIN
t
IL2 MAX
IL2
iL2
IL2 MIN
t
t1 t2
IL2 MIN
t
- IL1 MIN
- IL1 MAX
vc1 VC1 MAX
VC1
VC1 MIN
t
ic2
1/2 Iˆ L2 p-p
t1 t2 t
-1/2 Iˆ L2 p-p
Vc2
Vc2
DVin T
I L1MAX = I L1 MIN + (24.10)
L1
Vin DT
IˆL1 = I L1MAX − I L1MIN = (24.11)
p− p L1
⎡ ⎤ DVin
∴ I L1MAX = ⎢ D 2 + RT ⎥ (24.13)
⎣ (1 − D ) 2 L1 ⎦ R
⎡ ⎤ DVin
I L1MIN = ⎢ D 2 − RT ⎥ (24.14)
⎣ (1 − D ) 2 L1 ⎦ R
V0 V
I L 2 MAX = I L 2 MIN − (1 − D )T = I L 2 MIN + in DT (24.15)
L2 L2
Vin DT
∴ IˆL 2 = I L 2 MAX − I L 2 MIN = (24.16)
p− p L2
I L 2 MAX + I L 2 MIN = −2 I 0 = 2 D in
V
(24.17)
1− D R
⎡ ⎤ DVin
∴ I L 2 MAX = ⎢ 1 + RT ⎥ (24.18)
⎣1 − D 2 L2 ⎦ R
⎡ ⎤ DVin
I L 2 MIN = ⎢ 1 − RT ⎥ (24.19)
⎣1 − D 2 L2 ⎦ R
vc1 = 1 ∫ ic1 dt
DT
(24.20)
c1 0
D 2Vin T
or vˆc1 = (24.24)
RC1(1 − D )
t2
vˆc 2 = 1 ∫ ic 2 dt which is the hatched area under ic2 waveform in Fig. 24.8
c 2 t1
V DT Vin DT 2
∴ vˆc = 1 × 1 × T × in = (24.25)
c1 2 2 2 L2 8 L2 C2
l converter of given
Equations 24.11, 24.16, 24.24 and 24.25 can be utilized to design a CuK
specification
The CUK converter as the dual of the Buck-Boost converter has current input and current
output stages. The basic SEPIC is a modification of the basic Boost and the CuK topologies.
Consider the Boost converter in Fig 24.9(b). At steady state, the average voltage across the input
inductor is zero. Equating the inductor voltages for the period when the switch T is ON with that
when it is OFF,
Vin .TON = ( Vout − Vin ) .TOFF
(24.26)
or, Vout = ( 1 ).Vin
1− ∂
where, ∂ is the duty ratio of the switch.
Fig. 24.10 Modified Boost with load across Diode for Boost-Buck
Operation. (left) without output filter, (right) with filter.
In the path, Vin-L-D-Vout, in Fig. 24.9(b), the average voltages across all the elements are
known. Thus, that appearing across the diode D is Vout – Vin. This voltage from Eqn 1 is:
A Boost-Buck converter is thus realized. This is the voltage that would appear in an
unfiltered form at the load in Fig. 24.10 (left). Now, since the source is a current source, the
output stage must be capacitive (voltage sink) which is taken care of by C2-D. The voltage across
D has high ripples, which can be filtered much like the Buck converter with an L (and a C3). The
CUK converter is thus realized. It is a I-V-I converter.
A glaring drawback of this derived converter topology is that the polarity of the output is
reversed. This is not acceptable for various reasons.
Now it is the turn of the Diode to be interchanged with the filter inductor. The inductor is
thus converted to be part of the switching circuit and it not just a filter. The SEPIC results – not
an entirely different one - but easily derivable from the previous topologies.
The SEPIC officially stands for “Single-Ended Primary Inductance Converter”. However,
the unofficial interpretation is more descriptive: “Secondary Polarity Inverted Cuk”.
Again, the basic input–output relation can be derived by considering the two inductors to
have average null voltage across themselves.
If the link capacitor has a voltage Vc across itself (consider it to be reasonably constant),
then for the input inductor, the volt-secs during the ON and OFF periods of the switch are:
Vin .TON = (VC − Vout − Vin )TOFF
(24.27)
or , VC = Vout − Vin (. 1 )
TOFF
For the output inductor,
VC .TON = V out .TOFF (24.28)
Thus the SEPIC is also basically a BOOST-BUCK converter akin to the CUK converter.
(The Boost stage comes first followed by the Buck stage and it is also I-V-I converter)
In the practical SEPIC converter, the two inductors are coupled with the polarities as
indicated by dots in Fig. 24.11(a). The turns ratio is and the coupling is very tight. For such a
coupled-transformer SEPIC, equating the positive and negative volt-secs for the two inductors,
(Vin .K .VC ).TON = (Vout + VC − Vin − K .Vout ).TOFF (24.30)
for the input inductor, and
Version 2 EE IIT, Kharagpur 13
(VC − K ' .Vin ).TON = [Vout − K ' (Vout + VC − Vin )].TOFF (24.31)
Equations (24.28) and (24.29) can be obtained from the above two by substituting both K and K’
to zero to have no coupling between the two coils.
The above two equations result in an identity to indicate that such a system cannot work.
This can be explained by examining the operation of the circuit. Initially when the
transistor is OFF, the capacitor C2 charges to the supply voltage Vin. When the transistor is
switched ON, the resulting active circuit is shown in Fig 24.12.
The circuits to the left and right of the transistor are identical and both the windings are induced
with the supply voltages, resulting in null emfs on either side, which explains why the ideal
circuit will not work. However, neither the coupling between the inductors nor the effective turns
ratio can be unity. This results in a circuit with the features of the uncoupled circuit and the
circuit performs.
The second voltage source, VC, induces N.VC into the primary, where N is the turns ratio. For the
interesting case, Vin = VC = V1, if the turns ratio, n, is increased slightly from unity, by 1/k (where
k < 1 is the coupling coefficient between windings), then the voltage induced by Vin will increase
the voltage at the Drain of the transistor to N. V1, thereby "bootstrapping" the leakage inductance
of the input inductor. Because the voltage at each end of this leakage inductance is the same, its
inductance is effectively infinite. Consequently, all variations in magnetizing current, (through
M) due to a varying V1 is supplied from the secondary winding source. By symmetry, setting
n = k causes the secondary-winding current to become constant while the primary source
supplies the magnetizing-current variations.
This effect can be desirable because, for n = 1/k, it results in constant (DC) primary current.
Noisy switching current does not appear at the converter input but is diverted instead to the
secondary winding. However, typical values of k are slightly less than one, and turns ratios of
nearly 1:1 may not be easy to wind. One simplification is to use a 1:1 transformer, such as a low-
cost, commodity, common-mode power-line input-filter choke, and add a small additional
inductance in series with the primary winding. This effectively increases the leakage inductance
so that the same secondary-winding dominance of magnetizing current is obtained with n = 1.
The waveforms in Fig. 24.13 show the voltage at the transistor Drain present on the fly
back (Boost) and SEPIC circuits. The fly back transformer leakage inductance produces a
voltage spike that adds an additional level to the "flat-top" voltage. This level is about 1.5 times
the supply voltage for inputs around 20 V. In comparison, the SEPIC FET switching waveform
is clamped, and shows very little overshoot, or ringing. This clamping results in less switching-
loss, output voltage noise and a power stage that can be operated at a much higher frequency
than that of the fly back.
Again, the fly back transformer leakage inductance also produces a significant voltage
spike relative to the SEPIC at the output diode. A relatively high voltage (~200V) output diode is
required for the fly back to handle the large negative ringing compared to the SEPIC’s 60V
Schottky diode. The 0.5 volt forward drop of the SEPIC’s Schottky diode relative to the one volt
forward drop of the flyback's ultra-fast diode, results in significant power savings for the SEPIC.
Source:
http://www.nptel.ac.in/courses/Webcourse-contents/IIT%20Kharagpur/Power%20Electronics/PDF/
L-24(DK&SSG)(PE)%20((EE)NPTEL).pdf