MOSFET Capacitances

MOSFET Capacitances
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NMOS Structure :
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MOS Capacitances: Parasitic capacitances associated with MOS are
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MOS Capacitances: Lump representation of the Parasitic MOSFET capacitances
Parasitic capacitances associated with this typical MOSFET structure as lumped equivalent capacitances observed
between the device terminals
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MOS Capacitances: Parasitic capacitances associated with MOS are
• The source and drain overlap region lengths are usually equal to each other because
of the symmetry of the MOSFET structure
• The on-chip capacitances found in MOS circuits are in general complicated functions
of the layout geometries and the manufacturing processes.
• Most of these capacitances are not lumped, but distributed, and their exact
calculations would usually require complex, three-dimensional nonlinear charge-
voltage models.
• Simple approximations for the on-chip MOSFET capacitances can be used in most
hand calculations.
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MOS Capacitances:
• Lumped representation can be easily used to analyse the dynamic transient
behaviour of the device.
• Most parasitic device capacitances are due to three-dimensional, distributed

charge-voltage relations within the device structure.
• Based on their physical origins, the parasitic device capacitances can be

classified into two major groups:
Oxide-related capacitances
Junction capacitances
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MOS - Top View
Oxide-related Capacitance :
MOS – 3D view
MOS Cross-sectional view 7

• The gate electrode overlaps both the Oxide-related Capacitance :
source region and the drain region at
the edges.
• The two overlap capacitances that arise

as a result of this structural
arrangement are called CGD (overlap)
and CGS (overlap), respectively.
• Assuming that both the source and the

drain diffusion regions have the same
width W, the overlap capacitances can
be found as
• Both of these overlap capacitances do

not depend on the bias conditions, i.e.,
they are voltage-independent.
 Cox is gate oxide capacitance per unit sq. area
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Voltage Dependent Capacitances:
• These capacitances result from the interaction between the gate voltage and the
channel charge.
• Since the channel region is connected to the source, the drain, and the substrate,
we can identify three capacitances between the gate and these regions,
i.e. Cgs, Cgd and Cgb respectively.
• In reality, the gate-to-channel capacitance is distributed.
• Then, the gate-to-source capacitance Cgs is actually the gate-to-channel

capacitance seen between the gate and the source terminals.
• Gate-to-drain capacitance Cgd is actually the gate-to-channel capacitance seen

between the gate and the drain terminals
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• MOSFET in cut-off mode - the surface is not inverted, no channel
Consequently, there is no conducting channel that links the surface to the source
and to the drain.
Therefore, the gate-to-source and the gate-to-drain capacitances are both equal to
zero: Cgs = Cgd = 0.
Gate-to-substrate capacitance can be approximated by -
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• MOSFET in linear-mode - the inverted channel extends across the
MOSFET, between the source and the drain
This channel/conducting inversion layer on the surface effectively shields the

substrate from the gate electric field; thus, Cgb = 0.
Here, the distributed gate-to-channel capacitance may be viewed as being shared
equally between the source and the drain,
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• MOSFET in saturation mode : the inversion layer on the surface does not
extend to the drain, but it is pinched off
The gate-to-drain capacitance component is therefore equal to zero, Cgd = 0
Since the source is still linked to the conducting channel, its shielding effect also forces the
gate-to-substrate capacitance to be zero, Cgb = 0
Finally, the distributed gate-to-channel capacitance as seen between the gate and the source
can be approximated by
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• Summary of the approximate oxide capacitance values in three
different operating modes of the MOSFET- including overlap
capacitances
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The variation of the distributed parasitic oxide capacitances as
functions of the gate-to-source voltage is:
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The distributed parasitic oxide capacitances:
• The sum of all three voltage dependent (distributed) gate oxide

capacitances (Cgb + Cgs + Cgd ) has:
A minimum value of 0.66 CoxWL (in saturation mode)

A maximum value of CoxWL (in cut-off and linear modes)
• For simple hand calculations where all three capacitances can be

considered to be connected in parallel, a constant worst-case value of
CoxW (L+2LD) can be used for the sum of MOSFET gate oxide
capacitances
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Junction Capacitance :
• Voltage-dependent source-substrate and drain-substrate junction capacitances,
Csb and Cdb, respectively.
• Both of these capacitances are due to the depletion charge surrounding the
respective source or drain diffusion regions embedded in the substrate.
• The calculation of the associated junction capacitances is complicated by the

three-dimensional shape of the diffusion regions that form the source-substrate
and the drain-substrate junctions
• Note that both of these junctions are reverse-biased under normal operating
conditions of the MOSFET and that the amount of junction capacitance is a
function of the applied terminal voltages 16
Fig. shows the simplified, partial geometry of a typical n-channel enhancement
MOSFET, focusing on the n-type diffusion region within the p-type substrate
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Junction Capacitance :
• As seen in Fig. the n+ diffusion region forms a number of planar pn junctions with the
surrounding p-type substrate, indicated here with 1 through 5
• The dimensions of the rectangular box representing the diffusion region are given as W, Y, xj.
• Also, comparing this three-dimensional view with Fig. we recognize that three of the five
planar junctions shown here (2, 3, and 4) are actually surrounded by the p+ channel-stop
implant.
• The junction labeled (1) is facing the channel, and the bottom junction (5) is facing the p-type
substrate, which has a doping density of NA
• Since the p+ channel-stop implant density is usually about 10NA, the junction capacitances
associated with these sidewalls will be different from the other junction capacitances
• In general, the actual shape of the diffusion regions as well as the doping profiles are much
more complicated.
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Thank you
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MOSFET Capacitances

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MOSFET Capacitances

• Most parasitic device capacitances are due to three-dimensional, distributed

• Based on their physical origins, the parasitic device capacitances can be

MOS Cross-sectional view 7

• The two overlap capacitances that arise

• Assuming that both the source and the

• Both of these overlap capacitances do

• In reality, the gate-to-channel capacitance is distributed.

• Then, the gate-to-source capacitance Cgs is actually the gate-to-channel

• Gate-to-drain capacitance Cgd is actually the gate-to-channel capacitance seen

This channel/conducting inversion layer on the surface effectively shields the

The gate-to-drain capacitance component is therefore equal to zero, Cgd = 0

• The sum of all three voltage dependent (distributed) gate oxide

A minimum value of 0.66 CoxWL (in saturation mode)

• For simple hand calculations where all three capacitances can be

• The calculation of the associated junction capacitances is complicated by the

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