DIGITAL SYSTEMS LAB MCQs

PANIMALAR ENGINEERING COLLEGE
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

MODEL EXAM QUESTION PAPER MCQs
1. How many AND gates are required for a 1-to-8 multiplexer?

a) 2
b) 6
c) 8
d) 5
2. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
3. Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input to Single Output
4. One that is not the outcome of magnitude comparator is ____________
a) a > b
b) a – b
c) a < b
d) a = b
5. The output of a full subtractor is same as ____________
a) Half adder
b) Full adder
c) Half subtractor
d) Decoder
6. What type of logic circuit is represented by the figure shown below?
a) XOR
b) XNOR
c) AND
d) XAND
7. In the 4:1 Mux, C1=0, C0=1, then output M=

a) X1
b) X0
c) X2
d) X3
8. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
9. If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
10. How many two input AND gates and two input OR gates are required to realize Y =
BD + CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
11. If two inputs are active on a priority encoder, which will be coded on the output?
a) The higher value
b) The lower value
c) Neither of the inputs
d) Both of the inputs
12. The enable input is also known as ___________
a) Select input
b) Decoded input
c) Strobe
d) Sink
13. Which RAM has a lesser access time?
a. Static RAM
b. Dynamic RAM
14. Hamming code provides
a. Error detection
b. Correction code
c. None of the above
d. Both a and b
15. If the information is 4 bits, then how many parity bits are required to form the
Hamming code.
a. 2
b. 1
c. 6
d. 3
16. The data can be erased in which type of ROM by exposing to UV light.
a. EPROM
b. PROM
c. EEPROM
d. All the above
17. With respect to PLA, identify the statements that are true
a. PLA provides full decoding and generates all the min terms.
b. Both AND and OR gates are programmable.
c. Only AND gates are programmable.
d. All the above.
18. For a 256*4 static RAM, how many address lines are required to access it.
a. 8
b. 6
c. 12
d. 16
19. What will be the parity bit, if the 3 bit message is 100 and it is checked for odd parity.
a. 0
b. 1
20. Which is more easier to program?
a. PAL
b. PLA
21. What will be the parity bit, if the 3 bit message is 101 and it is checked for even
parity.
a. 0
b. 1
22. If the information is 10111 bits, then how many parity bits are required to form the
Hamming code.
a. 3
b. 4
c. 5
d. 6
23. Which type of memory can be erased by using electrical signals?
a. RAM
b. PROM
c. EPROM
d. EEPROM
24.Programmable Logic Blocks of FPGAs are called as
a. Logic Blocks
b. Configurable Logic Blocks
c. PLA
d. Both a and b
25. The table that is not a part of the asynchronous analysis procedure is ____________
a. Transition table
b. State table
c. Flow table
d. Excitation table
26. In asynchronous circuit, the changes occur with the change of
a. Output
b. Clock Pulse
c. Time
d. Input
27. The race in which stable state depends on order is called
a. Critical
b. Non Critical
c. Identical
d. Defined
28. Time delay is the memory element of
a. Registers
b. Asynchronous circuits
c. Synchronous circuits
d. Flip flops
29. In a combinational circuit, if the output goes momentarily to 0, when it should have
remained a 1, then it is called
a. Dynamic hazard
b. Static 1 hazard
c. Static 0 hazard
d. None
30. Hazards can be eliminated by
a. Enclosing the minterms and maxterms
b. Neglecting one or more minterms and maxterms
c. Nelecting the don’t care conditions for minterms and maxterms
d. All the above
31. The unwanted switching transients that may appear that may appear at the output of a
circuit are called
a. Hazards
b. Difference
c. Race around condition
d. All the above
32. From the Merge Graph, the geometrical pattern consisting of two triangles connecting
(A, B, D) & (C, E, F) and two lines (A, F) & (D, E) are found. What are the set of
compatibles we are left with
a. (A, B, D), (C, E, F), (A, F), (D, E)
b. (A, B, D), (C, E, F), (A, F)
c. (A, B, D), (A, F), (D, E)
d. (A, B, D), (C, E, F)
33. Essential hazards can be eliminated by adjusting
a. by adjusting the amount of delays in the affected path.
b. Race around condition
c. Nelecting the don’t care conditions for minterms and maxterms
d. All the above.
34. In a combinational circuit, if the output goes momentarily to 1, when it should have
remained a 0, then it is called
a. Dynamic hazard
b. Static 1 hazard
c. Static 0 hazard
d. None
35. Which circuit is easier to design?
a. Synchronous circuits
b. Asynchronous circuits.
36. Which among the two circuits are faster?
a. Synchronous circuits
b. Asynchronous circuits.

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PANIMALAR ENGINEERING COLLEGE

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

1. How many AND gates are required for a 1-to-8 multiplexer?

7. In the 4:1 Mux, C1=0, C0=1, then output M=

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