LMK1D1208I I C-Configurable, Low-Additive Jitter LVDS Buffer

LMK1D1208I
SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023
LMK1D1208I I2C-Configurable, Low-Additive Jitter LVDS Buffer
1 Features 3 Description
• High-performance LVDS clock buffer family with The LMK1D1208I is an I2C-programmable LVDS
2 inputs and 8 outputs clock buffer. The device has two inputs and eight
• Output frequency up to 2 GHz pairs of differential LVDS clock outputs (OUT0 through
• Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% OUT7) with minimum skew for clock distribution.
• Device configurability through I2C programming The inputs can either be LVDS, LVPECL, LVCMOS,
– Individual input and output enable/disable HCSL, or CML.
– Individual output amplitude select (standard or The LMK1D1208I is specifically designed for driving
boosted) 50-Ω transmission lines. When driving inputs in
– Bank input multiplexer single-ended mode, apply the appropriate bias
• Four programmable I2C addresses through IDX voltage to the unused negative input pin (see Figure
pins 9-6).
• Low additive jitter: < 60 fs RMS maximum in
12-kHz to 20-MHz at 156.25 MHz I2C programming enables this device to be configured
– Very low phase noise floor: -164 dBc/Hz as a single bank buffer (one of the two inputs
(typical) is distributed to eight output pairs) or as a dual
• Very low propagation delay: < 575 ps maximum bank buffer (each input is distributed to four outputs
• Output skew: 20 ps maximum pairs). Each output can be configured to have
• Universal inputs accept LVDS, LVPECL, LVCMOS, either a standard (350 mV) or boosted (500 mV)
HCSL and CML swing. This device also incorporates individual output
• Fail-safe inputs channel enable or disable through I2C programming.
• LVDS reference voltage, VAC_REF, available for The LMK1D1208I has fail-safe inputs that prevent
capacitive coupled inputs oscillation at the outputs in the absence of an input
• Industrial temperature range: –40°C to 105°C signal and allows for input signals before VDD is
• Packages available supplied.
– 6-mm × 6-mm, 40-Pin VQFN (RHA) The device operates in a 1.8-V, 2.5-V, or 3.3-V
supply environment and is characterized from –40°C
2 Applications
to 105°C (ambient temperature).
• Telecommunications and networking
• Medical imaging Package Information
• Test and measurement equipment PACKAGE SIZE
PART NUMBER PACKAGE(1)
(NOM)(2)
• Wireless communications
LMK1D1208I VQFN (40) 6.00 mm × 6.00 mm
• Pro audio/video
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
ADC CLOCK
200 MHz
100
156.25 MHz
Oscillator
LMK1D1208I
LVDS Buffer
SDA
SCL FPGA CLOCK
IDX1
IDX0 100
Application Example
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK1D1208I
SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023 www.ti.com
Table of Contents
1 Features............................................................................1 9.5 Programming............................................................ 20
2 Applications..................................................................... 1 9.6 Register Maps...........................................................21
3 Description.......................................................................1 10 Application and Implementation................................ 25
4 Revision History.............................................................. 2 10.1 Application Information........................................... 25
5 Device Comparison......................................................... 3 10.2 Typical Application.................................................. 25
6 Pin Configuration and Functions...................................4 10.3 Power Supply Recommendations...........................28
7 Specifications.................................................................. 6 10.4 Layout..................................................................... 29
7.1 Absolute Maximum Ratings........................................ 6 11 Device and Documentation Support..........................31
7.2 ESD Ratings............................................................... 6 11.1 Documentation Support.......................................... 31
7.3 Recommended Operating Conditions.........................6 11.2 Receiving Notification of Documentation Updates.. 31
7.4 Thermal Information....................................................7 11.3 Support Resources................................................. 31
7.5 Electrical Characteristics.............................................7 11.4 Trademarks............................................................. 31
7.6 Typical Characteristics.............................................. 11 11.5 Electrostatic Discharge Caution.............................. 31
8 Parameter Measurement Information.......................... 12 11.6 Glossary.................................................................. 31
9 Detailed Description......................................................14 12 Mechanical, Packaging, and Orderable
9.1 Overview................................................................... 14 Information.................................................................... 31
9.2 Functional Block Diagram......................................... 14 12.1 Package Option Addendum.................................... 32
9.3 Feature Description...................................................15 12.2 Tape and Reel Information......................................34
9.4 Device Functional Modes..........................................18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (February 2022) to Revision A (June 2023) Page

• Changed table title from: Device Information to: Package Information.............................................................. 1
• Added the Device Comparison table for the LMK1Dxxxx buffer device family................................................... 3
• Moved the Power Supply Recommendations and Layout sections to the Application and Implementation
section.............................................................................................................................................................. 28
2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: LMK1D1208I

LMK1D1208I
www.ti.com SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023
5 Device Comparison
DEVICE OUTPUT
DEVICE FEATURES PACKAGE BODY SIZE
TYPE SWING
Global output enable and swing 350 mV

LMK1D2108 Dual 1:8 VQFN (48) 7.00 mm × 7.00 mm
control through pin control 500 mV



Global output enable control 350 mV

LMK1D1216 2:16 VQFN (48) 7.00 mm × 7.00 mm
through pin control 500 mV
Global output enable control 350 mV

LMK1D1212 2:12 VQFN (40) 6.00 mm × 6.00 mm
Individual output enable control 350 mV

LMK1D1208P 2:8 VQGN (40) 6.00 mm × 6.00 mm
Individual output enable control 350 mV

LMK1D1208I 2:8 VQFN (40) 6.00 mm × 6.00 mm
through I2C 500 mV
Global output enable control
LMK1D1208 2:8 350 mV VQFN (28) 5.00 mm × 5.00 mm
through pin control
Individual output enable control
LMK1D1204P 2:4 350 mV VQGN (28) 5.00 mm × 5.00 mm
through pin control
Global output enable control
LMK1D1204 2:4 350 mV VQFN (16) 3.00 mm × 3.00 mm
through pin control
Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

LMK1D1208I
6 Pin Configuration and Functions
OUT3_N
OUT2_N
OUT1_N
OUT3_P
OUT2_P
OUT1_P
NC
NC
NC
NC
30 29 28 27 26 25 24 23 22 21
NC 31 20 VDD
OUT4_P 32 19 OUT0_N
OUT4_N 33 18 OUT0_P
OUT5_P 34 17 NC
6mm x 6mm
OUT5_N 35 40 pin QFN 16 IDX1
NC 36 15 IDX0
NC 37 14 VAC_REF0
Thermal Pad
OUT6_P 38 13 IN0_N
OUT6_N 39 12 IN0_P
VDD 40 11 VDD
1 2 3 4 5 6 7 8 9 10
VAC_REF1
NC
OUT7_P
OUT7_N
NC
SDA
SCL
NC
IN1_P
IN1_N
Figure 6-1. LMK1D1208I: RHA Package 40-Pin VQFN (Top View)
Table 6-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME LMK1D1208I
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P, IN0_N 12, 13 I Primary: Differential input pair or single-ended input
IN1_P, IN1_N 8, 9 I Secondary: Differential input pair or single-ended input.
I2C PROGRAMMING
SDA 5 I/O I2C data
SCL 6 I I2C clock
I2C address bit[0]. This is a 2-level input that is decoded in
IDX0 15 I,S,PU conjunction with pin 15 to set the I2C address. It has internal
670-kΩ pullup.
I2C address bit[1]. This is a 2-level input that is decoded in
IDX1 16 I,S, PU conjunction with pin 16 to set the I2C address. It has internal
670-kΩ pullup.
BIAS VOLTAGE OUTPUT
Bias voltage output for capacitive coupled inputs. If used, TI
VAC_REF0, VAC_REF1 14, 10 O
recommends using a 0.1-µF capacitor to GND on this pin.
DIFFERENTIAL CLOCK OUTPUT
OUT0_P, OUT0_N 18, 19 O Differential LVDS output pair number 0

LMK1D1208I
Table 6-1. Pin Functions (continued)

PIN
TYPE(1) DESCRIPTION
NAME LMK1D1208I
SUPPLY VOLTAGE
VDD 11, 20, 40 P Device power supply (1.8 V, 2.5 V, or 3.3 V)
GROUND
Die Attach Pad. Connect to the printed circuit board (PCB)
DAP DAP G
ground plane for heat dissipation.
NO CONNECT
1, 4, 7, 17, 21, 26,
NC — No connection. Leave floating.
27, 30, 31, 36, 37
(1) The definitions below define the I/O type for each pin.
• I = Input
• O = Output
• I / O = Input / Output
• PU = Internal 670-kΩ Pullup
• S = Hardware Configuration Pin
• P = Power Supply
• G = Ground

LMK1D1208I
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage –0.3 3.6 V
VIN Input voltage –0.3 3.6 V
VO Output voltage –0.3 VDD + 0.3 V
IIN Input current –20 20 mA
IO Continuous output current –50 50 mA
TJ Junction temperature 135 °C
Tstg Storage temperature (2) –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Device unpowered
7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±3000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per ANSI/ESDA/
±1000
JEDEC JS-002, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
3.3-V supply 3.135 3.3 3.465
VDD Core supply voltage 2.5-V supply 2.375 2.5 2.625 V
1.8-V supply 1.71 1.8 1.89
Supply Requires monotonic ramp (10-90% of
Supply voltage ramp 0.1 20 ms
Ramp VDD)
TA Operating free-air temperature –40 105 °C
TJ Operating junction temperature –40 135 °C

LMK1D1208I
7.4 Thermal Information

LMK1D1208I
THERMAL METRIC(1) VQFN UNIT
40 PINS
RθJA Junction-to-ambient thermal resistance 39.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.4 °C/W
RθJB Junction-to-board thermal resistance 20.2 °C/W
ΨJT Junction-to-top characterization parameter 1 °C/W
ΨJB Junction-to-board characterization parameter 20.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics

VDD = 1.8 V ± 5 %, –40°C ≤ TA ≤ 105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY CHARACTERISTICS
All-outputs enabled and
IDDSTAT LMK1D1208I unterminated, f = 0 Hz (AMP_SEL 55 mA
=1)
All-outputs enabled, RL = 100
IDD100M LMK1D1208I Ω, f =100 MHz (AMP_SEL = 0, 75 95 mA
default)
All-outputs enabled, RL = 100 Ω, f
IDD100M LMK1D1208I 110 mA
=100 MHz, AMP_SEL = 1
IDX INPUT CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
Minimum input voltage for a
VIH Input high voltage 0.7 × VCC VCC + 0.3 V
logical "1" state
Maximum input voltage for a
VIL Input low voltage –0.3 0.3 × VCC V
logical "0" state
VDD can be 1.8V/2.5V/3.3V with
IIH Input high current 30 µA
VIH = VDD
VDD can be 1.8V/2.5V/3.3V with
IIL Input low current –30 µA
VIH = VDD
Rpull-up(IDX) Input pullup resistor 670 kΩ
I2C INTERFACE CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
VIH Input high voltage 0.7 × VCC VCC + 0.3 V
VIL Input low voltage –0.3 0.3 × VCC V
CIN_SE Input capacitance at 25°C 2 pF
VOL Output low voltage IOL = 3 mA 0.3 V
Standard 100
fSCL I2C clock rate Fast mode 400 kHz
Ultra Fast mode 1000
tSU(START) START condition setup time SCL high before SDA low 0.6 us
tH(START) START condition hold time SCL low after SDA low 0.6 us
tW(SCLH) SCL pulse width high 0.6 us
tW(SCLL) SCL pulse width low 1.3 us
tSU(SDA) SDA setup time 100 ns

LMK1D1208I
tH(SDA) SDA hold time SDA valid after SCL low 0 0.9 us
tR(IN) SDA/SCL input rise time 300 ns
tF(IN) SDA/SCL input fall time 300 ns
tF(OUT) SDA output fall time CBUS <= 400 pF 300 ns
tSU(STOP) STOP condition setup time 0.6 us
tBUS Bus free time between STOP and START 1.3 us
SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN Input frequency Clock input DC 250 MHz
Assumes a square wave input
VIN_S-E Single-ended Input Voltage Swing 0.4 3.465 V
with two levels
Input Slew Rate (20% to 80% of the
dVIN/dt 0.05 V/ns
amplitude)
IIH Input high current VDD = 3.465 V, VIH = 3.465 V 50 µA
IIL Input low current VDD = 3.465 V, VIL = 0 V –30 µA
CIN_SE Input capacitance at 25°C 3.5 pF
DIFFERENTIAL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN Input frequency Clock input 2 GHz
Differential input voltage peak-to-peak VICM = 1 V (VDD = 1.8 V) 0.3 2.4

VIN,DIFF(p-p) VPP
{2*(VINP-VINN)} VICM = 1.25 V (VDD = 2.5 V/3.3 V) 0.3 2.4
VIN,DIFF(P-P) > 0.4 V (VDD = 1.8
VICM Input common mode voltage 0.25 2.3 V
V/2.5/3.3 V)
VDD = 3.465 V, VINP = 2.4 V, VINN
= 1.2 V
VDD = 3.465 V, VINP = 0 V, VINN =
1.2 V
CIN_S-E Input capacitance (Single-ended) at 25°C 3.5 pF
LVDS DC OUTPUT CHARACTERISTICS
Differential output voltage magnitude | VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
|VOD| 250 350 450 mV
VOUTP - VOUTN| Ω, AMP_SEL = 0
Differential output voltage magnitude | VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
|VOD| 400 500 650 mV
VOUTP - VOUTN| Ω, AMP_SEL = 1
Change in differential output voltage
magnitude. Per output, defined as the VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
ΔVOD –15 15 mV
difference between VOD in logic hi/lo Ω, AMP_SEL = 0
states.
Change in differential output voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
ΔVOD –20 20 mV
magnitude Ω, AMP_SEL = 1
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
1 1.2
Steady-state common mode output Ω (VDD = 1.8 V)
VOC(SS) V
voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
1.1 1.375
Ω (VDD = 2.5 V/3.3 V)
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω
0.8 1
Steady-state common mode output (VDD = 1.8 V), AMP_SEL = 1
VOC(SS) V
voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω
0.9 1.1
(VDD = 2.5 V/3.3 V), AMP_SEL = 1
Change in steady-state common mode
V = 0.3 V, RLOAD = 100
ΔVOC(SS) output voltage. Per output, defined as the IN,DIFF(P-P) –15 15 mV
Ω, AMP_SEL = 0
difference in VOC in logic hi/lo states.
Change in steady-state common mode VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
ΔVOC(SS) –20 20 mV
output voltage Ω, AMP_SEL = 1
LVDS AC OUTPUT CHARACTERISTICS

LMK1D1208I
Vring Output overshoot and undershoot –0.1 0.1 VOD
Ω, fOUT = 491.52 MHz
VOS Output AC common mode 50 100 mVpp
Ω , AMP_SEL = 0
VOS Output AC common mode 75 150 mVpp
Ω, AMP_SEL = 1
IOS Short-circuit output current (differential) VOUTP = VOUTN –12 12 mA
Short-circuit output current (common-
IOS(cm) VOUTP = VOUTN = 0 –24 24 mA
mode)
tPD Propagation delay 0.3 0.575 ns
Ω (2)
Skew between outputs with the
tSK, O Output skew same load conditions (4 and 8 20 ps
channel) (3)
Skew between outputs on
different parts subjected to the
tSK, PP Part-to-part skew same operating conditions with 250 ps
the same input and output
loading.
50% duty cycle input, crossing
tSK, P Pulse skew point-to-crossing-point distortion –20 20 ps
(4)
fIN = 156.25 MHz with 50% duty-

cycle, Input slew rate = 1.5V/ns,
tRJIT(ADD) Random additive Jitter (rms) Integration range = 12 kHz – 20 50 60 fs, RMS
MHz, with output load RLOAD =
100 Ω
PN1kHz –143
Phase Noise for a carrier frequency of PN10kHz –152
156.25 MHz with 50% duty-cycle, Input
Phase noise PN100kHz –157 dBc/Hz
slew rate = 1.5V/ns with output load
RLOAD = 100 Ω PN1MHz –160
PNfloor –164
fIN = 156.25 MHz. The difference
in power level at fIN when the
selected clock is active and the
MUXISO Mux Isolation 80 dB
unselected clock is static versus
when the selected clock is inactive
and the unselected clock is active.
ODC Output duty cycle With 50% duty cycle input 45 55 %
tR/tF Output rise and fall time 20% to 80% with RLOAD = 100 Ω 300 ps
20% to 80% with RLOAD = 100 Ω
tR/tF Output rise and fall time 300 ps
(AMP_SEL= 1)
Time taken for outputs to go from
ten/disable Output Enable and Disable Time disable state to enable state and 1 us
vice versa. (5) (6)
Outputs are held in high Z mode
with OUTP = OUTN (max applied
IleakZ Output leakage current in High Z external voltage is the lesser 50 uA
of VDD or 1.89V and minimum
applied external voltage is 0V
VAC_REF Reference output voltage VDD = 2.5 V, ILOAD = 100 µA 0.9 1.25 1.375 V
POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5 V/ 3.3 V

LMK1D1208I
10 kHz, 100 mVpp ripple injected
–70
Power Supply Noise Rejection (fcarrier = on VDD
PSNR dBc
156.25 MHz) 1 MHz, 100 mVpp ripple injected
–50
on VDD
(1) Measured between single-ended/differential input crossing point to the differential output crossing point.
(2) For the dual bank devices, the inputs are phase aligned and have 50% duty cycle.
(3) Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
(4) Applies to the dual bank family.
(5) Time starts after the acknowledge bit

LMK1D1208I
7.6 Typical Characteristics

Figure 7-1 captures the variation of the LMK1D1208I current consumption with input frequency and supply
voltage. Figure 7-2 shows the variation of the differential output voltage (VOD) swept across frequency.
It is important to note that Figure 7-1 and Figure 7-2 serve as a guidance to the users on what to expect for
the range of operating frequency supported by LMK1D1208I. These graphs were plotted for a limited number of
frequencies and load conditions which may not represent the customer system.
90
85
80
Current Consumption (mA)
75
70
65
VDD = 1.8 V, TA = -40
VDD = 1.8 V, TA = 25
VDD = 1.8 V,TA = 105
VDD = 2.5 V, TA = -40
60 VDD = 2.5 V, TA = 25
VDD = 2.5 V,TA = 105
VDD = 3.3 V, TA = -40
VDD = 3.3 V, TA = 25
VDD = 3.3 V,TA =105
55
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
Frequency (MHz)
Figure 7-1. LMK1D1208I Current Consumption vs. Frequency

380
VDD = 1.8 V, T A = -40 VDD = 2.5 V, T A = 105
370 VDD = 1.8 V, T A = 25 VDD = 3.3 V, T A = -40
360 VDD = 1.8 V, T a = 105 VDD = 3.3 V, T A = 25
VDD = 2.5 V, T A = -40 VDD = 3.3 V, T A = 105
350 VDD = 2.5 V, T A = 25
340
330
320
VOD (mV)
310
300
290
280
270
260
250
240
100 200 300 400 500 600 700 800 900 1000 2000
Frequency (MHz)
Figure 7-2. LMK1D1208I VOD vs. Frequency

LMK1D1208I
8 Parameter Measurement Information
LVDS 100 W Oscilloscope
Figure 8-1. LVDS Output DC Configuration During Device Test
100
Phase Noise/
LMK1D1208I Balun

Spectrum Analyzer
Figure 8-2. LVDS Output AC Configuration During Device Test
VIH
Vth
IN
VIL
IN
Vth
Figure 8-3. DC-Coupled LVCMOS Input During Device Test
OUTNx VOH
VOD
OUTPx VOL
80%
20% VOUT,DIFF,PP (= 2 x VOD)
0V
tr tf
Figure 8-4. Output Voltage and Rise/Fall Time

LMK1D1208I
INNx
INPx
tPLH0 tPHL0
OUTN0
OUTP0
tPLH1 tPHL1
OUTN1
OUTP1
tPLH2 tPHL2
OUTN2
OUTP2
tPLH7 tPHL7
OUTN7
OUTP7
A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference
between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7)
B. Part-to-part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference
between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7)
Figure 8-5. Output Skew and Part-to-Part Skew
Vring
OUTNx
VOD
0 V Differential
OUTPx
Figure 8-6. Output Overshoot and Undershoot
VOS
GND
Figure 8-7. Output AC Common Mode

LMK1D1208I
9 Detailed Description
9.1 Overview
The LMK1D1208I is a low-additive jitter, I2C-programmable, LVDS output clock buffer that uses CMOS
transistors to control the output current. Therefore, proper biasing and termination are required to ensure correct
operation of the device and to maximize signal integrity. The LMK1D1208I also includes status and control
registers for configuring the different modes in the device.
The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the
receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI
recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage
different than the output common-mode voltage of the LMK1D1208I, AC coupling must be used.If the LVDS
receiver has internal 100-Ω termination, external termination must be omitted.
9.2 Functional Block Diagram
VDD
VDD
Rpull-up
IDX0, IDX1
2
SDA OUTx_AMP_SEL Output Swing

I2C Logic
SCL
Control
INx_EN
BANKx_IN_SEL
OUTx_EN
OUT[0:N/2-1]
IN0
Input Selection
Bank Control
IN1
OUT[N/2:N-1]
Reference
VAC_REF
Voltage
GND

LMK1D1208I
9.3 Feature Description

The LMK1D1208I is an I2C-programmable, low-additive jitter, LVDS fan-out buffer that can generate up to eight
copies of two selectable LVPECL, LVDS, HCSL, CML, or LVCMOS inputs. This feature-rich device allows the
user to have flexibility on the configuration based on their application use-case.
9.3.1 Fail-Safe Input
The LMK1D120x family of devices is designed to support fail-safe input operation. This feature allows the user
to drive the device inputs before VDD is applied without damaging the device. Refer to Specifications for more
information on the maximum input supported by the device. The device also incorporates an input hysteresis,
which prevents random oscillation in absence of an input signal, allowing the input pins to be left open.
9.3.2 Input Stage Configurability
The LMK1D1208I has an input stage that accepts up to two clock inputs and can be configured as either a 2:1
mux or as a dual bank. When configured as a 2:1 mux, the LMK1D1208I device can select one of the two clock
inputs and then distribute it to the eight LVDS output pairs. In the dual bank mode, the LMK1D1208I can assign
each clock input to fan out four LVDS output pairs per bank. Refer to the Device Functional Modes for how to
configure the two input stages.
Unused inputs can be left floating to reduce overall component cost. Both AC and DC coupling schemes can be
used with the LMK1D1208I to provide greater system flexibility.
9.3.3 Dual Output Bank
LMK1D1208I has eight LVDS output pairs which are grouped into two banks, each with four LVDS output pairs.
The Table 9-1 outlines this mapping.
Table 9-1. Output Bank Map
BANK CLOCK OUTPUTS
0 OUT0, OUT1, OUT2, OUT3
1 OUT4, OUT5, OUT6, OUT7
9.3.4 I2C
The I2C control is used to configure the different features in the LMK1D1208I. These features include individual
input and output channel enable or disable, input mux select in each bank, bank muting (setting bank outputs
to logic low), and individual output amplitude control. The I2C logic is also capable of fast mode where the
frequency is 400 kHz.
9.3.4.1 I2C Address Assignment
The I2C address is assigned by the two pins, IDX0 and IDX1. Each IDX pin supports two levels allowing the
LMK1D1208I to assume four different I2C addresses. See Table 9-2 for address pin assignment.
Table 9-2. I2C Address Assignment
I2C ADDRESS IDX1 IDX0
0x68 L L
0x69 L H
0x6A H L
0x6B H H

LMK1D1208I
9.3.5 LVDS Output Termination

TI recommends that unused outputs are terminated differentially with a 100-Ω resistor for optimum performance.
Unterminated outputs are also okay, but this will result in a slight degradation in performance (Output AC
common-mode VOS) in the outputs being used.
Figure 9-1 and Figure 9-2 show how the LMK1D1208I can be connected to LVDS receiver inputs with DC and
AC coupling, respectively.
Z = 50 W
LMK1D12XX 100 W LVDS
Z = 50 W
Figure 9-1. Output DC Termination

100 nF
Z = 50 W
LMK1D12XX 100 W LVDS
Z = 50 W
100 nF
Figure 9-2. Output AC Termination (With the Receiver Internally Biased)
9.3.6 Input Termination

The LMK1D1208I inputs can be interfaced with LVDS, LVPECL, HCSL or LVCMOS drivers.
Figure 9-3 and Figure 9-4 show how LVDS drivers can be connected to LMK1D1208I inputs with DC coupling
and AC coupling, respectively.
Z = 50 W
LVDS 100 W LMK1D12XX
Z = 50 W
Figure 9-3. LVDS Clock Driver Connected to LMK1D1208I Input (DC-Coupled)

100 nF
Z = 50 W
LVDS LMK1D12XX
Z = 50 W
100 nF
50 W 50 W
VAC_REF
Figure 9-4. LVDS Clock Driver Connected to LMK1D1208I Input (AC-Coupled)
Figure 9-5 shows how to connect LVPECL inputs to the LMK1D1208I. The series resistors are required to
reduce the LVPECL signal swing if the signal swing is >1.6 VPP.

LMK1D1208I
75 W 100 nF
Z = 50 W
LVPECL LMK1D12XX
Z = 50 W
75 W 100 nF
150 W 150 W 50 W 50 W
VAC_REF
Figure 9-5. LVPECL Clock Driver Connected to LMK1D1208I Input
Figure 9-6 shows how to couple a LVCMOS clock input to the LMK1D1208I directly.
R
LVCMOS S
(1.8/2.5/3.3 V) Z = 50 :
LMK1D12XX
V IH V IL
V th
2
Figure 9-6. 1.8-V, 2.5-V, or 3.3-V LVCMOS Clock Driver Connected to LMK1D1208I Input
For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors.

LMK1D1208I
9.4 Device Functional Modes

The outputs of Bank 0 and Bank 1 can be one of three options: logic low, buffered IN0, or buffered IN1.
These output types should only be attained by maintaining the register setting combination outlined in Table
9-3. The LMK1D1208I registers must be programmed within these possible logic states to ensure proper device
functionality. Using the device outside the intended logic can result in degraded performance.
Table 9-3. Register Control Logic Table
BANKx OUTPUTS BANKx_IN_SEL BANKx_MUTE IN0_EN IN1_EN
Logic low X 1 X X
IN0 1 0 1 X
IN1 0 0 X 1
9.4.1 Input Enable Control

The LMK1D1208I allows for individual input channel enable or disable through the INx_EN register field. The
inputs should be disabled when not in use to reduce the power consumption.
Table 9-4 describes the control of this function. INx_EN is set by register 0x02 (R2). See R2 Register for more
information on this register.
Table 9-4. Input Control
INx_EN ACTIVE CLOCK INPUT
0 INx_P, INx_N disabled
1 INx_P, INx_N enabled
9.4.2 Bank Input Selection

Bank 0 and Bank 1 can choose between the two inputs to fanout four LVDS output pairs each. In the 2:1 input
mux mode, each bank must select the same clock input to output eight identical clocks. With the dual bank
mode, each bank can select a different clock input to distribute both inputs separately; this is analogous to
having two 1:4 buffers. When operating in dual bank mode, TI recommends that Bank 0 not select IN1 and Bank
1 not select IN0 to avoid crosstalk and degraded performance.
The BANKx_IN_SEL register field configures this function described in Table 9-5. BANKx_IN_SEL is set by
register 0x02 (R2). See R2 Register for more information on this register.
Table 9-5. Bank Input Selection
BANKx_IN_SEL BANK CLOCK INPUT
0 BANKx selects IN1_P, IN1_N
1 BANKx selects IN0_P, IN0_N
9.4.3 Bank Mute Control

Each bank, Bank 0 or Bank 1, can be individually muted such that the bank outputs are set to logic low (OUTx_P
is low and OUTx_N is high).
Table 9-6 describes the control of this function. The BANKx_MUTE register field is set by register 0x02 (R2). See
R2 Register for more information on this register.
Table 9-6. Bank Mute Control
BANKx_MUTE BANK CLOCK OUTPUTS
0 BANKx outputs selected INx
1 BANKx outputs logic low

LMK1D1208I
9.4.4 Output Enable Control

The outputs of the LMK1D1208I can be individually enabled or disabled through the OUTx_EN register field.
The disabled state of the outputs is high impedance as this reduces the power consumption and also prevents
back-biasing of the devices connected to these outputs. Unused outputs should be disabled to eliminate the
need for a termination resistor. In the case of enabled unused outputs, TI recommends a 100-Ω termination for
optimal performance.
Table 9-7 describes the control of this function. OUTx_EN is set by register 0x00 (R0). See R0 Register for more
information on this register.
Table 9-7. Output Control
OUTx_EN CLOCK OUTPUTS
OUTx_P, OUTx_N disabled in

0
Hi-Z state
1 OUTx_P, OUTx_N enabled
9.4.5 Output Amplitude Selection

The amplitude of the LMK1D1208I outputs can be individually programmed through the OUTx_AMP_SEL
register field. The boosted LVDS swing mode can be used in applications which require a higher output swing
for better noise performance (higher slew rate) or for swing requirements in the receiver that the standard LVDS
swing cannot meet.
Table 9-8 describes the control of this function. OUTx_AMP_SEL is set by register 0x01 (R1). See R1 Register
for more information on this register.
Table 9-8. Output Amplitude Selection Table
OUTx_AMP_SEL OUTPUT AMPLITUDE (VOD)
0 Standard LVDS swing (350 mV)
1 Boosted LVDS swing (500 mV)

LMK1D1208I
9.5 Programming
The LMK1D1208I uses I2C to program the states of its eight output drivers. See I2C for more information on the
I2C features and address assignment, and Register Maps for the list of programmable registers.
Table 9-9. Command Code Definition
BIT DESCRIPTION
0 = Block Read or Block Write operation
7
1 = Byte Read or Byte Write operation
(6:0) Register address for Byte operations, or starting register address for Block, operations
1 7 1 1 8 1 1
S Peripheral Address R/W A Data Byte A P
MSB LSB MSB LSB
S Start Condition
Sr Repeated Start Condition
R/W 1 = Read (Rd); 0 = Write (Wr)

A Acknowledge (ACK = 0 and NACK =1)
P Stop Condition
Controller-to-Peripheral Transmission
Peripheral-to-Controller Transmission
Figure 9-7. Generic Programming Sequence

1 7 1 1 8 1 8 1 1
S Peripheral Address Wr A CommandCode A Data Byte A P
Figure 9-8. Byte Write Protocol
1 7 1 1 8 1 1 7 1 1
S Peripheral Address Wr A CommandCode A S Peripheral Address Rd A
8 1 1
Data Byte A P
1
Figure 9-9. Byte Read Protocol
1 7 1 1 8 1 8 1
S Peripheral Address Wr A CommandCode A Byte Count = N A
8 1 8 1 8 1 1
Data Byte 0 A Data Byte 1 A … Data Byte N-1 A P
Figure 9-10. Block Write Protocol
1 7 1 1 8 1 1 7 1 1
S Peripheral Address Wr A CommandCode A S Peripheral Address Rd A
8 1 8 1 8 1 1
Data Byte N A Data Byte 0 A Data Byte N-1 A P
1 1 1
Figure 9-11. Block Read Protocol

LMK1D1208I
9.6 Register Maps

9.6.1 LMK1D1208I Registers
Table 9-10 lists the LMK1D1208I registers. All register locations not listed should be considered as reserved
locations and the register contents should not be modified.
TI highly suggests that the user only operates within the logic states listed in Table 9-3 for optimum performance.
Table 9-10. LMK1D1208I Registers
Address Acronym Register Fields Section
0h R0 Output Enable Control Go
1h R1 Output Amplitude Control Go
2h R2 Input Enable and Bank Setting Control Go
5h R5 Device/Revision Identification Go
Eh R14 I2C Address Readback Go
Complex bit access types are encoded to fit into small table cells. Table 9-11 shows the codes that are used for
access types in this section.
Table 9-11. LMK1D1208I Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Reset/default value in
hexadecimal
9.6.1.1 R0 Register (Address = 0h) [reset = 0h]

R0 is shown in Table 9-12.
The R0 register contains bits that enable or disable individual output clock channels [7:0].
Return to the Summary Table.
Table 9-12. R0 Register Field Descriptions
Bit Field Type Reset Description
7 OUT7_EN R/W 0h This bit controls the output enable signal for output channel
OUT7_P/OUT7_N.
0h = Output Disabled (Hi-Z)
1h = Output Enabled
OUT6_P/OUT6_N.
1h = Output Enabled
OUT5_P/OUT5_N.
1h = Output Enabled
OUT4_P/OUT4_N.
1h = Output Enabled

LMK1D1208I
Table 9-12. R0 Register Field Descriptions (continued)

OUT3_P/OUT3_N.
1h = Output Enabled
OUT2_P/OUT2_N.
1h = Output Enabled
OUT1_P/OUT1_N.
1h = Output Enabled
OUT0_P/OUT0_N.
1h = Output Enabled

The R1 register contains bits that set the output amplitude to a standard or boosted LVDS swing.
7 OUT7_AMP_SEL R/W 0h This bit sets the output amplitude for output channel OUT7_P/
OUT7_N.
0h = Standard LVDS Swing (350 mV)
1h = Boosted LVDS Swing (500 mV)
OUT6_N.
OUT5_N.
OUT4_N.
OUT3_N.
OUT2_N.
0h = Standard LVDS swing (350 mV)
1h = Boosted LVDS swing (500 mV)

LMK1D1208I
Table 9-13. R1 Register Field Descriptions (continued)

OUT1_N.
OUT0_N.
9.6.1.3 R2 Register (Address = 2h) [reset = F1h]

The R2 register contains bits that enable/disable the input channels and control the banks.
7 Reserved R/W 1h Register bit can be written to 1.
Writing a different value than 1 will affect device functionality.
6 Reserved R/W 1h Register bit can be written to 1.
Writing a different value than 1 will affect device functionality.
5 BANK1_IN_SEL R/W 1h This bit sets the input channel for Bank 1.
0h = IN1_P/IN1_N
1h = IN0_P/IN0_N
4 BANK0_IN_SEL R/W 1h This bit sets the input channel for Bank 0.
0h = IN1_P/IN1_N
1h = IN0_P/IN0_N
3 BANK1_MUTE R/W 0h This bit sets the outputs in Bank 1 to logic low level.
0h = INx_P/INx_N
1h = Logic low
2 BANK0_MUTE R/W 0h This bit sets the outputs in Bank 0 to logic low level.
0h = INx_P/INx_N
1h = Logic low
1 IN1_EN R/W 0h This bit controls the input enable signal for input channel IN1_P/
IN1_N.
0h = Input Disabled (reduces power consumption)
1h = Input Enabled
0 IN0_EN R/W 1h This bit controls the input enable signal for input channel IN0_P/
IN0_N.
0h = Input Disabled (reduces power consumption)
1h = Input Enabled

LMK1D1208I

The R5 register contains the silicon revision code and the device identification code.
7:4 REV_ID R 2h These bits provide the silicon revision code.
3:0 DEV_ID R 0h These bits provide the device identification code.
9.6.1.5 R14 Register (Address = Eh) [reset = 0h]

The R14 register contains the bits that report the current state of the I2C address based on the IDX0 and IDX1
input pins.
7:0 IDX_RB R 0h These bits report the I2C address state.

LMK1D1208I
10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information

The LMK1D1208I is a low-additive jitter universal to LVDS fan-out buffer with two selectable inputs. The small
package, low output skew, and low additive jitter make for a flexible device in demanding applications.
10.2 Typical Application
1.8V/ 2.5V/ 3.3V
FPGA
IN0_P
156.25 MHz LVDS
100
from Backplane
IN0_N
50 50
CPU
100
156.25 MHz LVCMOS
Oscillator IN1_P
2.5V PHY
1 k 100
IN1_N
1 k
ASIC
SDA 100
SCL
IDX1
IDX0
Figure 10-1. Fan-Out Buffer for Line Card Application

LMK1D1208I
10.2.1 Design Requirements

The LMK1D1208I shown in Figure 10-1 is configured to select two inputs: a 156.25-MHz LVDS clock from the
backplane at IN0, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator at IN1. The LVDS clock is AC-coupled
and biased using the integrated reference voltage generator. A resistor divider is used to set the threshold
voltage correctly for the LVCMOS clock. 0.1-µF capacitors are used to reduce noise on both VAC_REF and IN1_N.
Either input signal can be then fanned out to desired devices via register control. The configuration example is
driving four LVDS receivers in a line card application with the following properties:
• The PHY device is capable of DC coupling with an LVDS driver such as the LMK1D1208I. This PHY device
features internal termination so no additional components are required for proper operation
• The ASIC LVDS receiver features internal termination and operates at the same common-mode voltage as
the LMK1D1208I. Again, no additional components are required.
• The FPGA requires external AC coupling, but has internal termination. 0.1-µF capacitors are placed to
provide AC coupling. Similarly, the CPU is internally terminated, and requires only external AC-coupling
capacitors.
• The unused outputs of the LMK1D1208I can be disabled by clearing the corresponding OUTx_EN register
through I2C. This results in a lower power consumption.
10.2.2 Detailed Design Procedure
See Input Termination for proper input terminations, dependent on single-ended or differential inputs.
See LVDS Output Termination for output termination schemes depending on the receiver application.
Unused outputs should be terminated differentially with a 100-Ω resistor or disabled through OUTx_EN register
control (see Table 9-7) for optimum performance. Outputs may be left unterminated, but will result in slight
degradation in performance (Output AC common-mode VOS ) in the outputs being used.
In this example, the PHY, ASIC, and FPGA or CPU require different schemes. Power-supply filtering and
bypassing is critical for low-noise applications.
See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in
Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043).

LMK1D1208I
10.2.3 Application Curves

The following graphs show the low additive noise of the LMK1D1208I. The low noise 156.25-MHz source with
24-fs RMS jitter shown in Figure 10-2 drives the LMK1D1208I, resulting in 46.4-fs RMS when integrated from 12
kHz to 20 MHz (Figure 10-3). The resultant additive jitter is a low 39.7-fs RMS for this configuration.
Reference signal is low-noise Rohde and Schwarz SMA100B
Figure 10-2. LMK1D1208I Reference Phase Noise, 156.25 MHz, 24-fs RMS (12 kHz to 20 MHz)
Figure 10-3. LMK1D1208I Output Phase Noise, 156.25 MHz, 46.4-fs RMS (12 kHz to 20 MHz)

LMK1D1208I
Figure 10-4 shows the low close-in phase noise of the LMK1D1208I device. The LMK1D1208I has excellent
flicker noise as a result of superior process technology and design. This enables their use for clock distribution in
radar systems, medical imaging systems etc which require ultra-low close-in phase noise clocks.
Figure 10-4. LMK1D1208I Output Phase Noise, 100 MHz, 1-kHz Offset: –147 dBc/Hz
10.3 Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against
the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the
device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must
be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends
adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package.
TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip
power supply that isolates the high-frequency switching noises generated by the clock driver. These beads
prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low DC
resistance, because it is imperative to provide adequate isolation between the board supply and the chip supply,
as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper
operation.
Figure 10-5 shows this recommended power-supply decoupling method.

LMK1D1208I
Board Chip
Ferrite Bead
Supply Supply
1 µF 10µF 0.1 µF (x3)
Figure 10-5. Power Supply Decoupling
10.4 Layout
10.4.1 Layout Guidelines
For reliability and performance reasons, the die temperature must be limited to a maximum of 135°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be
soldered down to ensure adequate heat conduction to of the package. Figure 10-6 and Figure 10-7 show the
LMK1D1208I top and bottom PCB layer examples.
10.4.2 Layout Example
Figure 10-6. Recommended PCB Layout, Top Layer

LMK1D1208I
Figure 10-7. Recommended PCB Layout Bottom Layer

LMK1D1208I
11 Device and Documentation Support

11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Power Consumption of LVPECL and LVDS Analog Design Journal
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application note
• Texas Instruments, Using Thermal Calculation Tools for Analog Components application note
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

LMK1D1208I
12.1 Package Option Addendum
Packaging Information
Orderable Package Lead/Ball MSL Peak Device
Status(1) Package Type Pins Package Qty Eco Plan(2) Op Temp (°C)
Device Drawing Finish(6) Temp(3) Marking(4) (5)
LMK1D1208IR ACTIVE VQFN RHA 40 2500 Green (RoHS& NIPDAU Level-2-260C-1 -40 to 85 LMK1D1208I
HAR no Sb/Br) YEAR
LMK1D1208IR ACTIVE VQFN RHA 40 250 Green (RoHS& NIPDAU Level-2-260C-1 -40 to 85 LMK1D1208I
HAT no Sb/Br) YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a
new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all
6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high
temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)
as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.

LMK1D1208I
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis
on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

LMK1D1208I
12.2 Tape and Reel Information

REEL DIMENSIONS TAPE DIMENSIONS
K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
Reel Reel
Package Package A0 B0 K0 P1 W Pin1
Device Pins SPQ Diameter Width W1
Type Drawing (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) (mm)
LMK1D1208IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 13.3 Q2
LMK1D1208IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 13.3 Q2

LMK1D1208I
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMK1D1208IRHAR VQFN RHA 40 2500 367.0 367.0 35.0
LMK1D1208IRHAT VQFN RHA 40 250 210.0 185.0 35.0

PACKAGE OPTION ADDENDUM
www.ti.com 10-Apr-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LMK1D1208IRHAR ACTIVE VQFN RHA 40 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LMK1D Samples
1208I
LMK1D1208IRHAT ACTIVE VQFN RHA 40 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LMK1D Samples
1208I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Apr-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK1D1208IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
LMK1D1208IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMK1D1208IRHAR VQFN RHA 40 2500 367.0 367.0 35.0
LMK1D1208IRHAT VQFN RHA 40 250 210.0 185.0 35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHA 40 VQFN - 1 mm max height
6 x 6, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040D SCALE 2.200
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6.1 B
A
5.9
PIN 1 INDEX AREA

0.5
0.3
6.1
5.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00 0.08 C
2X 4.5
2.9 0.1 (0.1) TYP
11 20 EXPOSED
36X 0.5 THERMAL PAD
10
21
2X 41 SYMM
4.5
1
30
SEE TERMINAL 0.3
40X
DETAIL 40 31 0.2
SYMM 0.1 C A B
PIN 1 ID 0.5
(OPTIONAL) 40X 0.05
0.3
4225822/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040D VQFN - 1 mm max height
( 2.9)
SYMM
40 31
40X (0.6)
1
30
40X (0.25)
(1.2)
TYP
41
SYMM
(5.8)
36X (0.5)
( 0.2) TYP
VIA
10 21
(R0.05)
TYP
11 20
(5.8)
LAND PATTERN EXAMPLE

SCALE:15X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK
METAL OPENING
SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4225822/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view.
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040D VQFN - 1 mm max height
(R0.05) TYP SYMM

40 31
40X (0.6)
1
30
4X ( 1.27)
40X (0.25)
(0.735) TYP
(0.735)
SYMM 41 TYP
(5.8)
36X (0.5)
METAL
TYP
10 21
11 20
(5.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:

76.46% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4225822/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

LMK1D1208I I C-Configurable, Low-Additive Jitter LVDS Buffer

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LMK1D1208I

SNAS828A – FEBRUARY 2022 – REVISED JUNE 2023

LMK1D1208I I2C-Configurable, Low-Additive Jitter LVDS Buffer

Changes from Revision * (February 2022) to Revision A (June 2023) Page

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Global output enable and swing 350 mV

Global output enable and swing 350 mV

Global output enable and swing 350 mV

Global output enable and swing 350 mV

Global output enable control 350 mV

Global output enable control 350 mV

Individual output enable control 350 mV

Individual output enable control 350 mV

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6 Pin Configuration and Functions

Table 6-1. Pin Functions

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Table 6-1. Pin Functions (continued)

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7.2 ESD Ratings

7.3 Recommended Operating Conditions

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7.4 Thermal Information

7.5 Electrical Characteristics

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Differential input voltage peak-to-peak VICM = 1 V (VDD = 1.8 V) 0.3 2.4

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fIN = 156.25 MHz with 50% duty-

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7.6 Typical Characteristics

Figure 7-1. LMK1D1208I Current Consumption vs. Frequency

Figure 7-2. LMK1D1208I VOD vs. Frequency

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8 Parameter Measurement Information

LVDS 100 W Oscilloscope

Figure 8-1. LVDS Output DC Configuration During Device Test

Figure 8-2. LVDS Output AC Configuration During Device Test

Figure 8-3. DC-Coupled LVCMOS Input During Device Test

20% VOUT,DIFF,PP (= 2 x VOD)

Figure 8-4. Output Voltage and Rise/Fall Time

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Figure 8-5. Output Skew and Part-to-Part Skew

Figure 8-6. Output Overshoot and Undershoot

Figure 8-7. Output AC Common Mode

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SDA OUTx_AMP_SEL Output Swing