UNIT -3

MEMORY ORGANIZATION

Memory Hierarchy

A memory unit is an essential component in any digital

computer since it is needed for storing programs and data.

Typically, a memory unit can be classified into two categories:

1. The memory unit that establishes direct communication

with the CPU is called Main Memory. The main memory
is often referred to as RAM (Random Access Memory).
2. The memory units that provide backup storage are
called Auxiliary Memory. For instance, magnetic disks
and magnetic tapes are the most commonly used auxiliary
memories.

Apart from the basic classifications of a memory unit, the

memory hierarchy consists all of the storage devices available in
a computer system ranging from the slow but high-capacity
auxiliary memory to relatively faster main memory.

The following image illustrates the components in a typical

memory hierarchy.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
Auxiliary Memory

Auxiliary memory is known as the lowest-cost, highest-capacity

and slowest-access storage in a computer system. Auxiliary
memory provides storage for programs and data that are kept for
long-term storage or when not in immediate use. The most
common examples of auxiliary memories are magnetic tapes
and magnetic disks.

A magnetic disk is a digital computer memory that uses a

magnetization process to write, rewrite and access data. For
example, hard drives, zip disks, and floppy disks.

Magnetic tape is a storage medium that allows for data archiving,

collection, and backup for different kinds of data.

Main Memory

The main memory in a computer system is often referred to

as Random Access Memory (RAM). This memory unit
communicates directly with the CPU and with auxiliary memory
devices through an I/O processor.

The programs that are not currently required in the main

memory are transferred into auxiliary memory to provide space
for currently used programs and data.

I/O Processor

The primary function of an I/O Processor is to manage the data

transfers between auxiliary memories and the main memory.

Cache Memory

The data or contents of the main memory that are used

frequently by CPU are stored in the cache memory so that the
processor can easily access that data in a shorter time. Whenever
the CPU requires accessing memory, it first checks the required
data into the cache memory. If the data is found in the cache

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
memory, it is read from the fast memory. Otherwise, the CPU
moves onto the main memory for the required data.

Main Memory

The main memory acts as the central storage unit in a computer

system. It is a relatively large and fast memory which is used to
store programs and data during the run time operations.

The primary technology used for the main memory is based on

semiconductor integrated circuits. The integrated circuits for the
main memory are classified into two major units.

1. RAM (Random Access Memory) integrated circuit chips

2. ROM (Read Only Memory) integrated circuit chips

RAM integrated circuit chips

The RAM integrated circuit chips are further classified into two
possible operating modes, static and dynamic.

The primary compositions of a static RAM are flip-flops that

store the binary information. The nature of the stored
information is volatile, i.e. it remains valid as long as power is
applied to the system. The static RAM is easy to use and takes
less time performing read and write operations as compared to
dynamic RAM.

The dynamic RAM exhibits the binary information in the form

of electric charges that are applied to capacitors. The capacitors
are integrated inside the chip by MOS transistors. The dynamic
RAM consumes less power and provides large storage capacity
in a single memory chip.

RAM chips are available in a variety of sizes and are used as per
the system requirement. The following block diagram
demonstrates the chip interconnection in a 128 * 8 RAM chip.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
 o A 128 * 8 RAM chip has a memory capacity of 128 words
of eight bits (one byte) per word. This requires a 7-bit
address and an 8-bit bidirectional data bus.
o The 8-bit bidirectional data bus allows the transfer of data
either from memory to CPU during a read operation or
from CPU to memory during a write operation.
o The read and write inputs specify the memory operation,
and the two chip select (CS) control inputs are for enabling
the chip only when the microprocessor selects it.
o The bidirectional data bus is constructed using three-state
buffers.
o The output generated by three-state buffers can be placed
in one of the three possible states which include a signal
equivalent to logic 1, a signal equal to logic 0, or a high-
impedance state.

Note: The logic 1 and 0 are standard digital signals whereas

the high-impedance state behaves like an open circuit,
which means that the output does not carry a signal and has
no logic significance.

The following function table specifies the operations of a 128 *

8 RAM chip.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
From the functional table, we can conclude that the unit is in
operation only when CS1 = 1 and CS2 = 0. The bar on top of the
second select variable indicates that this input is enabled when it
is equal to 0.

ROM integrated circuit

The primary component of the main memory is RAM integrated

circuit chips, but a portion of memory may be constructed with
ROM chips.

A ROM memory is used for keeping programs and data that are
permanently resident in the computer.

Apart from the permanent storage of data, the ROM portion of

main memory is needed for storing an initial program called
a bootstrap loader. The primary function of the bootstrap
loader program is to start the computer software operating when
power is turned on.

ROM chips are also available in a variety of sizes and are also
used as per the system requirement. The following block
diagram demonstrates the chip interconnection in a 512 * 8
ROM chip.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
 o A ROM chip has a similar organization as a RAM chip.
However, a ROM can only perform read operation; the
data bus can only operate in an output mode.
o The 9-bit address lines in the ROM chip specify any one of
the 512 bytes stored in it.
o The value for chip select 1 and chip select 2 must be 1 and
0 for the unit to operate. Otherwise, the data bus is said to
be in a high-impedance state.

Auxiliary Memory

An Auxiliary memory is known as the lowest-cost, highest-

capacity and slowest-access storage in a computer system. It is
where programs and data are kept for long-term storage or when
not in immediate use. The most common examples of auxiliary
memories are magnetic tapes and magnetic disks.

Magnetic Disks

A magnetic disk is a type of memory constructed using a

circular plate of metal or plastic coated with magnetized
materials. Usually, both sides of the disks are used to carry out
read/write operations. However, several disks may be stacked on
one spindle with read/write head available on each surface.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
The following image shows the structural representation for a
magnetic disk.

o The memory bits are stored in the magnetized surface in

spots along the concentric circles called tracks.
o The concentric circles (tracks) are commonly divided into
sections called sectors.

Magnetic Tape

Magnetic tape is a storage medium that allows data archiving,

collection, and backup for different kinds of data. The magnetic
tape is constructed using a plastic strip coated with a magnetic
recording medium.

The bits are recorded as magnetic spots on the tape along

several tracks. Usually, seven or nine bits are recorded
simultaneously to form a character together with a parity bit.

Magnetic tape units can be halted, started to move forward or in

reverse, or can be rewound. However, they cannot be started or
stopped fast enough between individual characters. For this
reason, information is recorded in blocks referred to as records.

Associative Memory

An associative memory can be considered as a memory unit

whose stored data can be identified for access by the content of
the data itself rather than by an address or memory location.

Associative memory is often referred to as Content

Addressable Memory (CAM).

When a write operation is performed on associative memory, no

address or memory location is given to the word. The memory

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
itself is capable of finding an empty unused location to store the
word.

On the other hand, when the word is to be read from an

associative memory, the content of the word, or part of the word,
is specified. The words which match the specified content are
located by the memory and are marked for reading.

The following diagram shows the block representation of an

Associative memory.

From the block diagram, we can say that an associative memory

consists of a memory array and logic for 'm' words with 'n' bits
per word.

The functional registers like the argument register A and key

register K each have n bits, one for each bit of a word. The
match register M consists of m bits, one for each memory word.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
The words which are kept in the memory are compared in
parallel with the content of the argument register.

The key register (K) provides a mask for choosing a particular

field or key in the argument word. If the key register contains a
binary value of all 1's, then the entire argument is compared
with each memory word. Otherwise, only those bits in the
argument that have 1's in their corresponding position of the key
register are compared. Thus, the key provides a mask for
identifying a piece of information which specifies how the
reference to memory is made.

The following diagram can represent the relation between the

memory array and the external registers in an associative
memory.

The cells present inside the memory array are marked by the
letter C with two subscripts. The first subscript gives the word
number and the second specifies the bit position in the word. For
instance, the cell Cij is the cell for bit j in word i.

Cache Memory
Prof. Nikita Ahuja
Department of Computer Sceince and Engineering
The data or contents of the main memory that are used
frequently by CPU are stored in the cache memory so that the
processor can easily access that data in a shorter time. Whenever
the CPU needs to access memory, it first checks the cache
memory. If the data is not found in cache memory, then the CPU
moves into the main memory.

Cache memory is placed between the CPU and the main

memory. The block diagram for a cache memory can be
represented as:

The cache is the fastest component in the memory hierarchy and

approaches the speed of CPU components.

Cache memory is organised as distinct set of blocks where each

set contains a small fixed number of blocks.

As shown in the above sets are represented by the rows. The

example contains N sets and each set contains four blocks.
Whenever an access is made to cache, the cache controller does
not search the entire cache in order to look for a match. Rather,
the controller maps the address to a particular set of the cache
and therefore searches only the set for a match.

If a required block is not found in that set, the block is not

present in the cache and cache controller does not search it
further. This kind of cache organisation is called set associative
because the cache is divided into distinct sets of blocks. As each
set contains four blocks the cache is said to be four way set
associative.

The basic operation of a cache memory is as follows:

o When the CPU needs to access memory, the cache is

examined. If the word is found in the cache, it is read from
the fast memory.
Prof. Nikita Ahuja
Department of Computer Sceince and Engineering
 o If the word addressed by the CPU is not found in the cache,
the main memory is accessed to read the word.
o A block of words one just accessed is then transferred
from main memory to cache memory. The block size may
vary from one word (the one just accessed) to about 16
words adjacent to the one just accessed.
o The performance of the cache memory is frequently
measured in terms of a quantity called hit ratio.
o When the CPU refers to memory and finds the word in
cache, it is said to produce a hit.
o If the word is not found in the cache, it is in main memory
and it counts as a miss.
o The ratio of the number of hits divided by the total CPU
references to memory (hits plus misses) is the hit ratio.

Levels of memory:

Level 1

It is a type of memory in which data is stored and accepted that

are immediately stored in CPU. Most commonly used register is
accumulator, Program counter, address register etc.

Level 2

It is the fastest memory which has faster access time where data
is temporarily stored for faster access.

Level 3

It is memory on which computer works currently. It is small in

size and once power is off data no longer stays in this memory.

Level 4

It is external memory which is not as fast as main memory but

data stays permanently in this memory.

Cache Mapping:
Prof. Nikita Ahuja
Department of Computer Sceince and Engineering
There are three different types of mapping used for the purpose
of cache memory which are as follows:

o Direct mapping,
o Associative mapping
o Set-Associative mapping

Direct Mapping -

In direct mapping, the cache consists of normal high-speed

random-access memory. Each location in the cache holds the
data, at a specific address in the cache. This address is given by
the lower significant bits of the main memory address. This
enables the block to be selected directly from the lower
significant bit of the memory address. The remaining higher
significant bits of the address are stored in the cache with the
data to complete the identification of the cached data.

As shown in the above figure, the address from processor is

divided into two field a tag and an index.

The tag consists of the higher significant bits of the address and
these bits are stored with the data in cache. The index consists of
the lower significant b of the address. Whenever the memory is
referenced, the following sequence of events occurs

1. The index is first used to access a word in the cache.

2. The tag stored in the accessed word is read.
3. This tag is then compared with the tag in the address.
4. If two tags are same this indicates cache hit and required
data is read from the cache word.
5. If the two tags are not same, this indicates a cache miss.
Then the reference is made to the main memory to find it.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
For a memory read operation, the word is then transferred into
the cache. It is possible to pass the information to the cache and
the process simultaneously.

In direct mapped cache, there can also be a line consisting of

more than one word as shown in the following figure

In such a case, the main memory address consists of a tag, an

index and a word within a line. All the words within a line in the
cache have the same stored tag

The index part in the address is used to access the cache and the
stored tag is compared with required tag address.

For a read operation, if the tags are same, the word within the
block is selected for transfer to the processor. If tags are not
same, the block containing the required word is first transferred
to the cache. In direct mapping, the corresponding blocks with
the same index in the main memory will map into the same
block in the cache, and hence only blocks with different indices
can be in the cache at the same time. It is important that all
words in the cache must have different indices. The tags may be
the same or different.

Set Associative Mapping -

In set associative mapping a cache is divided into a set of blocks.

The number of blocks in a set is known as associativity or set
size. Each block in each set has a stored tag. This tag together
with index completely identify the block.

Thus, set associative mapping allows a limited number of blocks,

with the same index and different tags.

An example of four way set associative cache having four

blocks in each set is shown in the following figure

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
In this type of cache, the following steps are used to access
the data from a cache:

1. The index of the address from the processor is used to

access the set.
2. Then the comparators are used to compare all tags of the
selected set with the incoming tag.
3. If a match is found, the corresponding location is accessed.
4. If no match is found, an access is made to the main
memory.

The tag address bits are always chosen to be the most significant
bits of the full address, the block address bits are the next
significant bits and the word/byte address bits are the least
significant bits. The number of comparators required in the set
associative cache is given by the number of blocks in a set. The
set can be selected quickly and all the blocks of the set can be
read out simultaneously with the tags before waiting for the tag
comparisons to be made. After a tag has been identified, the
corresponding block can be selected.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
Fully associative mapping

In fully associative type of cache memory, each location in

cache stores both memory address as well as data.

Whenever a data is requested, the incoming memory address a

simultaneously compared with all stored addresses using the
internal logic the associative memory.

If a match is found, the corresponding is read out. Otherwise,

the main memory is accessed if address is not found in cache.

This method is known as fully associative mapping approach

because cached data is related to the main memory by storing
both memory address and data in the cache. In all organisations,
data can be more than one word as shown in the following
figure.

A line constitutes four words, each word being 4 bytes. In such

case, the least significant part of the address selects the
particular byte, the next part selects the word, and the remaining
bits form the address. These address bits are compared to the

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
address in the cache. The whole line can be transferred to and
from the cache in one transaction if there are sufficient data
paths between the main memory and the cache. With only one
data word path, the words of the line have to be transferred in
separate transactions.

The main advantage of fully associative mapped cache is that it

provides greatest flexibility of holding combinations of blocks
in the cache and conflict for a given cache.

It suffers from certain disadvantages:

1. It is expensive method because of the high cost of

associative memory.
2. It requires a replacement algorithm in order to select a
block to be removed whenever cache miss occurs.
3. Such an algorithm must be implemented in hardware to
maintain a high speed of operation.

The fully associative mechanism is usually employed by

microprocessors with small internal cache.

A bit Aj in the argument register is compared with all the bits in

column j of the array provided that Kj = 1. This process is done
for all columns j = 1, 2, 3......, n.

If a match occurs between all the unmasked bits of the argument

and the bits in word i, the corresponding bit Mi in the match
register is set to 1. If one or more unmasked bits of the argument
and the word do not match, Mi is cleared to 0.

Cache Memory

The data or contents of the main memory that are used

frequently by CPU are stored in the cache memory so that the

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
processor can easily access that data in a shorter time. Whenever
the CPU needs to access memory, it first checks the cache
memory. If the data is not found in cache memory, then the CPU
moves into the main memory.

Cache memory is placed between the CPU and the main

memory. The block diagram for a cache memory can be
represented as:

The cache is the fastest component in the memory hierarchy and

approaches the speed of CPU components.

Cache memory is organised as distinct set of blocks where each

set contains a small fixed number of blocks.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
As shown in the above sets are represented by the rows. The
example contains N sets and each set contains four blocks.
Whenever an access is made to cache, the cache controller does
not search the entire cache in order to look for a match. Rather,
the controller maps the address to a particular set of the cache
and therefore searches only the set for a match.

If a required block is not found in that set, the block is not

present in the cache and cache controller does not search it
further. This kind of cache organisation is called set associative
because the cache is divided into distinct sets of blocks. As each
set contains four blocks the cache is said to be four way set
associative.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
The basic operation of a cache memory is as follows:

o When the CPU needs to access memory, the cache is

examined. If the word is found in the cache, it is read from
the fast memory.
o If the word addressed by the CPU is not found in the cache,
the main memory is accessed to read the word.
o A block of words one just accessed is then transferred
from main memory to cache memory. The block size may
vary from one word (the one just accessed) to about 16
words adjacent to the one just accessed.
o The performance of the cache memory is frequently
measured in terms of a quantity called hit ratio.
o When the CPU refers to memory and finds the word in
cache, it is said to produce a hit.
o If the word is not found in the cache, it is in main memory
and it counts as a miss.
o The ratio of the number of hits divided by the total CPU
references to memory (hits plus misses) is the hit ratio.

Levels of memory:

Level 1

It is a type of memory in which data is stored and accepted that

are immediately stored in CPU. Most commonly used register is
accumulator, Program counter, address register etc.

Level 2

It is the fastest memory which has faster access time where data
is temporarily stored for faster access.

Level 3

It is memory on which computer works currently. It is small in

size and once power is off data no longer stays in this memory.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
Level 4

It is external memory which is not as fast as main memory but

data stays permanently in this memory.

Cache Mapping:

There are three different types of mapping used for the purpose
of cache memory which are as follows:

o Direct mapping,
o Associative mapping
o Set-Associative mapping

Direct Mapping -

In direct mapping, the cache consists of normal high-speed

random-access memory. Each location in the cache holds the
data, at a specific address in the cache. This address is given by
the lower significant bits of the main memory address. This
enables the block to be selected directly from the lower
significant bit of the memory address. The remaining higher
significant bits of the address are stored in the cache with the
data to complete the identification of the cached data.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
As shown in the above figure, the address from processor is
divided into two field a tag and an index.

The tag consists of the higher significant bits of the address and
these bits are stored with the data in cache. The index consists of
the lower significant b of the address. Whenever the memory is
referenced, the following sequence of events occurs

1. The index is first used to access a word in the cache.

2. The tag stored in the accessed word is read.
3. This tag is then compared with the tag in the address.
4. If two tags are same this indicates cache hit and required
data is read from the cache word.
5. If the two tags are not same, this indicates a cache miss.
Then the reference is made to the main memory to find it.

For a memory read operation, the word is then transferred into

the cache. It is possible to pass the information to the cache and
the process simultaneously.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
In direct mapped cache, there can also be a line consisting of
more than one word as shown in the following figure

In such a case, the main memory address consists of a tag, an

index and a word within a line. All the words within a line in the
cache have the same stored tag

The index part in the address is used to access the cache and the
stored tag is compared with required tag address.

For a read operation, if the tags are same, the word within the
block is selected for transfer to the processor. If tags are not
same, the block containing the required word is first transferred
to the cache. In direct mapping, the corresponding blocks with
the same index in the main memory will map into the same
block in the cache, and hence only blocks with different indices
can be in the cache at the same time. It is important that all
words in the cache must have different indices. The tags may be
the same or different.

Set Associative Mapping -

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
In set associative mapping a cache is divided into a set of blocks.
The number of blocks in a set is known as associativity or set
size. Each block in each set has a stored tag. This tag together
with index completely identify the block.

Thus, set associative mapping allows a limited number of blocks,

with the same index and different tags.

An example of four way set associative cache having four

blocks in each set is shown in the following figure

In this type of cache, the following steps are used to access

the data from a cache:

1. The index of the address from the processor is used to

access the set.
2. Then the comparators are used to compare all tags of the
selected set with the incoming tag.
3. If a match is found, the corresponding location is accessed.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
 4. If no match is found, an access is made to the main
memory.

The tag address bits are always chosen to be the most significant
bits of the full address, the block address bits are the next
significant bits and the word/byte address bits are the least
significant bits. The number of comparators required in the set
associative cache is given by the number of blocks in a set. The
set can be selected quickly and all the blocks of the set can be
read out simultaneously with the tags before waiting for the tag
comparisons to be made. After a tag has been identified, the
corresponding block can be selected.

Fully associative mapping

In fully associative type of cache memory, each location in

cache stores both memory address as well as data.

Whenever a data is requested, the incoming memory address a

simultaneously compared with all stored addresses using the
internal logic the associative memory.

If a match is found, the corresponding is read out. Otherwise,

the main memory is accessed if address is not found in cache.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
This method is known as fully associative mapping approach
because cached data is related to the main memory by storing
both memory address and data in the cache. In all organisations,
data can be more than one word as shown in the following
figure.

A line constitutes four words, each word being 4 bytes. In such

case, the least significant part of the address selects the
particular byte, the next part selects the word, and the remaining
bits form the address. These address bits are compared to the
address in the cache. The whole line can be transferred to and
from the cache in one transaction if there are sufficient data
paths between the main memory and the cache. With only one
data word path, the words of the line have to be transferred in
separate transactions.

The main advantage of fully associative mapped cache is that it

provides greatest flexibility of holding combinations of blocks
in the cache and conflict for a given cache.
Prof. Nikita Ahuja
Department of Computer Sceince and Engineering
It suffers from certain disadvantages:

1. It is expensive method because of the high cost of

associative memory.
2. It requires a replacement algorithm in order to select a
block to be removed whenever cache miss occurs.
3. Such an algorithm must be implemented in hardware to
maintain a high speed of operation.

The fully associative mechanism is usually employed by

microprocessors with small internal cache.

Memory interleaving

Abstraction is one of the most important aspects of computing.

It is a widely implemented Practice in the Computational field.
Memory Interleaving is less or More an Abstraction technique.
Though it’s a bit different from Abstraction. It is a Technique
that divides memory into a number of modules such that
Successive words in the address space are placed in the
Different modules.
Consecutive Word in a Module:

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
Figure-1: Consecutive Word in a Module
Let us assume 16 Data’s to be Transferred to the Four Module.
Where Module 00 be Module 1, Module 01 be Module 2,
Module 10 be Module 3 & Module 11 be Module 4. Also, 10,
20, 30….130 are the data to be transferred.
From the figure above in Module 1, 10 [Data] is transferred
then 20, 30 & finally, 40 which are the Data. That means the
data are added consecutively in the Module till its max
capacity.
Most significant bit (MSB) provides the Address of the Module
& the least significant bit (LSB) provides the address of the
data in the module.
For Example, to get 90 (Data) 1000 will be provided by the
processor. This 10 will indicate that the data is in module 10
(module 3) & 00 is the address of 90 in Module 10 (module 3).

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
So,

Module 1 Contains Data : 10, 20, 30, 40

Module 2 Contains Data : 50, 60, 70, 80
Module 3 Contains Data : 90, 100, 110, 120
Module 4 Contains Data : 130, 140, 150, 160
Consecutive Word in Consecutive Module:

Figure-2: Consecutive Word in Consecutive Module

Now again we assume 16 Data’s to be transferred to the Four
Module. But Now the consecutive Data are added in
Consecutive Module. That is, 10 [Data] is added in Module 1,
20 [Data] in Module 2 and So on.
Least Significant Bit (LSB) provides the Address of the
Module & Most significant bit (MSB) provides the address of
the data in the module.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
For Example, to get 90 (Data) 1000 will be provided by the
processor. This 00 will indicate that the data is in module 00
(module 1) & 10 is the address of 90 in Module 00 (module 1).
That is,

Module 1 Contains Data : 10, 50, 90, 130

Module 2 Contains Data : 20, 60, 100, 140
Module 3 Contains Data : 30, 70, 110, 150
Module 4 Contains Data : 40, 80, 120, 160
Why do we use Memory Interleaving? [Advantages]:
Whenever Processor requests Data from the main memory. A
block (chunk) of Data is Transferred to the cache and then to
Processor. So whenever a cache miss occurs the Data is to be
fetched from the main memory. But main memory is relatively
slower than the cache. So to improve the access time of the
main memory interleaving is used.
We can access all four Modules at the same time thus
achieving Parallelism. From Figure 2 the data can be acquired
from the Module using the Higher bits. This method Uses
memory effectively.

What is virtual memory?

Virtual memory is a memory management technique where
secondary memory can be used as if it were a part of the main
memory. Virtual memory is a common technique used in a
computer's operating system (OS).

Virtual memory uses both hardware and software to enable a

computer to compensate for physical memory shortages,
temporarily transferring data from random access memory
(RAM) to disk storage. Mapping chunks of memory to disk files
enables a computer to treat secondary memory as though it were
main memory.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
Today, most personal computers (PCs) come with at least 8 GB
(gigabytes) of RAM. But, sometimes, this is not enough to run
several programs at one time. This is where virtual memory
comes in. Virtual memory frees up RAM by swapping data that
has not been used recently over to a storage device, such as a
hard drive or solid-state drive (SSD).

Virtual memory is important for improving system performance,

multitasking and using large programs. However, users should
not overly rely on virtual memory, since it is considerably
slower than RAM. If the OS has to swap data between virtual
memory and RAM too often, the computer will begin to slow
down -- this is called thrashing.

Virtual memory was developed at a time when physical memory

-- also referenced as RAM -- was expensive. Computers have a
finite amount of RAM, so memory will eventually run out when
multiple programs run at the same time. A system using virtual
memory uses a section of the hard drive to emulate RAM. With
virtual memory, a system can load larger or multiple programs
running at the same time, enabling each one to operate as if it
has more space, without having to purchase more RAM.

How virtual memory works

Virtual memory uses both hardware and software to operate.
When an application is in use, data from that program is stored
in a physical address using RAM. A memory management unit
(MMU) maps the address to RAM and automatically translates
addresses. The MMU can, for example, map a logical address
space to a corresponding physical address.

If, at any point, the RAM space is needed for something more
urgent, data can be swapped out of RAM and into virtual
memory. The computer's memory manager is in charge of
keeping track of the shifts between physical and virtual memory.
If that data is needed again, the computer's MMU will use
a context switch to resume execution.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
While copying virtual memory into physical memory, the OS
divides memory with a fixed number of addresses into either
pagefiles or swap files. Each page is stored on a disk, and when
the page is needed, the OS copies it from the disk to main
memory and translates the virtual addresses into real addresses.

However, the process of swapping virtual memory to physical is

rather slow. This means using virtual memory generally causes a
noticeable reduction in performance. Because of swapping,
computers with more RAM are considered to have better
performance.

Types of virtual memory

A computer's MMU manages virtual memory operations. In
most computers, the MMU hardware is integrated into the
central processing unit (CPU). The CPU also generates the
virtual address space. In general, virtual memory is
either paged or segmented.

Paging divides memory into sections or paging files. When a

computer uses up its available RAM, pages not in use are
transferred to the hard drive using a swap file. A swap file is a
space set aside on the hard drive to be used as the virtual
memory extension for the computer's RAM. When the swap file
is needed, it is sent back to RAM using a process called page
swapping. This system ensures the computer's OS and
applications do not run out of real memory. The maximum size
of the page file can be 1 ½ to four times the physical memory of
the computer.

The virtual memory paging process uses page tables, which

translate the virtual addresses that the OS and applications use
into the physical addresses that the MMU uses. Entries in the
page table indicate whether the page is in RAM. If the OS or a
program does not find what it needs in RAM, then the MMU
responds to the missing memory reference with a page fault
exception to get the OS to move the page back to memory when

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
it is needed. Once the page is in RAM, its virtual address
appears in the page table.

Segmentation is also used to manage virtual memory. This

approach divides virtual memory into segments of different
lengths. Segments not in use in memory can be moved to virtual
memory space on the hard drive. Segmented information or
processes are tracked in a segment table, which shows if a
segment is present in memory, whether it has been modified and
what its physical address is. In addition, file systems in
segmentation are only made up of segments that are mapped
into a process's potential address space.

Segmentation and paging differ as a memory model in terms of

how memory is divided; however, the processes can also be
combined. In this case, memory gets divided into frames or
pages. The segments take up multiple pages, and the virtual
address includes both the segment number and the page number.

Other page replacement methods include first-in-first-out

(FIFO), optimal algorithm and least recently used (LRU) page
replacement. The FIFO method has memory select the
replacement for a page that has been in the virtual address for
the longest time. The optimal algorithm method selects page
replacements based on which page is unlikely to be replaced
after the longest amount of time; although difficult to implement,
this leads to less page faults. The LRU page replacement
method replaces the page that has not been used for the longest
time in the main memory.

How to manage virtual memory

Managing virtual memory within an OS can be straightforward,
as there are default settings that determine the amount of hard
drive space to allocate for virtual memory. Those settings will
work for most applications and processes, but there may be
times when it is necessary to manually reset the amount of hard
drive space allocated to virtual memory -- for example, with

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
applications that depend on fast response times or when the
computer has multiple hard disk drives (HDDs).

When manually resetting virtual memory, the minimum and

maximum amount of hard drive space to be used for virtual
memory must be specified. Allocating too little HDD space for
virtual memory can result in a computer running out of RAM. If
a system continually needs more virtual memory space, it may
be wise to consider adding RAM. Common OSes may generally
recommend users not increase virtual memory beyond 1 ½ times
the amount of RAM.

Managing virtual memory differs by OS. For this reason, IT

professionals should understand the basics when it comes to
managing physical memory, virtual memory and virtual
addresses.

RAM cells in SSDs also have a limited lifespan. RAM cells

have a limited number of writes, so using them for virtual
memory often reduces the lifespan of the drive.

What are the benefits of using virtual memory?

The advantages to using virtual memory include:

 It can handle twice as many addresses as main memory.

 It enables more applications to be used at once.
 It frees applications from managing shared memory and
saves users from having to add memory modules when RAM
space runs out.
 It has increased speed when only a segment of a program
is needed for execution.
 It has increased security because of memory isolation.
 It enables multiple larger applications to run
simultaneously.
 Allocating memory is relatively inexpensive.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
 It does not need external fragmentation.
 CPU use is effective for managing logical partition
workloads.
 Data can be moved automatically.
 Pages in the original process can be shared during
a fork system call operation that creates a copy of itself.

In addition to these benefits, in a virtualized computing

environment, administrators can use virtual memory
management techniques to allocate additional memory to a
virtual machine (VM) that has run out of resources.
Such virtualization management tactics can improve VM
performance and management flexibility.

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering
This image shows an example of how physical memory is
separated by a virtual memory manager.
What are the limitations of using virtual memory?
Although the use of virtual memory has its benefits, it also
comes with some tradeoffs worth considering, such as:

 Applications run slower if they are running from virtual

memory.
 Data must be mapped between virtual and physical
memory, which requires extra hardware support for address
translations, slowing down a computer further.
 The size of virtual storage is limited by the amount
of secondary storage, as well as the addressing scheme with
the computer system.
 Thrashing can occur if there is not enough RAM, which
will make the computer perform slower.
 It may take time to switch between applications using
virtual memory.
 It lessens the amount of available hard drive space.
Virtual memory (virtual RAM) vs. physical memory (RAM)
When talking about the differences between virtual and physical
memory, the biggest distinction commonly made is to speed.
RAM is considerably faster than virtual memory. RAM,
however, tends to be more expensive.

When a computer requires storage, RAM is the first used.

Virtual n actively add RAM to a computer by buying and
installing more RAM chips. This is useful if they are
experiencing slowdowns due to memory swaps happening too
often. The amount of RAM depends on what is installed on a
computer. Virtual memory, on the other hand, is limited by the
Prof. Nikita Ahuja
Department of Computer Sceince and Engineering
size of the computer's hard drive. Virtual memory settings can
often be controlled through the OS.

In addition, RAM uses swapping techniques, while virtual

memory uses paging. While physical memory is limited to the
size of the RAM chip, virtual memory is limited by the size of
the hard disk. RAM also has direct access to the CPU, while
virtual RAM does not.

The history of virtual memory

Before virtual memory was developed, computers had RAM and
secondary memory. Early computers used magnetic core
memory for main memory and magnetic drums for their
secondary memory. Computer memory was expensive and,
usually, in short supply back in the 1940s and 1950s. As
computer programs grew in size and complexity, developers had
to worry that their programs would use up all of a computer's
main memory and run out of memory.

In those early days, programmers used a process called

overlaying to run programs that were larger than available
memory. Parts of a program that were not continually in use
were set up as overlays that, when needed, would overwrite the
existing overlay in memory. It required extensive programming
to make overlaying work, and that was a key impetus for the
development of automated virtual memory.

German physicist Fritz-Rudolf Güntsch has been credited with

developing the concept of virtual memory in 1956 -- though this
point has been contested. Güntsch did, however, end up
describing a form of cache memory.

The first apparent real instance of a virtual memory system

came from the University of Manchester in Manchester,
England, in its attempt to develop a one-level storage system for
the Atlas computer. The system used paging to map virtual
addresses to a programmer onto the primary memory. Atlas was
developed in 1959 and later commissioned in 1962.
Prof. Nikita Ahuja
Department of Computer Sceince and Engineering
In 1961, the first commercial computer with virtual memory was
released by the Burroughs Corp. This version of virtual memory
used segmentation, as opposed to paging.

In 1969, IBM researchers demonstrated that virtual memory

overlay systems worked better than the earlier manual systems.
Up until this point, there was still a debate over this.
Mainframes and minicomputers in the 1970s generally used
virtual memory. Virtual memory technology was not included in
early PCs because developers thought running out of memory
would not be a problem in those machines. That assumption
proved incorrect. Intel introduced virtual memory in the
protected mode of the 80286 processor in 1982, and paging
support when the 80386 came out in 1985.

***********************************************

Prof. Nikita Ahuja

Department of Computer Sceince and Engineering