Quectel EG25-G Hardware Design V1.4

EG25-G
Hardware Design
LTE Standard Module Series
Version: 1.4
Date: 2020-09-21
Status: Released
www.quectel.com
EG25-G Hardware Design
Our aim is to provide customers with timely and comprehensive service. For any assistance,
please contact our company headquarters:
Quectel Wireless Solutions Co., Ltd.

Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai
200233, China
Tel: +86 21 5108 6236
Email: [email protected]
Or our local office. For more information, please visit:

http://www.quectel.com/support/sales.htm.
For technical support, or to report documentation errors, please visit:

http://www.quectel.com/support/technical.htm
Or email to [email protected].
General Notes
Quectel offers the information as a service to its customers. The information provided is based upon
customers’ requirements. Quectel makes every effort to ensure the quality of the information it makes
available. Quectel does not make any warranty as to the information contained herein, and does not
accept any liability for any injury, loss or damage of any kind incurred by use of or reliance upon the
information. All information supplied herein is subject to change without prior notice.
Disclaimer
While Quectel has made efforts to ensure that the functions and features under development are free
from errors, it is possible that these functions and features could contain errors, inaccuracies and
omissions. Unless otherwise provided by valid agreement, Quectel makes no warranties of any kind,
implied or express, with respect to the use of features and functions under development. To the maximum
extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with
the use of the functions and features under development, regardless of whether such loss or damage
may have been foreseeable.
Duty of Confidentiality
The Receiving Party shall keep confidential all documentation and information provided by Quectel,
except when the specific permission has been granted by Quectel. The Receiving Party shall not access
or use Quectel’s documentation and information for any purpose except as expressly provided herein.
Furthermore, the Receiving Party shall not disclose any of the Quectel's documentation and information
to any third party without the prior written consent by Quectel. For any noncompliance to the above
requirements, unauthorized use, or other illegal or malicious use of the documentation and information,
Quectel will reserve the right to take legal action.
EG25-G_Hardware_Design 1 / 104
Copyright
The information contained here is proprietary technical information of Quectel Wireless Solutions Co., Ltd.
Transmitting, reproducing, disseminating and editing this document as well as using the content without
permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in
the event of a patent grant or registration of a utility model or design.
Copyright © Quectel Wireless Solutions Co., Ltd. 2020. All rights reserved.
About the Document
Revision History
Version Date Author Description
Lorry XU/
1.0 2018-12-12 Initial
Harry HUANG
1. Deleted notes of EG25-G’s Telematics and Data-only
versions because Telematics version is default.
2. Updated supported protocols and USB serial driver
(Table 2)
3. Updated DC characteristics of PWRKEY pin (Table 4)
4. Updated timing of turning on module (Figure 12)
5. Updated reference circuit with translator chip of UART
interfaces (Figure 20)
6. Added timing sequence for entering emergency
download mode (Chapter 3.20)
7. Updated GNSS performance (Table 25)
Lorry XU/
1.1 2019-07-05 8. Updated module operating frequencies (Table 27)
Ethan SHAN
9. Updated GNSS frequency (Table 29)
10. Updated reference circuit of GNSS antenna (Figure
38)
11. Updated conducted RF receiving sensitivity of
LTE-TDD B41 (Table 37)
12. Updated module bottom dimensions (Figure 45)
13. Updated the recommended stencil thickness from
0.15mm~0.18mm to 0.13mm~0.15mm (Chapter 8.2)
14. Added recommended compatible footprint (Chapter
7.3)
15. Added tape and reel directions (Figure 51)
1.2 2019-07-25 Lorry XU Updated recommended footprint (Chapter 7.2)
1.3 2020-04-10 Ward WANG/ 1. Updated the AT command used for disabling receive
Ethan SHAN diversity (Chapter 5.3.1).

2. Updated current consumption and GNSS current
consumption (Table 34 and 35).
3. Updated notes (Chapter 6.5).
4. Added the note about the standard that the package
warpage level of the module conforms to (Chapter
7.1).
5. Updated top view of the module (Figure 48).
6. Updated module storage information (Chapter 8.1).
7. Updated module manufacturing and soldering
information (Chapter 8.2).
1. Updated the description of module form factor (Table
2, Chapter 2.1 and 7.3).
2. Updated the Wi-Fi&BT modules used for the wireless
connectivity of EG25-G module as FC20 series and
FC21 (Table 4, Chapter 3.2 and 3.14).
3. Updated the AT command for the operation of
ANT_MAIN and ANT_DIV (Chapter 5.1.3).
Ethan SHAN/ 4. Updated the picture of module mechanical dimensions
1.4 2020-09-21
Fanny CHEN (Chapter 7.1).
5. Updated the recommended compatible footprint and
the note 3 about the stencil selection when using LCC
form factor (Chapter 7.3).
6. Updated the cooling down slope of reflow soldering
thermal profile (Chapter 8.2).
7. Updated the module storage information (Chapter
8.1).
Contents
About the Document ................................................................................................................................... 3

Contents ....................................................................................................................................................... 5
Table Index ................................................................................................................................................... 8
Figure Index ............................................................................................................................................... 10
1 Introduction ........................................................................................................................................ 12
1.1. Safety Information.................................................................................................................... 13
2 Product Concept ................................................................................................................................ 14

2.1. General Description ................................................................................................................. 14
2.2. Key Features ........................................................................................................................... 15
2.3. Functional Diagram ................................................................................................................. 18
2.4. Evaluation Board ..................................................................................................................... 18
3 Application Interfaces ....................................................................................................................... 19

3.2. Pin Assignment ........................................................................................................................ 20
3.3. Pin Description......................................................................................................................... 21
3.4. Operating Modes ..................................................................................................................... 33
3.5. Power Saving........................................................................................................................... 33
3.5.1. Sleep Mode .................................................................................................................... 33
3.5.1.1. UART Application ................................................................................................. 34
3.5.1.2. USB Application with USB Remote Wakeup Function ........................................ 34
3.5.1.3. USB Application with USB Suspend/Resume and RI Function .......................... 35
3.5.1.4. USB Application without USB Suspend Function ................................................ 36
3.5.2. Airplane Mode ................................................................................................................ 36
3.6. Power Supply........................................................................................................................... 37
3.6.1. Power Supply Pins ......................................................................................................... 37
3.6.2. Decrease Voltage Drop .................................................................................................. 38
3.6.3. Reference Design for Power Supply .............................................................................. 39
3.6.4. Monitor the Power Supply .............................................................................................. 39
3.7. Power-on/off Scenarios ........................................................................................................... 39
3.7.1. Turn on Module Using the PWRKEY ............................................................................. 39
3.7.2. Turn off Module .............................................................................................................. 41
3.7.2.1. Turn off Module Using the PWRKEY Pin............................................................. 42
3.7.2.2. Turn off Module Using AT Command ................................................................... 42
3.8. Reset Module........................................................................................................................... 42
3.9. (U)SIM Interface ...................................................................................................................... 44
3.10. USB Interface .......................................................................................................................... 46
3.11. UART Interfaces ...................................................................................................................... 48
3.12. PCM and I2C Interfaces .......................................................................................................... 50
3.13. SD Card Interface .................................................................................................................... 53
3.14. Wireless Connectivity Interfaces ............................................................................................. 54
3.14.1. WLAN Interface .............................................................................................................. 57

3.14.2. BT Interface* .................................................................................................................. 57
3.15. ADC Interfaces ........................................................................................................................ 57
3.16. SGMII Interface........................................................................................................................ 58
3.17. Network Status Indication ........................................................................................................ 60
3.18. STATUS ................................................................................................................................... 62
3.19. Behaviors of RI ........................................................................................................................ 62
3.20. USB_BOOT Interface .............................................................................................................. 63
4 GNSS Receiver ................................................................................................................................... 65

4.2. GNSS Performance ................................................................................................................. 65
4.3. Layout Guidelines .................................................................................................................... 66
5 Antenna Interfaces............................................................................................................................. 67
5.1. Main/Rx-diversity Antenna Interfaces ...................................................................................... 67
5.1.1. Pin Definition .................................................................................................................. 67
5.1.2. Operating Frequency ..................................................................................................... 67
5.1.3. Reference Design of RF Antenna Interface ................................................................... 69
5.2. GNSS Antenna Interface ......................................................................................................... 69
5.3. Reference Design of RF Layout .............................................................................................. 71
5.4. Antenna Installation ................................................................................................................. 72
5.4.1. Antenna Requirement .................................................................................................... 72
5.4.2. Recommended RF Connector for Antenna Installation ................................................. 73
6 Electrical, Reliability and Radio Characteristics ............................................................................ 76

6.1. Absolute Maximum Ratings ..................................................................................................... 76
6.2. Power Supply Ratings ............................................................................................................. 77
6.3. Operating and Storage Temperatures ..................................................................................... 77
6.4. Current Consumption .............................................................................................................. 78
6.5. RF Output Power ..................................................................................................................... 83
6.6. RF Receiving Sensitivity .......................................................................................................... 84
6.7. Electrostatic Discharge ............................................................................................................ 85
6.8. Thermal Consideration ............................................................................................................ 86
7 Mechanical Dimensions .................................................................................................................... 88

7.1. Mechanical Dimensions of the Module.................................................................................... 88
7.2. Recommended Footprint ......................................................................................................... 90
7.3. Recommended Compatible Footprint...................................................................................... 91
7.4. Design Effect Drawings of the Module .................................................................................... 92
8 Storage, Manufacturing and Packaging .......................................................................................... 93

8.1. Storage..................................................................................................................................... 93
8.2. Manufacturing and Soldering .................................................................................................. 94
8.3. Packaging ................................................................................................................................ 95
9 Appendix A References..................................................................................................................... 97
10 Appendix B GPRS Coding Schemes ............................................................................................. 101

11 Appendix C GPRS Multi-slot Classes ............................................................................................ 102
12 Appendix D EDGE Modulation and Coding Schemes ................................................................. 104
Table Index
Table 1: Supported Frequency Bands and GNSS Function of EG25-G Module ....................................... 14
Table 2: Key Features of EG25-G Module ................................................................................................. 15
Table 3: I/O Parameters Definition ............................................................................................................. 21
Table 4: Pin Description ............................................................................................................................. 21
Table 5: Overview of Operating Modes ...................................................................................................... 33
Table 6: Pin Definition of VBAT and GND Pins .......................................................................................... 37
Table 7: Pin Definition of PWRKEY............................................................................................................ 40
Table 8: Pin Definition of RESET_N........................................................................................................... 43
Table 9: Pin Definition of (U)SIM Interface ................................................................................................. 44
Table 10: Pin Definition of USB Interface ................................................................................................... 46
Table 11: Pin Definition of Main UART Interface ........................................................................................ 48
Table 12: Pin Definition of Debug UART Interface..................................................................................... 48
Table 13: Logic Levels of Digital I/O ........................................................................................................... 49
Table 14: Pin Definition of PCM and I2C Interfaces .................................................................................. 51
Table 15: Pin Definition of SD Card Interface ............................................................................................ 53
Table 16: Pin Definition of Wireless Connectivity Interfaces...................................................................... 54
Table 17: Pin Definition of ADC Interfaces ................................................................................................. 58
Table 18: Characteristic of ADC ................................................................................................................. 58
Table 19: Pin Definition of SGMII Interface ................................................................................................ 59
Table 20: Pin Definition of Network Connection Status/Activity Indication ................................................ 61
Table 21: Working State of Network Connection Status/Activity Indication ............................................... 61
Table 22: Pin Definition of STATUS............................................................................................................ 62
Table 23: Behaviors of RI ........................................................................................................................... 63
Table 24: Pin Definition of USB_BOOT Interface ...................................................................................... 63
Table 25: GNSS Performance .................................................................................................................... 65
Table 26: Pin Definition of RF Antennas .................................................................................................... 67
Table 27: Module Operating Frequencies .................................................................................................. 67
Table 28: Pin Definition of GNSS Antenna Interface ................................................................................. 69
Table 29: GNSS Frequency ....................................................................................................................... 70
Table 30: Antenna Requirements ............................................................................................................... 72
Table 31: Absolute Maximum Ratings ........................................................................................................ 76
Table 32: Power Supply Ratings ................................................................................................................ 77
Table 33: Operating and Storage Temperatures ........................................................................................ 77
Table 34: EG25-G Current Consumption ................................................................................................... 78
Table 35: GNSS Current Consumption of EG25-G Module....................................................................... 82
Table 36: RF Output Power ........................................................................................................................ 83
Table 37: EG25-G Conducted RF Receiving Sensitivity ............................................................................ 84
Table 38: Electrostatic Discharge Characteristics (25 ºC, 45% Relative Humidity) .................................. 85
Table 39: Recommended Thermal Profile Parameters .............................................................................. 95
Table 40: Related Documents .................................................................................................................... 97
Table 41: Terms and Abbreviations ............................................................................................................ 97
Table 42: Description of Different Coding Schemes ................................................................................ 101

Table 43: GPRS Multi-slot Classes .......................................................................................................... 102
Table 44: EDGE Modulation and Coding Schemes ................................................................................. 104
Figure Index
Figure 1: Functional Diagram ..................................................................................................................... 18

Figure 2: Pin Assignment (Top View) ......................................................................................................... 20
Figure 3: Sleep Mode Application via UART .............................................................................................. 34
Figure 4: Sleep Mode Application with USB Remote Wakeup .................................................................. 35
Figure 5: Sleep Mode Application with RI .................................................................................................. 35
Figure 6: Sleep Mode Application without Suspend Function ................................................................... 36
Figure 7: Power Supply Limits during Burst Transmission ........................................................................ 38
Figure 8: Star Structure of the Power Supply............................................................................................. 38
Figure 9: Reference Circuit of Power Supply............................................................................................. 39
Figure 10: Turn on the Module by Using Driving Circuit ............................................................................ 40
Figure 11: Turn on the Module by Using Keystroke ................................................................................... 40
Figure 12: Timing of Turning on Module .................................................................................................... 41
Figure 13: Timing of Turning off Module .................................................................................................... 42
Figure 14: Reference Circuit of RESET_N by Using Driving Circuit ......................................................... 43
Figure 15: Reference Circuit of RESET_N by Using Button...................................................................... 43
Figure 16: Timing of Resetting Module ...................................................................................................... 44
Figure 17: Reference Circuit of (U)SIM Interface with an 8-pin (U)SIM Card Connector ......................... 45
Figure 18: Reference Circuit of (U)SIM Interface with a 6-pin (U)SIM Card Connector ........................... 45
Figure 19: Reference Circuit of USB Interface .......................................................................................... 47
Figure 20: Reference Circuit with Translator Chip ..................................................................................... 49
Figure 21: Reference Circuit with Transistor Circuit .................................................................................. 50
Figure 22: Primary Mode Timing ................................................................................................................ 51
Figure 23: Auxiliary Mode Timing ............................................................................................................... 51
Figure 24: Reference Circuit of PCM and I2C Application with Audio Codec ........................................... 52
Figure 25: Reference Circuit of SD Card Interface .................................................................................... 53
Figure 26: Reference Circuit of Wireless Connectivity Interfaces with FC20 Series or FC21 Module ..... 56
Figure 27: Simplified Block Diagram for Ethernet Application ................................................................... 59
Figure 28: Reference Circuit of SGMII Interface with PHY AR8033 Application ....................................... 60
Figure 29: Reference Circuit of the Network Indication ............................................................................. 61
Figure 30: Reference Circuits of STATUS ................................................................................................. 62
Figure 31: Reference Circuit of USB_BOOT Interface .............................................................................. 64
Figure 32: Timing Sequence for Entering Emergency Download Mode.................................................... 64
Figure 33: Reference Circuit of RF Antenna Interface ............................................................................... 69
Figure 34: Reference Circuit of GNSS Antenna ........................................................................................ 70
Figure 35: Microstrip Design on a 2-layer PCB ......................................................................................... 71
Figure 36: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 71
Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 71
Figure 38: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 72
Figure 39: Dimensions of the U.FL-R-SMT Connector (Unit: mm) ............................................................ 73
Figure 40: Mechanicals of U.FL-LP Connectors ........................................................................................ 74
Figure 41: Space Factor of Mated Connector (Unit: mm) .......................................................................... 75
Figure 42: Referenced Heatsink Design (Heatsink at the Top of the Module) .......................................... 86
Figure 43: Referenced Heatsink Design (Heatsink at the Backside of Your PCB) .................................... 87
Figure 44: Module Top and Side Dimensions ............................................................................................ 88
Figure 45: Module Bottom Dimensions (Bottom View) .............................................................................. 89
Figure 46: Recommended Footprint (Top View) ........................................................................................ 90
Figure 47: Recommended Compatible Footprint (Top View)..................................................................... 91
Figure 48: Top View of the Module............................................................................................................. 92
Figure 49: Bottom View of the Module ....................................................................................................... 92
Figure 50: Reflow Soldering Thermal Profile ............................................................................................. 94
Figure 51: Tape Specifications ................................................................................................................... 95
Figure 52: Reel Specifications.................................................................................................................... 96
Figure 53: Tape and Reel Directions .......................................................................................................... 96
1 Introduction
This document defines EG25-G module, and describes its air interface and hardware interfaces which are
connected with your applications.
This document can help you quickly understand module interface specifications, electrical and
mechanical details as well as other related information of EG25-G module. To facilitate its application in
different fields, relevant reference design is also provided for your reference. Associated with application
note and user guide, you can use EG25-G module to design and set up mobile applications easily.
1.1. Safety Information
The following safety precautions must be observed during all phases of operation, such as usage, service
or repair of any cellular terminal or mobile incorporating EG25-G module. Manufacturers of the cellular
terminal should notify users and operating personnel of the following safety information by incorporating
these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’
failure to comply with these precautions.
Full attention must be paid to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.
Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If there is an Airplane Mode, it should be enabled prior to
boarding an aircraft. Please consult the airline staff for more restrictions on the use
of wireless devices on an aircraft.
Wireless devices may cause interference on sensitive medical equipment, so

please be aware of the restrictions on the use of wireless devices when in
hospitals, clinics or other healthcare facilities.
Cellular terminals or mobiles operating over radio signal and cellular network
cannot be guaranteed to connect in certain conditions, such as when the mobile bill
is unpaid or the (U)SIM card is invalid. When emergent help is needed in such
conditions, use emergency call if the device supports it. In order to make or receive
a call, the cellular terminal or mobile must be switched on in a service area with
adequate cellular signal strength. In an emergency, the device with emergency call
function cannot be used as the only contact method considering network
connection cannot be guaranteed under all circumstances.
The cellular terminal or mobile contains a transceiver. When it is ON, it receives

and transmits radio frequency signals. RF interference can occur if it is used close
to TV sets, radios, computers or other electric equipment.
In locations with explosive or potentially explosive atmospheres, obey all posted

signs and turn off wireless devices such as mobile phone or other cellular
terminals. Areas with explosive or potentially explosive atmospheres include
fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities,
and areas where the air contains chemicals or particles such as grain, dust or
metal powders.
2 Product Concept
2.1. General Description
EG25-G is an LTE-FDD/LTE-TDD/WCDMA/GSM wireless communication module with receive diversity.

It provides data connectivity on LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, UMTS,
EDGE and GPRS networks. It also provides GNSS and voice functionality for your specific applications.
The following table shows the supported frequency bands, GNSS and digital audio functions of EG25-G
module.
Table 1: Supported Frequency Bands and GNSS Function of EG25-G Module
Frequency Bands/
GNSS Function/ EG25-G
Digital Audio
LTE-FDD
B1/B2/B3/B4/B5/B7/B8/B12/B13/B18/B19/B20/B25/B26/B28
(with receive diversity)
LTE-TDD
B38/B39/B40/B41
WCDMA
B1/B2/B4/B5/B6/B8/B19
GSM 850/900/1800/1900 MHz
GNSS Function (Optional) GPS, GLONASS, BeiDou, Galileo, QZSS
Digital Audio (PCM) Supported
With a compact profile of 29.0 mm × 32.0 mm × 2.4 mm, EG25-G can meet almost all requirements for
M2M applications such as automotive, smart metering, tracking system, security, router, wireless POS,
mobile computing device, PDA phone, tablet PC, etc.
1)
EG25-G is an SMD type module which can be embedded into applications through its 144-pin LGA
pads.
NOTE
1)
LGA form factor is used for EG25-G module, while LCC is recommended only in the compatible design
with EC25 series/EC21 series/EC20 R2.1/EG25-G/UC200T series modules.
2.2. Key Features
The following table describes the detailed features of EG25-G module.
Table 2: Key Features of EG25-G Module
Features Description
Supply voltage: 3.3–4.3 V

Power Supply
Typical supply voltage: 3.8 V
Class 4 (33 dBm ±2 dB) for GSM850
Class 4 (33 dBm ±2 dB) for EGSM900
Class 1 (30 dBm ±2 dB) for DCS1800
Class 1 (30 dBm ±2 dB) for PCS1900
Class E2 (27 dBm ±3 dB) for GSM850 8-PSK
Transmitting Power Class E2 (27 dBm ±3 dB) for EGSM900 8-PSK
Class E2 (26 dBm ±3 dB) for DCS1800 8-PSK
Class E2 (26 dBm ±3 dB) for PCS1900 8-PSK
Class 3 (24 dBm +1/-3 dB) for WCDMA bands
Class 3 (23 dBm ±2 dB) for LTE-FDD bands
Class 3 (23 dBm ±2 dB) for LTE-TDD bands
Support up to non-CA Cat 4 FDD and TDD
Support 1.4/3/5/10/15/20 MHz RF bandwidth
LTE Features Support MIMO in DL direction
LTE-FDD: Max. 150 Mbps (DL), Max. 50 Mbps (UL)
LTE-TDD: Max. 130 Mbps (DL), Max. 30 Mbps (UL)
Support 3GPP R8 DC-HSDPA, HSPA+, HSDPA, HSUPA and WCDMA
Support QPSK, 16-QAM and 64-QAM modulation
UMTS Features DC-HSDPA: Max. 42 Mbps (DL)
HSUPA: Max. 5.76 Mbps (UL)
WCDMA: Max. 384 kbps (DL), Max. 384 kbps (UL)
GPRS:
Support GPRS multi-slot class 33 (33 by default)
GSM Features Coding scheme: CS-1, CS-2, CS-3 and CS-4
Max. 107 kbps (DL), Max. 85.6 kbps (UL)
EDGE:
Support EDGE multi-slot class 33 (33 by default)

Support GMSK and 8-PSK for different MCS (Modulation and Coding
Scheme)
Downlink coding schemes: MCS 1-9
Uplink coding schemes: MCS 1-9
Max. 296 kbps (DL), Max. 236.8 kbps (UL)
Support TCP/UDP/PPP/FTP/FTPS/HTTP/HTTPS/NTP/PING/QMI/NITZ/
SMTP/SSL/MQTT/CMUX/SMTPS/FILE/MMS* protocols
Internet Protocol
Support PAP (Password Authentication Protocol) and CHAP (Challenge
Features
Handshake Authentication Protocol) protocols which are usually used for
PPP connections
Text and PDU modes
Point-to-point MO and MT
SMS
SMS cell broadcast
SMS storage: ME by default
(U)SIM Interface Support USIM/SIM card: 1.8 V, 3.0 V
Support one digital audio interface: PCM interface

GSM: HR/FR/EFR/AMR/AMR-WB
Audio Features WCDMA: AMR/AMR-WB
LTE: AMR/AMR-WB
Support echo cancellation and noise suppression
Used for audio function with external codec
Support 16-bit linear data format
PCM Interface Support long frame synchronization and short frame synchronization
Support master and slave modes, but must be the master in long frame
synchronization
Compliant with USB 2.0 specification (slave only); the data transfer rate can
reach up to 480 Mbps
Used for AT command communication, data transmission, GNSS NMEA
USB Interface sentences output, software debugging, firmware upgrade and voice over
USB
Support USB serial drivers for: Windows 7/8/8.1/10, Linux 2.6–5.4, Android
4.x–9.x, etc.
Main UART:
Used for AT command communication and data transmission
Baud rates reach up to 921600 bps, 115200 bps by default
UART Interfaces Support RTS and CTS hardware flow control
Debug UART:
Used for Linux console and log output
115200bps baud rate
SD Card Interface Support SD 3.0 protocol
SGMII Interface Support 10 Mbps/100 Mbps/1000 Mbps Ethernet work mode
Support maximum 150 Mbps (DL)/50 Mbps (UL) for 4G network
Rx-diversity Support LTE/WCDMA Rx-diversity
Gen8C Lite of Qualcomm

GNSS Features Protocol: NMEA 0183
Data update rate: 1 Hz by default
Compliant with 3GPP TS 27.007, 27.005 and Quectel enhanced AT
AT Commands
commands
Two pins including NET_MODE and NET_STATUS to indicate network
Network Indication
connectivity status
Including main antenna interface (ANT_MAIN), Rx-diversity antenna
Antenna Interfaces
interface (ANT_DIV) and GNSS antenna interface (ANT_GNSS)
Size: (29.0 ±0.15) mm × (32.0 ±0.15) mm × (2.4 ±0.2) mm
Physical Characteristics Package: LGA
Weight: approx. 4.9 g
Operation temperature range: -35 °C to +75 °C 1)
Temperature Range Extended temperature range: -40 °C to +85 °C 2)
Storage temperature range: -40 °C to +90 °C
Firmware Upgrade USB interface or DFOTA
RoHS All hardware components are fully compliant with EU RoHS directive.
NOTES
1) Within
1. operation temperature range, the module is 3GPP compliant.
2)
2. Within extended temperature range, the module remains the ability to establish and maintain a
voice, SMS, data transmission, etc. There is no unrecoverable malfunction. There are also no effects
on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce
in their value and exceed the specified tolerances. When the temperature returns to normal operating
temperature levels, the module will meet 3GPP specifications again.
3. “*” means under development.
2.3. Functional Diagram
The following figure shows a block diagram of EG25-G and illustrates the major functional parts.
 Power management
 Baseband
 DDR+NAND flash
 Radio frequency
 Peripheral interfaces
ANT_MAIN ANT_GNSS ANT_DIV
PAM SAW Switch
Duplex LNA
SAW
VBAT_RF
PA
APT
PRx DRx
Tx
NAND
Transceiver DDR2
SDRAM
IQ Control
VBAT_BB
PMIC
Control
PWRKEY
RESET_N
Baseband
ADCs
STATUS 19.2M
XO
VDD_EXT USB (U)SIM PCM I2C UARTs SGMII WLAN BT GPIOs SD
Figure 1: Functional Diagram
2.4. Evaluation Board
In order to help you develop applications with EG25-G, Quectel supplies an evaluation board (UMTS&LTE
EVB), USB to RS-232 converter cable, earphone, antenna and other peripherals to control or test the
module. For more details, see document [8].
3 Application Interfaces
EG25-G is equipped with 144 LGA pads that can be connected to cellular application platform. The
subsequent chapters will provide detailed descriptions of the following functions/interfaces.
 Power supply
 (U)SIM interface
 USB interface
 UART interfaces
 PCM and I2C interfaces
 SD card interface
 Wireless connectivity interfaces
 ADC interfaces
 Status indication
 SGMII interface
 USB_BOOT interface
3.2. Pin Assignment
The following figure shows the pin assignment of EG25-G module.
RESERVED
RESERVED
RESERVED
USB_VBUS
VBAT_RF
VBAT_BB
VBAT_BB
VBAT_RF
USB_DM
USB_DP
STATUS
GND
GND
DCD
RXD
DTR
CTS
TXD
RTS
RI
114
113
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
WAKEUP_IN 1) 1 54 GND
AP_READY 2 53 GND
129 117
RESERVED 3 52 GND
108 103 99 95 90 85
W_DISABLE# 4 130 118 51 GND
NET_MODE 1) 5 131 119 50 GND
NET_STATUS 6 49 ANT_MAIN
132 120 109 104 100 96 91 86
VDD_EXT 7 48 GND
RESERVED 141 133 121 144 RESERVED
RESERVED 142 82 79 76 73 143 RESERVED
134 122
GND 8 110 105 83 80 77 74 92 87 47 ANT_GNSS
GND 9 135 123 84 81 78 75 46 GND
USIM_GND 10 45 ADC0
1361) 124
DBG_RXD 11 44 ADC1
111 106 101 97 93 88
DBG_TXD 12 1371) 125 43 RESERVED
USIM_PRESENCE 13 42 I2C_SDA
1381) 126
USIM_VDD 14 41 I2C_SCL
USIM_DATA 15 139 127 112 107 102 98 94 89 40 BT_CTS 1)
USIM_CLK 16 39 BT_RXD
140 128
USIM_RST 17 38 BT_TXD
RESERVED 18 37 BT_RTS
116
115 USB_BOOT 1)
19
20
21 PWRKEY 2)
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SDC2_DATA3
SDC2_DATA2
SDC2_DATA1
SDC2_DATA0
RESET_N
GND
ANT_DIV
GND
SD_INS_DET
SDC2_CLK
SDC2_CMD
VDD_SDIO
GND
RESERVED
PCM_IN
PCM_OUT
PCM_SYNC
PCM_CLK
Power Pins Signal Pins WLAN Pins RESERVED Pins
GND Pins Bluetooth Pins SGMII Pins
Figure 2: Pin Assignment (Top View)
NOTES
1)
1. means pins WAKEUP_IN, NET_MODE, WLAN_EN, COEX_UART_RX, COEX_UART_TX,
USB_BOOT and BT_CTS cannot be pulled up before startup.
2) PWRKEY output voltage is 0.8 V because of the diode drop in the Qualcomm chipset.
2.
3. Pins USB_BOOT and COEX_UART_RX are connected inside the module and share the same
network.
4. Pins 37~40, 118, 127 and 129~139 are used for wireless connectivity interfaces, among which pins
118, 127 and 129~138 are WLAN function pins, and the rest are Bluetooth (BT) function pins. BT
function is under development.

5. Pins 119~126 and 128 are used for SGMII interface.
6. Pins 24~27 are multiplexing pins used for audio design on EG25-G module and BT function on FC20
series or FC21 module.
7. Keep all RESERVED pins and unused pins unconnected.
8. GND pins 85~112 should be connected to ground in the design. RESERVED pins 73~84 should not
be designed in schematic and PCB decal, and these pins should be served as a keepout area.
3.3. Pin Description
The following tables show the pin definition of EG25-G module.
Table 3: I/O Parameters Definition
Type Description
AI Analog Input
AO Analog Output
DI Digital Input
DO Digital Output
IO Bidirectional
OD Open Drain
PI Power Input
PO Power Output
Table 4: Pin Description
Power Supply
Pin Name Pin No. I/O Description DC Characteristics Comment
Power supply for Vmax = 4.3 V It must be provided

VBAT_BB 59, 60 PI module’s baseband Vmin = 3.3 V with sufficient current
part Vnorm = 3.8 V up to 0.8 A.
Power supply for Vmax = 4.3 V It must be provided
VBAT_RF 57, 58 PI
module’s RF part Vmin = 3.3 V with sufficient current
Vnorm = 3.8 V up to 1.8 A in a burst

transmission.
Power supply for
Provide 1.8 V for Vnorm = 1.8 V external GPIO’s pull up
VDD_EXT 7 PO
external circuit IOmax = 50 mA circuits.
If unused, keep it open.
8, 9, 19,
22, 36, 46,
GND 48, 50–54, Ground
56, 72,
85–112
Power-on/off
The output voltage is

Turn on/off the 0.8V because of the
PWRKEY 21 DI VH = 0.8 V
module diode drop in the
Qualcomm chipset.
VIHmax = 2.1 V
Reset signal of the If unused, keep it
RESET_N 20 DI VIHmin = 1.3 V
module open.
VILmax = 0.5 V
Status Indication
The drive current An external pull-up

Indicate the module
STATUS 61 OD should be less than resistor is required. If
operating status
0.9 mA. unused, keep it open.
1.8 V power domain.
Indicate the Cannot be pulled up
VOHmin = 1.35 V
NET_MODE 5 DO module’s network before startup.
VOLmax = 0.45 V
registration mode If unused, keep it
open.
Indicate the 1.8 V power domain.
NET_ VOHmin = 1.35 V
6 DO module’s network If unused, keep it
STATUS VOLmax = 0.45 V
activity status open.
USB Interface
Vmax = 5.25 V Typical: 5.0 V

USB connection
USB_VBUS 71 PI Vmin = 3.0 V If unused, keep it
detection
Vnorm = 5.0 V open.
USB 2.0 compliant.

Require differential
USB differential data
USB_DP 69 IO impedance of 90 Ω.
bus (+)
If unused, keep it
open.
USB 2.0 compliant.
USB differential data
USB_DM 70 IO impedance of 90 Ω.
bus (-)
If unused, keep it
open.
(U)SIM Interface
Specified ground for

USIM_GND 10
(U)SIM card
IOmax = 50 mA
For 1.8 V (U)SIM:

Either 1.8 V or 3.0 V
Vmax = 1.9 V
Power supply for is supported by the
USIM_VDD 14 PO Vmin = 1.7 V
(U)SIM card module
automatically.
For 3.0 V (U)SIM:
Vmax = 3.05 V
Vmin = 2.7 V
For 1.8 V (U)SIM:
VILmax = 0.6 V
VIHmin = 1.2 V
VOLmax = 0.45 V
VOHmin = 1.35 V
Data signal of
USIM_DATA 15 IO
(U)SIM card
For 3.0 V (U)SIM:
VILmax = 1.0 V
VIHmin = 1.95 V
VOLmax = 0.45 V
VOHmin = 2.55 V
For 1.8 V (U)SIM:
VOLmax = 0.45 V
VOHmin = 1.35 V
Clock signal of
USIM_CLK 16 DO
(U)SIM card
For 3.0 V (U)SIM:
VOLmax = 0.45 V
VOHmin = 2.55 V
For 1.8 V (U)SIM:

VOLmax = 0.45 V
VOHmin = 1.35 V
Reset signal of
USIM_RST 17 DO
(U)SIM card
For 3.0 V (U)SIM:
VOLmax = 0.45 V
VOHmin = 2.55 V
VILmin = -0.3 V
1.8 V power domain.
USIM_ (U)SIM card VILmax = 0.6 V
13 DI If unused, keep it
PRESENCE insertion detection VIHmin = 1.2 V
open.
VIHmax = 2.0 V
Main UART Interface
1.8 V power domain.

VOLmax = 0.45 V
RI 62 DO Ring indicator If unused, keep it
VOHmin = 1.35 V
open.
1.8 V power domain.
Data carrier VOLmax = 0.45 V
DCD 63 DO If unused, keep it
detection VOHmin = 1.35 V
open.
1.8 V power domain.
VOLmax = 0.45 V
CTS 64 DO Clear to send If unused, keep it
VOHmin = 1.35 V
open.
VILmin = -0.3 V
1.8 V power domain.
VILmax = 0.6 V
RTS 65 DI Request to send If unused, keep it
VIHmin = 1.2 V
open.
VIHmax = 2.0 V
1.8 V power domain.
VILmin = -0.3 V Pulled up by default.
Data terminal ready, VILmax = 0.6 V Low level wakes up
DTR 66 DI
sleep mode control VIHmin = 1.2 V the module.
VIHmax = 2.0 V If unused, keep it
open.
1.8 V power domain.
VOLmax = 0.45 V
TXD 67 DO Transmit data If unused, keep it
VOHmin = 1.35 V
open.
VILmin = -0.3 V
1.8 V power domain.
VILmax = 0.6 V
RXD 68 DI Receive data If unused, keep it
VIHmin = 1.2 V
open.
VIHmax = 2.0 V
Debug UART Interface
1.8 V power domain.

VOLmax = 0.45 V
DBG_TXD 12 DO Transmit data If unused, keep it
VOHmin = 1.35 V
open.
VILmin = -0.3 V
1.8 V power domain.
VILmax = 0.6 V
DBG_RXD 11 DI Receive data If unused, keep it
VIHmin = 1.2 V
open.
VIHmax = 2.0 V
ADC Interfaces
General-purpose
Voltage range: If unused, keep it
ADC0 45 AI analog to digital
0.3 V to VBAT_BB open.
converter
General-purpose
Voltage range: If unused, keep it
ADC1 44 AI analog to digital
0.3 V to VBAT_BB open.
converter
PCM Interface
VILmin = -0.3 V
1.8 V power domain.
VILmax = 0.6 V
PCM_IN 24 DI PCM data input If unused, keep it
VIHmin = 1.2 V
open.
VIHmax = 2.0 V
1.8 V power domain.
VOLmax = 0.45 V
PCM_OUT 25 DO PCM data output If unused, keep it
VOHmin = 1.35 V
open.
1.8 V power domain.
VOLmax = 0.45 V
In master mode, it is
VOHmin = 1.35 V
PCM data frame an output signal. In
VILmin = -0.3 V
PCM_SYNC 26 IO synchronization slave mode, it is an
VILmax = 0.6 V
signal input signal.
VIHmin = 1.2 V
If unused, keep it
VIHmax = 2.0 V
open.
1.8 V power domain.
VOLmax = 0.45 V
In master mode, it is
VOHmin = 1.35 V
an output signal. In
VILmin = -0.3 V
PCM_CLK 27 IO PCM clock slave mode, it is an
VILmax = 0.6 V
input signal.
VIHmin = 1.2 V
If unused, keep it
VIHmax = 2.0 V
open.
I2C Interface
An external pull-up to
I2C serial clock.
1.8V is required.
I2C_SCL 41 OD Used for external
If unused, keep it
codec.
open.
An external pull-up to
I2C serial data.
1.8V is required.
I2C_SDA 42 OD Used for external
If unused, keep it
codec.
open.
SD Card Interface
1.8 V signaling:
VOLmax = 0.45 V
VOHmin = 1.4 V
VILmin = -0.3 V
SDIO signal level can
VILmax = 0.58 V
be selected
VIHmin = 1.27 V
according to SD card
VIHmax = 2.0 V
SDC2_ SD card SDIO bus supported level, see
28 IO
DATA3 DATA3 SD 3.0 protocol for
3.0 V signaling:
more details.
VOLmax = 0.38 V
If unused, keep it
VOHmin = 2.01 V
open.
VILmin = -0.3 V
VILmax = 0.76 V
VIHmin = 1.72 V
VIHmax = 3.34 V
1.8 V signaling:
VOLmax = 0.45 V
VOHmin = 1.4 V
VILmin = -0.3 V SDIO signal level can
VILmax = 0.58 V be selected
VIHmin = 1.27 V according to SD card
SDC2_ SD card SDIO bus VIHmax = 2.0 V supported level, see
29 IO
3.0 V signaling: more details.
VOLmax = 0.38 V If unused, keep it
VOHmin = 2.01 V open.
VILmin = -0.3 V
VILmax = 0.76 V
VIHmin = 1.72 V
VIHmax = 3.34 V
1.8 V signaling:
VOLmax = 0.45 V
VOHmin = 1.4 V
VILmin = -0.3 V
VILmax = 0.58 V
be selected
VIHmin = 1.27 V
VIHmax = 2.0 V
30 IO
3.0 V signaling:
more details.
VOLmax = 0.38 V
If unused, keep it
VOHmin = 2.01 V
open.
VILmin = -0.3 V
VILmax = 0.76 V
VIHmin = 1.72 V
VIHmax = 3.34 V
1.8 V signaling:
VOLmax = 0.45 V
VOHmin = 1.4 V
VILmin = -0.3 V
VILmax = 0.58 V
be selected
VIHmin = 1.27 V
VIHmax = 2.0 V
31 IO
3.0 V signaling:
more details.
VOLmax = 0.38 V
If unused, keep it
VOHmin = 2.01 V
open.
VILmin = -0.3 V
VILmax = 0.76 V
VIHmin = 1.72 V
VIHmax = 3.34 V
1.8 V signaling:
be selected
VOLmax = 0.45 V
VOHmin = 1.4 V
SD card SDIO bus supported level, see
SDC2_CLK 32 DO
clock SD 3.0 protocol for
3.0 V signaling:
more details.
VOLmax = 0.38 V
If unused, keep it
VOHmin = 2.01 V
open.
1.8 V signaling: SDIO signal level can
SD card SDIO bus VOLmax = 0.45 V be selected
SDC2_CMD 33 IO
command VOHmin = 1.4 V according to SD card
VILmin = -0.3 V supported level, see
VILmax = 0.58 V SD 3.0 protocol for

VIHmin = 1.27 V more details.
VIHmax = 2.0 V If unused, keep it
open.
3.0 V signaling:
VOLmax = 0.38 V
VOHmin = 2.01 V
VILmin = -0.3 V
VILmax = 0.76 V
VIHmin = 1.72 V
VIHmax = 3.34 V
VILmin = -0.3 V
1.8 V power domain.
SD_INS_ SD card insertion VILmax = 0.6 V
23 DI If unused, keep it
DET detect VIHmin = 1.2 V
open.
VIHmax = 2.0 V
1.8/2.85 V
configurable.
SD card SDIO bus Cannot be used for
VDD_SDIO 34 PO IOmax = 50 mA
pull-up power SD card power.
If unused, keep it
open.
Wireless Connectivity Interfaces
WLAN_SLP_ If unused, keep it

118 DO WLAN sleep clock
CLK open.
1.8 V power domain.
WLAN power VOLmax = 0.45 V Active high.
PM_ENABLE 127 DO
control VOHmin = 1.35 V If unused, keep it
open.
VOLmax = 0.45 V
VOHmin = 1.35 V
1.8 V power domain.
SDC1_ WLAN SDIO data VILmin = -0.3 V
129 IO If unused, keep it
DATA3 bus D3 VILmax = 0.6 V
open.
VIHmin = 1.2 V
VIHmax = 2.0 V
VOLmax = 0.45 V
VOHmin = 1.35 V
1.8 V power domain.
open.
VIHmin = 1.2 V
VIHmax = 2.0 V
VOLmax = 0.45 V
VOHmin = 1.35 V
1.8 V power domain.
open.
VIHmin = 1.2 V
VIHmax = 2.0 V
VOLmax = 0.45 V
VOHmin = 1.35 V
1.8 V power domain.
open.
VIHmin = 1.2 V
VIHmax = 2.0 V
1.8 V power domain.
WLAN SDIO bus VOLmax = 0.45 V
SDC1_CLK 133 DO If unused, keep it
clock VOHmin = 1.35 V
open.
1.8 V power domain.
WLAN SDIO bus VOLmax = 0.45 V
SDC1_CMD 134 DO If unused, keep it
command VOHmin = 1.35 V
open.
Wake up the host VILmin = -0.3 V 1.8 V power domain.
WAKE_ON_ (EG25-G module) VILmax = 0.6 V Active low.
135 DI
WIRELESS by FC20 series or VIHmin = 1.2 V If unused, keep it
FC21 module. VIHmax = 2.0 V open.
1.8 V power domain.
WLAN function Active high.
control via FC20 VOLmax = 0.45 V Cannot be pulled up
WLAN_EN 136 DO
series or FC21 VOHmin = 1.35 V before startup.
module If unused, keep it
open.
1.8 V power domain.
VILmin = -0.3 V
Cannot be pulled up
COEX_UART_ LTE/WLAN&BT VILmax = 0.6 V
137 DI before startup.
RX coexistence signal VIHmin = 1.2 V
If unused, keep it
VIHmax = 2.0 V
open.
1.8 V power domain.
Cannot be pulled up
COEX_UART_ LTE/WLAN&BT VOLmax = 0.45 V
138 DO before startup.
TX coexistence signal VOHmin = 1.35 V
If unused, keep it
open.
VILmin = -0.3 V
1.8 V power domain.
BT UART request to VILmax = 0.6 V
BT_RTS 37 DI If unused, keep it
send VIHmin = 1.2 V
open.
VIHmax = 2.0 V
BT_TXD 38 DO BT UART transmit VOLmax = 0.45 V 1.8 V power domain.
data VOHmin = 1.35 V If unused, keep it

open.
VILmin = -0.3 V
1.8 V power domain.
BT UART receive VILmax = 0.6 V
BT_RXD 39 DI If unused, keep it
data VIHmin = 1.2 V
open.
VIHmax = 2.0 V
1.8 V power domain.
Cannot be pulled up
BT UART clear to VOLmax = 0.45 V
BT_CTS 40 DO before startup.
send VOHmin = 1.35 V
If unused, keep it
open.
BT function control 1.8 V power domain.
VOLmax = 0.45 V
BT_EN 139 DO via FC20 series or If unused, keep it
VOHmin = 1.35 V
FC21 module open.
SGMII Interface
For 1.8 V:
VOLmax = 0.45 V
1.8/2.85 V power
VOHmin = 1.4 V
domain.
EPHY_RST_N 119 DO Ethernet PHY reset
If unused, keep it
For 2.85 V:
open.
VOLmax = 0.35 V
VOHmin = 2.14 V
VILmin = -0.3 V
1.8 V power domain.
Ethernet PHY VILmax = 0.6 V
EPHY_INT_N 120 DI If unused, keep it
interrupt VIHmin = 1.2 V
open.
VIHmax = 2.0 V
For 1.8 V:
VILmax = 0.58 V 1.8/2.85 V power
VIHmin = 1.27 V domain.
VOLmax = 0.45 V Require external
SGMII MDIO VOHmin = 1.4 V pull-up to
SGMII_MDATA 121 IO (Management Data USIM2_VDD, and
Input/Output) data For 2.85 V: the resistor should be
VILmax = 0.71 V 1.5 kΩ.
VIHmin = 1.78 V If unused, keep it
VOLmax = 0.35 V open.
VOHmin = 2.14 V
For 1.8 V: 1.8/2.85 V power
SGMII MDIO
VOLmax = 0.45 V domain.
SGMII_MCLK 122 DO (Management Data
VOHmin = 1.4 V If unused, keep it
Input/Output) clock
open.
For 2.85 V:
VOLmax = 0.35 V
VOHmin = 2.14 V
Connect with a
0.1 μF capacitor, and
SGMII transmission is close to the PHY
SGMII_TX_M 123 AO
- minus side.
If unused, keep it
open.
Connect with a
0.1 μF capacitor, and
SGMII transmission is close to the PHY
SGMII_TX_P 124 AO
- plus side.
If unused, keep it
open.
Connect with a
0.1 μF capacitor,
SGMII receiving which is close to the
SGMII_RX_P 125 AI
- plus pin of the module.
If unused, keep it
open.
Connect with a
0.1 μF capacitor,
SGMII receiving which is close to the
SGMII_RX_M 126 AI
- minus pin of the module.
If unused, keep it
open.
Configurable power
source.
SGMII MDIO pull-up 1.8/2.85 V power
USIM2_VDD 128 PO
power source domain.
If unused, keep it
open.
RF Interfaces
50 Ω impedance.
ANT_DIV 35 AI Diversity antenna If unused, keep it
open.
ANT_MAIN 49 IO Main antenna 50 Ω impedance.
50 Ω impedance.
ANT_GNSS 47 AI GNSS antenna
If unused, keep it
open.
Other Interface Pins
1.8 V power domain.

Cannot be pulled up
VILmin = -0.3 V
before startup.
VILmax = 0.6 V
WAKEUP_IN 1 DI Sleep mode control Low level wakes up
VIHmin = 1.2 V
the module.
VIHmax = 2.0 V
If unused, keep it
open.
1.8 V power domain.
Pull-up by default.
VILmin = -0.3 V
At low voltage level,
Airplane mode VILmax = 0.6 V
W_DISABLE# 4 DI module can enter into
control VIHmin = 1.2 V
airplane mode.
VIHmax = 2.0 V
If unused, keep it
open.
VILmin = -0.3 V
Application 1.8 V power domain.
VILmax = 0.6 V
AP_READY 2 DI processor sleep If unused, keep it
VIHmin = 1.2 V
state detection open.
VIHmax = 2.0 V
USB_BOOT Interface
1.8 V power domain.

VILmin = -0.3 V
Force the module to Cannot be pulled up
VILmax = 0.6 V
USB_BOOT 115 DI enter emergency before startup.
VIHmin = 1.2 V
download mode It is recommended to
VIHmax = 2.0 V
reserve test point.
RESERVED Pins
3, 18, 43,
55, 73–84,
Keep these pins
RESERVED 113, 114, Reserved
unconnected.
116, 117,
140–144
NOTES
1)
1. PCM interface pins multiplexing pins used for audio design on EG25-G module and BT function on
FC20 series or FC21 module.
2. BT function is under development.
3.4. Operating Modes
The following table briefly outlines the operating modes to be mentioned in the following chapters.
Table 5: Overview of Operating Modes
Mode Details
Software is active. The module has registered on the network, and it is

Idle
Normal ready to send and receive data.
Operation Network connection is ongoing. In this mode, the power consumption is
Talk/Data
decided by network setting and data transfer rate.
Minimum
AT+CFUN=0 can set the module to a minimum functionality mode without removing
Functionality
the power supply. In this case, both RF function and (U)SIM card will be invalid.
Mode
AT+CFUN=4 or W_DISABLE# pin can set the module to enter airplane mode. In this
Airplane Mode
case, RF function will be invalid.
The current consumption of the module will be reduced to the minimal level. During
Sleep Mode this mode, the module can still receive paging message, SMS, voice call and
TCP/UDP data from the network normally.
The power management unit shuts down the power supply. Software goes inactive.
Power Down
The serial interface is not accessible. Operating voltage (connected to VBAT_RF and
Mode
VBAT_BB) remains applied.
3.5. Power Saving
3.5.1. Sleep Mode
EG25-G is able to reduce its current consumption to a minimum value during the sleep mode. The
following sub-chapters describes power saving procedures of EG25-G module.
3.5.1.1. UART Application
If the host communicates with module via UART interface, the following preconditions can let the module
enter sleep mode.
 Execute AT+QSCLK=1 to enable sleep mode.

 Drive DTR to high level.
The following figure shows the connection between the module and the host.
Module Host
RXD TXD
TXD RXD
RI EINT
DTR GPIO
AP_READY GPIO
GND GND
Figure 3: Sleep Mode Application via UART
 Driving the host DTR to low level will wake up the module.
 When EG25-G has a URC to report, RI signal will wake up the host. See Chapter 3.19 for details
about RI behaviors.
 AP_READY will detect the sleep state of the host (can be configured to high level or low level
detection). See AT+QCFG="apready" for details.
3.5.1.2. USB Application with USB Remote Wakeup Function
If the host supports USB suspend/resume and remote wakeup functions, the following three preconditions
must be met to let the module enter sleep mode.

 Ensure the DTR is held at high level or keep it open.
 The host’s USB bus, which is connected with the module’s USB interface, enters suspend state.
Module Host
USB_VBUS VDD
USB_DP USB_DP
USB_DM USB_DM
AP_READY GPIO
GND GND
Figure 4: Sleep Mode Application with USB Remote Wakeup
 Sending data to EG25-G via USB will wake up the module.

 When EG25-G has a URC to report, the module will send remote wake-up signals via USB bus so as
to wake up the host.
3.5.1.3. USB Application with USB Suspend/Resume and RI Function
If the host supports USB suspend and resume, but does not support remote wake-up function, the RI
signal is needed to wake up the host.
There are three preconditions to let the module enter sleep mode.
 Execute AT+QSCLK=1 to enable the sleep mode.

 The host’s USB bus, which is connected with the module’s USB interface, enters suspend state.
Module Host
USB_VBUS VDD
USB_DP USB_DP
USB_DM USB_DM
AP_READY GPIO
RI EINT
GND GND
Figure 5: Sleep Mode Application with RI
 Sending data to EG25-G via USB will wake up the module.

 When EG25-G has a URC to report, RI signal will wake up the host.
3.5.1.4. USB Application without USB Suspend Function
If the host does not support USB suspend function, USB_VBUS should be disconnected with an external
control circuit to let the module enter sleep mode.

 Disconnect USB_VBUS.
Module Host
GPIO
Power
USB_VBUS Switch VDD
USB_DP USB_DP
USB_DM USB_DM
RI EINT
AP_READY GPIO
GND GND
Figure 6: Sleep Mode Application without Suspend Function
Switching on the power switch to supply power to USB_VBUS will wake up the module.
NOTE
Please pay attention to the level match shown in dotted line between the module and the host. For more
details about EG25-G power management application, see document [1].
3.5.2. Airplane Mode
When the module enters airplane mode, the RF function will be disabled, and all AT commands related to
it will be inaccessible. This mode can be set via the following ways.
Hardware:
The W_DISABLE# pin is pulled up by default. Driving it to low level will let the module enter airplane
mode.
Software:
AT+CFUN provides the choice of the functionality level through setting <fun> into 0, 1 or 4.
 AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.
 AT+CFUN=1: Full functionality mode (by default).
 AT+CFUN=4: Airplane mode. RF function is disabled.
NOTES
1. The W_DISABLE# control function is disabled in firmware by default. It can be enabled by

AT+QCFG="airplanecontrol".
2. The execution of AT+CFUN will not affect GNSS function.
3.6. Power Supply
3.6.1. Power Supply Pins
EG25-G provides four VBAT pins for connection with the external power supply. There are two separate
voltage domains for VBAT.
 Two VBAT_RF pins for module’s RF part

 Two VBAT_BB pins for module’s baseband part
The following table shows the details of VBAT pins and ground pins.
Table 6: Pin Definition of VBAT and GND Pins
Pin Name Pin No. Description Min. Typ. Max. Unit
Power supply for module’s RF

VBAT_RF 57, 58 3.3 3.8 4.3 V
part
Power supply for module’s
VBAT_BB 59, 60 3.3 3.8 4.3 V
baseband part
8, 9, 19, 22, 36,
GND 46, 48, 50–54, Ground - 0 - V
56, 72, 85–112
3.6.2. Decrease Voltage Drop
The power supply range of the module is from 3.3 V to 4.3 V. Please make sure that the input voltage will
never drop below 3.3 V. The following figure shows the voltage drop during burst transmission in 2G
network. The voltage drop will be less in 3G and 4G networks.
Burst Burst
Transmission Transmission
VBAT Ripple
Drop
Min.3.3 V
Figure 7: Power Supply Limits during Burst Transmission
To decrease voltage drop, a bypass capacitor of about 100 µF with low ESR (ESR = 0.7 Ω) should be
used, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low
ESR. It is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC
array, and place these capacitors close to VBAT_BB/VBAT_RF pins. The main power supply from an
external application has to be a single voltage source and can be expanded to two sub paths with star
structure. The width of VBAT_BB trace should be no less than 1 mm; and the width of VBAT_RF trace
should be no less than 2 mm. In principle, the longer the VBAT trace is, the wider it will be.
In addition, in order to avoid the damage caused by electric surge and electrostatics discharge (ESD), it is
suggested that a TVS diode with suggested low reverse stand-off voltage VRWM 4.5 V, low clamping
voltage VC and high reverse peak pulse current IPP should be used. The following figure shows the star
structure of the power supply.
VBAT
VBAT_RF
VBAT_BB
+ +
D1 C1 C2 C3 C4 C5 C6 C7 C8
4.5 V 100 μF 100 nF 33 pF 10 pF 100 μF 100 nF 33 pF 10 pF
Module
Figure 8: Star Structure of the Power Supply
3.6.3. Reference Design for Power Supply
Power design for the module is very important, as the performance of the module largely depends on the
power source. The power supply should be able to provide sufficient current up to 2.0 A at least. If the
voltage drop between the input and output is not too high, it is suggested that an LDO should be used to
supply power for the module. If there is a big voltage difference between the input source and the desired
output (VBAT), a buck converter is preferred to be used as the power supply.
The following figure shows a reference design for +5.0 V input power source. The typical output of the
power supply is about 3.8 V and the maximum load current is 3.0 A.
MIC29302WU
DC_IN VBAT
2 4
IN OUT
GND
ADJ
EN
100K
1%
1
5
51K
4.7K 470R
470 μF 100 nF
470 μF 100 nF
47K
VBAT_EN 47K 1%
Figure 9: Reference Circuit of Power Supply
NOTE
In order to avoid damaging internal flash, please do not switch off the power supply when the module
works normally. Only after the module is shut down by PWRKEY or AT command, then the power supply
can be cut off.
3.6.4. Monitor the Power Supply
AT+CBC can be used to monitor the VBAT_BB voltage value. For more details, see document [2].
3.7. Power-on/off Scenarios
3.7.1. Turn on Module Using the PWRKEY
The following table shows the pin definition of PWRKEY.
Table 7: Pin Definition of PWRKEY
Pin Name Pin No. I/O Description Comment
The output voltage is 0.8 V

PWRKEY 21 DI Turn on/off the module because of the diode drop in
the Qualcomm chipset.
When EG25-G is in power-down mode, it can be turned on to normal mode by driving the PWRKEY pin to
a low level for at least 500 ms. It is recommended to use an open drain/collector driver to control the
PWRKEY. After STATUS pin (require external pull-up resistor) outputs a low level, PWRKEY pin can be
released. A simple reference circuit is illustrated in the following figure.
PWRKEY
≥ 500 ms
4.7K
10 nF
Turn-on pulse
47K
Figure 10: Turn on the Module by Using Driving Circuit
The other way to control the PWRKEY is using a button directly. When pressing the key, electrostatic
strike may generate from finger. Therefore, a TVS component is indispensable to be placed nearby the
button for ESD protection. A reference circuit is shown in the following figure.
S1
PWRKEY
TVS
Close to S1
Figure 11: Turn on the Module by Using Keystroke
The power-on scenario is illustrated in the following figure.
NOTE 1
VBAT ≥ 500 ms
VH = 0.8 V
PWRKEY VIL ≤ 0.5 V
About 100 ms
VDD_EXT
≥ 100 ms. After this time, the BOOT_CONFIG

pins can be set to high level by external circuit.
BOOT_CONFIG &
USB_BOOT Pins
RESET_N
≥ 2.5 s
STATUS
(OD)
≥ 12 s
UART Inactive Active
≥ 13 s
USB Inactive Active
Figure 12: Timing of Turning on Module
NOTES
1. Make sure that VBAT is stable before pulling down PWRKEY pin. It is recommended that the time
between powering up VBAT and pulling down PWRKEY pin is no less than 30 ms.
2. PWRKEY can be pulled down directly to GND with a recommended 10 kΩ resistor if module needs to
be powered on automatically and shutdown is not needed.
3.7.2. Turn off Module
The following procedures can be used to turn off the module normally:
 Use the PWRKEY pin.

 Use AT+QPOWD command.
3.7.2.1. Turn off Module Using the PWRKEY Pin
Driving the PWRKEY pin to a low level voltage for at least 650 ms, the module will execute power-off
procedure after the PWRKEY is released. The power-off scenario is illustrated in the following figure.
VBAT
≥ 650 ms ≥ 29.5 s
PWRKEY
STATUS
(OD)
Module RUNNING Power-down procedure OFF

Status
Figure 13: Timing of Turning off Module
3.7.2.2. Turn off Module Using AT Command
It is also a safe way to use AT+QPOWD to turn off the module, which is similar to turn off the module via
PWRKEY pin.
See document [2] for details about AT+QPOWD.
NOTES
1. In order to avoid damaging internal flash, please do not switch off the power supply when the module
works normally. Only after the module is shut down by PWRKEY or AT command, then the power
supply can be cut off.
2. When turning off module with the AT command, please keep PWRKEY at high level after the
execution of the command. Otherwise the module will be turned on again after successfully turn-off.
3.8. Reset Module
The RESET_N pin can be used to reset the module. The module can be reset by driving RESET_N to a
low level voltage for 150–460 ms.
Table 8: Pin Definition of RESET_N
RESET_N 20 DI Reset the module 1.8 V power domain
The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button
can be used to control the RESET_N.
RESET_N
150–460 ms
4.7K
Reset pulse
47K
Figure 14: Reference Circuit of RESET_N by Using Driving Circuit
S2
RESET_N
TVS
Close to S2
Figure 15: Reference Circuit of RESET_N by Using Button
The reset scenario is illustrated in the following figure.
VBAT
≤ 460 ms
≥ 150 ms
RESET_N VIH ≥ 1.3 V
VIL ≤ 0.5 V
Module Running Resetting Restart

Status
Figure 16: Timing of Resetting Module
NOTES
1. Use RESET_N only when failed to turn off the module by AT+QPOWD and PWRKEY pin.
2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins.
3.9. (U)SIM Interface
EG25-G’s (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8 V and 3.0 V
(U)SIM cards are supported.
Table 9: Pin Definition of (U)SIM Interface
Either 1.8 V or 3.0 V is supported

USIM_VDD 14 PO Power supply for (U)SIM card
by the module automatically.
USIM_DATA 15 IO Data signal of (U)SIM card
USIM_CLK 16 DO Clock signal of (U)SIM card
USIM_RST 17 DO Reset signal of (U)SIM card
USIM_ 1.8 V power domain.

13 DI (U)SIM card insertion detection
PRESENCE If unused, keep it open.
USIM_GND 10 Specified ground for (U)SIM card
EG25-G supports (U)SIM card hot-plug via the USIM_PRESENCE pin. The function supports low level
and high level detections. By default, it is disabled, and can be configured via AT+QSIMDET. See
document [2] for more details about the command.
The following figure shows a reference design for (U)SIM interface with an 8-pin (U)SIM card connector.
VDD_EXT USIM_VDD
51K 15K
USIM_GND 100 nF (U)SIM Card Connector
USIM_VDD
VCC GND
USIM_RST 0R
RST VPP
Module USIM_CLK
CLK IO
USIM_PRESENCE 0R
USIM_DATA 0R
GND
33 pF 33 pF 33 pF
GND GND
Figure 17: Reference Circuit of (U)SIM Interface with an 8-pin (U)SIM Card Connector
If (U)SIM card detection function is not needed, please keep USIM_PRESENCE unconnected. A
reference circuit of (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following
figure.
USIM_VDD
15K
USIM_GND 100 nF
(U)SIM Card Connector
USIM_VDD
VCC GND
USIM_RST 0R
RST VPP
Module USIM_CLK
CLK IO
0R
USIM_DATA 0R
33 pF 33 pF 33 pF
GND GND
Figure 18: Reference Circuit of (U)SIM Interface with a 6-pin (U)SIM Card Connector
In order to enhance the reliability and availability of the (U)SIM card in your applications, please follow the
criteria below in (U)SIM circuit design:
 Keep placement of (U)SIM card connector to the module as close as possible. Keep the trace length
as less than 200 mm as possible.
 Keep (U)SIM card signals away from RF and VBAT traces.
 Make sure the bypass capacitor between USIM_VDD and USIM_GND less than 1 μF, and place it as
close to (U)SIM card connector as possible. If the ground is complete on your PCB, USIM_GND can
be connected to PCB ground directly.
 To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with surrounded ground.
 In order to offer good ESD protection, it is recommended to add a TVS diode array whose parasitic
capacitance should not be more than 15 pF. The 0 Ω resistors should be added in series between the
module and the (U)SIM card to facilitate debugging. The 33 pF capacitors are used for filtering
interference of EGSM900. Please note that the (U)SIM peripheral circuit should be close to the
(U)SIM card connector.
 The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace
and sensitive occasion are applied, and should be placed close to the (U)SIM card connector.
3.10. USB Interface
EG25-G contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0
specification and supports high-speed (480 Mbps) and full-speed (12 Mbps) modes. The USB interface
can only serves as a slave device and is used for AT command communication, data transmission, GNSS
NMEA sentences output, software debugging, firmware upgrade and voice over USB. The following table
shows the pin definition of USB interface.
Table 10: Pin Definition of USB Interface
USB_DP 69 IO USB differential data bus (+)
impedance of 90 Ω
USB_DM 70 IO USB differential data bus (-)
impedance of 90 Ω
USB_VBUS 71 PI USB connection detection Typical 5.0 V
GND 72 Ground
For more details about the USB 2.0 specifications, please visit http://www.usb.org/home.
The USB interface is recommended to be reserved for firmware upgrade in your design. The following
figure shows a reference circuit of USB interface.
Test Points
Minimize these stubs
Module MCU
R3 NM_0R
VDD R4 NM_0R
USB_VBUS ESD Array
L1 USB_DM
USB_DM
USB_DP USB_DP
Close to Module GND

GND
Figure 19: Reference Circuit of USB Interface
A common mode choke L1 is recommended to be added in series between the module and customer’s
MCU in order to suppress EMI spurious transmission. Meanwhile, the 0 Ω resistors (R3 and R4) should
be added in series between the module and the test points so as to facilitate debugging, and the resistors
are not mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 components
must be placed close to the module, and also these resistors should be placed close to each other. The
extra stubs of trace must be as short as possible.
The following principles should be complied with when design the USB interface, so as to meet USB 2.0
specification.
 It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90 Ω.
 Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.
 Junction capacitance of the ESD protection component might cause influences on USB data lines, so
please pay attention to the selection of the component. Typically, the stray capacitance should be
less than 2 pF.
 Keep the ESD protection components to the USB connector as close as possible.
3.11. UART Interfaces
The module provides two UART interfaces: the main UART interface and the debug UART interface. The
following shows their features.
 The main UART interface supports 4800 bps, 9600 bps, 19200 bps, 38400 bps, 57600 bps, 115200
bps, 230400 bps, 460800 bps and 921600 bps baud rates, and the default is 115200 bps. It also
supports RTS and CTS hardware flow control, and can be used for data transmission and AT
command communication.
 The debug UART interface supports 115200 bps baud rate. It is used for Linux console and log
output.
The following tables show the pin definition of the UART interfaces.
Table 11: Pin Definition of Main UART Interface
RI 62 DO Ring indicator
DCD 63 DO Data carrier detection
CTS 64 DO Clear to send
RTS 65 DI Request to send 1.8 V power domain

Data terminal ready,
DTR 66 DI
sleep mode control
TXD 67 DO Transmit data
RXD 68 DI Receive data
Table 12: Pin Definition of Debug UART Interface
DBG_TXD 12 DO Transmit data

1.8 V power domain
DBG_RXD 11 DI Receive data
The logic levels are described in the following table.
Table 13: Logic Levels of Digital I/O
Parameter Min. Max. Unit
VIL -0.3 0.6 V
VIH 1.2 2.0 V
VOL 0 0.45 V
VOH 1.35 1.8 V
The module provides 1.8 V UART interfaces. A level translator should be used if your application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments is
recommended. The following figure shows a reference design.
VDD_EXT VCCA VCCB VDD_MCU

0.1 μF 0.1 μF
10K
120K
OE GND
RI A1 B1 RI_MCU
DCD A2 B2 DCD_MCU
CTS A3 Translator B3 CTS_MCU
RTS A4 B4 RTS_MCU
DTR A5 B5 DTR_MCU
TXD A6 B6 TXD_MCU
RXD A7 B7 RXD_MCU
51K 51K
A8 B8
Figure 20: Reference Circuit with Translator Chip
Please visit http://www.ti.com for more information.
Another example with transistor translation circuit is shown as below. For the design of circuits in dotted
lines, see that of circuits in solid lines, but please pay attention to the direction of connection.
4.7K
VDD_EXT VDD_EXT
1 nF
MCU/ARM Module
10K
TXD RXD
RXD TXD
1 nF
10K
VDD_EXT
VCC_MCU 4.7K
RTS RTS
CTS CTS
GPIO DTR
EINT RI
GPIO DCD
GND GND
Figure 21: Reference Circuit with Transistor Circuit
NOTE
Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps.
3.12. PCM and I2C Interfaces
EG25-G provides one Pulse Code Modulation (PCM) digital interface for audio design, which supports the
following modes and one I2C interface:
 Primary mode (short frame synchronization, works as both master and slave)
 Auxiliary mode (long frame synchronization, works as master only)
In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports
256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK at 8 kHz PCM_SYNC, and also supports 4096 kHz
PCM_CLK at 16 kHz PCM_SYNC.
In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC rising edge represents the MSB. In this mode, the PCM interface operates with a
256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK and an 8 kHz, 50% duty cycle PCM_SYNC.
EG25-G supports 16-bit linear data format. The following figures show the primary mode’s timing
relationship with 8 kHz PCM_SYNC and 2048 kHz PCM_CLK, as well as the auxiliary mode’s timing
relationship with 8 kHz PCM_SYNC and 256 kHz PCM_CLK.
125 μs
PCM_CLK 1 2 255 256
PCM_SYNC
MSB LSB MSB
PCM_OUT
MSB LSB MSB
PCM_IN
Figure 22: Primary Mode Timing
125 μs
PCM_CLK 1 2 31 32
PCM_SYNC
MSB LSB
PCM_OUT
MSB LSB
PCM_IN
Figure 23: Auxiliary Mode Timing
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Table 14: Pin Definition of PCM and I2C Interfaces
PCM_IN 24 DI PCM data input 1.8 V power domain
PCM_OUT 25 DO PCM data output 1.8 V power domain
PCM data frame

PCM_SYNC 26 IO 1.8 V power domain
synchronization signal
PCM_CLK 27 IO PCM data bit clock 1.8 V power domain
An external pull-up to 1.8V is

I2C_SCL 41 OD I2C serial clock
required.
An external pull-up to 1.8V is
I2C_SDA 42 OD I2C serial data
required.
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See document [2]
for more details about AT+QDAI.
The following figure shows a reference design of PCM and I2C interfaces with external codec IC.
MICBIAS
INP
BIAS
PCM_CLK BCLK
INN
PCM_SYNC LRCK
PCM_OUT DAC
PCM_IN ADC
LOUTP
I2C_SCL SCL
I2C_SDA SDA LOUTN
4.7K
4.7K
Module Codec
1.8V
Figure 24: Reference Circuit of PCM and I2C Application with Audio Codec
NOTES
1. It is recommended to reserve an RC (R = 22 Ω, C = 22 pF) circuits on the PCM lines, especially for

PCM_CLK.
2. EG25-G works as a master device pertaining to I2C interface.
3.13. SD Card Interface
EG25-G supports SDIO 3.0 interface for SD card.
The following table shows the pin definition of SD card interface.
Table 15: Pin Definition of SD Card Interface
SDC2_DATA3 28 IO SD card SDIO bus DATA3
SDC2_DATA2 29 IO SD card SDIO bus DATA2 SDIO signal level can be

selected according to SD
card supported level, see
SD 3.0 protocol for more
details.
SDC2_CLK 32 DO SD card SDIO bus clock If unused, keep it open.
SDC2_CMD 33 IO SD card SDIO bus command
1.8/2.85 V configurable.
Cannot be used for SD
VDD_SDIO 34 PO SD card SDIO bus pull up power
card power. If unused,
keep it open.
1.8 V power domain.
SD_INS_DET 23 DI SD card insertion detection
The following figure shows a reference design of SD card.

Module VDD_EXT VDD_3V SD Card Connector
VDD_SDIO VDD
+
C10 C9 C8 C7
R7 R8 R9 R10 R11 R12
100 μF 100 nF 33 pF 10 pF
NM NM NM NM NM 470K
R1 0R
SDC2_DATA3 CD/DAT3
R2 0R
SDC2_DATA2 DAT2
R3 0R
SDC2_DATA1 DAT1
R4 0R
SDC2_DATA0 DAT0
R5 0R
SDC2_CLK CLK
R6 0R
SDC2_CMD CMD
SD_INS_DET DETECTIVE
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 D7 C6 D6
NM NM NM NM NM NM VSS
Figure 25: Reference Circuit of SD Card Interface
In SD card interface design, in order to ensure good communication performance with SD card, the
following design principles should be complied with:
 SD_INS_DET must be connected.

 The voltage range of SD card power supply VDD_3V is 2.7–3.6 V and a sufficient current up to 0.8 A
should be provided. As the maximum output current of VDD_SDIO is 50 mA which can only be used
for SDIO pull-up resistors, an externally power supply is needed for SD card.
 To avoid jitter of bus, resistors R7–R11 are needed to pull up the SDIO to VDD_SDIO. Value of these
resistors is among 10–100 kΩ and the recommended value is 100 kΩ. VDD_SDIO should be used as
the pull-up power.
 In order to adjust signal quality, it is recommended to add 0 Ω resistors R1–R6 in series between the
module and the SD card. The bypass capacitors C1–C6 are reserved and not mounted by default. All
resistors and bypass capacitors should be placed close to the module.
 In order to offer good ESD protection, it is recommended to add a TVS diode on SD card pins near
the SD card connector with junction capacitance less than 15 pF.
 Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DC-DC signals, etc.
 It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data trace
is 50 Ω (±10%).
 Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of
SDIO bus should be less than 15 pF.
 It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1 mm
and the total routing length less than 50 mm. The total trace length inside the module is 27 mm, so
the exterior total trace length should be less than 23 mm.
3.14. Wireless Connectivity Interfaces
EG25-G supports a low-power SDIO 3.0 interface for WLAN and UART/PCM interfaces for BT function.
The following table shows the pin definition of wireless connectivity interfaces.
Table 16: Pin Definition of Wireless Connectivity Interfaces
WLAN Part
SDC1_DATA3 129 IO WLAN SDIO data bus D3 1.8V power domain
SDC1_CLK 133 DO WLAN SDIO bus clock 1.8V power domain
SDC1_CMD 134 IO WLAN SDIO bus command 1.8V power domain
1.8V power domain

WLAN function control via FC20 Active high.
WLAN_EN 136 DO
series or FC21 module. Cannot be pulled up before
startup.
Coexistence and Control Part
WLAN_SLP_CLK 118 DO WLAN sleep clock
1.8V power domain

PM_ENABLE 127 DO WLAN power control.
Active high.
Wake up the host (EG25-G
WAKE_ON_
135 DI module) by FC20 series or FC21 1.8V power domain
WIRELESS
module.
1.8V power domain
LTE/WLAN&BT coexistence
COEX_UART_RX 137 DI Cannot be pulled up before
signal
startup
1.8V power domain
LTE/WLAN&BT coexistence
COEX_UART_TX 138 DO Cannot be pulled up before
signal
startup
BT Part
BT_RTS 37 DI BT UART request to send 1.8V power domain
BT_TXD 38 DO BT UART transmit data 1.8V power domain
BT_RXD 39 DI BT UART receive data 1.8V power domain
1.8V power domain

BT_CTS 40 DO BT UART clear to send Cannot be pulled up before
startup
PCM_IN 1) 24 DI PCM data input 1.8V power domain
PCM_OUT 1) 25 DO PCM data output 1.8V power domain
PCM data frame synchronization

PCM_SYNC 1) 26 IO 1.8V power domain
signal
PCM_CLK 1) 27 IO PCM data bit clock 1.8V power domain
BT function control via FC20 1.8V power domain.

BT_EN 139 DO
series or FC21 module. Active high.
The following figure shows a reference design of wireless connectivity interfaces with Quectel FC20
series or FC21 module.
FC20 Series or
Module FC21 Module
PM_ENABLE DCDC/LDO VDD_3V3

POWER
VDD_EXT VIO
SDC1_DATA3 SDIO_D3
SDC1_DATA2 SDIO_D2
SDC1_DATA1 SDIO_D1
SDC1_DATA0 SDIO_D0
WLAN SDC1_CLK SDIO_CLK
SDC1_CMD SDIO_CMD
WLAN_EN WLAN_EN
WLAN_SLP_CLK 32KHZ_IN
WAKE_ON_WIRELESS WAKE_ON_WIRELESS
COEX_UART_RX LTE_UART_TXD
COEX
COEX_UART_TX LTE_UART_RXD
BT_EN BT_EN
BT_RTS BT_UART_RTS
BT_CTS BT_UART_CTS
BT_TXD BT_UART_RXD
Bluetooth BT_RXD BT_UART_TXD
PCM_IN PCM_OUT
PCM_OUT PCM_IN
PCM_SYNC PCM_SYNC
PCM_CLK PCM_CLK
Figure 26: Reference Circuit of Wireless Connectivity Interfaces with FC20 Series or FC21 Module
NOTES
1. FC20 series or FC21 module can only be used as a slave device.

2. When BT function is enabled on EG25-G module, PCM_SYNC and PCM_CLK pins are only used to
output signals. BT function is under development.
1) Pins 24~27 are multiplexing pins used for audio design on EG25-G module and BT function on BT
3.
module.
4. For more information about wireless connectivity interfaces, see document [5].
3.14.1. WLAN Interface
EG25-G provides a low power SDIO 3.0 interface and control interface for WLAN design.
SDIO interface supports SDR mode (up to 50 MHz).

As SDIO signals are very high-speed, in order to ensure the SDIO interface design corresponds with the
SDIO 3.0 specification, please comply with the following principles:
 It is important to route the SDIO signal traces with total grounding. The impedance of SDIO signal
trace is 50 Ω ±10%.
 Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DC-DC signals, etc.
 It is recommended to keep matching length between CLK and DATA/CMD less than 1 mm and total
routing length less than 50 mm.
 Keep termination resistors within 15–24 Ω on clock lines near the module and keep the route
distance from the module clock pins to termination resistors less than 5mm.
 Make sure the adjacent trace spacing is 2 times of the trace width and bus capacitance is less than
15 pF.
3.14.2. BT Interface*
EG25-G supports a dedicated UART interface and a PCM interface for BT application.
Further information about BT interface will be added in future version of this document.
NOTE
“*” means under development.
3.15. ADC Interfaces
The module provides two analog-to-digital converter (ADC) interfaces. AT+QADC=0 can be used to read
the voltage value on ADC0 pin. AT+QADC=1 can be used to read the voltage value on ADC1 pin. For
more details about these AT commands, see document [2].
In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground.
Table 17: Pin Definition of ADC Interfaces
Pin Name Pin No. Description
ADC0 45 General-purpose analog to digital converter
ADC1 44 General-purpose analog to digital converter
The following table describes the characteristic of ADC function.
Table 18: Characteristic of ADC
Parameter Min. Typ. Max. Unit
ADC0 Voltage Range 0.3 VBAT_BB V
ADC1 Voltage Range 0.3 VBAT_BB V
ADC Resolution 15 bits
NOTES
1. ADC input voltage must not exceed that of VBAT_BB.

2. It is prohibited to supply any voltage to ADC pins when VBAT power supply is removed.
3. It is recommended to use a resistor divider circuit for ADC application.
3.16. SGMII Interface
EG25-G includes an integrated Ethernet MAC with an SGMII interface and two management interfaces.
The key features of the SGMII interface are shown below:
 IEEE802.3 compliant
 Support 10 Mbps/100 Mbps/1000 Mbps Ethernet work mode
 Support maximum 150 Mbps (DL)/50 Mbps (UL) for 4G network
 Support VLAN tagging
 Support IEEE1588 and Precision Time Protocol (PTP)
 Can be used to connect to external Ethernet PHY like AR8033, or to an external switch
 Management interfaces support dual voltage 1.8/2.85 V
The following table shows the pin definition of SGMII interface.
Table 19: Pin Definition of SGMII Interface
Control Signal Part
EPHY_RST_N 119 DO Ethernet PHY reset 1.8/2.85 V power domain
EPHY_INT_N 120 DI Ethernet PHY interrupt 1.8 V power domain
SGMII MDIO (Management Data

SGMII_MDATA 121 IO 1.8/2.85 V power domain
Input/Output) data
SGMII MDIO (Management Data
SGMII_MCLK 122 DO 1.8/2.85 V power domain
Input/Output) clock
SGMII MDIO pull-up power Configurable power source.
USIM2_VDD 128 PO
source 1.8/2.85 V power domain.
SGMII Signal Part
SGMII_TX_M 123 AO SGMII transmission - minus Connect with a 0.1 μF capacitor,

which is close to the PHY side.
SGMII_TX_P 124 AO SGMII transmission - plus If unused, keep it open.
SGMII_RX_P 125 AI SGMII receiving - plus Connect with a 0.1 μF capacitor,

which is close to the two pins of
the module.
SGMII_RX_M 126 AI SGMII receiving - minus
The following figure shows the simplified block diagram for Ethernet application.
SGMII
MDI Ethernet
Module AR8033 RJ45
Transformer
Control
Figure 27: Simplified Block Diagram for Ethernet Application
The following figure shows a reference design of SGMII interface with PHY AR8033 application.
Module R1 10K AR8033

VDD_EXT
R2 1.5K
USIM2_VDD
EPHY_INT_N INT
EPHY_RST_N RSTN
Control SGMII_MDATA MDIO
SGMII_MCLK MDC
USIM2_VDD USIM2_VDD
Close to Module
SGMII_RX_P C1 0.1 μF SOP
SGMII_RX_M C2 0.1 μF
SON
SGMII Data
SGMII_TX_P 0.1 μF C3 SIP
0.1 μF C4
SGMII_TX_M SIN
Close to AR8033
Figure 28: Reference Circuit of SGMII Interface with PHY AR8033 Application
In order to enhance the reliability and availability in your applications, please follow the criteria below in
the Ethernet PHY circuit design:
 Keep SGMII data and control signals away from other sensitive circuits/signals such as RF circuits,
analog signals, etc., as well as noisy signals such as clock signals, DC-DC signals, etc.
 Keep the maximum trace length less than 10-inch and keep skew on the differential pairs less than
20mil.
 The differential impedance of SGMII data trace is 100 Ω ±10%, and the reference ground of the area
should be complete.
 Make sure the trace spacing between SGMII RX and TX is at least 3 times of the trace width, and the
same to the adjacent signal traces.
3.17. Network Status Indication
The network indication pins can be used to drive network status indication LEDs. The module provides
two pins which are NET_MODE and NET_STATUS. The following tables describe the pin definition and
logic level changes in different network status.
Table 20: Pin Definition of Network Connection Status/Activity Indication
1.8 V power domain

Indicate the module’s network
NET_MODE 5 DO Cannot be pulled up
registration mode
before startup
Indicate the module’s network activity
NET_STATUS 6 DO 1.8 V power domain
status
Table 21: Working State of Network Connection Status/Activity Indication
Pin Name Logic Level Changes Network Status
Always High Registered on LTE network

NET_MODE
Always Low Others
Flicker slowly (200 ms High/1800 ms Low) Network searching
Flicker slowly (1800 ms High/200 ms Low) Idle

NET_STATUS
Flicker quickly (125 ms High/125 ms Low) Data transfer is ongoing
Always High Voice calling
A reference circuit is shown in the following figure.
Module VBAT
2.2K
Network 4.7K
Indicator
47K
Figure 29: Reference Circuit of the Network Indication
3.18. STATUS
The STATUS pin is an open drain output for indicating the module’s operation status. It can be connected
to a GPIO of DTE with a pull-up resistor, or as LED indication circuit as below. When the module is turned
on normally, the STATUS will present the low state. Otherwise, the STATUS will present high-impedance
state.
Table 22: Pin Definition of STATUS
An external pull-up resistor

STATUS 61 OD Indicate the module’s operation status is required.
The following figure shows different circuit designs of STATUS, and you can choose either one according
to your application demands.
Module VDD_MCU Module VBAT
10K
2.2K
STATUS MCU_GPIO STATUS
Figure 30: Reference Circuits of STATUS
NOTE
The status pin cannot be used as indication of module shutdown status when VBAT power supply is
removed.
3.19. Behaviors of RI
AT+QCFG="risignaltype","physical" can be used to configure RI behaviors.
No matter on which port a URC is presented, the URC will trigger the behaviors of RI pin.
NOTE
URC can be outputted from UART port, USB AT port and USB modem port through configuration via
AT+QURCCFG. The default port is USB AT port.
The default behaviors of the RI are shown as below, and can be changed by AT+QCFG="urc/ri/ring".
See document [2] for details.
Table 23: Behaviors of RI
State Response
Idle RI keeps at high level
URC RI outputs 120 ms low pulse when a new URC returns
3.20. USB_BOOT Interface
EG25-G provides a USB_BOOT pin. You can pull up USB_BOOT to 1.8 V before VDD_EXT is powered
up, and the module will enter emergency download mode when it is powered on. In this mode, the module
supports firmware upgrade over USB interface.
Table 24: Pin Definition of USB_BOOT Interface
1.8 V power domain.

Force the module to enter Active high.
USB_BOOT 115 DI
emergency download mode It is recommended to reserve test
points.
The following figures show the reference circuit of USB_BOOT interface and timing sequence of entering
emergency download mode.
Module
VDD_EXT
Test points
4.7K
USB_BOOT
Close to test points
TVS
Figure 31: Reference Circuit of USB_BOOT Interface
NOTE 1
VBAT ≥ 500 ms
VH = 0.8 V
PWRKEY VIL≤ 0.5 V

About 100 ms
VDD_EXT USB_BOOT can be pulled up to 1.8 V before

VDD_EXT Is powered up, and the module will
enter emerge ncy download mode wh en i t is
powered on.
USB_BOOT
RESET_N
Figure 32: Timing Sequence for Entering Emergency Download Mode
NOTES
1. Please make sure that VBAT is stable before pulling down PWRKEY pin. It is recommended that the
time between powering up VBAT and pulling down PWRKEY pin is no less than 30 ms.
2. When using MCU to control module to enter the emergency download mode, please follow the above
timing sequence. It is not recommended to pull up USB_BOOT to 1.8 V before powering up VBAT.
Connect the test points as shown in Figure 31 can manually force the module to enter download
mode.
4 GNSS Receiver
EG25-G includes a fully integrated global navigation satellite system solution that supports Gen8C Lite of
Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS).
EG25-G supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate
via USB interface by default.
By default, EG25-G GNSS engine is switched off. It has to be switched on via AT command. For more
details about GNSS engine technology and configurations, see document [3].
4.2. GNSS Performance
The following table shows the GNSS performance of EG25-G.
Table 25: GNSS Performance
Parameter Description Conditions Typ. Unit
Cold start Autonomous -146 dBm

Sensitivity
Reacquisition Autonomous -156 dBm
(GNSS)
Tracking Autonomous -157 dBm
Autonomous 35 s
Cold start
@ open sky
XTRA enabled 15 s
TTFF
Autonomous 28 s
(GNSS) Warm start
@ open sky
XTRA enabled 3 s
Hot start Autonomous 2 s
@ open sky XTRA enabled 1.6 s
Accuracy Autonomous
CEP-50 < 2.5 m
(GNSS) @ open sky
NOTES
1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep
positioning for at least 3 minutes continuously).
2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock
within 3 minutes after loss of lock.
3. Cold start sensitivity: the minimum GNSS signal power at which the module can fix position
successfully within 3 minutes after executing cold start command.
4.3. Layout Guidelines
The following layout guidelines should be taken into account in your design.
 Maximize the distance among GNSS antenna, main antenna and Rx-diversity antenna.
 Digital circuits such as (U)SIM card, USB interface, camera module and display connector should be
kept away from the antennas.
 Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar
isolation and protection.
 Keep 50 Ω characteristic impedance for the ANT_GNSS trace.
See Chapter 5 for GNSS antenna reference design and antenna installation information.
5 Antenna Interfaces
EG25-G antenna interfaces include a main antenna interface, an Rx-diversity antenna interface which is
used to resist the fall of signals caused by high speed movement and multipath effect, and a GNSS
antenna interface. The impedance of the antenna ports is 50 Ω.
5.1. Main/Rx-diversity Antenna Interfaces
5.1.1. Pin Definition
The pin definition of main antenna and Rx-diversity antenna interfaces is shown below.
Table 26: Pin Definition of RF Antennas
ANT_MAIN 49 IO Main antenna 50 Ω impedance
50 Ω impedance.
ANT_DIV 35 AI Receive diversity antenna If unused, keep it
open.
5.1.2. Operating Frequency
Table 27: Module Operating Frequencies
3GPP Bands Transmit Receive Unit
GSM850 824–849 869–894 MHz
EGSM900 880–915 925–960 MHz
DCS1800 1710–1785 1805–1880 MHz
PCS1900 1850–1910 1930–1990 MHz
WCDMA B1 1920–1980 2110–2170 MHz
WCDMA B2 1850–1910 1930–1990 MHz
WCDMA B4 1710–1755 2110–2155 MHz
WCDMA B5 824–849 869–894 MHz
WCDMA B6 830–840 875–885 MHz
WCDMA B8 880–915 925–960 MHz
WCDMA B19 830–845 875–890 MHz
LTE-FDD B1 1920–1980 2110–2170 MHz
LTE-FDD B2 1850–1910 1930–1990 MHz
LTE-FDD B3 1710–1785 1805–1880 MHz
LTE-FDD B4 1710–1755 2110–2155 MHz
LTE-FDD B5 824–849 869–894 MHz
LTE-FDD B7 2500–2570 2620–2690 MHz
LTE-FDD B8 880–915 925–960 MHz
LTE-FDD B12 699–716 729–746 MHz
LTE-FDD B13 777–787 746–756 MHz
LTE-FDD B18 815–830 860–875 MHz
LTE-FDD B19 830–845 875–890 MHz
LTE-FDD B20 832–862 791–821 MHz
LTE-FDD B25 1850–1915 1930–1995 MHz
LTE-FDD B26 814–849 859–894 MHz
LTE-FDD B28 703–748 758–803 MHz
LTE-TDD B38 2570–2620 2570–2620 MHz
LTE-TDD B39 1880–1920 1880–1920 MHz
LTE-TDD B40 2300–2400 2300–2400 MHz
LTE-TDD B41 2496–2690 2496–2690 MHz
5.1.3. Reference Design of RF Antenna Interface
A reference design of ANT_MAIN and ANT_DIV antenna pads is shown as below. A π-type matching
circuit should be reserved for better RF performance. The capacitors are not mounted by default.
Main
Module Antenna
R1 0R
ANT_MAIN
C1 C2
NM NM
Diversity
Antenna
R2 0R
ANT_DIV
C3 C4
NM NM
Figure 33: Reference Circuit of RF Antenna Interface
NOTES
1. Keep a proper distance between the main antenna and the Rx-diversity antenna to improve the
receiving sensitivity.
2. For the operation of ANT_MAIN and ANT_DIV, see AT+QCFG="divctl" in document [9] for details.
3. Place the π-type matching components (R1&C1&C2, R2&C3&C4) as close to the antenna as
possible.
5.2. GNSS Antenna Interface
The following tables show the pin definition and frequency specification of GNSS antenna interface.
Table 28: Pin Definition of GNSS Antenna Interface
50 Ω impedance.
ANT_GNSS 47 AI GNSS antenna
Table 29: GNSS Frequency
Type Frequency Unit
GPS 1575.42 ±1.023 MHz
GLONASS 1597.5–1605.8 MHz
Galileo 1575.42 ±2.046 MHz
BeiDou 1561.098 ±2.046 MHz
QZSS 1575.42 MHz
A reference design of GNSS antenna is shown as below.
VDD
0.1 μF GNSS
10R
Antenna
Module
47 nH
0R 100 pF
ANT_GNSS
NM NM
Figure 34: Reference Circuit of GNSS Antenna
NOTES
1. An external LDO can be selected to supply power according to the active antenna requirement.
2. If the module is designed with a passive antenna, then the VDD circuit is not needed.
5.3. Reference Design of RF Layout
For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50 Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
height from the reference ground to the signal layer (H), and the space between RF traces and the ground
(S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance.
The following figures are reference designs of microstrip or coplanar waveguide with different PCB
structures.
Figure 35: Microstrip Design on a 2-layer PCB
Figure 36: Coplanar Waveguide Design on a 2-layer PCB
Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground)
Figure 38: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground)
In order to ensure RF performance and reliability, the following principles should be complied with in RF
layout design:
 Please use an impedance simulation tool to control the characteristic impedance of RF traces as
50 Ω.
 The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully
connected to ground.
 The distance between the RF pins and the RF connector should be as short as possible, and all the
right-angle traces should be changed to curved ones.
 There should be clearance area under the signal pin of the antenna connector or solder joint.
 The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around
RF traces and the reference ground could help to improve RF performance. The distance between
the ground vias and RF traces should be no less than two times the width of RF signal traces (2 × W).
For more details about RF layout, see document [6].
5.4. Antenna Installation
5.4.1. Antenna Requirement
The following table shows the requirements on main antenna, Rx-diversity antenna and GNSS antenna.
Table 30: Antenna Requirements
Type Requirements
Frequency range: 1559–1609 MHz

GNSS 1)
Polarization: RHCP or linear
VSWR: < 2 (Typ.)

Passive antenna gain: > 0 dBi
Active antenna noise figure: < 1.5 dB
Active antenna gain: > 0 dBi
Active antenna embedded LNA gain: < 17 dB
VSWR: ≤ 2
Efficiency: > 30%
Max. input power: 50 W
Input impedance: 50 Ω
Cable insertion loss: < 1 dB
(GSM850, EGSM900, WCDMA B5/B6/B8/B19,
GSM/WCDMA/LTE
LTE-FDD B5/B8/B12/B13/B18/B19/B20/B26/B28)
Cable insertion loss: < 1.5 dB
(DCS1800, PCS1900, WCDMA B1/B2/B4,
LTE-FDD B1/B2/B3/B4/B25, LTE-TDD B39)
Cable insertion loss < 2 dB
(LTE-FDD B7, LTE-TDD B38/B40/B41)
NOTE
1) It
is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of
active antenna may generate harmonics which will affect the GNSS performance.
5.4.2. Recommended RF Connector for Antenna Installation
If RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT connector

provided by Hirose.
Figure 39: Dimensions of the U.FL-R-SMT Connector (Unit: mm)
U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT.
Figure 40: Mechanicals of U.FL-LP Connectors
The following figure describes the space factor of mated connector.
Figure 41: Space Factor of Mated Connector (Unit: mm)
For more details, please visit http://www.hirose.com.
6 Electrical, Reliability and Radio

Characteristics
6.1. Absolute Maximum Ratings
Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are
listed in the following table.
Table 31: Absolute Maximum Ratings
Parameter Min. Max. Unit
VBAT_RF/VBAT_BB -0.3 4.7 V
USB_VBUS -0.3 5.5 V
Peak Current of VBAT_BB 0 0.8 A
Peak Current of VBAT_RF 0 1.8 A
Voltage at Digital Pins -0.3 2.3 V
Voltage at ADC0 0 VBAT_BB V
Voltage at ADC1 0 VBAT_BB V
6.2. Power Supply Ratings
Table 32: Power Supply Ratings
Parameter Description Conditions Min. Typ. Max. Unit
The actual input voltages

VBAT_BB and must be kept between the
3.3 3.8 4.3 V
VBAT_RF minimum and maximum
VBAT
values.
Voltage drop during Maximum power control
400 mV
burst transmission level on EGSM900.
Peak supply current
Maximum power control
IVBAT (during transmission 1.8 2.0 A
level on EGSM900.
slot)
USB connection
USB_VBUS 3.0 5.0 5.25 V
detection
6.3. Operating and Storage Temperatures
The operating and storage temperatures are listed in the following table.
Table 33: Operating and Storage Temperatures
Parameter Min. Typ. Max. Unit
Operating Temperature Range 1) -35 +25 +75 ºC
Extended Temperature Range 2) -40 +85 ºC
Storage Temperature Range -40 +90 ºC
NOTES
1) Within
1. operating temperature range, the module is 3GPP compliant.
2)
2. Within extended temperature range, the module remains the ability to establish and maintain a
voice, SMS, data transmission, etc. There is no unrecoverable malfunction. There are also no effects
on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce
in their value and exceed the specified tolerances. When the temperature returns to the normal
operating temperature levels, the module will meet 3GPP specifications again.
3. “*” means under development.
6.4. Current Consumption
Table 34: EG25-G Current Consumption
OFF state Power down 15 μA
AT+CFUN=0 (USB disconnected) 1.8 mA
GSM @ DRX=2 (USB disconnected) 2.9 mA
GSM @ DRX=5 (USB suspended) 2.5 mA
DCS @ DRX=2 (USB disconnected) 2.9 mA
DCS @ DRX=5 (USB disconnected) 2.4 mA
DCS @ DRX=5 (USB suspended) 2.5 mA
IVBAT DCS @ DRX=9 (USB disconnected) 2.3 mA

Sleep state
WCDMA @ PF=64 (USB disconnected) 2.7 mA
WCDMA @ PF=64 (USB suspended) 2.9 mA
LTE-FDD @ PF=32 (USB disconnected) 4.3 mA
LTE-FDD @ PF=64 (USB suspended) 3.4 mA
LTE-TDD @ PF=32 (USB disconnected) 4.6 mA
LTE-TDD @ PF=64 (USB suspended) 3.5 mA
EGSM @ DRX=5 (USB disconnected) 12 mA
EGSM @ DRX=5 (USB connected) 22 mA
WCDMA @ PF=64 (USB disconnected) 12 mA
WCDMA @ PF=64 (USB connected) 24 mA

Idle state
LTE-FDD @ PF=64 (USB disconnected) 18 mA
LTE-FDD @ PF=64 (USB connected) 29 mA
LTE-TDD @ PF=64 (USB disconnected) 18 mA
LTE-TDD @ PF=64 (USB connected) 29 mA
EGSM900 4DL/1UL @ 32.5 dBm 280 mA
EGSM900 3DL/2UL @ 32 dBm 530 mA
GSM850 4DL/1UL @ 32.5 dBm 285 mA
GSM850 3DL/2UL @ 32 dBm 532 mA

GPRS data
transfer GSM850 2DL/3UL @ 30 dBm 610 mA
(GNSS OFF)
DCS1800 4DL/1UL @ 29.5 dBm 162 mA
DCS1800 3DL/2UL @ 29 dBm 271 mA
DCS1800 2DL/3UL @ 27 dBm 365 mA
DCS1800 1DL/4UL @ 26 dBm 460 mA
PCS1900 4DL/1UL @ 29.5 dBm 170 mA
PCS1900 3DL/2UL @ 29 dBm 310 mA
PCS1900 2DL/3UL @ 27 dBm 400 mA
PCS1900 1DL/4UL @ 26 dBm 480 mA
GSM850 3DL/2UL @ 26 dBm 350- mA
EDGE data GSM850 1DL/4UL @ 23 dBm 573 mA

transfer
(GNSS OFF) DCS1800 4DL/1UL @ 26 dBm 200 mA
DCS1800 3DL/2UL @ 25 dBm 371 mA
DCS1800 2DL/3UL @ 23 dBm 522 mA
DCS1800 1DL/4UL @ 22 dBm 670 mA
PCS1900 4DL/1UL @ 26 dBm 210 mA
PCS1900 3DL/2UL @ 25 dBm 370 mA
PCS1900 2DL/3UL @ 23 dBm 525 mA
PCS1900 1DL/4UL @ 22 dBm 670 mA
WCDMA B1 HSDPA @ 21 dBm 546 mA
WCDMA B1 HSUPA @ 20.5 dBm 530 mA
WCDMA data WCDMA B2 HSUPA @ 20.5 dBm 560 mA

transfer
(GNSS OFF) WCDMA B4 HSDPA @ 21 dBm 565 mA
LTE-FDD B1 @ 22.3 dBm 743 mA

LTE data
transfer LTE-FDD B18 @ 22.3 dBm 710 mA
(GNSS OFF)
LTE-TDD B38 @ 22.3 dBm 490 mA
GSM EGSM900 PCL = 5 @ 32.5 dBm 290 mA

voice call EGSM900 PCL = 12 @ 19.5 dBm 140 mA
EGSM900 PCL = 19 @ 5.5 dBm 110 mA
GSM850 PCL = 5 @ 32.5 dBm 300 mA
GSM850 PCL = 12 @ 19.5 dBm 160 mA
GSM850 PCL = 19 @ 5.5 dBm 125 mA
DCS1800 PCL = 0 @ 29.5 dBm 180 mA
DCS1800 PCL = 7 @ 16.5 dBm 152 mA
DCS1800 PCL = 15 @ 0.5 dBm 135 mA
PCS1900 PCL = 0 @ 29.5 dBm 190 mA
PCS1900 PCL = 7 @ 16.5 dBm 162 mA
PCS1900 PCL = 15 @ 0.5 dBm 143 mA
WCDMA B1 @ 22.5 dBm 605 mA

WCDMA voice
call
Table 35: GNSS Current Consumption of EG25-G Module
Cold start @ Passive Antenna 47 mA

Searching
(AT+CFUN=0)
Lost state @ Passive Antenna 47 mA
IVBAT
Instrument Environment 25 mA
(GNSS)
Tracking
Open Sky @ Passive Antenna 30 mA
(AT+CFUN=0)
Open Sky @ Active Antenna 29 mA
6.5. RF Output Power
The following table shows the RF output power of EG25-G module.
Table 36: RF Output Power
Frequency Bands Max. Output Power Min. Output Power
GSM850/EGSM900 33 dBm ±2 dB 5 dBm ±5 dB
DCS1800/PCS1900 30 dBm ±2 dB 0 dBm ±5 dB
DCS1800/PCS1900 (8-PSK) 26 dBm ±3 dB 0 dBm ±5 dB
GSM850/EGSM900 (8-PSK) 27 dBm ±3 dB 5 dBm ±5 dB
WCDMA B1/B2/B4/B5/B6/B8/B19 24 dBm +1/ -3 dB < -49 dBm
LTE-FDD
B1/B2/B3/B4/B5/B7/B8/B12/B13/B18/B19/B20/B25/ 23 dBm ±2 dB < -39 dBm
B26/B28
LTE-TDD B38/B39/B40/B41 23 dBm ±2 dB < -39 dBm
NOTES
1. In GPRS 4 slots TX mode, the maximum output power is reduced by 3.0 dB. The design conforms to
the GSM specification as described in Chapter 13.16 of 3GPP TS 51.010-1.
2. EG25-G supports LTE B25, and Qorvo Phase 6 PAMiD QM77031 in the module does not actually
support LTE B25. Qorvo has confirmed that the SAW integrated in the PA can support LTE B2, but
B25 can work at the same frequency as B2. B25 is 5 MHz wider than B2. Therefore, the sensitivity of
the RX channels 8630–8689 is poor, and there is a big gap with the 3GPP standard. At a high
temperature of 75 °C, the maximum power of channels 26640–26689 will be reduced by about
2.5 dB.
6.6. RF Receiving Sensitivity
The following tables show the conducted RF receiving sensitivity of EG25-G module.
Table 37: EG25-G Conducted RF Receiving Sensitivity
Frequency Bands Primary Diversity SIMO 1) 3GPP (SIMO)
GSM900 -108 dBm NA NA -102 dBm
GSM850 -108 dBm NA NA -102 dBm
DCS1800 -107.4 dBm NA NA -102 dBm
PCS1900 -107.5 dBm NA NA -102 dBm
WCDMA B1 -108.2 dBm -108.5 dBm -109.2 dBm -106.7 dBm
WCDMA B2 -109.5 dBm -109 dBm -110 dBm -104.7 dBm
WCDMA B4 -109.5 dBm NA NA -106.7 dBm
WCDMA B5 -109.2 dBm -109.5 dBm -110.4 dBm -104.7 dBm
WCDMA B6 -109 dBm -109.5 dBm -110.5 dBm -106.7 dBm
WCDMA B8 -109.5 dBm NA NA -103.7 dBm
WCDMA B19 -109 dBm -109.5 dBm -110.1 dBm -106.7 dBm
LTE-FDD B1 (10 MHz) -97.3 dBm -98.3 dBm -99.5 dBm -96.3 dBm
LTE-FDD B2 (10 MHz) -98 dBm -99 dBm -99.9 dBm -94.3 dBm
LTE-FDD B5 (10 MHz) -98 dBm -98.5 dBm -99.9 dBm -94.3 dBm
LTE-FDD B18 (10 MHz) -98 dBm -99.4 dBm -100 dBm -96.3 dBm
LTE-FDD B25 (10 MHz) -98 dBm -98.4 dBm -100 dBm -92.8 dBm
LTE-TDD B38 (10 MHz) -97.5 dBm -97.5 dBm -99 dBm -96.3 dBm
LTE-TDD B39 (10 MHz) -98 dBm -98.2 dBm -99.5 dBm -96.3 dBm
LTE-TDD B40 (10 MHz) -97.8 dBm -97.5 dBm -99.2 dBm -96.3 dBm
LTE-TDD B41 (10 MHz) -97.3 dBm -97.4 dBm -99 dBm -94.3 dBm
NOTE
1)
SIMO is a smart antenna technology that uses a single antenna at the transmitter side and two
antennas at the receiver side, which can improve RX performance.
6.7. Electrostatic Discharge
The module is not protected against electrostatic discharge (ESD) in general. Consequently, it is subject
to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and
packaging procedures must be applied throughout the processing, handling and operation of any
application that incorporates the module.
The following table shows the module’s electrostatic discharge characteristics.
Table 38: Electrostatic Discharge Characteristics (25 ºC, 45% Relative Humidity)
Tested Interfaces Contact Discharge Air Discharge Unit
VBAT, GND ±10 ±16 kV
All Antenna Interfaces ±10 ±16 kV
Other Interfaces ±0.5 ±1 kV
6.8. Thermal Consideration
In order to achieve better performance of the module, it is recommended to comply with the following
principles for thermal consideration:
 On your PCB design, please keep placement of the module away from heating sources, especially
high power components such as ARM processor, audio power amplifier, power supply, etc.
 Do not place components on the opposite side of the PCB area where the module is mounted, in
order to facilitate adding of heatsink when necessary.
 Do not apply solder mask on the opposite side of the PCB area where the module is mounted, so as
to ensure better heat dissipation performance.
 The reference ground of the area where the module is mounted should be complete, and add ground
vias as many as possible for better heat dissipation.
 Make sure the ground pads of the module and PCB are fully connected.
 According to your application demands, the heatsink can be mounted on the top of the module, or the
opposite side of the PCB area where the module is mounted, or both of them.
 The heatsink should be designed with as many fins as possible to increase heat dissipation area.
Meanwhile, a thermal pad with high thermal conductivity should be used between the heatsink and
module/PCB.
The following shows two kinds of heatsink designs for reference and you can choose one or both of them
according to their application structure.
EG25-G Module Heatsink Heatsink
Thermal Pad
Shielding Cover
Application Board Application Board
Figure 42: Referenced Heatsink Design (Heatsink at the Top of the Module)
Thermal Pad
Thermal Pad
EG25-G Module
Heatsink
Heatsink
Application Board
Shielding Cover Application Board
Figure 43: Referenced Heatsink Design (Heatsink at the Backside of Your PCB)
NOTES
1. The module offers the best performance when the internal BB chip stays below 105 °C. When the
maximum temperature of the BB chip reaches or exceeds 105 °C, the module works normal but
provides reduced performance (such as RF output power, data rate, etc.). When the maximum BB
chip temperature reaches or exceeds 115 °C, the module will disconnect from the network, and it will
recover to network connected state after the maximum temperature falls below 115 °C. Therefore,
the thermal design should be maximally optimized to make sure the maximum BB chip temperature
always maintains below 105 °C. You can execute AT+QTEMP and get the maximum BB chip
temperature from the first returned value.
2. For more detailed guidelines on thermal design, see document [7].
7 Mechanical Dimensions
This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm,
and the dimensional tolerances are ±0.05 mm unless otherwise specified.
7.1. Mechanical Dimensions of the Module
(32+/-0.15)
2.4+/-0.2
(29+/-0.15)
0.8
Figure 44: Module Top and Side Dimensions
32±0.15
1.90 1.30 3.85
Pin 1
3.5
3.4
5.96 2.0
1.30 1.30
3.0 2.0
2.0
0.87
1.8 3.0 1.8
29±0.15
1.15
2.8
2.15
4.82
1.05 1.10 1.10

1.6
6.8
4.8
0.80
1.7
1.25
3.2 3.4 3.2 3.4 3.2
3.5
4.37
2.49
1.50
2.40
3.45 1.30
Figure 45: Module Bottom Dimensions (Bottom View)
NOTE
The package warpage level of the module conforms to the JEITA ED-7306 standard.
7.2. Recommended Footprint
32±0.15 3.45
3.85 1.30
1.90
Pin 1 3.5 0.80 3.4

0.80 2.0
1.30 1.30
2.0 3.0
2.0
4.80
1.8 3.0 1.8

29±0.15
0.5 0.5
2.8 4.80
Keepout area
1.10 1.10 4.80
0.5 0.5 0.8
0.80 4.80
1.25
1.25
3.4 3.2 3.4 3.2 3.4 3.2 6.8
3.5
24.7 1.9
1.50
1.30 1.50
Figure 46: Recommended Footprint (Top View)
NOTES
1. The keepout area should not be designed.

2. For easy maintenance of the module, please keep about 3 mm between the module and other
components in the host PCB.
7.3. Recommended Compatible Footprint
24.70
3.85 3.45 R0.40
1.90
Pin 1
3.40
1.10
2.00
3.00
2.00
1.10
7.80
2.00
4.80
29.0+/-0.15
1.80 3.00 1.80
0.50
2.80 0.50 4.80
Keepout area
0.50 0.50 4.80
15.60
4.80
3.20 3.40 3.20 3.40 3.20

3.50
3.40
1.90
2.50
1.00
1.30 0.80
32.0+/-0.15
Figure 47: Recommended Compatible Footprint (Top View)
NOTES
1. The keepout area should not be designed.

2. For easy maintenance of the module, please keep about 3 mm between the module and other
components in the host PCB.
3. LGA form factor is used for EG25-G module, while LCC is recommended only in the compatible
design with EC25 series/EC21 series/EC20 R2.1/EG25-G/UC200T series modules. If you use LCC
form factor, you should choose the stencil matched with LGA package instead of that matched with
LCC package. For more details, see document [4].
7.4. Design Effect Drawings of the Module
Figure 48: Top View of the Module
Figure 49: Bottom View of the Module
NOTE
These are renderings of EG25-G module. For authentic appearance, see the module that you receive
from Quectel.
8 Storage, Manufacturing and

Packaging
8.1. Storage
EG25-G is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage
requirements are shown below.
1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity
should be 35%–60%.
2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition.
3. The floor life of the module is 168 hours 1) in a plant where the temperature is 23 ±5 °C and relative
humidity is below 60%. After the vacuum-sealed packaging is removed, the module must be
processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the
module should be stored in an environment where the relative humidity is less than 10% (e.g. a drying
cabinet).
4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under
the following circumstances:
 The module is not stored in Recommended Storage Condition;

 Violation of the third requirement above occurs;
 Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;
 Before module repairing.
5. If needed, the pre-baking should follow the requirements below:
 The module should be baked for 8 hours at 120 ±5 °C;

 All modules must be soldered to PCB within 24 hours after the baking, otherwise they should be
put in a dry environment such as in a drying oven.
NOTES
1)
1. This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033.
2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules
to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or
the relative moisture is over 60%, it is recommended to start the solder reflow process within 24
hours after the package is removed. And do not remove the package of tremendous modules if they
are not ready for soldering.
3. Please take the module out of the packaging and put it on high-temperature resistant fixtures before
the baking. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for baking procedure.
8.2. Manufacturing and Soldering
Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the
stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly
so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the
thickness of stencil for the module is recommended to be 0.13–0.15 mm. For more details, see
document [4].
It is suggested that the peak reflow temperature is 238–246 ºC, and the absolute maximum reflow
temperature is 246 ºC. To avoid damage to the module caused by repeated heating, it is strongly
recommended that the module should be mounted after reflow soldering for the other side of PCB has
been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and
related parameters are shown below.
Temp. (°C)
Reflow Zone
Max slope: Cooling down slope:
2 to 3°C/s C -1.5 to -3°C/s
246
238
220
B D
200
Soak Zone
150 A
100
Max slope: 1 to 3°C/s
Figure 50: Reflow Soldering Thermal Profile
Table 39: Recommended Thermal Profile Parameters
Factor Recommendation
Soak Zone
Max. slope 1–3 °C/s
Soak time (between A and B: 150 °C and 200 °C) 70–120 s
Reflow Zone
Max. slope 2–3 °C/s
Reflow time (D: over 220 °C) 45–70 s
Max. temperature 238–246 °C
Cooling down slope -1.5 to -3 °C/s
Reflow Cycle
Max. reflow cycle 1
8.3. Packaging
EG25-G is packaged in tap and reel carriers. Each reel is 11.88m long and contains 250 modules. The
figure below shows the package details, measured in mm.
1.75±0.1
44.00±0.1 .1
±0 0.35±0.05
2.00±0.1 4.00±0.1 50
1.
20.20±0.15
29.3±0.15
30.3±0.15
30.3±0.15
44.00±0.3
32.5±0.15 4.2±0.15
33.5±0.15 3.1±0.15
32.5±0.15
33.5±0.15
Figure 51: Tape Specifications
48.5
Cover tape
13
100 Direction of feed
44.5+0.20
-0.00
Figure 52: Reel Specifications
1083
Carrier tape Carrier tape

packing module unfolding
Figure 53: Tape and Reel Directions
9 Appendix A References
Table 40: Related Documents
SN Document Name Remark
Power management application note

Quectel_EC2x&EGxx_Power_Management_ for EC25 series, EC21 series, EC20
[1]
Application_Note R2.1, EG95 series, EG91 series,
EG21-G and EG25-G modules
AT commands manual for EC2x
[2] Quectel_LTE_Standard_AT_Commands_Manual series, EG9x series, EG2x-G and
EM05 series modules
GNSS application note for EC2x
Quectel_EC2x&EG9x&EG2x-G&EM05_Series_GNSS
[3] series, EG9x series, EG2x-G and
_Application_Note
EM05 series modules
[4] Quectel_Module_Secondary_SMT_User_Guide Module secondary SMT user guide
[5] Quectel_EG25-G_Reference_Design EG25-G reference design
Quectel_EC2x&EG2x-G_Series_PCB_Design_ PCB design guideline for EC2x

[6]
Guideline series and EG2x-G modules
[7] Quectel_Module_Thermal_Design_Guide Module thermal design guide
UMTS&LTE EVB user guide for

[8] Quectel_UMTS&LTE_EVB_User_Guide
UMTS&LTE modules
QCFG AT commands manual for
Quectel_LTE_Standard_QCFG_AT_Commands
[9] EC2x series, EG9x series, EG2x-G
_Manual
and EM05 series modules
Table 41: Terms and Abbreviations
Abbreviation Description
AMR Adaptive Multi-rate
bps Bits Per Second
CHAP Challenge Handshake Authentication Protocol
CS Coding Scheme
CSD Circuit Switched Data
CTS Clear To Send
DC-HSPA+ Dual-carrier High Speed Packet Access
DFOTA Delta Firmware Upgrade Over The Air
DL Downlink
DTR Data Terminal Ready
DTX Discontinuous Transmission
EFR Enhanced Full Rate
ESD Electrostatic Discharge
FDD Frequency Division Duplex
FR Full Rate
GLONASS Global Navigation Satellite System (Russia)
GMSK Gaussian Minimum Shift Keying
GNSS Global Navigation Satellite System
GPS Global Positioning System
GSM Global System for Mobile Communications
HR Half Rate
HSPA High Speed Packet Access
HSDPA High Speed Downlink Packet Access
HSUPA High Speed Uplink Packet Access
I/O Input/Output
Inorm Normal Current
LED Light Emitting Diode
LNA Low Noise Amplifier
LTE Long Term Evolution
MIMO Multiple Input Multiple Output
MO Mobile Originated
MS Mobile Station (GSM engine)
MSL Moisture Sensitivity Level
MT Mobile Terminated
PAP Password Authentication Protocol
PCB Printed Circuit Board
PDU Protocol Data Unit
PPP Point-to-Point Protocol
QAM Quadrature Amplitude Modulation
QPSK Quadrature Phase Shift Keying
RF Radio Frequency
RHCP Right Hand Circularly Polarized
Rx Receive
SGMII Serial Gigabit Media Independent Interface
SIMO Single Input Multiple Output
SMS Short Message Service
TDD Time Division Duplexing
TDMA Time Division Multiple Access
TD-SCDMA Time Division-Synchronous Code Division Multiple Access
TX Transmitting Direction
UL Uplink
UMTS Universal Mobile Telecommunications System
URC Unsolicited Result Code
(U)SIM (Universal) Subscriber Identity Module
VLAN Virtual Local Area Network
Vmax Maximum Voltage Value
Vnorm Normal Voltage Value
Vmin Minimum Voltage Value
VIHmax Maximum Input High Level Voltage Value
VIHmin Minimum Input High Level Voltage Value
VILmax Maximum Input Low Level Voltage Value
VILmin Minimum Input Low Level Voltage Value
VImax Absolute Maximum Input Voltage Value
VImin Absolute Minimum Input Voltage Value
VOHmax Maximum Output High Level Voltage Value
VOHmin Minimum Output High Level Voltage Value
VOLmax Maximum Output Low Level Voltage Value
VOLmin Minimum Output Low Level Voltage Value
VSWR Voltage Standing Wave Ratio
WCDMA Wideband Code Division Multiple Access
WLAN Wireless Local Area Network

10Appendix B GPRS Coding Schemes

Table 42: Description of Different Coding Schemes
Scheme CS-1 CS-2 CS-3 CS-4
Code Rate 1/2 2/3 3/4 1
USF 3 3 3 3
Pre-coded USF 3 6 6 12
Radio Block excl.USF and BCS 181 268 312 428
BCS 40 16 16 16
Tail 4 4 4 -
Coded Bits 456 588 676 456
Punctured Bits 0 132 220 -
Data Rate Kb/s 9.05 13.4 15.6 21.4

11Appendix C GPRS Multi-slot Classes

Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot
classes are product dependent, and determine the maximum achievable data rates in both the uplink and
downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots,
while the second number indicates the amount of uplink timeslots. The active slots determine the total
number of slots the GPRS device can use simultaneously for both uplink and downlink communications.
The description of different multi-slot classes is shown in the following table.
Table 43: GPRS Multi-slot Classes
Multi-slot Class Downlink Slots Uplink Slots Active Slots
1 1 1 2
2 2 1 3
3 2 2 3
4 3 1 4
5 2 2 4
6 3 2 4
7 3 3 4
8 4 1 5
9 3 2 5
10 4 2 5
11 4 3 5
12 4 4 5
13 3 3 NA

14 4 4 NA
15 5 5 NA
16 6 6 NA
17 7 7 NA
18 8 8 NA
19 6 2 NA
20 6 3 NA
21 6 4 NA
22 6 4 NA
23 6 6 NA
24 8 2 NA
25 8 3 NA
26 8 4 NA
27 8 4 NA
28 8 6 NA
29 8 8 NA
30 5 1 6
31 5 2 6
32 5 3 6
33 5 4 6

12Appendix D EDGE Modulation and

Coding Schemes
Table 44: EDGE Modulation and Coding Schemes
Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslots 4 Timeslots
MCS-1 GMSK C 8.80 kbps 17.60 kbps 35.20 kbps
MCS-2 GMSK B 11.2 kbps 22.4 kbps 44.8 kbps
MCS-3 GMSK A 14.8 kbps 29.6 kbps 59.2 kbps
MCS-4 GMSK C 17.6 kbps 35.2 kbps 70.4 kbps
MCS-5 8-PSK B 22.4 kbps 44.8 kbps 89.6 kbps
MCS-6 8-PSK A 29.6 kbps 59.2 kbps 118.4 kbps
MCS-7 8-PSK B 44.8 kbps 89.6 kbps 179.2 kbps

Quectel EG25-G Hardware Design V1.4

Uploaded by

Copyright:

Available Formats

Quectel EG25-G Hardware Design V1.4

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Quectel EG25-G Hardware Design V1.4

Uploaded by

Copyright:

Available Formats

EG25-G

LTE Standard Module Series

Quectel Wireless Solutions Co., Ltd.

Or our local office. For more information, please visit:

For technical support, or to report documentation errors, please visit:

About the Document

Version Date Author Description

1.2 2019-07-25 Lorry XU Updated recommended footprint (Chapter 7.2)

Ethan SHAN diversity (Chapter 5.3.1).

About the Document ................................................................................................................................... 3

2 Product Concept ................................................................................................................................ 14

3 Application Interfaces ....................................................................................................................... 19

3.14.1. WLAN Interface .............................................................................................................. 57

4 GNSS Receiver ................................................................................................................................... 65

6 Electrical, Reliability and Radio Characteristics ............................................................................ 76

7 Mechanical Dimensions .................................................................................................................... 88

8 Storage, Manufacturing and Packaging .......................................................................................... 93

10 Appendix B GPRS Coding Schemes ............................................................................................. 101

Table 42: Description of Different Coding Schemes ................................................................................ 101

Figure 1: Functional Diagram ..................................................................................................................... 18

1.1. Safety Information

Wireless devices may cause interference on sensitive medical equipment, so

The cellular terminal or mobile contains a transceiver. When it is ON, it receives

In locations with explosive or potentially explosive atmospheres, obey all posted

2.1. General Description

EG25-G is an LTE-FDD/LTE-TDD/WCDMA/GSM wireless communication module with receive diversity.

Table 1: Supported Frequency Bands and GNSS Function of EG25-G Module

GSM 850/900/1800/1900 MHz

GNSS Function (Optional) GPS, GLONASS, BeiDou, Galileo, QZSS

Digital Audio (PCM) Supported

2.2. Key Features

The following table describes the detailed features of EG25-G module.

Table 2: Key Features of EG25-G Module

Supply voltage: 3.3–4.3 V

Support EDGE multi-slot class 33 (33 by default)

(U)SIM Interface Support USIM/SIM card: 1.8 V, 3.0 V

Support one digital audio interface: PCM interface

SD Card Interface Support SD 3.0 protocol

SGMII Interface Support 10 Mbps/100 Mbps/1000 Mbps Ethernet work mode

Support maximum 150 Mbps (DL)/50 Mbps (UL) for 4G network

Rx-diversity Support LTE/WCDMA Rx-diversity

Gen8C Lite of Qualcomm

Firmware Upgrade USB interface or DFOTA

2.3. Functional Diagram

ANT_MAIN ANT_GNSS ANT_DIV

PAM SAW Switch

VDD_EXT USB (U)SIM PCM I2C UARTs SGMII WLAN BT GPIOs SD

Figure 1: Functional Diagram

2.4. Evaluation Board

3.1. General Description

3.2. Pin Assignment

The following figure shows the pin assignment of EG25-G module.

Power Pins Signal Pins WLAN Pins RESERVED Pins

GND Pins Bluetooth Pins SGMII Pins

Figure 2: Pin Assignment (Top View)

function is under development.

3.3. Pin Description

The following tables show the pin definition of EG25-G module.

Table 3: I/O Parameters Definition