74HC HCT165

74HC165; 74HCT165
8-bit parallel-in/serial out shift register

Rev. 7 — 1 September 2021 Product data sheet
1. General description
The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device
features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary
serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is
loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at
DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of
the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This
enables the device to be used in HIGH-to-LOW level shifting applications.
2. Features and benefits

• Wide supply voltage range from 2.0 to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Asynchronous 8-bit parallel load
• Synchronous serial input
• Input levels:
• For 74HC165: CMOS level
• For 74HCT165: TTL level
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Applications
• Parallel-to-serial data conversion
Nexperia 74HC165; 74HCT165
4. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC165D -40 °C to +125 °C SO16 plastic small outline package; 16 leads; SOT109-1
74HCT165D body width 3.9 mm
74HC165PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
74HCT165PW body width 4.4 mm
74HC165BQ -40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
74HCT165BQ very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
5. Functional diagram
SRG8
1 C2[LOAD]
G1[SHIFT]
15 ≥1
10 2 1 C3/
DS
11
D0 10
12 3D
D1 11
13 2D
D2
12
14 2D
D3
3 13
D4
4 14
D5
5 9 3
D6 Q7
6 7 4
D7 Q7
1 5
PL
9
CP CE 6
7
2 15
mna985 mna986
Fig. 1. Logic symbol Fig. 2. IEC logic symbol
11 12 13 14 3 4 5 6
D0 D1 D2 D3 D4 D5 D6 D7
1 PL
10 DS
Q7 9
2 CP 8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT Q7 7
15 CE
mna992
Fig. 3. Functional diagram
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 7 — 1 September 2021 2 / 18

6. Pinning information
6.1. Pinning
74HC165
74HCT165
16 VCC
terminal 1
PL
74HC165 index area
74HCT165
1
CP 2 15 CE
PL 1 16 VCC
D4 3 14 D3
CP 2 15 CE D5 4 13 D2
D6 5 12 D1
D4 3 14 D3
D7 6 GND(1) 11 D0
D5 4 13 D2
Q7 7 10 DS
D6 5 12 D1
9
GND
Q7
D7 6 11 D0 001aah565
Q7 7 10 DS Transparent top view
(1) This is not a ground pin. There is no electrical or

GND 8 9 Q7
mechanical requirement to solder the pad. In case
001aah564 soldered, the solder land should remain floating or
connected to GND.
Fig. 4. Pin configuration SOT109-1 (SO16) and
SOT403-1 (TSSOP16) Fig. 5. Pin configuration SOT763-1 (DHVQFN16)
6.2. Pin description

Table 2. Pin description
Symbol Pin Description
PL 1 asynchronous parallel load input (active LOW)
CP 2 clock input (LOW-to-HIGH edge-triggered)
Q7 7 complementary output from the last stage
GND 8 ground (0 V)
Q7 9 serial output from the last stage
DS 10 serial data input
D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn)
CE 15 clock enable input (active LOW)
VCC 16 positive supply voltage

7. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care; ↑ = LOW-to-HIGH clock transition.
Operating modes Inputs Qn registers Outputs
PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7
parallel load L X X X L L L to L L H
L X X X H H H to H H L
serial shift H L ↑ l X L q0 to q5 q6 q6
H L ↑ h X H q0 to q5 q6 q6
H ↑ L l X L q0 to q5 q6 q6
H ↑ L h X H q0 to q5 q6 q6
hold "do nothing" H H X X X q0 q1 to q6 q7 q7
H X H X X q0 q1 to q6 q7 q7
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
inhibit serial shift

mna993
load
Fig. 6. Timing diagram

8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7 V
IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA
IO output current -0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC supply current - 50 mA
IGND ground current -50 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation Tamb = -40 °C to +125 °C [2] - 500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C.
9. Recommended operating conditions

Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC165 74HCT165 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VI input voltage 0 - VCC 0 - VCC V
VO output voltage 0 - VCC 0 - VCC V
Tamb ambient temperature -40 - +125 -40 - +125 °C
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
10. Static characteristics

Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit
+85 °C +125 °C
Min Typ Max Min Max Min Max
74HC165
VIH HIGH-level input VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
voltage VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level input VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
voltage VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V


+85 °C +125 °C
VOH HIGH-level VI = VIH or VIL
output voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level VI = VIH or VIL
output voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA
current
ICC supply current VI = VCC or GND; IO = 0 A; - - 8.0 - 80 - 160 μA
VCC = 6.0 V
CI input - 3.5 - - - - - pF
capacitance
74HCT165
VIH HIGH-level input VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
voltage
VIL LOW-level input VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
voltage
VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V
IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level VI = VIH or VIL
output voltage IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA
current
ICC supply current VI = VCC or GND; IO = 0 A; - - 8.0 - 80 - 160 μA
VCC = 6.0 V
ΔICC additional supply per input pin; VI = VCC - 2.1 V;
current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
Dn and DS inputs - 35 126 - 157.5 - 171.5 μA
CP, CE, and PL inputs - 65 234 - 292.5 - 318.5 μA
CI input - 3.5 - - - - - pF
capacitance

11. Dynamic characteristics

Table 7. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V);
CL = 50 pF unless otherwise specified; for test circuit, see Fig. 12
+85 °C +125 °C
74HC165
tpd propagation CP or CE to Q7, Q7; see Fig. 7 [1]
delay VCC = 2.0 V - 52 165 - 205 - 250 ns
VCC = 4.5 V - 19 33 - 41 - 50 ns
VCC = 6.0 V - 15 28 - 35 - 43 ns
VCC = 5.0 V; CL = 15 pF - 16 - - - - - ns
PL to Q7, Q7; see Fig. 8
VCC = 2.0 V - 50 165 - 205 - 250 ns
VCC = 4.5 V - 18 33 - 41 - 50 ns
VCC = 6.0 V - 14 28 - 35 - 43 ns
VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns
D7 to Q7, Q7; see Fig. 9
VCC = 2.0 V - 36 120 - 150 - 180 ns
VCC = 4.5 V - 13 24 - 30 - 36 ns
VCC = 6.0 V - 10 20 - 26 - 31 ns
VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns
tt transition time Q7, Q7 output; see Fig. 7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tW pulse width CP input HIGH or LOW;
see Fig. 7
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
PL input LOW; see Fig. 8
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
trec recovery time PL to CP, CE; see Fig. 8
VCC = 2.0 V 100 22 - 125 - 150 - ns
VCC = 4.5 V 20 8 - 25 - 30 - ns
VCC = 6.0 V 17 6 - 21 - 26 - ns


+85 °C +125 °C
tsu set-up time DS to CP, CE; see Fig. 10
VCC = 2.0 V 80 11 - 100 - 120 - ns
VCC = 4.5 V 16 4 - 20 - 24 - ns
VCC = 6.0 V 14 3 - 17 - 20 - ns
CE to CP and CP to CE;
see Fig. 10
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
Dn to PL; see Fig. 11
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
th hold time DS to CP, CE and Dn to PL;
see Fig. 10
VCC = 2.0 V 5 2 - 5 - 5 - ns
VCC = 4.5 V 5 2 - 5 - 5 - ns
VCC = 6.0 V 5 2 - 5 - 5 - ns
see Fig. 10
VCC = 2.0 V 5 -17 - 5 - 5 - ns
VCC = 4.5 V 5 -6 - 5 - 5 - ns
VCC = 6.0 V 5 -5 - 5 - 5 - ns
fmax maximum CP input; see Fig. 7
frequency VCC = 2.0 V 6 17 - 5 - 4 - MHz
VCC = 4.5 V 30 51 - 24 - 20 - MHz
VCC = 6.0 V 35 61 - 28 - 24 - MHz
VCC = 5.0 V; CL = 15 pF - 56 - - - - - MHz
CPD power per package; VI = GND to VCC [3] - 35 - - - - - pF
dissipation
capacitance
74HCT165
tpd propagation CE, CP to Q7, Q7; see Fig. 7 [1]
delay VCC = 4.5 V - 17 34 - 43 - 51 ns
VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns
PL to Q7, Q7; see Fig. 8
VCC = 4.5 V - 20 40 - 50 - 60 ns
VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns
D7 to Q7, Q7; see Fig. 9
VCC = 4.5 V - 14 28 - 35 - 42 ns
VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns


+85 °C +125 °C
tt transition time Q7, Q7 output; see Fig. 7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tW pulse width CP input; see Fig. 7
VCC = 4.5 V 16 6 - 20 - 24 - ns
PL input; see Fig. 8
VCC = 4.5 V 20 9 - 25 - 30 - ns
trec recovery time PL to CP, CE; see Fig. 8
VCC = 4.5 V 20 8 - 25 - 30 - ns
tsu set-up time DS to CP, CE; see Fig. 10
VCC = 4.5 V 20 2 - 25 - 30 - ns
see Fig. 10
VCC = 4.5 V 20 7 - 25 - 30 - ns
Dn to PL; see Fig. 11
VCC = 4.5 V 20 10 - 25 - 30 - ns
th hold time DS to CP, CE and Dn to PL;
see Fig. 10
VCC = 4.5 V 7 -1 - 9 - 11 - ns
see Fig. 10
VCC = 4.5 V 0 -7 - 0 - 0 - ns
fmax maximum CP input; see Fig. 7
frequency VCC = 4.5 V 26 44 - 21 - 17 - MHz
VCC = 5.0 V; CL = 15 pF - 48 - - - - - MHz
CPD power per package; [3] - 35 - - - - - pF
dissipation VI = GND to VCC - 1.5 V
capacitance
[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
2 2
PD = CPD × VCC × fi + Σ (CL × VCC × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
2
Σ (CL × VCC × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.

11.1. Waveforms and test circuit

1/fmax
VI
CP or CE input VM
GND
tW
tPHL tPLH
VOH
90 % 90 %
Q7 or Q7 output VM
VOL 10 % 10 %
tTHL tTLH
mna987
Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the
maximum clock frequency and the output transition times
VI
PL input VM
GND
tW trec
VI
CE, CP input VM
GND
tPHL
VOH
Q7 or Q7 output VM
VOL
mna988

Fig. 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel
load to clock (CP) and clock enable (CE) recovery time
VI
D7 input VM
GND
tPLH tPHL
VOH
Q7 output VM
VOL
tPHL tPLH
VOH
Q7 output VM
VOL
mna989

Fig. 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW

VI (1)
CP, CE input VM
GND
th th
tsu tsu
VI
DS input VM
GND
tsu
VI tW
CP, CE input VM
GND mna990
(1) CE may change only from HIGH-to-LOW while CP is LOW.

The shaded areas indicate when the input is permitted to change for predictable output performance
Fig. 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs,
from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable
input (CE)
VI
Dn input VM VM
GND
tsu th tsu th
VI
PL input VM VM
GND mna991

Fig. 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
Table 8. Measurement points

Type Input Output
VI VM VM
74HC165 VCC 0.5VCC 0.5VCC
74HCT165 3V 1.3 V 1.3 V

tW
VI
90 %
negative
pulse VM VM
10 %
0V
tf tr
tr tf
VI
90 %
positive
pulse VM VM
10 %
0V
tW
VCC VCC
VI VO RL S1
G DUT open
RT CL
001aad983
Test data is given in Table 9.

Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig. 12. Test circuit for measuring switching times
Table 9. Test data

Type Input Load S1 position
VI tr, tf CL RL tPHL, tPLH
74HC165 VCC 6 ns 15 pF, 50 pF 1 kΩ open
74HCT165 3V 6 ns 15 pF, 50 pF 1 kΩ open

12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D E A
X
y HE v M A
16 9
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 8 L
e w M detail X
bp
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8
o
o
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT109-1 076E07 MS-012
03-02-19
Fig. 13. Package outline SOT109-1 (SO16)

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
D E A
X
y HE v M A
16 9
Q
A2 (A 3 )
A
A1
pin 1 index
θ
Lp
L
1 8
detail X
w M
e bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.
mm
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8o
1.1 0.25 0.65 1 0.2 0.13 0.1
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.06 0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

ISSUE DATE
99-12-27
SOT403-1 MO-153
03-02-18
Fig. 14. Package outline SOT403-1 (TSSOP16)

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm SOT763-1
D B A
A
A1
E c
terminal 1 detail X
index area
terminal 1 C
e1
index area
e b v M C A B y1 C y
w M C
2 7
1 8
Eh e
16 9
15 10
Dh
X
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT
max.
A1 b c D (1) Dh E (1) Eh e e1 L v w y y1
0.05 0.30 3.6 2.15 2.6 1.15 0.5

mm 1 0.2 0.5 2.5 0.1 0.05 0.05 0.1
0.00 0.18 3.4 1.85 2.4 0.85 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

ISSUE DATE
02-10-17
SOT763-1 --- MO-241 ---
03-01-27
Fig. 15. Package outline SOT763-1 (DHVQFN16)

13. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
14. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT165 v.7 20210901 Product data sheet - 74HC_HCT165 v.6
Modifications: • Section 2 updated.
• Type numbers 74HC165DB and 74HCT165DB (SOT338-1/SSOP16) removed.
Modifications: • Table 4: Derating values for Ptot total power dissipation updated.
Modifications: • Table 7: Hold time for 74HC165 has been updated.
• The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
Modifications: • Type numbers 74HC165N and 74HCT165N (SOT38-4) removed.
74HC_HCT165 v.3 20080314 Product data sheet - 74HC_HCT165_CNV v.2
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Package SOT763-1 (DHVQFN16) added to Section 4 and Section 12.
• Family data added, see Section 10
74HC_HCT165_CNV v.2 December Product specification - -
1990

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such equipment or applications and therefore such inclusion and/or use is at
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Quick reference data — The Quick reference data is an extract of the
Data sheet status product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
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[2] The term 'short data sheet' is explained in section "Definitions". or problem which is based on any weakness or default in the customer’s
[3] The product status of device(s) described in this document may have applications or products, or the application or use by customer’s third party
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multiple devices. The latest product status information is available on customer’s applications and products using Nexperia products in order to
the internet at https://www.nexperia.com. avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Definitions Limiting values — Stress above one or more limiting values (as defined in
Draft — The document is a draft version only. The content is still under the Absolute Maximum Ratings System of IEC 60134) will cause permanent
internal review and subject to formal approval, which may result in damage to the device. Limiting values are stress ratings only and (proper)
modifications or additions. Nexperia does not give any representations or operation of the device at these or any other conditions above those
warranties as to the accuracy or completeness of information included herein given in the Recommended operating conditions section (if present) or the
and shall have no liability for the consequences of use of such information. Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
Short data sheet — A short data sheet is an extract from a full data sheet
the quality and reliability of the device.
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain Terms and conditions of commercial sale — Nexperia products are
detailed and full information. For detailed and full information see the relevant sold subject to the general terms and conditions of commercial sale, as
full data sheet, which is available on request via the local Nexperia sales published at http://www.nexperia.com/profile/terms, unless otherwise agreed
office. In case of any inconsistency or conflict with the short data sheet, the in a valid written individual agreement. In case an individual agreement is
full data sheet shall prevail. concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
Product specification — The information and data provided in a Product
terms and conditions with regard to the purchase of Nexperia products by
data sheet shall define the specification of the product as agreed between
customer.
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be No offer to sell or license — Nothing in this document may be interpreted
valid in which the Nexperia product is deemed to offer functions and qualities or construed as an offer to sell products that is open for acceptance or the
beyond those described in the Product data sheet. grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
Disclaimers may be subject to export control regulations. Export might require a prior
Limited warranty and liability — Information in this document is believed authorization from competent authorities.
to be accurate and reliable. However, Nexperia does not give any
Non-automotive qualified products — Unless this data sheet expressly
representations or warranties, expressed or implied, as to the accuracy
states that this specific Nexperia product is automotive qualified, the
or completeness of such information and shall have no liability for the
product is not suitable for automotive use. It is neither qualified nor tested in
consequences of use of such information. Nexperia takes no responsibility
accordance with automotive testing or application requirements. Nexperia
for the content in this document if provided by an information source outside
accepts no liability for inclusion and/or use of non-automotive qualified
of Nexperia.
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
In the event that customer uses the product for design-in and use in
special or consequential damages (including - without limitation - lost
automotive applications to automotive specifications and standards,
profits, lost savings, business interruption, costs related to the removal
customer (a) shall use the product without Nexperia’s warranty of the
or replacement of any products or rework charges) whether or not such
product for such automotive applications, use and specifications, and (b)
damages are based on tort (including negligence), warranty, breach of
whenever customer uses the product for automotive applications beyond
contract or any other legal theory.
Nexperia’s specifications such use shall be solely at customer’s own risk,
Notwithstanding any damages that customer might incur for any reason and (c) customer fully indemnifies Nexperia for any liability, damages or failed
whatsoever, Nexperia’s aggregate and cumulative liability towards customer product claims resulting from customer design and use of the product for
for the products described herein shall be limited in accordance with the automotive applications beyond Nexperia’s standard warranty and Nexperia’s
Terms and conditions of commercial sale of Nexperia. product specifications.
Right to make changes — Nexperia reserves the right to make changes Translations — A non-English (translated) version of a document is for
to information published in this document, including without limitation reference only. The English version shall prevail in case of any discrepancy
specifications and product descriptions, at any time and without notice. This between the translated and English versions.
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical Notice: All referenced brands, product names, service names and
systems or equipment, nor in applications where failure or malfunction trademarks are the property of their respective owners.
of an Nexperia product can reasonably be expected to result in personal

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description............................................................. 3
7. Functional description................................................. 4
8. Limiting values............................................................. 5
9. Recommended operating conditions..........................5
10. Static characteristics..................................................5
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit.......................................10
12. Package outline........................................................ 13
13. Abbreviations............................................................ 16
14. Revision history........................................................16
15. Legal information......................................................17
© Nexperia B.V. 2021. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: [email protected]
Date of release: 1 September 2021

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8-bit parallel-in/serial out shift register

2. Features and benefits

Fig. 1. Logic symbol Fig. 2. IEC logic symbol

Fig. 3. Functional diagram

Product data sheet Rev. 7 — 1 September 2021 2 / 18

Q7 7 10 DS Transparent top view

(1) This is not a ground pin. There is no electrical or

6.2. Pin description

Product data sheet Rev. 7 — 1 September 2021 3 / 18

inhibit serial shift

Fig. 6. Timing diagram

Product data sheet Rev. 7 — 1 September 2021 4 / 18

9. Recommended operating conditions

10. Static characteristics

Product data sheet Rev. 7 — 1 September 2021 5 / 18

Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit

Product data sheet Rev. 7 — 1 September 2021 6 / 18

11. Dynamic characteristics

Product data sheet Rev. 7 — 1 September 2021 7 / 18

Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit

Product data sheet Rev. 7 — 1 September 2021 8 / 18

Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit

[1] tpd is the same as tPHL and tPLH.

Product data sheet Rev. 7 — 1 September 2021 9 / 18

11.1. Waveforms and test circuit

Measurement points are given in Table 8.

Measurement points are given in Table 8.

Measurement points are given in Table 8.

Product data sheet Rev. 7 — 1 September 2021 10 / 18

(1) CE may change only from HIGH-to-LOW while CP is LOW.

Measurement points are given in Table 8.

Table 8. Measurement points

Product data sheet Rev. 7 — 1 September 2021 11 / 18

Test data is given in Table 9.

Table 9. Test data

Product data sheet Rev. 7 — 1 September 2021 12 / 18

12. Package outline

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE REFERENCES EUROPEAN

Fig. 13. Package outline SOT109-1 (SO16)

Product data sheet Rev. 7 — 1 September 2021 13 / 18

DIMENSIONS (mm are the original dimensions)

OUTLINE REFERENCES EUROPEAN

Fig. 14. Package outline SOT403-1 (TSSOP16)

Product data sheet Rev. 7 — 1 September 2021 14 / 18

0.05 0.30 3.6 2.15 2.6 1.15 0.5

OUTLINE REFERENCES EUROPEAN

Fig. 15. Package outline SOT763-1 (DHVQFN16)

Product data sheet Rev. 7 — 1 September 2021 15 / 18

14. Revision history

Product data sheet Rev. 7 — 1 September 2021 16 / 18

Product data sheet Rev. 7 — 1 September 2021 17 / 18

© Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 7 — 1 September 2021 18 / 18

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