74HC HCT597

74HC597; 74HCT597
8-bit shift register with input flip-flops

Rev. 5 — 26 October 2021 Product data sheet
1. General description
The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage
register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift
register have positive edge-triggered clocks. The shift register also has direct load (from storage)
and clear inputs. Inputs include clamp diodes that enable the use of current limiting resistors to
interface inputs to voltages in excess of VCC.
2. Features and benefits

• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Input levels:
• For 74HC597: CMOS level
• For 74HCT597: TTL level
• 8-bit parallel storage register inputs
• Shift register has direct overriding load and clear
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• ESD protection:
• • HBM EIA/JESD22-A114F exceeds 2000 V
• MM EIA/JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC597D -40 °C to +125 °C SO16 plastic small outline package; 16 leads; SOT109-1
74HCT597D body width 3.9 mm
74HCT597DB -40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1
body width 5.3 mm
74HC597PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
74HCT597PW body width 4.4 mm
Nexperia 74HC597; 74HCT597
4. Functional diagram
STCP MR DS
12 10 14 STCP MR DS
15
D0
12 10 14
1 D0 15
D1
2 D1 1
D2
3 D2 2
D3 8-BIT
INPUT
SHIFT D3 3 INPUT 8-BIT
4 FLIP-FLOPS
D4 REGISTER FLIP- SHIFT
5 D4 4 FLOPS REGISTER
D5
6 D5 5
D6
7 9 D6 6
D7 Q
D7 7 9 Q
13 11
13 11
PL SHCP PL SHCP
aaa-012057 aaa-012056
Fig. 1. Functional diagram Fig. 2. Logic symbol
R SRG8
10
11 C3/
13 C2
12 C1
14 1 3D
15 1D 2D
1 1D 2D
2
3
4
5
6
7 9
aaa-012055
Fig. 3. IEC Logic symbol
74HC_HCT597 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 5 — 26 October 2021 2 / 20

MR
SHCP
PL
STCP
DS
C2
D0 1D
S 2D
C1 R
C3 3S
D1 1D
S 3R
C1 R
C3 3S
D2 1D
S 3R
C1 R
C3 3S
D3 1D
S 3R
C1 R
C3 3S
D4 1D
S 3R
C1 R
C3 3S
D5 1D
S 3R
C1 R
C3 3S
D6 1D
S 3R
C1 R
C3 3S
D7 1D
S 3R
Q
C1 R
aaa-012058
Fig. 4. Logic diagram

5. Pinning information
5.1. Pinning
74HC597
74HCT597
74HC597
D1 1 16 VCC 74HCT597
D2 2 15 D0
D1 1 16 VCC
D3 3 14 DS D2 2 15 D0
D3 3 14 DS
D4 4 13 PL
D4 4 13 PL
D5 5 12 STCP D5 5 12 STCP
D6 6 11 SHCP
D6 6 11 SHCP
D7 7 10 MR
D7 7 10 MR GND 8 9 Q
GND 8 9 Q
aaa-012054
aaa-012939
Fig. 6. Pin configuration SOT338-1 (SSOP16) and
Fig. 5. Pin configuration SOT109-1 (SO16) SOT403-1 (TSSOP16)
5.2. Pin description

Table 2. Pin description
Symbol Pin Description
GND 8 ground (0 V)
Q 9 serial data output
MR 10 asynchronous master reset input (active LOW)
SHCP 11 shift register clock input (LOW-to-HIGH, edge-triggered)
STCP 12 storage register clock input (LOW-to-HIGH, edge-triggered)
PL 13 parallel load input (active LOW)
DS 14 serial data input
D0, D1, D2, D3, D4, D5, D6, D7 15, 1, 2, 3, 4, 5, 6, 7 parallel data inputs
VCC 16 supply voltage

6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition.
Inputs Function
STCP SHCP PL MR
↑ X X X data loaded to input latches
↑ X L H data loaded from inputs to shift register
no clock edge X L H data transferred from input flip-flops to shift register
X X L L invalid logic, state of shift register is indeterminate
when signals removed
X X H L shift register cleared
X ↑ H H shift register clocked Qn = Qn-1, Q0 = DS
SHCP
DS
MR
PL
STCP
D0 H L L
D1 L L L
D2 H L L
D3 L L L
D4 H L H
D5 H L H
D6 L L L
D7 H H L
Q L L H L H H L H L H L H L L L L L H H
reset
shift serial shift serial shift serial shift
register
serial shift
load input parallel load load input parallel load parallel load both
register shift register register shift register input and shift registers
aaa-012059
Fig. 7. Timing diagram

7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7 V
IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA
IO output current VO = -0.5 V to (VCC + 0.5 V) - ±25 mA
ICC supply current - +50 mA
IGND ground current -50 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation [1] - 500 mW
[1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT338-1 (SSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
8. Recommended operating conditions

Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC597 74HCT597 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VI input voltage 0 - VCC 0 - VCC V
VO output voltage 0 - VCC 0 - VCC V
Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V

9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74HC597
VIH HIGH-level VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
input voltage VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level input VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
voltage VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level VI = VIH or VIL
output voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; - - ±0.1 - ±1.0 - ±1.0 μA
current VCC = 6.0 V
ICC supply current VI = VCC or GND; IO = 0 A; - - 8.0 - 80.0 - 160.0 μA
VCC = 6.0 V
CI input - 3.5 - - - - - pF
capacitance


74HCT597
VIH HIGH-level VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
input voltage
VIL LOW-level input VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
voltage
VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V
IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 20 μA - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; - - ±0.1 - ±1.0 - ±1.0 μA
current VCC = 5.5 V
ICC supply current VI = VCC or GND; IO = 0 A; - - 8.0 - 80.0 - 160.0 μA
VCC = 5.5 V
ΔICC additional VI = VCC - 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; DS input - 25 90 - 112.5 - 122.5 μA
per input pin; Dn inputs - 30 108 - 135 - 147 μA
per input pin; PL, MR - 150 540 - 675 - 735 μA
inputs
per input pin; STCP, - 150 540 - 675 - 735 μA
SHCP inputs
CI input - 3.5 - - - - - pF
capacitance

10. Dynamic characteristics

Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 14.
74HC597
tpd propagation SHCP to Q; see Fig. 8 [1]
delay VCC = 2.0 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns
VCC = 6.0 V - 16 30 - 37 - 45 ns
MR to Q; see Fig. 9 [1]
VCC = 2.0 V - 58 175 - 220 - 265 ns
VCC = 4.5 V - 21 35 - 44 - 53 ns
VCC = 6.0 V - 17 30 - 37 - 45 ns
STCP to Q; see Fig. 8 [1]
VCC = 2.0 V - 80 250 - 315 - 375 ns
VCC = 4.5 V - 29 50 - 63 - 75 ns
VCC = 5.0 V; CL = 15 pF - 25 - - - - - ns
VCC = 6.0 V - 23 43 - 54 - 64 ns
PL to Q; see Fig. 10 [1]
VCC = 2.0 V - 69 215 - 270 - 325 ns
VCC = 4.5 V - 25 43 - 54 - 65 ns
VCC = 5.0 V; CL = 15 pF - 21 - - - - - ns
VCC = 6.0 V - 20 37 - 46 - 55 ns
tt transition Q; see Fig. 10 [2]
time VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns


tW pulse width STCP HIGH or LOW;
see Fig. 8
VCC = 2.0 V 80 11 - 100 - 120 - ns
VCC = 4.5 V 16 4 - 20 - 24 - ns
VCC = 6.0 V 14 3 - 17 - 20 - ns
SHCP HIGH or LOW;
see Fig. 8
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
MR LOW; see Fig. 9
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
PL LOW; see Fig. 10
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
trec recovery MR to SHCP; see Fig. 11
time VCC = 2.0 V 60 -3 - 75 - 90 - ns
VCC = 4.5 V 12 -1 - 15 - 18 - ns
VCC = 6.0 V 10 -1 - 13 - 15 - ns
tsu set-up time Dn to STCP; see Fig. 12
VCC = 2.0 V 60 8 - 75 - 90 - ns
VCC = 4.5 V 12 3 - 15 - 18 - ns
VCC = 6.0 V 10 2 - 13 - 15 - ns
DS to SHCP; see Fig. 12
VCC = 2.0 V 60 11 - 75 - 90 - ns
VCC = 4.5 V 12 4 - 15 - 18 - ns
VCC = 6.0 V 10 3 - 13 - 15 - ns
PL to SHCP; see Fig. 13
VCC = 2.0 V 60 11 - 75 - 90 - ns
VCC = 4.5 V 12 4 - 15 - 18 - ns
VCC = 6.0 V 10 3 - 13 - 15 - ns
th hold time Dn to STCP; see Fig. 12
VCC = 2.0 V 5 -3 - 5 - 5 - ns
VCC = 4.5 V 5 -1 - 5 - 5 - ns
VCC = 6.0 V 5 -1 - 5 - 5 - ns
PL, DS to SHCP; see Fig. 12
VCC = 2.0 V 5 -6 - 5 - 5 - ns
VCC = 4.5 V 5 -2 - 5 - 5 - ns
VCC = 6.0 V 5 -2 - 5 - 5 - ns


fmax maximum SHCP; see Fig. 8
frequency VCC = 2.0 V 6.0 29 - 4.8 - 4.0 - MHz
VCC = 4.5 V 30 87 - 24 - 20 - MHz
VCC = 5.0 V; CL = 15 pF - 96 - - - - - MHz
VCC = 6.0 V 35 104 - 28 - 24 - MHz
CPD power CL = 50 pF; f = 1 MHz; [3] - 29 - - - - - pF
dissipation VI = GND to VCC
capacitance
74HCT597
tpd propagation SHCP to Q; see Fig. 8 [1]
delay VCC = 4.5 V - 23 40 - 50 - 60 ns
VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns
MR to Q; see Fig. 9 [1]
VCC = 4.5 V - 28 49 - 61 - 74 ns
STCP to Q; see Fig. 8 [1]
VCC = 4.5 V - 33 57 - 71 - 86 ns
VCC = 5.0 V; CL = 15 pF - 29 - - - - - ns
PL to Q; see Fig. 10 [1]
VCC = 4.5 V - 30 52 - 65 - 78 ns
VCC = 5.0 V; CL = 15 pF - 26 - - - - - ns
tt transition Q; see Fig. 10 [2]
time VCC = 4.5 V - 7 15 - 19 - 22 ns
tW pulse width STCP HIGH or LOW;
see Fig. 8
VCC = 4.5 V 16 6 - 20 - 24 - ns
SHCP HIGH or LOW;
see Fig. 8
VCC = 4.5 V 16 7 - 20 - 24 - ns
MR LOW; see Fig. 9
VCC = 4.5 V 25 14 - 31 - 38 - ns
PL LOW; see Fig. 10
VCC = 4.5 V 20 10 - 25 - 30 - ns
trec recovery MR to SHCP; see Fig. 11
time VCC = 4.5 V 12 -2 - 15 - 18 - ns
tsu set-up time Dn to STCP; see Fig. 12
VCC = 4.5 V 12 5 - 15 - 18 - ns
DS to SHCP; see Fig. 12
VCC = 4.5 V 12 2 - 15 - 18 - ns
PL to SHCP; see Fig. 13
VCC = 4.5 V 12 4 - 15 - 18 - ns
th hold time Dn to STCP; see Fig. 12
VCC = 4.5 V 5 -1 - 5 - 5 - ns
PL, DS to SHCP; see Fig. 12
VCC = 4.5 V 5 -2 - 5 - 5 - ns


fmax maximum SHCP; see Fig. 8
frequency VCC = 4.5 V 30 75 - 24 - 20 - MHz
VCC = 5.0 V; CL = 15 pF - 83 - - - - - MHz
CPD power CL = 50 pF; f = 1 MHz; [3] - 32 - - - - - pF
dissipation VI = GND to VCC - 1.5 V
capacitance
[1] tpd is the same as tPLH and tPHL.

[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
2 2
PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
2
∑(CL × VCC × fo) = sum of outputs.
10.1. Waveforms and test circuit

1/fmax
VI
STCP, SHCP
VM
input
GND
tW
tPLH tPHL
VOH
Q output VM
VOL
aaa-012368
Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 8. SHCP and STCP clock inputs to Q output propagation delays, pulse width and maximum clock frequency
VI
MR input VM
GND
tW
tPHL
VOH
Q output VM
VOL
aaa-012369

Fig. 9. Input MR to Q output propagation delays and MR pulse width

1/fmax
VI
PL input VM
GND
tW
tPHL tPLH
VOH
90 % 90 %
Q output VM
10 % 10 %
VOL
tTHL tTLH
aaa-012371

Fig. 10. Input PL to Q output propagation delays, PL pulse width and output transition times
VI
MR input VM
GND
trec
VI
SHCP input VM
GND
aaa-012372

Fig. 11. Input MR to shift clock SHCP and storage clock STCP recovery times
VI
positive
VM
DS, Dn input
GND
VI
negative
VM
DS, Dn input
GND
tsu th
VI
SHCP input VM
GND
VI
STCP input VM
GND
tsu th
aaa-012374

Fig. 12. Set-up and hold times for DS, Dn inputs to SHCP, STCP inputs

VI
PL input VM
GND
VI
SHCP input VM
GND
tsu th
aaa-012375

Fig. 13. Set-up and hold times for PL input to SHCP input
Table 8. Measurement points

Type Input Output
VM VI VM
74HC597 0.5 × VCC GND to VCC 0.5 × VCC
74HCT597 1.3 V GND to 3 V 1.3 V
tW
VI
90 %
negative
pulse VM VM
10 %
0V
tf tr
tr tf
VI
90 %
positive
pulse VM VM
10 %
0V
tW
VCC VCC
VI VO RL S1
G DUT open
RT CL
001aad983
Test data is given in Table 9.

Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig. 14. Test circuit for measuring switching times
Table 9. Test data

Type Input Load S1 position
VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC597 VCC 6 ns 15 pF, 50 pF 1 kΩ open GND VCC
74HCT597 3V 6 ns 15 pF, 50 pF 1 kΩ open GND VCC

11. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D E A
X
y HE v M A
16 9
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 8 L
e w M detail X
bp
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8
o
o
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT109-1 076E07 MS-012
03-02-19
Fig. 15. Package outline SOT109-1 (SO16)

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
D E A
X
c
y HE v M A
16 9
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 8 detail X
w M
e bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
max.
mm
0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.00 8o
2 0.25 0.65 1.25 0.2 0.13 0.1
0.05 1.65 0.25 0.09 6.0 5.2 7.6 0.63 0.7 0.55 0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

ISSUE DATE
99-12-27
SOT338-1 MO-150
03-02-19
Fig. 16. Package outline SOT338-1 (SSOP16)

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
D E A
X
y HE v M A
16 9
Q
A2 (A 3 )
A
A1
pin 1 index
θ
Lp
L
1 8
detail X
w M
e bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
max.
mm
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8o
1.1 0.25 0.65 1 0.2 0.13 0.1
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.06 0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

ISSUE DATE
99-12-27
SOT403-1 MO-153
03-02-18
Fig. 17. Package outline SOT403-1 (TSSOP16)

12. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
13. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT597 v.5 20211026 Product data sheet - 74HC_HCT597 v.4
Modifications: • The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Type number 74HC597DB (SOT338-1/SSOP16) removed.
• Type number 74HCT597PW (SOT403-1/TSSOP16) added.
• Section 2 updated.
• Table 4: Derating values for Ptot total power dissipation updated.
74HC_HCT597 v.4 20160225 Product data sheet - 74HC_HCT597 v.3
Modifications: • Type numbers 74HC597N and 74HCT597N (SOT38-4) removed.
74HC_HCT597 v.3 20140415 Product data sheet - 74HC_HCT597_CNV v.2
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT597_CNV v.2 19901201 Product specification - -

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[2] The term 'short data sheet' is explained in section "Definitions". or problem which is based on any weakness or default in the customer’s
[3] The product status of device(s) described in this document may have applications or products, or the application or use by customer’s third party
changed since this document was published and may differ in case of customer(s). Customer is responsible for doing all necessary testing for the
multiple devices. The latest product status information is available on customer’s applications and products using Nexperia products in order to
the internet at https://www.nexperia.com. avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Definitions Limiting values — Stress above one or more limiting values (as defined in
Draft — The document is a draft version only. The content is still under the Absolute Maximum Ratings System of IEC 60134) will cause permanent
internal review and subject to formal approval, which may result in damage to the device. Limiting values are stress ratings only and (proper)
modifications or additions. Nexperia does not give any representations or operation of the device at these or any other conditions above those
warranties as to the accuracy or completeness of information included herein given in the Recommended operating conditions section (if present) or the
and shall have no liability for the consequences of use of such information. Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
Short data sheet — A short data sheet is an extract from a full data sheet
the quality and reliability of the device.
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain Terms and conditions of commercial sale — Nexperia products are
detailed and full information. For detailed and full information see the relevant sold subject to the general terms and conditions of commercial sale, as
full data sheet, which is available on request via the local Nexperia sales published at http://www.nexperia.com/profile/terms, unless otherwise agreed
office. In case of any inconsistency or conflict with the short data sheet, the in a valid written individual agreement. In case an individual agreement is
full data sheet shall prevail. concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
Product specification — The information and data provided in a Product
terms and conditions with regard to the purchase of Nexperia products by
data sheet shall define the specification of the product as agreed between
customer.
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be No offer to sell or license — Nothing in this document may be interpreted
valid in which the Nexperia product is deemed to offer functions and qualities or construed as an offer to sell products that is open for acceptance or the
beyond those described in the Product data sheet. grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
Disclaimers may be subject to export control regulations. Export might require a prior
Limited warranty and liability — Information in this document is believed authorization from competent authorities.
to be accurate and reliable. However, Nexperia does not give any
Non-automotive qualified products — Unless this data sheet expressly
representations or warranties, expressed or implied, as to the accuracy
states that this specific Nexperia product is automotive qualified, the
or completeness of such information and shall have no liability for the
product is not suitable for automotive use. It is neither qualified nor tested in
consequences of use of such information. Nexperia takes no responsibility
accordance with automotive testing or application requirements. Nexperia
for the content in this document if provided by an information source outside
accepts no liability for inclusion and/or use of non-automotive qualified
of Nexperia.
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
In the event that customer uses the product for design-in and use in
special or consequential damages (including - without limitation - lost
automotive applications to automotive specifications and standards,
profits, lost savings, business interruption, costs related to the removal
customer (a) shall use the product without Nexperia’s warranty of the
or replacement of any products or rework charges) whether or not such
product for such automotive applications, use and specifications, and (b)
damages are based on tort (including negligence), warranty, breach of
whenever customer uses the product for automotive applications beyond
contract or any other legal theory.
Nexperia’s specifications such use shall be solely at customer’s own risk,
Notwithstanding any damages that customer might incur for any reason and (c) customer fully indemnifies Nexperia for any liability, damages or failed
whatsoever, Nexperia’s aggregate and cumulative liability towards customer product claims resulting from customer design and use of the product for
for the products described herein shall be limited in accordance with the automotive applications beyond Nexperia’s standard warranty and Nexperia’s
Terms and conditions of commercial sale of Nexperia. product specifications.
Right to make changes — Nexperia reserves the right to make changes Translations — A non-English (translated) version of a document is for
to information published in this document, including without limitation reference only. The English version shall prevail in case of any discrepancy
specifications and product descriptions, at any time and without notice. This between the translated and English versions.
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical Notice: All referenced brands, product names, service names and
systems or equipment, nor in applications where failure or malfunction trademarks are the property of their respective owners.
of an Nexperia product can reasonably be expected to result in personal

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................4
5.1. Pinning.........................................................................4
5.2. Pin description............................................................. 4
6. Functional description................................................. 5
7. Limiting values............................................................. 6
8. Recommended operating conditions..........................6
9. Static characteristics....................................................7
10. Dynamic characteristics............................................ 9
10.1. Waveforms and test circuit...................................... 12
11. Package outline........................................................ 15
12. Abbreviations............................................................ 18
13. Revision history........................................................18
14. Legal information......................................................19
© Nexperia B.V. 2021. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: [email protected]
Date of release: 26 October 2021

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8-bit shift register with input flip-flops

2. Features and benefits

Fig. 1. Functional diagram Fig. 2. Logic symbol

Fig. 3. IEC Logic symbol

Product data sheet Rev. 5 — 26 October 2021 2 / 20

Fig. 4. Logic diagram

Product data sheet Rev. 5 — 26 October 2021 3 / 20

5.2. Pin description

Product data sheet Rev. 5 — 26 October 2021 4 / 20

Fig. 7. Timing diagram

Product data sheet Rev. 5 — 26 October 2021 5 / 20

8. Recommended operating conditions

Product data sheet Rev. 5 — 26 October 2021 6 / 20

Product data sheet Rev. 5 — 26 October 2021 7 / 20

Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit

Product data sheet Rev. 5 — 26 October 2021 8 / 20

10. Dynamic characteristics

Product data sheet Rev. 5 — 26 October 2021 9 / 20

Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit

Product data sheet Rev. 5 — 26 October 2021 10 / 20

Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit

Product data sheet Rev. 5 — 26 October 2021 11 / 20

Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit

[1] tpd is the same as tPLH and tPHL.

10.1. Waveforms and test circuit

Measurement points are given in Table 8.

Measurement points are given in Table 8.

Product data sheet Rev. 5 — 26 October 2021 12 / 20

Measurement points are given in Table 8.

Measurement points are given in Table 8.

Measurement points are given in Table 8.

Product data sheet Rev. 5 — 26 October 2021 13 / 20

Measurement points are given in Table 8.

Table 8. Measurement points

Test data is given in Table 9.

Table 9. Test data

Product data sheet Rev. 5 — 26 October 2021 14 / 20

11. Package outline

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE REFERENCES EUROPEAN

Fig. 15. Package outline SOT109-1 (SO16)

Product data sheet Rev. 5 — 26 October 2021 15 / 20

DIMENSIONS (mm are the original dimensions)

OUTLINE REFERENCES EUROPEAN

Fig. 16. Package outline SOT338-1 (SSOP16)

Product data sheet Rev. 5 — 26 October 2021 16 / 20

DIMENSIONS (mm are the original dimensions)

OUTLINE REFERENCES EUROPEAN

Fig. 17. Package outline SOT403-1 (TSSOP16)

Product data sheet Rev. 5 — 26 October 2021 17 / 20

13. Revision history

Product data sheet Rev. 5 — 26 October 2021 18 / 20

Product data sheet Rev. 5 — 26 October 2021 19 / 20

© Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 5 — 26 October 2021 20 / 20

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