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BUK9MHH-65PNN
Dual TrenchPLUS FET Logic Level FET
Rev. 02 — 19 May 2010 Objective data sheet

1. Product profile

1.1 General description

Dual N-channel enhancement mode field-effect power transistor in SO20. Device is
manufactured using NXP High-Performance Architecture (HPA) TrenchPLUS technology,
featuring very low on-state resistance, integrated current sensing transistors and over
temperature protection diodes.

1.2 Features and benefits

„ Integrated current sensors „ Integrated temperature sensors

1.3 Applications
„ Lamp switching „ Power distribution
„ Motor drive systems „ Solenoid drivers

1.4 Quick reference data

Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
FET1 and FET2 static characteristics
RDSon drain-source VGS = 5 V; ID = 10 A; - 9.8 11.5 mΩ
on-state Tj = 25 °C; see Figure 15;
resistance see Figure 16
ID/Isense ratio of drain Tj = 25 °C; VGS = 5 V; 6193 6881 7569 A/A
current to sense see Figure 17
current
V(BR)DSS drain-source ID = 250 µA; VGS = 0 V; 65 - - V
breakdown Tj = 25 °C
voltage
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Dual TrenchPLUS FET Logic Level FET

2. Pinning information
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1 G1 gate 1
20 11 D1 A1 D2 A2
2 IS1 current sense 1
3 D1 drain FET1 FET2
4 A1 anode 1
5 C1 cathode 1
6 G2 gate 2 1 10
7 IS2 current sense 2 SOT163-1 (SO20)
G1 IS1 S1 KS1 C1 G2 IS2 S2 KS2 C2
8 D2 drain 2
003aaa745
9 A2 anode 2
10 C2 cathode 2
11 D2 drain 2
12 KS2 Kelvin source 2
13 S2 source 2
14 S2 source 2
15 D2 drain 2
16 D1 drain 1
17 KS1 Kelvin source 1
18 S1 source 1
19 S1 source 1
20 D1 drain 1

3. Ordering information
Table 3. Ordering information
Type number Package
Name Description Version
BUK9MHH-65PNN SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

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Dual TrenchPLUS FET Logic Level FET

4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Typ Max Unit
FET1 and FET2
VDS drain-source voltage 25 °C ≤ Tj ≤ 150 °C - - 65 V
VDGR drain-gate voltage RGS = 20 kΩ; 25 °C ≤ Tj ≤ 150 °C - - 65 V
VGS gate-source voltage -15 - 15 V
ID drain current VGS = 5 V; Tsp = 25 °C; see Figure 1 [1][2] - - 15 A
VGS = 5 V; Tsp = 100 °C; see Figure 1 [1][2] - - 9.5 A
IDM peak drain current Tsp = 25 °C; pulsed; tp ≤ 10 µs; - - 319 A
see Figure 4
Ptot total power dissipation Tsp = 25 °C; see Figure 2 - - 5 W
Tstg storage temperature -55 - 150 °C
Tj junction temperature -55 - 150 °C
Visol(FET-TSD) FET to temperature - - 100 V
sense diode isolation
voltage
FET1 and FET2 source-drain diode
IS source current Tsp = 25 °C [1][3] - - 7 A
ISM peak source current pulsed; tp ≤ 10 µs; Tsp = 25 °C - - 319 A
FET1 and FET2 avalanche ruggedness
EDS(AL)S non-repetitive ID = 15.1 A; Vsup = 65 V; VGS = 5 V; [4][5][6] - - 878 mJ
drain-source Tj(init) = 25 °C; unclamped; see Figure 3
avalanche energy
FET1 and FET2 electrostatic discharge
VESD electrostatic discharge HBM; C = 100 pF; R = 1.5 kΩ; all pins - - 0.15 kV
voltage HBM; C = 100 pF; R = 1.5 kΩ; pins 8, - - 4 kV
11 and 15 to pins 6, 7, 12, 13 and 14
shorted
HBM; C = 100 pF; R = 1.5 kΩ; pins 3, - - 4 kV
16 and 20 to pins 1, 2, 17, 18 and 19
shorted

[1] Single device conducting.

[2] Continuous current is limited by package.
[3] Current is limited by chip power dissipation rating.
[4] Single-pulse avalanche rating limited by maximum junction temperature of 150 °C.
[5] Repetitive rating defined in avalanche rating figure.
[6] Refer to application note AN10273 for further information.

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Dual TrenchPLUS FET Logic Level FET

001aal615 003aab388
16 120

ID
(A) Pder
(%)
12
80

40
4

0 0
0 50 100 150 200 0 50 100 150 200
Tsp (°C) Tsp (°C)

Fig 1. Continuous drain current as a function of Fig 2. Normalized total power dissipation as a
solder point temperature, FET1 and FET2 function of solder point temperature, FET1 and
FET2

001aal679
102

IAL
(A)
(1)

10

(2)

1
(3)

10−1
10−3 10−2 10−1 1 10
tAL (ms)

Fig 3. Single-Pulse and repetitive avalanche rating; avalanche current as a function of avalanche time

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Dual TrenchPLUS FET Logic Level FET

001aal760
103
ID
(A)
Limit RDSon = VDS / ID
102 tp = 10 μs

100 μs

10

1 1 ms
DC
10 ms

10−1 100 ms

10−2
10−1 1 10 102
VDS (V)

Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-sp) thermal resistance FET1 - - 25 K/W
from junction to solder FET2 - - 25 K/W
point
Rth(j-a) thermal resistance mounted on a printed-circuit board; both - 73 - K/W
from junction to channels conducting; zero heat sink
ambient area; see Figure 5
mounted on a printed-circuit board; both - 60 - K/W
channels conducting; 200 mm² copper
heat sink area; see Figure 6
mounted on a printed-circuit board; both - 51 - K/W
channels conducting; 400 mm² copper
heat sink area; see Figure 7
mounted on a printed-circuit board; one - 105 - K/W
channel conducting; zero heat sink
area; see Figure 5
mounted on a printed-circuit board; one - 90 - K/W
channel conducting; 200 mm² copper
heat sink area; see Figure 6
mounted on a printed-circuit board; one - 70 - K/W
channel conducting; 400 mm² copper
heat sink area; see Figure 7

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Objective data sheet Rev. 02 — 19 May 2010 5 of 16

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Dual TrenchPLUS FET Logic Level FET

001aae478 001aae479

Fig 5. PCB used for thermal tests; zero heat sink area Fig 6. PCB used for thermal tests; heat sink area
200 mm²

001aae480

Fig 7. PCB used for thermal tests; heat sink area 400 mm²

001aal806
102
Zth(j-amb) δ = 0.5
(K/W)
0.2
10
0.1
0.05
0.02
1

10−1
tp
P δ=
T
10−2
single shot
tp t
T
10−3
10−6 10−5 10−4 10−3 10−2 10−1 1 10 102 103 104
tp (s)

Fig 8. Transient thermal impedance from junction to ambient as a function of pulse duration

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Dual TrenchPLUS FET Logic Level FET

6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
FET1 and FET2 static characteristics
V(BR)DSS drain-source ID = 250 µA; VGS = 0 V; Tj = 25 °C 65 - - V
breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 59 - - V
VGSth gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C; 1 1.5 2 V
voltage see Figure 13; see Figure 14
ID = 1 mA; VDS = VGS; Tj = 150 °C; 0.5 - - V
see Figure 13; see Figure 14
ID = 1 mA; VDS = VGS; Tj = -55 °C; - - 2.3 V
see Figure 13; see Figure 14
IDSS drain leakage current VDS = 52 V; VGS = 0 V; Tj = 25 °C - 0.02 3 µA
VDS = 52 V; VGS = 0 V; Tj = 150 °C - - 125 µA
IGSS gate leakage current VDS = 0 V; VGS = 15 V; Tj = 25 °C - 2 300 nA
RDSon drain-source on-state VGS = 4.5 V; ID = 10 A; Tj = 25 °C; - - 12.6 mΩ
resistance see Figure 15; see Figure 16
VGS = 5 V; ID = 10 A; Tj = 25 °C; - 9.8 11.5 mΩ
see Figure 15; see Figure 16
VGS = 5 V; ID = 10 A; Tj = 150 °C; - - 21.9 mΩ
see Figure 15; see Figure 16
VGS = 10 V; ID = 10 A; Tj = 25 °C; - - 10.6 mΩ
see Figure 15; see Figure 16
ID/Isense ratio of drain current to VGS = 5 V; Tj = 25 °C; see Figure 17 6193 6881 7569 A/A
sense current
SF(TSD) temperature sense IF = 250 µA; 25 °C ≤ Tj ≤ 150 °C; -5.4 -5.7 -6 mV/K
diode temperature see Figure 18
coefficient
VF(TSD) temperature sense IF = 250 µA; Tj = 25 °C; see Figure 18 2.855 2.9 2.945 V
diode forward voltage

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Dual TrenchPLUS FET Logic Level FET

Table 6. Characteristics …continued

Symbol Parameter Conditions Min Typ Max Unit
FET1 and FET2 dynamic characteristics
QG(tot) total gate charge ID = 10 A; VDS = 52 V; VGS = 5 V; - 44.6 - nC
QGS gate-source charge see Figure 19 - 7.22 - nC
QGD gate-drain charge - 16.8 - nC
Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 3643 - pF
Coss output capacitance Tj = 25 °C; see Figure 20 - 496 - pF
Crss reverse transfer - 186 - pF
capacitance
td(on) turn-on delay time VDS = 30 V; RL = 3 Ω; VGS = 5 V; - 40 - ns
tr rise time RG(ext) = 10 Ω - 76 - ns
td(off) turn-off delay time VDS = 30 V; VGS = 5 V; RG(ext) = 10 Ω - 188 - ns
tf fall time VDS = 30 V; RL = 3 Ω; VGS = 5 V; - 108 - ns
RG(ext) = 10 Ω
LD internal drain from pin to center of die - 0.9 - nH
inductance
LS internal source from source lead to source bonding - 2 - nH
inductance pad
FET1 and FET2 source-drain diode
VSD source-drain voltage IS = 10 A; VGS = 0 V; Tj = 25 °C; - 0.85 1.2 V
see Figure 21
trr reverse recovery time IS = 10 A; dIS/dt = -100 A/µs; - 54 - ns
Qr recovered charge VGS = -10 V; VDS = 30 V - 0.131 - nC

003a a d955 003a a d956

240 60
ID
RDS on
(A) 10.0
200 (mΩ)

5.0 45
160 4.5
4.0

120 3.5 30

80 3.0

15
VGS(V) =2.5 V
40

0 0
0 2 4 6 8 10 0 2 4 6 8 10
VDS (V) VGS (V)

Fig 9. Output characteristics: drain current as a Fig 10. Drain-source on-state resistance as a function
function of drain current; typical values, FET1 of gate-source voltage; typical values, FET1
and FET2 and FET2

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Dual TrenchPLUS FET Logic Level FET

003a a d957 003aae484

350 100
ID
gfs
(A)
(S )

75
300

50

250
25
Tj = 150 °C 25 °C

200 0
0 10 20 30 40 50 0 1 2 3 4
I D (A) VGS (V)

Fig 11. Forward transconductance as a function of Fig 12. Transfer characteristics; drain current as a
drain current; typical values, FET1 and FET2 function of gate-source voltage; typical values,
FET1 and FET2

001aal621 001aal622
10−1 2.5
ID VGS(th)
(A) (V)
10−2 2.0
max

min typ max

10−3 1.5
typ

10−4 1.0 min

10−5 0.5

10−6 0
0 1 2 3 −60 0 60 120 180
VGS (V) Tj (°C)

Fig 13. Sub-threshold drain current as a function of Fig 14. Gate-source threshold voltage as a function of
gate-source voltage, FET1 and FET2 junction temperature, FET1 and FET2

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Dual TrenchPLUS FET Logic Level FET

001aal794
003aae485 2.0
100
2.5 3.0 3.5 4.0 4.5
RDSon a
(mΩ)
80 1.5

60
5.0 1.0

40

0.5
20

VGS (V) = 10 V
0
0 −60 0 60 120 180
0 40 80 120 160 200 Tj (°C)
ID (A)

Fig 15. Drain-source on-state resistance as a function Fig 16. Normalized Drain-source on-state resistance
of drain current; typical values, FET1 and FET2 factor as a function of junction temperature

003a a d959 001aae485

10000 3.0

I D/I s ens e
VF(TSD)
8000 (V)

2.5
6000

4000
2.0

2000

0 1.5
2 4 6 8 10 0 40 80 120 160
VGS (V) Tj (°C)

Fig 17. Ratio of drain current to sense current as a Fig 18. Temperature sense diode forward voltage as a
function of gate-source voltage; typical values, function of junction temperature; typical
FET1 and FET2 values, FET1 and FET2

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Dual TrenchPLUS FET Logic Level FET

001aal818 003aae483
5 104
VGS
(V) C
(pF) Ciss
4
VDS = 14 V VDS = 52 V

103
3
Coss

2 Crss
102

0 10
0 10 20 30 40 50 10-1 1 10 102
QG (nC) VDS (V)

Fig 19. Gate-source voltage as a function of turn-on Fig 20. Input, output and reverse transfer capacitances
gate charge; typical values, FET1 and FET2 as a function of drain-source voltage; typical
values, FET1 and FET2

001aal614
60

IS
(A)

45

30

15

0
0 0.5 1.0 1.5
VSD (V)

Fig 21. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET1
and FET2

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Dual TrenchPLUS FET Logic Level FET

7. Package outline

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

D E A
X

c
y HE v M A

20 11

Q
A2 A
A1 (A 3)

pin 1 index
θ
Lp
L

1 10 detail X
e w M
bp

0 5 10 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)
θ
max.
0.3 2.45 0.49 0.32 13.0 7.6 10.65 1.1 1.1 0.9
mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1
0.1 2.25 0.36 0.23 12.6 7.4 10.00 0.4 1.0 0.4 8o
o
0.012 0.096 0.019 0.013 0.51 0.30 0.419 0.043 0.043 0.035 0
inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.49 0.29 0.394 0.016 0.039 0.016

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT163-1 075E04 MS-013
03-02-19

Fig 22. Package outline SOT163-1 (SO20)

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Dual TrenchPLUS FET Logic Level FET

8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BUK9MHH-65PNN v.2 20100519 Objective data sheet - BUK9MHH-65PNN_1
Modifications: • Various changes to content.
BUK9MHH-65PNN_1 20100511 Objective data sheet - -

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Dual TrenchPLUS FET Logic Level FET

9. Legal information

9.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive
Draft — The document is a draft version only. The content is still under applications. The product is not designed, authorized or warranted to be
internal review and subject to formal approval, which may result in suitable for use in medical, military, aircraft, space or life support equipment,
modifications or additions. NXP Semiconductors does not give any nor in applications where failure or malfunction of an NXP Semiconductors
representations or warranties as to the accuracy or completeness of product can reasonably be expected to result in personal injury, death or
information included herein and shall have no liability for the consequences of severe property or environmental damage. NXP Semiconductors accepts no
use of such information. liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
Short data sheet — A short data sheet is an extract from a full data sheet customer’s own risk.
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and Applications — Applications that are described herein for any of these
full information. For detailed and full information see the relevant full data products are for illustrative purposes only. NXP Semiconductors makes no
sheet, which is available on request via the local NXP Semiconductors sales representation or warranty that such applications will be suitable for the
office. In case of any inconsistency or conflict with the short data sheet, the specified use without further testing or modification.
full data sheet shall prevail.
NXP Semiconductors does not accept any liability related to any default,
Product specification — The information and data provided in a Product damage, costs or problem which is based on a weakness or default in the
data sheet shall define the specification of the product as agreed between customer application/use or the application/use of customer’s third party
NXP Semiconductors and its customer, unless NXP Semiconductors and customer(s) (hereinafter both referred to as “Application”). It is customer’s
customer have explicitly agreed otherwise in writing. In no event however, sole responsibility to check whether the NXP Semiconductors product is
shall an agreement be valid in which the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary
deemed to offer functions and qualities beyond those described in the testing for the Application in order to avoid a default of the Application and the
Product data sheet. product. NXP Semiconductors does not accept any liability in this respect.

Quick reference data — The Quick reference data is an extract of the

9.3 Disclaimers product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limited warranty and liability — Information in this document is believed to Limiting values — Stress above one or more limiting values (as defined in the
be accurate and reliable. However, NXP Semiconductors does not give any Absolute Maximum Ratings System of IEC 60134) will cause permanent
representations or warranties, expressed or implied, as to the accuracy or damage to the device. Limiting values are stress ratings only and (proper)
completeness of such information and shall have no liability for the operation of the device at these or any other conditions above those given in
consequences of use of such information. the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
In no event shall NXP Semiconductors be liable for any indirect, incidental, repeated exposure to limiting values will permanently and irreversibly affect
punitive, special or consequential damages (including - without limitation - lost the quality and reliability of the device.
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such Terms and conditions of commercial sale — NXP Semiconductors
damages are based on tort (including negligence), warranty, breach of products are sold subject to the general terms and conditions of commercial
contract or any other legal theory. sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
Notwithstanding any damages that customer might incur for any reason agreement is concluded only the terms and conditions of the respective
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards agreement shall apply. NXP Semiconductors hereby expressly objects to
customer for the products described herein shall be limited in accordance applying the customer’s general terms and conditions with regard to the
with the Terms and conditions of commercial sale of NXP Semiconductors. purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make No offer to sell or license — Nothing in this document may be interpreted or
changes to information published in this document, including without construed as an offer to sell products that is open for acceptance or the grant,
limitation specifications and product descriptions, at any time and without conveyance or implication of any license under any copyrights, patents or
notice. This document supersedes and replaces all information supplied prior other industrial or intellectual property rights.
to the publication hereof.

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Dual TrenchPLUS FET Logic Level FET

Export control — This document as well as the item(s) described herein may Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
be subject to export control regulations. Export might require a prior FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
authorization from national authorities. ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
9.4 Trademarks
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Notice: All referenced brands, product names, service names and trademarks Corporation.
are the property of their respective owners.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

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11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits . . . . . . . . . . . . . . . . . . . . .1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information . . . . . . . . . . . . . . . . . . . . . .2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
5 Thermal characteristics . . . . . . . . . . . . . . . . . . .5
6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .7
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .12
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .13
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .14
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .14
9.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
9.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .15
10 Contact information. . . . . . . . . . . . . . . . . . . . . .15

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2010. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 May 2010
Document identifier: BUK9MHH-65PNN