LMC662

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LMC662 CMOS Dual Operational Amplifier

Check for Samples: LMC662

1FEATURES DESCRIPTION
•
2 Rail-to-Rail Output Swing The LMC662 CMOS Dual operational amplifier is
ideal for operation from a single supply. It operates
• Specified for 2 kΩ and 600Ω Loads from +5V to +15V and features rail-to-rail output
• High Voltage Gain: 126 dB swing in addition to an input common-mode range
• Low Input Offset Voltage: 3 mV that includes ground. Performance limitations that
have plagued CMOS amplifiers in the past are not a
• Low Offset Voltage Drift: 1.3 μV/°C
problem with this design. Input VOS, drift, and
• Ultra Low Input Bias Current: 2 fA broadband noise as well as voltage gain into realistic
• Input Common-Mode Range Includes V− loads (2 kΩ and 600Ω) are all equal to or better than
• Operating Range from +5V to +15V Supply widely accepted bipolar equivalents.
• ISS = 400 μA/amplifier; Independent of V+ This chip is built with TI's advanced Double-Poly
Silicon-Gate CMOS process.
• Low Distortion: 0.01% at 10 kHz
• Slew Rate: 1.1 V/μs See the LMC660 datasheet for a Quad CMOS
operational amplifier with these same features.
APPLICATIONS
• High-Impedance Buffer or Preamplifier
• Precision Current-to-Voltage Converter
• Long-Term Integrator
• Sample-and-Hold Circuit
• Peak Detector
• Medical Instrumentation
• Industrial Controls
• Automotive Sensors

Connection Diagram
Typical Application

Figure 1. 8-Pin PDIP, SOIC Figure 2. Low-Leakage Sample-and-Hold

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1998–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Absolute Maximum Ratings (1) (2) (3)

Differential Input Voltage ±Supply Voltage
Supply Voltage (V+ − V−) 16V
Output Short Circuit to V+ See (4)
Output Short Circuit to V− See (5)
Lead Temperature
(Soldering, 10 sec.) 260°C
Storage Temp. Range −65°C to +150°C
Voltage at Input/Output Pins (V+) +0.3V, (V−) −0.3V
Current at Output Pin ±18 mA
Current at Input Pin ±5 mA
Current at Power Supply Pin 35 mA
Power Dissipation See (6)
Junction Temperature 150°C
ESD Tolerance (7) 1000V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) A military RETS electrical test specification is available on request.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
(5) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or
multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30
mA over long term may adversely affect reliability.
(6) The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max)–TA)/θJA.
(7) Human body model, 1.5 kΩ in series with 100 pF.

Operating Ratings (1)

Temperature Range
LMC662AI −40°C ≤ TJ ≤ +85°C
LMC662C 0°C ≤ TJ ≤ +70°C
Supply Voltage Range 4.75V to 15.5V
Power Dissipation See (2)
(3)
Thermal Resistance (θJA)
8-Pin PDIP 101°C/W
8-Pin SOIC 165°C/W

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA.
(3) All numbers apply for packages soldered directly into a PC board.

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DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
LMC662AI LMC662C
Parameter Test Conditions Typ (1) Units
Limit (1) Limit (1)
Input Offset Voltage 1 3 6 mV
3.3 6.3 max
Input Offset Voltage
1.3 μV/°C
Average Drift
Input Bias Current 0.002 pA
4 2 max
Input Offset Current 0.001 pA
2 1 max
Input Resistance >1 TeraΩ
Common Mode 0V ≤ VCM ≤ 12.0V 83 70 63 dB
+
Rejection Ratio V = 15V 68 62 min
Positive Power Supply 5V ≤ V+ ≤ 15V 83 70 63 dB
Rejection Ratio VO = 2.5V 68 62 min
Negative Power Supply 0V ≤ V− ≤ −10V 94 84 74 dB
Rejection Ratio 83 73 min
Input Common-Mode V+ = 5V & 15V −0.4 −0.1 −0.1 V
Voltage Range For CMRR ≥ 50 dB 0 0 max
V+ − 1.9 V+ − 2.3 V+ − 2.3 V
+
V − 2.5 V+ − 2.4 min
Large Signal RL = 2 kΩ (2) 2000 440 300 V/mV
Voltage Gain Sourcing 400 200 min
Sinking 500 180 90 V/mV
120 80 min
RL = 600Ω (2) 1000 220 150 V/mV
Sourcing 200 100 min
Sinking 100 50 V/mV
250
60 40 min
+
Output Swing V = 5V 4.87 4.82 4.78 V
RL = 2 kΩ to V+/2 4.79 4.76 min
0.10 0.15 0.19 V
0.17 0.21 max
V+ = 5V 4.61 4.41 4.27 V
RL = 600Ω to V+/2 4.31 4.21 min
0.30 0.50 0.63 V
0.56 0.69 max
V+ = 15V 14.63 14.50 14.37 V
RL = 2 kΩ to V+/2 14.44 14.32 min
0.26 0.35 0.44 V
0.40 0.48 max
V+ = 15V 13.90 13.35 12.92 V
+
RL = 600Ω to V /2 13.15 12.76 min
0.79 1.16 1.45 V
1.32 1.58 max

(1) Typical values represent the most likely parametric norm. Limits are specified by testing or correlation.
(2) V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
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DC Electrical Characteristics (continued)

Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
LMC662AI LMC662C
Parameter Test Conditions Typ (1) Units
Limit (1) Limit (1)
Output Current Sourcing, VO = 0V 22 16 13 mA
V+ = 5V 14 11 min
Sinking, VO = 5V 21 16 13 mA
14 11 min
Output Current Sourcing, VO = 0V 40 28 23 mA
V+ = 15V 25 21 min
Sinking, VO = 13V 39 28 23 mA
(3)
See 24 20 min
Supply Current Both Amplifiers 0.75 1.3 1.6 mA
VO = 1.5V 1.5 1.8 max

(3) Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.

AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− =
0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
LMC662AI LMC662C
Parameter Test Conditions Typ (1) Units
Limit (1) Limit (1)
Slew Rate See (2) 1.1 0.8 0.8 V/μs
0.6 0.7 min
Gain-Bandwidth Product 1.4 MHz
Phase Margin 50 Deg
Gain Margin 17 dB
Amp-to-Amp Isolation See (3) 130 dB
Input-Referred Voltage Noise F = 1 kHz 22 nV√Hz
Input-Referred Current Noise F = 1 kHz 0.0002 pA√Hz
Total Harmonic Distortion F = 10 kHz, AV = −10
RL = 2 kΩ, VO = 8 VPP 0.01 %
V+ = 15V

(1) Typical values represent the most likely parametric norm. Limits are specified by testing or correlation.
(2) V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
(3) Input referred. V+ = 15V and RL = 10 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 13 VPP.

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Typical Performance Characteristics

VS = ±7.5V, TA = 25°C unless otherwise specified
Supply Current
vs.
Supply Voltage Offset Voltage

Figure 3. Figure 4.

Input Bias Current Output Characteristics Current Sinking

Figure 5. Figure 6.

Input Voltage Noise

vs.
Output Characteristics Current Sourcing Frequency

Figure 7. Figure 8.

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Typical Performance Characteristics (continued)

VS = ±7.5V, TA = 25°C unless otherwise specified
CMRR
vs.
Frequency Open-Loop Frequency Response

Figure 9. Figure 10.

Frequency Response
vs.
Capacitive Load Non-Inverting Large Signal Pulse Response

Figure 11. Figure 12.

Stability Stability
vs. vs.
Capacitive Load Capacitive Load

Note: Avoid resistive loads < 500Ω, as they may cause instability. Note: Avoid resistive loads < 500Ω, as they may cause instability.
Figure 13. Figure 14.

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APPLICATION HINTS

AMPLIFIER TOPOLOGY
The topology chosen for the LMC662, shown in Figure 15, is unconventional (compared to general-purpose op
amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from
the output of the integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to
the load, while maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks
now fall to the integrator.
As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed
forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the
integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path
consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain
stages with two fed forward.

Figure 15. LMC662 Circuit Topology (Each Amplifier)

The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, even with a 600Ω load.
The gain while sinking is higher than most CMOS op amps, due to the additional gain stage; however, under
heavy load (600Ω) the gain will be reduced as indicated in the Electrical Characteristics.

COMPENSATING INPUT CAPACITANCE

The high input resistance of the LMC662 op amps allows the use of large feedback and source resistor values
without losing gain accuracy due to loading. However, the circuit will be especially sensitive to its layout when
these large-value resistors are used.
Every amplifier has some capacitance between each input and AC ground, and also some differential
capacitance between the inputs. When the feedback network around an amplifier is resistive, this input
capacitance (along with any additional capacitance due to circuit board traces, the socket, etc.) and the feedback
resistors create a pole in the feedback path. In the following General Operational Amplifier Circuit, Figure 16, the
frequency of this pole is

(1)
where: CS is the total capacitance at the inverting input, including amplifier input capacitance and any stray
capacitance from the IC socket (if one is used), circuit board traces, etc., and RP is the parallel combination of RF
and RIN. This formula, as well as all formulae derived below, apply to inverting and non-inverting op-amp
configurations.
When the feedback resistors are smaller than a few kΩ, the frequency of the feedback pole will be quite high,
since CS is generally less than 10 pF. If the frequency of the feedback pole is much higher than the “ideal”
closed-loop bandwidth (the nominal closed-loop bandwidth in the absence of CS), the pole will have a negligible
effect on stability, as it will add only a small amount of phase shift.

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However, if the feedback pole is less than approximately 6 to 10 times the “ideal” −3 dB frequency, a feedback
capacitor, CF, should be connected between the output and the inverting input of the op amp. This condition can
also be stated in terms of the amplifier's low-frequency noise gain: To maintain stability, a feedback capacitor will
probably be needed if:

(2)
where:

(3)
is the amplifier's low-frequency noise gain and GBW is the amplifier's gain bandwidth product. An amplifier's low-
frequency noise gain is represented by the formula:

(4)
regardless of whether the amplifier is being used in an inverting or non-inverting mode. Note that a feedback
capacitor is more likely to be needed when the noise gain is low and/or the feedback resistor is large.
If the above condition is met (indicating a feedback capacitor will probably be needed), and the noise gain is
large enough that:

(5)
the following value of feedback capacitor is recommended:

(6)
If

(7)
the feedback capacitor should be:

(8)
Note that these capacitor values are usually significantly smaller than those given by the older, more
conservative formula:

(9)

CS consists of the amplifier's input capacitance plus any stray capacitance from the circuit board and socket. CF
compensates for the pole caused by CS and the feedback resistor.

Figure 16. General Operational Amplifier Circuit

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Using the smaller capacitors will give much higher bandwidth with little degradation of transient response. It may
be necessary in any of the above cases to use a somewhat larger feedback capacitor to allow for unexpected
stray capacitance, or to tolerate additional phase shifts in the loop, or excessive capacitive load, or to decrease
the noise or bandwidth, or simply because the particular circuit implementation needs more feedback
capacitance to be sufficiently stable. For example, a printed circuit board's stray capacitance may be larger or
smaller than the breadboard's, so the actual optimum value for CF may be different from the one estimated using
the breadboard. In most cases, the value of CF should be checked on the actual circuit, starting with the
computed value.

CAPACITIVE LOAD TOLERANCE

Like many other op amps, the LMC662 may oscillate when its applied load appears capacitive. The threshold of
oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain
follower. See the Typical Performance Characteristics.
The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole
frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at
low gains. As shown in Figure 17, the addition of a small resistor (50Ω to 100Ω) in series with the op amp's
output, and a capacitor (5 pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe
value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be
tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near
the threshold for oscillation.

Figure 17. Rx, Cx Improve Capacitive Load Tolerance

Capacitive load driving capability is enhanced by using a pull up resistor to V+ Figure 18. Typically a pull up
resistor conducting 500 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical
Characteristics).

Figure 18. Compensating for Large Capacitive Loads with a Pull Up Resistor

PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK

It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC662,
typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining
low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though
it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination,
the surface leakage will be appreciable.

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To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC662's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs. See Figure 19. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the
LMC662's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance
of 1011Ω would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier's
performance. See Figure 20, Figure 21, and Figure 22 for typical connections of guard rings for standard op-amp
configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide
some protection; see Figure 23.

Figure 19. Example, using the LMC660,

of Guard Ring in P.C. Board Layout

Figure 20. Guard Ring Connections: Inverting Amplifier

Figure 21. Guard Ring Connections: Non-Inverting Amplifier

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Figure 22. Guard Ring Connections: Follower

Figure 23. Guard Ring Connections: Howland Current Pump

The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Do not insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 24.

(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)

Figure 24. Air Wiring

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BIAS CURRENT TESTING

The test method of Figure 25 is appropriate for bench-testing bias current with reasonable accuracy. To
understand its operation, first close switch S2 momentarily. When S2 is opened, then

(10)

Figure 25. Simple Input Bias Current Test Circuit

A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When
determining the magnitude of Ib−, the leakage of the capacitor and socket must be taken into account. Switch S2
should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2 shorted)

(11)
where Cx is the stray capacitance at the + input.

Typical Single-Supply Applications

(V+ = 5.0 VDC)
Additional single-supply applications ideas can be found in the LM358 datasheet. The LMC662 is pin-for-pin
compatible with the LM358 and offers greater bandwidth and input resistance over the LM358. These features
will improve the performance of many existing single-supply applications. Note, however, that the supply voltage
range of the LM662 is smaller than that of the LM358.

Figure 26. Low-Leakage Sample-and-Hold

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(V+ = 5.0 VDC)

Figure 27. Instrumentation Amplifier

For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects
CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7.

Oscillator frequency is determined by R1, R2, C1, and C2:

fOSC = 1/2πRC
where R = R1 = R2 and C = C1 = C2.

Figure 28. Sine-Wave Oscillator

This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V

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(V+ = 5.0 VDC)

Figure 29. 1 Hz Square-Wave Oscillator

Figure 30. Power Amplifier

fO = 10 Hz
Q = 2.1
Gain = −8.8

Figure 31. 10 Hz Bandpass Filter

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(V+ = 5.0 VDC)

fc = 10 Hz
d = 0.895
Gain = 1
2 dB passband ripple

Figure 32. 10 Hz High-Pass Filter

Figure 33. 1 Hz Low-Pass Filter

(Maximally Flat, Dual Supply Only)

Gain = −46.8
Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV).

Figure 34. High Gain Amplifier with

Offset Voltage Reduction

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REVISION HISTORY

Changes from Revision B (March 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 15

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LMC662AIM NRND SOIC D 8 95 Non-RoHS Call TI Level-1-235C-UNLIM -40 to 85 LMC66

& Green 2AIM
LMC662AIM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC66 Samples
2AIM
LMC662AIMX NRND SOIC D 8 2500 Non-RoHS Call TI Level-1-235C-UNLIM -40 to 85 LMC66
& Green 2AIM
LMC662AIMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC66 Samples
2AIM
LMC662AIN/NOPB ACTIVE PDIP P 8 40 RoHS & Green NIPDAU Level-1-NA-UNLIM -40 to 85 LMC Samples
662AIN
LMC662CM NRND SOIC D 8 95 Non-RoHS Call TI Level-1-235C-UNLIM 0 to 70 LMC66
& Green 2CM
LMC662CM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 LMC66 Samples
2CM
LMC662CMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM 0 to 70 LMC66 Samples
2CM
LMC662CN/NOPB ACTIVE PDIP P 8 40 RoHS & Green NIPDAU Level-1-NA-UNLIM 0 to 70 LMC Samples
662CN

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMC662AIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMC662AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMC662CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Jan-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMC662AIMX SOIC D 8 2500 367.0 367.0 35.0
LMC662AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMC662CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Jan-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LMC662AIM D SOIC 8 95 495 8 4064 3.05
LMC662AIM D SOIC 8 95 495 8 4064 3.05
LMC662AIM/NOPB D SOIC 8 95 495 8 4064 3.05
LMC662AIN/NOPB P PDIP 8 40 502 14 11938 4.32
LMC662CM D SOIC 8 95 495 8 4064 3.05
LMC662CM D SOIC 8 95 495 8 4064 3.05
LMC662CM/NOPB D SOIC 8 95 495 8 4064 3.05
LMC662CN/NOPB P PDIP 8 40 502 14 11938 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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