COMPUTER ORGANIZATION

PARALLEL-PORT
KEYBOARD INTERFACED TO PROCESSOR

• The output of the encoder consists of

→ bits representing the encoded character and
→ one signal called valid, which indicates the key is pressed.
• The information is sent to the interface-circuits (Figure 7.10).
• Interface-circuits contain
1) Data register DATAIN &
2) Status-flag SIN.
• When a key is pressed, the Valid signal changes from 0 to1.
Then, SIN=1  when ASCII code is loaded into DATAIN.
SIN = 0  when processor reads the contents of the DATAIN.
• The interface-circuit is connected to the asynchronous bus.
• Data transfers on the bus are controlled using the handshake signals:
1) Master ready &
2) Slave ready.

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INPUT-INTERFACE-CIRCUIT

Figure 4.29: Input-interface-circuit

• Output-lines of DATAIN are connected to the data-lines of bus by means of 3-state drivers (Fig 4.29).
• Drivers are turned on when
→ processor issues a read signal and
→ address selects DATAIN.
• SIN signal is generated using a status-flag circuit (Figure 4.30).
SIN signal is connected to line D0 of the processor-bus using a 3-state driver.
• Address-decoder selects the input-interface based on bits A1 through A31.
• Bit A0 determines whether the status or data register is to be read, when Master-ready is active.
• Processor activates the Slave-ready signal, when either the Read-status or Read-data is equal to 1.

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PRINTER INTERFACED TO PROCESSOR

• Keyboard is connected to a processor using a parallel-port.

• Processor uses
→ memory-mapped I/O and
→ asynchronous bus protocol.
• On the processor-side of the interface, we have:
→ Data-lines
→ Address-lines
→ Control or R/W line
→ Master-Ready signal and
→ Slave-Ready signal.
• On the keyboard-side of the interface, we have:
→ Encoder-circuit which generates a code for the key pressed.
→ Debouncing-circuit which eliminates the effect of a key.
→ Data-lines which contain the code for the key.
→ Valid line changes from 0 to 1 when the key is pressed. This causes the code to be loaded
into DATAIN and SIN to be set to 1.

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GENERAL 8 BIT PARALLEL PROCESSING

Figure 4.34: General 8 bit parallel interface

• Data-lines P7 through PO can be used for either input or output purposes (Figure 4.34).
• For increased flexibility,
→ some lines can be used as inputs and
→ some lines can be used as outputs.
• The DATAOUT register is connected to data-lines via 3-state drivers that are controlled by a DDR.
• The processor can write any 8-bit pattern into DDR. (DDR  Data Direction Register).
• If DDR=1,
Then, data-line acts as an output-line;
Otherwise, data-line acts as an input-line.
• Two lines, C1 and C2 are used to control the interaction between interface-circuit and I/0 device.
Two lines, C1 and C2 are also programmable.
• Line C2 is bidirectional to provide different modes of signaling, including the handshake.
• The Ready and Accept lines are the handshake control lines on the processor-bus side.
Hence, the Ready and Accept lines can be connected to Master-ready and Slave-ready.
• The input signal My-address should be connected to the output of an address-decoder.
The address-decoder recognizes the address assigned to the interface.
• There are 3 register select lines: RS0-RS2.
Three register select lines allows up to eight registers in the interface.
• An interrupt-request INTR is also provided.
INTR should be connected to the interrupt-request line on the computer-bus.

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STANDARD I/O INTERFACE
• Consider a computer system using different interface standards.
• Let us look in to Processor bus and Peripheral Component Interconnect (PCI) bus (Figure 4.38).
• These two buses are interconnected by a circuit called Bridge.
• The bridge translates the signals and protocols of one bus into another.
• The bridge-circuit introduces a small delay in data transfer between processor and the devices.

• The 3 major standard I/O interfaces are:

1) PCI (Peripheral Component Interconnect)
2) SCSI (Small Computer System Interface)
3) USB (Universal Serial Bus)
• PCI defines an expansion bus on the motherboard.
• SCSI and USB are used for connecting additional devices both inside and outside the computer-box.
• SCSI bus is a high speed parallel bus intended for devices such as disk and video display.
• USB uses a serial transmission to suit the needs of equipment ranging from keyboard to game
control to internal connection.
• IDE (Integrated Device Electronics) disk is compatible with ISA which shows the connection to an
Ethernet.

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PCI
• PCI is developed as a low cost bus that is truly processor independent.
• PCI supports high speed disk, graphics and video devices.
• PCI has plug and play capability for connecting I/O devices.
• To connect new devices, the user simply connects the device interface board to the bus.

DATA TRANSFER IN PCI

• The data are transferred between cache and main-memory.
• The data is a sequence of words which are stored in successive memory-locations.
• During read-operation,
 When the processor specifies an address, the memory responds by sending a sequence of
data-words from successive memory-locations.
• During write-operation,
 When the processor sends an address, a sequence of data-words is written into successive
memory-locations.
• PCI supports read and write-operation.
• A read/write-operation involving a single word is treated as a burst of length one.
• PCI has 3 address-spaces. They are
1) Memory address-space
2) I/O address-space &
3) Configuration address-space.
• I/O Address-space  Intended for use with processor.
Configuration space  Intended to give PCI, its plug and play capability.
• PCI Bridge provides a separate physical connection to main-memory.
• The master maintains the address information on the bus until data-transfer is completed.
• At any time, only one device acts as Bus-Master.
• A master is called “initiator” which is either processor or DMA.
• The addressed-device that responds to read and write commands is called a Target.
• A complete transfer operation on the bus, involving an address and burst of data is called a
transaction.

• Individual word transfers are called “phases’.

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• During Clock cycle-1,

 The processor a
→ asserts FRAME# to indicate the beginning of a transaction;
→ sends the address on AD lines and command on C/BE# Lines.
• During Clock cycle-2,
 The processor removes the address and disconnects its drives from AD lines.
 Selected target
→ enables its drivers on AD lines and
→ fetches the requested-data to be placed on bus.
 Selected target
→ asserts DEVSEL# and
→ maintains it in asserted state until the end of the transaction.
 C/BE# is
→ used to send a bus command and it is
→ used for different purpose during the rest of the transaction.
• During Clock cycle-3,
 The initiator asserts IRDY# to indicate that it is ready to receive data.
 If the target has data ready to send then it asserts TRDY#. In our eg, the target sends 3
more words of data in clock cycle 4 to 6.
• During Clock cycle-5
 The indicator uses FRAME# to indicate the duration of the burst, since it read 4 words, the
initiator negates FRAME# during clock cycle 5.
• During Clock cycle-7,
 After sending 4th word, the target
→ disconnects its drivers and
→ negates DEVSEL# during clock cycle 7.

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DEVICE CONFIGURATION OF PCI
• The PCI has a configuration ROM that stores information about that device.
• The configuration ROM’s of all devices are accessible in the configuration address-space.
• The initialization software read these ROM’s whenever the system is powered up or reset.
• In each case, it determines whether the device is a printer, keyboard or disk controller.
• Devices are assigned address during initialization process.
• Each device has an input signal called IDSEL# (Initialization device select) which has 21 address-
lines (AD11 to AD31).
• During configuration operation,
 The address is applied to AD input of the device and
 The corresponding AD line is set to 1 and all other lines are set to 0.
AD11 - AD31  Upper address-line
A0 - A10  Lower address-line: Specify the type of the operation and to access the
content of device configuration ROM.
• The configuration software scans all 21 locations. PCI bus has interrupt-request lines.
• Each device may requests an address in the I/O space or memory space

SCSI Bus
• SCSI stands for Small Computer System Interface.
• SCSI refers to the standard bus which is defined by ANSI (American National Standard Institute).
• SCSI bus the several options. It may be,

Narrow bus It has 8 data-lines & transfers 1 byte at a time.

Wide bus It has 16 data-lines & transfer 2 byte at a time.
Single-Ended Transmission Each signal uses separate wire.
HVD (High Voltage Differential) It was 5v (TTL cells)
LVD (Low Voltage Differential) It uses 3.3v

• Because of these various options, SCSI connector may have 50, 68 or 80 pins. The data transfer rate
ranges from 5MB/s to 160MB/s 320Mb/s, 640MB/s. The transfer rate depends on,
1) Length of the cable
2) Number of devices connected.
• To achieve high transfer rate, the bus length should be 1.6m for SE signaling and 12m for LVD
signaling.
• The SCSI bus us connected to the processor-bus through the SCSI controller. The data are
stored on a disk in blocks called sectors.
Each sector contains several hundreds of bytes. These data will not be stored in contiguous
memory-location.
• SCSI protocol is designed to retrieve the data in the first sector or any other selected sectors.
• Using SCSI protocol, the burst of data are transferred at high speed.
• The controller connected to SCSI bus is of 2 types. They are1) Initiator * 2) Target
1) Initiator
 It has the ability to select a particular target & to send commands specifying the operation to
be performed.
 They are the controllers on the processor side.
2) Target
 The disk controller operates as a target.
 It carries out the commands it receive from the initiator.
 The initiator establishes a logical connection with the intended target.

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Steps for Read-operation
1) The SCSI controller contends for control of the bus (initiator).
2) When the initiator wins the arbitration-process, the initiator
→ selects the target controller and
→ hands over control of the bus to it.
3) The target starts an output operation. The initiator sends a command specifying the required read-
operation.
4) The target
→ sends a message to initiator indicating that it will temporarily suspend connection b/w them.
→ then releases the bus.
5) The target controller sends a command to the disk drive to move the read head to the first sector
involved in the requested read-operation.
6. The target
→ transfers the contents of the data buffer to the initiator and
→ then suspends the connection again.
7) The target controller sends a command to the disk drive to perform another seek operation.
8) As the initiator controller receives the data, it stores them into the main-memory using the DMA
approach.
9) The SCSI controller sends an interrupt to the processor indicating that the data are now available.

BUS SIGNALS OF SCSI

• The bus has no address-lines. Instead, it has data-lines to identify the bus-controllers involved in the
selection/reselection/arbitration-process.
• For narrow bus, there are 8 possible controllers numbered from 0 to 7. For a wide bus, there are 16
controllers.
• Once a connection is established b/w two controllers, there is no further need for addressing & the
data-lines are used to carry the data.
• All
signal
names
are

proceeded by minus sign.

• This indicates that the signals are active or that the data-line is equal to 1, when they are in the
low voltage state.

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PHASES IN SCSI BUS
• The phases in SCSI bus operation are:
1) Arbitration
2) Selection
3) Information transfer
4) Reselection

1) Arbitration
• When the –BSY signal is in inactive state,
→ the bus will be free &
→ any controller can request the use of bus.
• SCSI uses distributed arbitration scheme because
each controller may generate requests at the same time.
• Each controller on the bus is assigned a fixed priority.
• When –BSY becomes active, all controllers that are requesting the bus
→ examines the data-lines &
→ determine whether highest priority device is requesting bus at the same time.
• The controller using the highest numbered line realizes that it has won the arbitration-process.
• At that time, all other controllers disconnect from the bus & wait for –BSY to become inactive again.

2) Information Transfer
• The information transferred between two controllers may consist of
→ commands from the initiator to the target
→ status responses from the target to the initiator or
→ data-transferred to/from the I/0 device.
• Handshake signaling is used to control information transfers, with the target controller taking the role
of the bus-master.
3) Selection
• Here, Device
→ wins arbitration and
→ asserts –BSY and –DB6 signals.
• The Select Target Controller responds by asserting –BSY.
• This informs that the connection that it requested is established.
4) Reselection
• The connection between the two controllers has been reestablished, with the target in control of the
bus as required for data transfer to proceed.

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USB
• USB stands for Universal Serial Bus.
• USB supports 3 speed of operation. They are,
1) Low speed (1.5 Mbps)
2) Full speed (12 mbps) &
3) High speed (480 mbps).
• The USB has been designed to meet the key objectives. They are,
1) Provide a simple, low-cost and easy to use interconnection system.
This overcomes difficulties due to the limited number of I/O ports available on a computer.
2) Accommodate a wide range of data transfer characteristics for I/O devices.
For e.g. telephone and Internet connections
3) Enhance user convenience through a “plug-and-play” mode of operation.
• Advantage: USB helps to add many devices to a computer system at any time without opening the
computer-box.
Port Limitation
 Normally, the system has a few limited ports.
 To add new ports, the user must open the computer-box to gain access to the internal
expansion bus & install a new interface card.
 The user may also need to know to configure the device & the s/w.
Plug & Play
 The main objective: USB provides a plug & play capability.
 The plug & play feature enhances the connection of new device at any time, while the system
is operation.
 The system should
→ Detect the existence of the new device automatically.
→ Identify the appropriate device driver s/w.
→ Establish the appropriate addresses.
→ Establish the logical connection for communication.

DEVICE CHARACTERISTICS OF USB

• The kinds of devices that may be connected to a computer cover a wide range of functionality.
• The speed, volume & timing constrains associated with data transfer to & from devices varies
significantly.
Eg: 1 Keyboard
 Since the event of pressing a key is not synchronized to any other event in a computer
system, the data generated by keyboard are called asynchronous.
The data generated from keyboard depends upon the speed of the human operator which is
about 100 bytes/sec.
Eg: 2 Microphone attached in a computer system internally/externally
 The sound picked up by the microphone produces an analog electric signal, which must be
converted into digital form before it can be handled by the computer.
 This is accomplished by sampling the analog signal periodically.
 The sampling process yields a continuous stream of digitized samples that arrive at regular
intervals, synchronized with the sampling clock. Such a stream is called isochronous (i.e.)
successive events are separated by equal period of time.
 If the sampling rate in „S‟ samples/sec then the maximum frequency captured by sampling
process is s/2.
 A standard rate for digital sound is 44.1 KHz.

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USB ARCHITECTURE
• To accommodate a large number of devices that can be added or removed at any time, the USB has
the tree structure as shown in the figure 7.17.
• Each node of the tree has a device called a Hub.
• A hub acts as an intermediate control point between the host and the I/O devices.
• At the root of the tree, a Root Hub connects the entire tree to the host computer.
• The leaves of the tree are the I/O devices being served (for example, keyboard or speaker).
• A hub copies a message that it receives from its upstream connection to all its downstream ports.
• As a result, a message sent by the host computer is broadcast to all I/O devices, but only the
addressed-device will respond to that message.

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USB ADDRESSING
• Each device may be a hub or an I/O device.
• Each device on the USB is assigned a 7-bit address.
• This address
→ is local to the USB tree and
→ is not related in any way to the addresses used on the processor-bus.
• A hub may have any number of devices or other hubs connected to it, and addresses are assigned
arbitrarily.
• When a device is first connected to a hub, or when it is powered-on, it has the address 0.
• The hardware of the hub detects the device that has been connected, and it records this fact as part
of its own status information.
• Periodically, the host polls each hub to
→ collect status information and
→ learn about new devices that may have been added or disconnected.
• When the host is informed that a new device has been connected, it uses sequence of commands to
→ send a reset signal on the corresponding hub port.
→ read information from the device about its capabilities.
→ send configuration information to the device, and
→ assign the device a unique USB address.
• Once this sequence is completed, the device
→ begins normal operation and
→ responds only to the new address.

USB PROTOCOLS
• All information transferred over the USB is organized in packets.
• A packet consists of one or more bytes of information.
• There are many types of packets that perform a variety of control functions.
• The information transferred on USB is divided into 2 broad categories: 1) Control and 2) Data.
• Control packets perform tasks such as
→ addressing a device to initiate data transfer.
→ acknowledging that data have been received correctly or
→ indicating an error.
• Data-packets carry information that is delivered to a device.
• A packet consists of one or more fields containing different kinds of information.
• The first field of any packet is called the Packet Identifier (PID) which identifies type of that
packet.
• They are transmitted twice.
1) The first time they are sent with their true values and
2) The second time with each bit complemented.
• The four PID bits identify one of 16 different packet types.
• Some control packets, such as ACK (Acknowledge), consist only of the PID byte.
• Control packets used for controlling data transfer operations are called Token Packets.

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Problem 1:
The input status bit in an interface-circuit is cleared as soon as the input data register is read. Why is
this important?
Solution:
After reading the input data, it is necessary to clear the input status flag before the program
begins a new read-operation. Otherwise, the same input data would be read a second time.

Problem 2:
What is the difference between a subroutine and an interrupt-service routine?
Solution:
A subroutine is called by a program instruction to perform a function needed by the calling
program.
An interrupt-service routine is initiated by an event such as an input operation or a hardware
error. The function it performs may not be at all related to the program being executed at the
time of interruption. Hence, it must not affect any of the data or status information relating to
that program.

Problem 3:
Three devices A, B, & C are connected to the bus of a computer. I/O transfers for all 3 devices use
interrupt control. Interrupt nesting for devices A & B is not allowed, but interrupt-requests from C may
be accepted while either A or B is being serviced. Suggest different ways in which this can be
accomplished in each of the following cases:
(a) The computer has one interrupt-request line.
(b) Two interrupt-request lines INTR1 & INTR2 are available, with INTR1 having higher priority.
Specify when and how interrupts are enabled and disabled in each case.
Solution:
(a) Interrupts should be enabled, except when C is being serviced. The nesting rules can be
enforced by manipulating the interrupt-enable flags in the interfaces of A and B.
(b) A and B should be connected to INTR , and C to INTR. When an interrupt-request is
received from either A or B, interrupts from the other device will be automatically disabled until
the request has been serviced. However, interrupt-requests from C will always be accepted.

Problem 4:
Consider a computer in which several devices are connected to a common interrupt-request line.
Explain how you would arrange for interrupts from device j to be accepted before the execution of the
interrupt service routine for device i is completed. Comment in particular on the times at which
interrupts must be enabled and disabled at various points in the system.
Solution:
Interrupts are disabled before the interrupt-service routine is entered. Once device i turns off
its interrupt-request, interrupts may be safely enabled in the processor. If the interface-circuit
of device i turns off its interrupt-request when it receives the interrupt acknowledge signal,
interrupts may be enabled at the beginning of the interrupt-service routine of device i.
Otherwise, interrupts may be enabled only after the instruction that causes device i to turn off
its interrupt-request has been executed.

Problem 5:
Consider the daisy chain arrangement. Assume that after a device generates an interrupt-request, it
turns off that request as soon as it receives the interrupt acknowledge signal. Is it still necessary to
disable interrupts in the processor before entering the interrupt service routine? Why?
Solution:
Yes, because other devices may keep the interrupt-request line asserted.

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