UNIT 5 (NOTES)

Peripheral Devices
A Peripheral Device is defined as the device which provides input/output functions for a
computer. It communicate with the outside world microcomputers use peripherals (I/O
devices). Commonly used peripherals are: A/D converter, D/A converter, CRT, printers, Hard
disks, floppy disks, magnetic tapes etc. A peripheral device is a device that is connected to a
computer system but is not part of the core computer system architecture.
Classification of Peripheral devices:
It is generally classified into 3 basic categories which are given below:

1. Input Devices:
The input devices is defined as it converts incoming data and instructions into a pattern
of electrical signals in binary code that are comprehensible to a digital computer.
Example:
Keyboard, mouse, scanner, microphone etc.
2. Output Devices:
An output device is generally reverse of the input process and generally translating the
digitized signals into a form intelligible to the user. The output device is also performed
for sending data from one computer system to another. For some time punched-card and
paper-tape readers were extensively used for input, but these have now been supplanted
by more efficient devices.
Example:
Monitors, headphones, printers etc.
3. Storage Devices:
Storage devices are used to store data in the system which is required for performing
any operation in the system. The storage device is one of the most requirement devices
and also provide better compatibility.
Example:
Hard disk, magnetic tape, Flash memory etc
Advantage of Peripherals Devices:
 It is helpful for taking input very easily.
 It is also provided a specific output.
 It has a storage device for storing information or data
 It also improves the efficiency of the system.

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Input-Output Interface ( I/O interface.)
 Input-output interface provides a method for transferring information between internal
storage and external I/0 devices.
 Peripherals connected to a computer need special communication links for interfacing
them with the central processing unit.
 The purpose of the communication link is to resolve the differences that exist between
the central computer and each peripheral
The major differences are: (Why I/O interface are needed)
1. Peripherals are electromechanical and electromagnetic devices and their manner of
operation is different from the operation of the CPU and memory, which are
electronic devices. Therefore, a conversion of signal values may be required.
2. The data transfer rate of peripherals is usually slower than the transfer rate of the
CPU, and consequently, a synchronization mechanism may be needed.
3. Data codes and formats in peripherals differ from the word format in the CPU and
memory.
4. The operating modes of peripherals are different from each other and each must be
controlled so as not to disturb the operation of other peripherals connected to the CPU
To resolve these differences, computer systems include special hardware components
between the CPU and peripherals to supervise and synchronize all input and output transfers.
These components are called interface units.
I/O BUS and Interface Module
 The I/O bus consists of data lines, address lines, and control lines.
 The I/O bus from the processor is attached to all peripherals interface.
 To communicate with a particular device, the processor places a device address on
address lines.
 Each Interface decodes the address and control received from the I/O bus, interprets them
for peripherals and provides signals for the peripheral controller.
 It is also synchronizes the data flow and supervises the transfer between peripheral and
processor. Each peripheral has its own controller.
For example, the printer controller controls the paper motion, the print timing

 The I/O bus is linked to all peripheral interfaces from the processor. The processor locates
a device address on the address line to interact with a specific device.
 Each interface contains an address decoder attached to the I/O bus that monitors the
address lines.
 When the address is recognized by the interface, it activates the direction between the bus
lines and the device that it controls.
 The interface disables the peripherals whose address does not equivalent to the address in
the bus.

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 An interface receives any of the following four commands (I/O command.) –
1. Control Command: A command control is given to activate the peripheral and to
inform its next task. This control command depends on the peripheral, and each
peripheral receives its sequence of control commands, depending on its mode of
operation.
2. Status Command: A status command is used to test various status conditions in
the interface and the peripheral. For example, the computer may wish to check the
status of the peripheral before a transfer is initiated.
3. Output data : A data output command creates the interface counter to the
command by sending data from the bus to one of its registers.
4. Input Data − The data input command is opposite to the data output command. In
data input, the interface gets an element of data from the peripheral and places it
in its buffer
I/O versus Memory Bus
 In addition to communicating with VO, the processor must communicate with the
memory unit.
There are three ways that computer buses can be used to communicate with memory
and I/O:
1. Separate set of address, control and data bus to I/O and memory.
In This case it is simple because both have different set of address space and
instruction but require more buses. This is done by using separate I/O
Processor (IOP) in addition to CPU.
2. Have common bus (data and address) for I/O and memory but separate control
lines. (Isolated I/O)
3. Have common bus (data, address, and control) for I/O and memory. (Memory
Mapped I/O)

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Isolated I/O
 It has common bus (data and address) for I/O and memory but separate read and write
control lines for I/O
 when CPU decode instruction then if data is for I/O then it places the address on the
address line and set I/O read or write control line on due to which data transfer occurs
between CPU and I/O.
 The address for I/O here is called ports.

Figure: Isolated I/O

Memory Mapped I/O

 The isolated 110 method isolates memory and 110 addresses so that memory address
values are not affected by interface address assignment since each has its own address
space.
 In Memory mapped I/O , the CPU uses same address space for both memory and I/O.
 The computers that employ only one set of read and write signals and do not distinguish
between memory and I/O addresses.
 The computer treats an interface register as being part of the memory system.
 The assigned addresses for interface registers cannot be used for memory words, which
reduces the memory address range available.

Figure: Memory Mapped I/O

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Example of I/O Interface

Example of I/O interface unit

 It consists of two data registers called ports, a control register, a status register, bus
buffers, and timing and control circuits. The interface communicates with the CPU
through the data bus.
 The chip select and register select inputs determine the address assigned to the interface.
The I/O read and write are two control lines that specify an input or output, respectively.
 The four registers communicate directly with the I/O device attached to the interface.
 The I/O data to and from the device can be transferred into either port
A or port B
 The control register receives control information from the CPU
 The bits in the status register are used for status conditions and for recording errors that
may occur during the data transfer.

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Data Transfer:
 The internal operations in a digital system are synchronized by means of clock pulses
supplied by a common pulse generator. Clock pulses are applied to all registers within
a unit and all data transfers among internal registers occur simultaneously during the
occurrence of a clock pulse.
 Two units, such as a CPU and an VO interface, are designed independently of each
other.
Two type of Data Transfer takes place between peripherals:

Synchronous Data Transfer

 If the registers in the interface share a common clock with the CPU registers, the
transfer between the two units is said to be synchronous.
Example: In a Master-Slave Flip Flop
 The master is designed to supply the data at a time when the slave is definitely
ready for it. Usually, the master will introduce sufficient delay to take into
account the slow response of the slave, without any request from the slave.
 The master does not expect any acknowledgment signal from the slave when
data is sent by the master to the slave

Advantages –
1. The design procedure is easy. The master does not wait for any acknowledges signal from the slave,
though the master waits for a time equal to slave’s response time.

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2. The slave does not generate an acknowledge signal, though it obeys the timing rules as per the protocol
set by the master or system designer.

Disadvantages –
1. If a slow speed unit connected to a common bus, it can degrade the overall rate of transfer in the system.
2. If the slave operates at a slow speed, the master will be idle for some time during data transfe r and vice
versa

Asynchronous Data Transfer

 The internal timing in each unit is independent from the other in that each uses its own
private clock for internal registers. In that case, the two units are said to be asynchronous
to each other. This approach is widely used in most computer systems
The Asynchronous data transfer is done by using two Method:
1. Strobe
2. Handshaking

A. Strobe control
 The strobe control method of asynchronous data transfer employs a single control line
to time each transfer.
 The strobe may be activated by either the source (source-initiated transfer) or the
destination unit (Destination initiated transfer).
 In A source initiated transfer, the source unit first places the data on the data bus.
After a brief delay to ensure that the data settle to a steady value, the source activates
the strobe pulse. The information on the data bus and the strobe signal remain in the
active state for a sufficient time period to allow the destination unit to receive the
data.
 The source removes the data from the bus a brief period after it disables its strobe
pulse.

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  In Destination Initiated Strobe, data transfer initiated by the destination unit. In this
case the destination unit activates the strobe pulse, informing the source to provide the
data.
 The source unit responds by placing the requested binary information on the data bus.
The data must be valid and remain in the bus long enough for the destination unit to
accept it.
 The destination unit then disables the strobe. The source removes the data from the
bus after a predetermined time interval

B. Handshaking Control
 The disadvantage of the strobe method is that the source unit that initiates the transfer has
no way of knowing whether the destination unit has actually received the data item that
was placed in the bus.
 Similarly, a destination unit that initiates the transfer has no way of knowing whether the
source unit has actually placed the data on the bus.
 The handshake method solves this problem by introducing a second control signal that
provides a reply to the unit that initiates the transfer.
 The basic principle of the two-wire handshaking method of data transfer is as follows.
1. One control line is in the same direction as the data flow in the bus from the source to
the destination. It is used by the source unit to inform the destination unit whether
there are valid data in the bus.
2. The other control line is in the other direction from the destination to the source. It is
used by the destination unit to inform the source whether it can accept data.
 The two handshaking lines are data valid, which is generated by the source unit, and data
accepted, generated by the destination unit.

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 In a Source initiated Transfer, the source unit initiates the transfer by placing the data
on the bus and enabling its data valid signal.
 The data accepted signal is activated by the destination unit after it accepts the data from
the bus.
 The source unit then disables its data valid signal, which invalidates the data on the bus.
 The destination unit then disables its data accepted signal and the system goes into its
initial state.
 In a Destination initiated Transfer, the source unit in this case does not place data on
the bus until after it receives the ready for data signal from the destination unit.
 Here Data accept line of Source initiated Transfer is replaced by ready for data signal.

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Advantage of the Handshaking method:
1. The Handshaking scheme provides degree of flexibility and reliability because the
successful completion of data transfer relies on active participation by both units.
2. If any of one unit is faulty, the data transfer will not be completed. Such an error
can be detected by means of a Timeout mechanism which provides an alarm if the
data is not completed within time

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Modes of data Transfer (I/O Techniques)
 Binary information received from an external device is usually stored in memory for later
processing. Information transferred from the central computer into an external device
originates in the memory unit.
 The CPU merely executes the instructions and may accept the data temporarily, but the
ultimate source or destination is the memory unit.
 Data transfer between the central computer and 110 devices may be handled in a variety
of modes, these are:
1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)

Programmed I/O (Example of Programmed I/O)

 In the programmed I/O method, the I/O device does not have direct access to Memory.
 A transfer from an I/O device to memory requires the execution of several instructions by
the CPU, including an input instruction to transfer the data from the device to the CPU
and a store instruction to transfer the data from the CPU to memory.
 The device transfers bytes of data one at a time which is placed on the I/O bus and
enables its data valid line.
 The interface accepts the byte into its data register and enables the data accepted line.
 The interface sets a bit in the status register that we will refer to as an F or "flag" bit
 The device can now disable the data valid line, but it will not transfer another byte until
the data accepted line is disabled by the interface. This is according to the handshaking
Procedure.
 A program is written for the computer to check the flag in the status register to determine
if a byte has been placed in the data register by the I/O device.
 If the flag is equal to 1, the CPU reads the data from the data register. The flag bit is then
cleared to 0 by either the CPU or the interface.
 Once the flag is cleared, the interface disables the data accepted line and the device
can then transfer the next data byte.

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 A flowchart of the program that must be written for the CPU is shown. It is assumed that
the device is sending a sequence of bytes that must be stored in memory. The transfer of
each byte requires three instructions:
1. Read the status register.
2. Check the status of the flag bit and branch to step 1 if not set or to step if set.
3. Read the data register

 The programmed VO method is particularly useful in small low-speed computers or in

systems that are dedicated to monitor a device continuously.
 The difference in information transfer rate between the CPU and the I/O device makes
this type of transfer inefficient.

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Interrupt-Initiated I/O
 An alternative to the CPU constantly monitoring the flag is to let the interface inform the
computer when it is ready to transfer data. This mode of transfer uses the interrupt
facility.
 While the CPU is running a program, it does not check the flag. However, when the flag
is set, The CPU momentarily interrupted from proceeding with the current program.
 The CPU responds to the interrupt signal by storing the return address from the program
counter into a memory stack and then control branches to a service routine that processes
the required I/O transfer.
 There are two ways of choosing the branch address:
1. Vectored Interrupt
2. Non-vectored Interrupt
 In vectored interrupt the source that interrupt the CPU provides the branch information.
This information is called interrupt vectored.
 In non-vectored interrupt, the branch address is assigned to the fixed address in the
memory.

Programmed I/O Interrupt Initiated I/O

Data transfer is initiated by the means of

instructions stored in the computer program. The I/O transfer is initiated by the
Whenever there is a request for I/O transfer the interrupt command issued to the
instructions are executed from the program. CPU.

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 Programmed I/O Interrupt Initiated I/O

There is no need for the CPU to stay

The CPU stays in the loop to know if the in the loop as the interrupt command
device is ready for transfer and has to interrupts the CPU when the device is
continuously monitor the peripheral device. ready for data transfer.

The CPU cycles are not wasted as

This leads to the wastage of CPU cycles as CPU continues with other work
CPU remains busy needlessly and thus the during this time and hence this
efficiency of system gets reduced. method is more efficient.

CPU can do any other work until it is

CPU cannot do any work until the transfer is interrupted by the command
complete as it has to stay in the loop to indicating the readiness of device for
continuously monitor the peripheral device. data transfer

Its module is faster than programmed

Its module is treated as a slow module. I/O module.

It can be tricky and complicated to

understand if one uses low level
It is quite easy to program and understand. language.

The performance of the system is severely The performance of the system is

degraded. enhanced to some extent.

Priority Interrupt

 There are number of I/O devices attached to the computer.

 They are all capable of generating the interrupt.
 When the interrupt is generated from more than one device, priority interrupt system
is used to determine which device is to be serviced first.
 Devices with high speed transfer are given higher priority and slow devices are
given lower priority.
 Establishing the priority can be done in two ways:
1. Using Software : by Polling Procedure
2. Using Hardware : by Daisy-Chaining Priority and Parallel Priority Interrupt
 A pooling procedure is used to identify highest priority in software means.
Polling
 A polling procedure is used to identify the highest-priority source by software means.
In this method there is one common branch address for all interrupts.

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  The program that takes care of interrupts begins at the branch address and polls the
interrupt sources in sequence. The order in which they are tested determines the
priority of each interrupt.
 The highest-priority source is tested first, and if its interrupt signal is ON, control
branches to a service routine for this source. Otherwise, the next-lower-priority source
is tested, and so on.
 The disadvantage of the software method is that if there are many interrupts, the time
required to poll them can exceed the time available to service the I/O device. In this
situation a hardware priority-interrupt unit can be used to speed up the operation

Hardware Procedure
 Hardware priority system function as an overall manager.
 It accepts interrupt request and determine the priorities.
 To speed up the operation each interrupting devices has its own interrupt vector.
 No polling is required, all decision are established by hardware priority interrupt unit.
 It can be established by serial (Daisy-Chaining Priority) or parallel (Parallel Priority
Interrupt) connection of interrupt lines.
Daisy-Chaining Priority
 Device with highest priority is placed first.
 Device that wants the attention send the interrupt request to the CPU.
 CPU then sends the INTACK signal which is applied to PI (priority in) of the first
device.
 If it had requested the attention, it place its VAD (vector address) on the bus. And it
block the signal by placing 0 in PO (priority out)
 If not it pass the signal to next device through PO (priority out) by placing 1.
 This process is continued until appropriate device is found.
 The device whose PI is 1 and PO is 0 is the device that send the interrupt request.

Parallel Priority Interrupt

 It consist of interrupt register whose bits are set separately by the interrupting devices.

15
 Priority is established according to the position of the bits in the register
 Mask register is used to provide facility for the higher priority devices to interrupt when
lower priority device is being serviced or disable all lower priority devices when higher is
being serviced.
 Corresponding interrupt bit and mask bit are ANDed and applied to priority encoder.
 Priority encoder generates two bits of vector address.
 Another output from it sets IST(interrupt status flip flop)

Direct Memory Access (DMA)

 The Transfer of Data between a fast storage devices is limited by the speed of the
CPU. Removing the CPU from the path and letting the peripheral device manage the
memory buses directly would improve the speed of transfer. This transfer technique is
called direct memory access (DMA).
 During DMA transfer, the CPU is idle and has no control of the memory buses.
 A DMA controller takes over the buses to manage the transfer directly between the
I/O device and memory.

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  The CPU may be placed in an idle state in a variety of ways. One common method
extensively used in microprocessor is to disable the buses through special control
signals such as:
A. Bus Request: The Bus Request (BR) input is used by the DMA controller to
request the CPU to stop having control of bus. When this input is active, the CPU
terminates the execution of the current instruction and place the address bus, the
DATA bus and the read and write line into high impedance state.
B. Bus Grant: The CPU activates the bus Grant (BG) output to inform the external
DMA that the buses are in high impedance state. The DMA that originated the bus
request can now take control of the buses to conduct memory transfers without
processor intervention.
 These two control signals in the CPU that facilitates the DMA transfer.
 When this input is active, the CPU terminates the execution of the current instruction
and places the address bus, data bus and read write lines into a high Impedance state.
High Impedance state means that the output is disconnected.
 When DMA terminates the transfer, it disables the bus request line. The CPU disables
the Bus Grant (BG), takes control of the bus, and returns to its normal operation.

Figure: CPU bus signal for BUS Transfer

 The transfer of data from memory can be made in several ways:
1. Burst Mode
2. Cycle Stealing Mode
Burst Mode: In this mode, once the DMA controller gains the charge of the system bus, then
it releases the system bus only after completion of data transfer. Till then the CPU has to wait
for the system buses.
Cycle Stealing Mode: In this mode, the DMA controller forces the CPU to stop its operation
and transfer the control over the bus for a short term to DMA controller. After the transfer of
every byte, the DMA controller releases the bus and then again requests for the system bus.
In this way, the DMA controller steals the clock cycle for transferring every byte

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DMA Controller
 The DMA controller needs the usual circuits of an interface to communicate with the
CPU and I/O device. In addition, it need address register, a word count register and a set
of address lines.
 The Address register and address lines are used for direct communication with the
memory.
 The data transfer may be done directly between the device and memory under control of
the DMA.
 The DMA unit communicates with the CPU via the data bus and control lines.
 The DMA controller has three registers:
1. Address Register
2. Word Count Register
3. Control Register
 Address Register: - Address Register contains an address to specify the desired location
in memory.
 Word Count Register: - WC holds the number of words to be transferred. The register is
increase/decrease by one after each word transfer and internally tested for zero
 Control Register :- Control Register specifies the mode of transfer
 The unit communicates with the CPU via the data bus and control lines. The registers in
the DMA are selected by the CPU through the address bus by enabling the DS (DMA
select) and RS (Register select) inputs. The RD (read) and WR (write) inputs are
bidirectional.
 When the BG (Bus Grant) input is 0, the CPU can communicate with the DMA registers
through the data bus to read from or write to the DMA registers.
 When BG =1, the DMA can communicate directly with the memory by specifying an
address in the address bus and activating the RD or WR control.

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DMA Transfer
 The CPU communicates with the DMA through the address and data buses as with
any interface unit. The DMA has its own address, which activates the DS and RS
lines. The CPU initializes the DMA through the data bus.
 Once the DMA receives the start control command, it can start the transfer between
the peripheral device and the memory
 When the peripheral device sends a DMA request, the DMA controller activates the
BR line, informing the CPU to stop control on the buses.
 The CPU responds with its BG line, informing the DMA that its buses are
disabled.
 The DMA then puts the current value of its address register into the address bus,
Initiates the RD or WR signal, and sends a DMA acknowledge to the peripheral
device.
 The direction of transfer depends on the status of the BG line.
 When BG = 0, the RD and WR are input lines allowing the CPU to communicate with
the internal DMA registers.
 When BG= 1, the RD and WR are output lines from the DMA controller to the
random-access memory to specify the read or write operation for the data.
 For each word that is transferred, the DMA increments its address register and
decrements its word count register.
 If the word count register reaches zero, the DMA stops any further transfer and
removes its bus request. It also informs the CPU of the termination by means of
interrupt.

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Input-Output Processor (IOP)
 Instead of having each interface communicate with the CPU, a computer may
incorporate one or more external processors and assign them the task of communicating
directly with all I/O devices.
 An input-output processor (IOP) may be classified as a processor with direct memory
access capability that communicates with I/O devices.
 The IOP is similar to a CPU except that it is designed to handle the details of I/O
processing.
 Unlike the DMA controller that must be set up entirely by the CPU, the IOP can
fetch and execute its own instructions, which is specifically designed for I/O
transfer.
 The block diagram indicated two processor (CPU and IOP), which can
communicate with Memory unit directly.
 The CPU is responsible for processing data needed in the solution of
computational tasks.
 The IOP provides the path for transfer of data between various peripherals devices and
memory unit.
 The data formats of peripheral devices differ from memory and CPU data formats.
 After the input data are assembled into a memory word, they are transferred from lOP
directly into memory by "stealing" one memory cycle from the CPU.
 Instructions that are read from memory by an IOP are sometimes called commands, to
distinguish them from instructions that are read by the CPU.

CPU-IOP Communication
 In most cases the memory unit acts as a message centre where each processor leaves
information for the other.
 The sequence of operations may be carried out as shown in the flowchart for the
communication between CPU and IOP.

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 The CPU sends an instruction to test the IOP path.
 The IOP responds by inserting a status word in memory for the CPU to check. The bits of
the status word indicate the condition of the IOP and I/O device, such as IOP overload
condition, device busy with another transfer, or device ready for I/O transfer.
 The CPU refers to the status word in memory to decide what to do next. If all is in order,
the CPU sends the instruction to start I/O transfer.
 The memory address received with this instruction tells the IOP where to find its program
 The CPU can now continue with another program while the IOP is busy with the I/O
program.
 When the IOP terminates the execution of its program, it sends an interrupt request to the
CPU.
 The CPU responds to the interrupt by issuing an instruction to read the status from the IOP.
 The IOP responds by placing the contents of its status report into a specified memory
location.

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Serial Communication
 Serial communication is the process of sequentially transferring the information/bits on the
same channel. Due to this, the cost of wire will be reduced, but it slows the transmission
speed.
 In serial communication, binary pulses are used to show the data
 The serial communication can either be asynchronous or synchronous.
Synchronous Communication
In the synchronous communication scheme, after a fixed number of data bytes, a special bit
pattern called SYNC is sent as shown Figure. There is no gap between adjacent characters in the
synchronous communication. There is a continuous stream of data bits coming at a fixed speed
in a synchronous communication scheme. Synchronous communication is used generally when
two computers are communicating to each other or when a buffered terminal is communicating
to the computer

Asynchronous Serial data transmission:

In the asynchronous communication scheme, each character includes start and stop bits, as
shown in Figure. There are some gaps between adjacent characters in the asynchronous
communication. In the asynchronous communication scheme, the bits within a character frame
(including start, parity and stop bits) are sent at the baud rate. Asynchronous communication
is used when slow speed peripherals communicate with the computer.

The Serial transmission modes are described as follows:

1. Simplex: In the simplex method, the data transmission can be performed only in one
direction. A sender can only transmit the data, and the receiver can only accept that data.
The receiver cannot reply back to the sender

2. Half duplex communication link: In half duplex, the communication link can be used for either
transmission or reception. Data is transmitted in only one direction at a time.

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3. Full duplex communication link: If the data is transmitted in both ways at the same time,
it is a full duplex i.e. transmission and reception can proceed simultaneously. This
communication link requires two wires for data, one for transmission and one for reception

Interrupt
An interrupt is a signal to the processor emitted by hardware or software indicating an
event that needs immediate attention. It alerts the processor to a high priority process
requiring interruption of the current working process. In I/O devices one of the bus control
lines is dedicated for this purpose and is called the Interrupt Service Routine (ISR).
An interrupt in computer architecture is a signal that requests the processor to suspend its
current execution and service the occurred interrupt. To service the interrupt the processor
executes the corresponding interrupt service routine (ISR). After the execution of the
interrupt service routine, the processor resumes the execution of the suspended program.
TYPES OF INTERRUPTS
There are many type of interrupts but basic type of interrupts are –
1. Hardware and software interrupts
2. Vectored and Non- vectored Interrupts
3. Mask able and non-maskable interrupts

Hardware and software interrupts

1. Hardware Interrupts: If the signal for the processor is generated from external
device or hardware is called hardware interrupts. There are 5 Hardware Interrupts in
processor. They are
1. INTR,
2. RST 7.5,
3. RST 6.5,
4. RST 5.5,
5. TRAP

1.TRAP(RST 4.5):-
 Non maskable

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  Edge and level triggered .
 Edge and level triggered means that the TRAP must go high and remain high
until it is acknowledged
 Highest priority
 vectored interrupt.
 In the case of sudden power failure, it executes a ISR (Interrupt service routine)
and send the data from main memory to backup memory.

2.RST 7.5:-
 Second highest priority.
 Maskable
 edge triggered interrupt.
 Edge sensitive means input goes high and no need to maintain high state until it is
recognized.

3.RST6.5 and RST5.5:-

 level triggered
 maskable interrupts.
 RST 6.5 has third highest priority and RST 5.5 has fourth highest priority.
4.INTR:-
 Level triggered
 Maskable interrupt.
 Lowest priority.

2. Software Interrupts are those which are inserted in between the program which
means these are mnemonics of microprocessor.
 There are 8 software interrupts. They are – RST 0, RST 1, RST 2, RST 3, RST 4,
RST 5, RST 6, RST 7.

Software interrupt can also divided in to two types:

 Normal Interrupts: the interrupts which are caused by the software instructions
are called software instructions.

 Exception: unplanned interrupts while executing a program is called Exception.

For example: while executing a program if we got a value which should be divided
by zero is called a exception.

Example: Division by zero, execution of an illegal opcode or memory related fault

could cause exceptions.
Mask able and non-maskable interrupts
 Maskable Interrupt: The hardware interrupt that can be ignored or delayed for
some time if the processor is executing a program with higher priority are termed

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 as maskable interrupts. These interrupts are either edge-triggered or level-
triggered, so they can be disabled.

INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts.
 Non Maskable Interrupt: The hardware interrupts that can neither be ignored
nor delayed and must immediately be serviced by the processor are termed as
non-maskable interrupts. It consists of both level as well as edge triggering and is
used in critical power failure conditions.

TRAP is a non-maskable interrupt.

Vectored and Non- vectored Interrupts

 Vectored Interrupts are those which have fixed vector address (starting address
of sub-routine) and after executing these, program control is transferred to that
address. When an interrupt is occurred and program control automatically
branches the program execution to a specific address
 Non-Vectored Interrupts (Scalar Interrupt) are those in which vector address is
not predefined. Interrupts that have a variable address. When an interrupt device
have to provide an address from where the execution of program will begin.
INTR is the only non-vectored interrupt

INTERRUPT HANDLING MECHANISM AND INTERRUPT SERVICE

ROUTINE (ISR):
 The job of the interrupt handler in Interrupt handling is to service the device and
stop it from interrupting. Once the handler returns, the CPU resumes what it was
doing before the interrupt occurred.
 The routine that gets executed when an interrupt request is made is called as
interrupt service routine.

 Step 1: When the interrupt occurs the processor is currently

executing i’th instruction and the program counter will be currently pointing to (i
+ 1)th instruction.
 Step 2: When the interrupt occurs the program counter value is stored on the
processes stack.

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  Step 3: The program counter is now loaded with the address of interrupt service
routine.
 Step 4: Once the interrupt service routine is completed the address on the processes
stack is pop and place back in the program counter.
 Step 5: Execution resumes from (i + 1)th line of compute routine

INTERRUPT HARDWARE
Many computers have facility to connect two or more input and output devices to it like
laptop may have 3 USB slots. All these input and output devices are connected via
switches as shown -

So there is a common interrupt line for all N input/output devices and the
interrupt handling works in the following manner ->
1. When no interrupt is issued by the input/output devices then all the switches are
open and the entire voltage from Vdd is flown through the single line INTR and
reaches the processor. Which means the processor gets a voltage of 1V.

2. When the interrupt is issued by the input/output devices then the switch
associated with the input/output device is closed, so the entire current now passes
via the switches which means the hardware line reaching the processes
i.e INTR line gets 0 voltage. This is an indication for the processor that an
interrupt has occurred and the processor needs to identify which input/output
device has triggered the interrupt

3. The value of INTR is a logical NOT of the requests from individual devices.

4. The resistor R is called as a pull up resistor because it pulls the line voltage to
high voltage state when all switches are open( no interrupt state).

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