My Lecture 2

Microprocessor
Programming and Interfacing

Dr. Syed Aqeel Haider
[email protected]
Lecture 2 2
Instruction Fetch and Execute
Lecture 2 3
Instruction fetch cycle
• At the beginning of each instruction cycle, the processor fetches an instruction from memory.
• In a typical processor, a register called the program counter (PC) holds the address of the
instruction to be fetched next.
• Always increments the PC after each instruction fetch so that it will fetch the next instruction in
sequence.
• The fetched instruction is loaded into a register in the processor known as the instruction register
(IR).
• The fetched instruction is loaded into a register in the processor known as the instruction register
(IR).
Lecture 2 4
Instruction Execute cycle
• Processor-memory: Data may be transferred from processor to memory or from memory to
processor.
• Processor-I/O: Data may be transferred to or from a peripheral device by transferring between the
processor and an I/O module.
• Data processing: The processor may perform some arithmetic or logic operation on data.
• Control: An instruction may specify that the sequence of execution be altered. For example, the
processor may fetch an instruction from location 149, which specifies that the next instruction be
from location 182. The processor will remember this fact by setting the program counter to 182.
Thus, on the next fetch cycle, the instruction will be fetched from location 182 rather than 150.
Lecture 2 5
Instruction Set
Lecture 2 6
Difference between RISC and CISC
Architecture
Lecture 2 7
Architectures for Recent Microprocessors
• VLIW : Very Long Instruction Word
• EPIC : Explicitly Parallel Instruction Computing
 Principle 1: Make it do each thing faster.
 Principle 2: Make it do more things at once.
Lecture 2 8
Bus Interconnection
• The bus was the dominant means of computer system component interconnection for decades.
• For general-purpose computers, it has gradually given way to various point-to-point interconnection
structures, which now dominate computer system design.
• A bus is a communication pathway connecting two or more devices.
• A key characteristic of a bus is that it is a shared transmission medium. Multiple devices connect to
the bus, and a signal transmitted by any one device is available for reception by all other devices
attached to the bus.
• If two devices transmit during the same time period, their signals will overlap and become garbled.
Thus, only one device at a time can successfully transmit.
• Typically, a bus consists of multiple communication pathways, or lines. Each line is capable of
transmitting signals representing binary 1 and binary 0.
• For example, an 8-bit unit of data can be transmitted over eight bus lines.
• A bus that connects major computer components (processor, memory, I/O) is called a system bus.
Lecture 2 9
Bus Interconnection
Lecture 2 10
Data Bus
• The data lines provide a path for moving data among system modules. These lines, collectively, are
called the data bus.
• The data bus may consist of 32, 64, 128, or even more separate lines, the number of lines being
referred to as the width of the data bus. Because each line can carry only one bit at a time, the
number of lines determines how many bits can be transferred at a time.
• The width of the data bus is a key factor in determining overall system performance. For example, if
the data bus is 32 bits wide and each instruction is 64 bits long, then the processor must access the
memory module twice during each instruction cycle.
Lecture 2 11
Address Bus
• The address lines are used to designate the source or destination of the data on the data bus. For
example, if the processor wishes to read a word (8, 16, or 32 bits) of data from memory, it puts the
address of the desired word on the address lines.
• Clearly, the width of the address bus determines the maximum possible memory capacity of the
system.
• Furthermore, the address lines are generally also used to address I/O ports.
• Typically, the higher-order bits are used to select a particular module on the bus, and the lower-
order bits select a memory location or I/O port within the module.
• For example, on an 8-bit address bus, address 01111111 and below might reference locations in a
memory module (module 0) with 128 words of memory, and address 10000000 and above refer to
devices attached to an I/O module (module 1).
Lecture 2 12
Control Bus
• The control lines are used to control the access to and the use of the data and address lines. Because
the data and address lines are shared by all components, there must be a means of controlling their use.
• Control signals transmit both command and timing information among system modules.
• Timing signals indicate the validity of data and address information.
• Command signals specify operations to be performed.
• Typical control lines include:
• Memory write: causes data on the bus to be written into the addressed location.
• Memory read: causes data from the addressed location to be placed on the bus.
• I/O write: causes data on the bus to be output to the addressed I/O port.
• I/O read: causes data from the addressed I/O port to be placed on the bus.
• Transfer ACK: indicates that data have been accepted from or placed on the bus.
• Bus request: indicates that a module needs to gain control of the bus.
• Bus grant: indicates that a requesting module has been granted control of the bus.
• Interrupt request: indicates that an interrupt is pending.
• Interrupt ACK: acknowledges that the pending interrupt has been recognized.
• Clock: is used to synchronize operations.
• Reset: initializes all modules.
Lecture 2 13
The End
Lecture 2 14

My Lecture 2

Uploaded by

Copyright:

Available Formats

My Lecture 2

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

My Lecture 2

Uploaded by

Copyright:

Available Formats

Microprocessor

Programming and Interfacing

You might also like