7

SI CAL DESIGN FLOW

flibs LEF DEF Sdc netlist U ScamDEF UPF

Floorplanning

Powerplanning

Placement

CTS

Post CTS

Routing

Post Route

closure
Signoff Timing
Physical verification
 Beif decription

Iaportesign
In this step we import all design files constraints files suchas
Netlist Adc impf def technology
file logical andphysical
libraries

Earp Lanning
Determines shapes and arrangements
the subcircuits ormodules as
of
well as donation external posts and Ip or macro blocks
of
Powerplanning

nets throughout the Chip

dk
Finds the spatial location cells within eachblock
Platement
of all
CI
Routes the Clocknets in the design with minimum skew and later
y
JostIS
Data path optimization which is done to avoidtimingfailuredue to
introduction Cts stage
ofskew in

Routing
modules based
Routing is nothing but ofinstanies
connection
on netlist connectivity
 Rante
Post
Datapath optimization which is done to avoid timingfailuredue
to added RC delays in Routing Stage

Signoff
checks we do with respect to ourdesign Includes
Different types of
Timing closure STA Physical verification DRC Lus ERCetc
 HE SIS
Synthesis is a process of converting a high level descriptionofthe
design written at Register transfer level RTL in a technology
mapped gate level representation

Three main steps of Synthesis

a Translation
b Optimization
c Technology Mapping

a Translation

So during translation the tool DC Genus interprets thelogic

constructs understands the primitive operators used in
Verilog
RTL description

The
final output of translation is in unoptimised internal
representation
of the RTL description

b Optimization

In this step the tool does

logic optimization andremoves
the redundantlogic
c
enology Mapping
So far design representation was independent of some specific
Target Technology but in this step the synthesis tool takesthe
internal representation and implements the representation ingates
using cells provided in the technology library
Tools
a RTL b lib
a Genus
b d
Design Compiler
Read RTL
Elabalation

Constraints
Apply
N

Mapping
Technology
W
Optimization

Scan Insertion

Incremental
Optimization

t
a Synthesized netlist
b outputSDC
c Scan DEF
1 Inputs RTL and lib are the inputs to synthesis lib is
used at the stage of technology Mapping

2 React
RTL is read and tool also checks in Rtc
for syntax errors
3 ELT
when the tool get the RTL file the designs are present in different
RTL files so during elaboration step the tool understands all
the verilog files and buildsone singlenetlist from all those verilog
files

a Builds data structures

b Infers
registers in the design
Performs highlevel HDL optimization such as dead
c Code

Is Converting the decision tree like converting if else statement

to a max
s is For example removingthe unloaded outputs

case is
I bo out io
I bt out it
endcase
 Max inferred and revisit this notthe
yourRTL
Check
Info if
intended behaviour ICDFor29 616

Mx inferred in file multiplexer v on line 20 column4

elaborationstep
Inferring during

Applying Constraints D Timing

4 Constraints

ii Design rule Constraints

Enample create clock name Clock period20 waveform210209

HiRisingEdge

infallingedge

Gac Synthesis
It In genericsynthesis the toolmaps thecells to thatgeneric
library Technology independent and gives us an un optimized
intermediate technology independentgate level netlist

logicaptimization
Tool tries to optimize the logic to removeredundant logic

Example a Removes the flopswhichhaveconstantvalues

b Removes unused cells wires
 Technology Mapping
During technology mapping these generic cells are mapped to
some specific target technology

Latch mapped V

module latch din dont en Porta

Input din en
output dontpart4
wire din en
wire dont Port4
wire m 0
assign Port 4 dont
CMOS40 LDLax10 dont GN th o D Idin dont
neg
MOS40 IVXIO le 4 Alen 2 no

endmodule

Cells to nm
Technology specific

Optimization
Ign
In design optimization the tool tries to optimize the design
to acheive optimal PPA Power performance Area
 Scan Chain Insertion
Scan chain insertion can be done by a synthesisteam
if it
is one pass flow or it can be done the DFTteam if
by
it is two pass flow
Incremental Optimization
So after scan chain insertion we do one more round of
incremental optimization

why do we need physical synthesis andwhat are the

Question additional

inputs
for it
Answers is For all standardcells poortools hasindependence to place as
per its wish but macros are the one we are fixing locations

In general synthesis genus tool considers thatmacros are connectedto

gates but in practical floorplan due to macroplacement memories
due to register path might notmeet as expected in synthesis

when we provide floorplan def which has macro locations syntheses

team uses this exact location andcompletes synthesis which is
known as physical aware synthesis

Since
physical location macros is known
of doingthis synthesis
by
tool can do more accurate optimization and report more realistic
timingnumbers and area numbers

Using the macro DEF synthesis team gets the idea abouttheinsertion
ofMBISTlogicinside the core area
 HYSICAL DESIGN
INPUTS
Is Verilog netlist e
Sdc
i Tech
lef
Physical def
N lib file
4 Sian def
Wii mm me file
Wii UPF CPF
Don't touch
I file
4 Don't use file
Xii Port DEF optional
Xiii Ewasplan DEF optional
 Netlist v
file
the connectivity information ofgates RTL
It contain

file is converted into technology dependentgatelevelnetlist

through the process of synthethis

Cii Sde constraint

file
a SDC
file is an ASCII text file with the extension soc that
contains designconstraints in the industry
and timing assignments
Standard Synopsys Design constraint format The constraints in
a sole are describedusing Tel tool commandlanguage
file
and follow Tecsyntaxrules

The constraints in SDCformat can be as

broadly categorized
constraints

b
a
Constraints
fortiming
area and Power
c Constraints
for design rules
for
d constraints
for interfaces
e Design rule Constraints

f timing Exceptions
 I create clock definition clock exceptions
Cii Generated clock definition is Multicycle path
Iii Virtual clock Lii False Path
Iv Input Delay Gil Half cyclepath
e Output Delay I Disable timing arcs
Ki Max Delay 01 Case Analysis
Will Min Delay
Hiii Max transition
tix Max fanout
X Clock latency
exit Clock uncertainty

contents are below

Description
of all these given
https://drive.google.com/drive/folders/10C-NALc82Laxbjx6dMkwVmnl5rucgzTP
hiii Aib liberty timing file
the timing information ofstandard cell lib contains
Contains

celltype functionality cell timings PUTConditions Powerdetails

leakage Dynamic

Ii common
partoflibcontains
in
librarynametechnologyname
Hi Units ofpower voltage current temperature
in Value of operating condition
His tellspecificinformation
Marx Tin typical of eachcell
Cell specific information in his
file is mainly
a CellName
b PG Pin Name
1 Area
of tell
d Leakage
Power in respect of inputs logicstate

Pindetails Pin Name

Pin Direction

Internal Power
Capacitance

Raise Capacita
Fall Capacitance
Fanout load nce

Hii Pinpart of lib file

IVI LEEPhy sa
The Physical library contains the abstract view of layout
for standard cell and macros LEF
file basicallycontains
I Size of the cell height and width
Symmetry of cell
Iii Pin name direction use shape layer
I Pins location

the Cadence tool or

This is library exchange formathdef for
CELL and FRAM Synopsys This isprovided
form for
by standard cell library vendor

Site information
Wi MMMe file
Taimode Multi corner file is used to generate different

analysis views based on different delay corners There are

various
library set files based on Voltage andtemperature
values like Ssoff itt

operating Modest fun

mode SianCapture ScanShift Testmode
Process Ss
ff.tt
Voltage lowVT 0.65 10 of065 typical V0 65 high 4 0.65 1010.6
Temperature Low Temp1m40 MediumTemp 0 C high Temp 125 C

DNot all scenarios are

taken intoaccount
Generally 216 Corners are present in total
but 530 40 corners are taken in ummc file
A We have to do timing analysis on all corners so that Chip
can function
properly
So using all corners the run time
is 130 40 corners are taken
very high for majorly
for timing analysis
 Nii Power intent UPFICPF file
The power intent file describes which power rails should
be routed to indivinal blocks It also contains information
multi voltage domains low power designs voltage shifters
Retention cells
always on Buffers I UPF Synopsys
Ii CPE Cadence

Xiii Stand
Contains scan chain information ofthe design DFTteamcreates
the Scan DEF and as an inputs to the PD team
gives

Cixi Don'ttouch and Don'tuse

there is one NANDgate we want
Suppose during Synthethis
to retain this NAND gate through out our design
Hence we will use don't touch nets
Don'ttouch HAND
gate
Tf we don't want to use some cells duringthe physical design

flow then we give don't use file For example ULut's we are
removing don'ttouch attribute on the wut's only after
postroutestage

4 Macho DEF
Contains
pin information location of size
ofMacro
Hi Port DEF
Contains the between theports
part location portname space
Wire load Model 7 present in deb

to calculate the net delays the PrimeTime I Tempus tool needs

information about the parasitic loads of wire
interconnec ions
Before routing and placement have been completed
Tool estimates these loads byusing wire load models
provided in the logic library
There are three possible settings in wire load models used
at different level of design
hiearchy

intop If the mode for the top level design is Top thetop
level were load model is used to compute the wire
capacitance all nets within the design at all levelsof
hiearchy
for

is Enclosed Segmented
In these modes wire load models on hiearchial cells
are used to calculate wire load capacitance resistance
and area nets inside these blocks
for
a Enclosed
In using the
enclosed mode Primetime determines net values
wire load model of the heiarchial cell that fully
encloses the net

b Segmented
If segmented mode is set Primetime separately determines
net values of the net in each levelof hiearchy
forthe total net valuefromthe sum all
andthen obtain
segments

of
segments
ofthe net
 Design
Mu

ni p ni n h ns NG
p y

Medium Medium

Is Zero wire load models

In zero wire load model the net delayof net is assumed as zero
the R and C constant values are taken as cero

In loadmodels
Custom wire
The net delay is taken generationchip of
fromprevious
same technology mode

in wireload Model
Contains the RC Constant values nets
of

Considering the design hierarchy :

TOP
MID (instance_u1)
BOTTOM (instance u5)
MID (instance u2)
BOTTOM (instance u5)
Wire load model for the given hierachy:

pt_shell> set_wire_load_mode enclosed

pt_shell> set_wire_load_model -name 10X10 \

[all instances BOTTOM]

pt_shell> set_wire_load_model -name 20X20 \

[all instances MID]

pt_shell> set_wire_load_model -name 30X30 \

Reporting wire load model:

report_wire_load
 SAIT
CHEE S
unity Checks are
done to check the

Adc and quality of libraries and

quality ofnetlist qualityof

lef
Check desi To check the qualityofnetlist

a Multidriven Nets
In multidriven sets there is no consistency that when I or o
is going to reach in the flops because of multidrivennets
is going to
Design
fail
I III multidriven nets
4
If you are finding any multi driven nets during synthethis
we will report it to the synthethis team

b Floating Inputs
Eating outputs

consider a circuit Forexampleduringworkingof amobile phone the

circuit gets heated then during that particular run the
noise interfere with the circuit and if the noisemargin
may
is low then it lead to the metastable state
may
FF
T Fiz
Jo
D Soultimately our main aim is to check for the floatinginputs
so that noise cannot interfere in thecircuit

So to avoid this floating input will to addtermcell

we
try
for floating input pins so that no signal interferes the design

Floating outputs are

not as dangerous as floating inputs

Iii Combinational loops

D9 HI a

Dj
a
CK CK
combinationalloop

a If there is some combinational loop present in netlist

D Using set disable timing we can disable one of the timing

arcs and on with our work
carry

Iv Undriven unloaded parts

ARTI design Engineer do not write the entirecode in asingle

day so he leaves certain spaces to accommodate in the

next stages leading to un driven parts

Dundriven ports is generally fine in the initial stages but

in last stage this issue cannotbe neglected Toresolvethis
issue we can connect term fell to the underiven inputs
b Assign Statements as

coming from other outputs

x Usually we assume some
signals
but during initial times the some inputs are directly
connected to Un GMD

Inputs are continuesly fluctuating due to IR drop resistance

If the input is greater than expected then this may
damage the gate

We do not want statement in

any assign input outportports
in the design So to avoid this issue Tie high and tie
dow cells to avoid the fluctuation

This addition
ofterm cell Tie cell is done after past route
the tool has done in placement Stage is well and good
If
Ni Emptymodule
Module

endmodule
Due to the empty module during the synthethis stage the tool
will allocate the more estimated area to the empty module
But
finalstages ofdesign should not have empty modules in
the design
Wi Unification
a Suppose a RTL engineer has written verilog code for Not gate
and this verilogcode was converted to Gatelevelnetlist

This AND
gatename will be presentfor will be for thousand
paths but we wantto optimize for only one path upsiring down
sizing Utswapping

each and
That means
every cell present in the path must
have their unique name which is called unification

0 Enabling Unification name will enable different name to

different cells so we can easily swap Ui upsizing Idownsize

set unification true If we want to resolve the

M problem temporarily
Before applying this command
depart to the synthethis team

4 Black box
any blackbox in the design
We should not have

If we are expecting a module and the module is notpresent

 The difference between EmptyModule and blackbox is that
emptymodules are intentionally present in the design

A module is called in the design but defining that module

is missing

Emptydodules BlackBox
Module YA B Module is
original

I
Innercontent notdefined

End Mode
Y odule instantiation is don

design do YE AtosBios
my

Original module do is missing

from the design
checks the quality
I Check
timing ofSdc
For
any of the belowpoints you can report it to thesynthethis
team
Missingclocks Assume we have too flops one clock is
going for
50 flops and other clock is soflops
going for By
mistake

the synthethis team forgot to define the second

By mistake if
clock So this comes under missing clock
till Multiple clocks reaching to same sink Pin
This will report we have multiple clocks at the same
if
sink pin
Ciii Missing Input output delay
There are 4 timing paths in the design
Input Reg Inputdelay
Reg Reg
Reg out output delay

Input output
For Input Reg and output there is no clocks for our
reg
flops calculation ofthesepaths are based on input output
delay constraints So if the Input output delay is missing
the tool will not able to do timing analysis
Is Unconstrained endpoints

For example
everypath is reg reg that means at the end we
need to have the register
If any constraint is missing
at the endpoint wet to neg thoseconstraint missing will
be reported under unconstrained endpoints
For example there are two differenttiming arcs if one of
thetiming arcs is missing then this will come under
unconstrained endpoints

pg
elk
X set driving all
The external driver that drives an input
port has impe
dance and parasitic load characteristics that can
affect
the signal timing To more accuratty take these effectsinto
account can use the setdriving cell command This
you
command
specifies the name of a library cell that is
preassumed to be driving the inputport

Using a library cell as a driver allows the tool to

more accuratly calculate the port delay andtransition
time especially for library cells having delays with
non linear dependence and capacitance

So using set load command to specify the amountof

capacitance on a port as a net allowing tool to
more accurately calculate the
effects of load on port
or

net delay
So check timing will check for set driving sell missing
constraint

Bygones
Design
setdrivingcell under load
Analysis jet
 Iilibrary
This command will check the inconsistency between tits andalef
among the standard cells

lets

Phtify
a
Ay
B D
i
y

toy timing are is

B

Physical def Ainput is present missing

B input is present
Y output is present

deb format Timing arc from Atoy is present and B Y is

not present
 OOD LANNING
Floorplanning Steps
Ii Decide core width and size die estimation
height for
M IO padsites are created
for placement of Io padplacement
Citi Macro Placement

N The standard cell rows created

for standard cell placement
v
Adding physical onlycells

Rough estimation area power andtiming are taken fromsynthesis

of
department

There are twotypes of approach

for completing floorplanring s
a Top down Approach
in Bottom
up Approach
I Top down Approach
In top down Approach the Chiptop level guy breaks thefloorplan
into different blocks whichis known as partioning

a PartitionShapes Square Rectangle Rectilinear

Block level Engineer completes the design andthe PEF file is

generated combinedwith otherblocks atlaterstage

In Bottom to top Approach 7

Block level decides the Is UtilizationRatio
guy
Y AspectRatio Iw
Aspect Ratio 1 Vertical
AspectRatio I horizontal

Rows are divided vertically in terms

ofsite
calledsite
The area in which the smallest all can be placed is
and obviously varies whentechnology
This is technology dependent

Changes The site information is present

in Tech lef

site
 Mamas are allinged to
Typesof
grids quid
manufacturing

in Placementguido
ginaggaduringggan

Coredimensions Ii width mustbe in 4 multiples

of placement grid
Height must be in 2 multiples of tell height

Macrodimensions I width must be in the multiplesofpolypitch

Height must be multiples offinfet
grid
The
first step of the floorplan is to read the netlist this will
init design
done
by the commando

Command to read DEF files

read def path of DEFfile
read side path of sacfile

Creating the Rows

create rows

Placingthe parts

editPin pinwidth pindepth spreaddirection edge layer

spreadtype spacing pin name
 Macro placement guidlines
Macro are like hard core IP's which is used to perform specific
tasko

is It priority Macros are placed according to the flyhie analysis

Preference Order t a macho parts

b macro macho
c macro standardcells
The moment when we load the DEF file we getchiptop
but we have to change it to floorplan view

There are generally three type of winos s a Physical views

b Amoebaviews
1
Floorplan views
d 3D view Innonus

So will switch to floorplan view andthen select

first we
all the unplaced macros into the core area

A Bad macro placement can lead to more congestion and

timing violation
Lin 2ndpriority
Macro placement is done according to hierarchical
naming
convention

RAMI G Cz Cz Ca G
SameNaming
Convention RAM

RAM

RAMA

Rains

are observing some common name thenthese macro should

If we
hear to eachother

3rd
priority
All macro should be placed to theboundary
near
of the core
Questions why macros should be placed near to the boundary
not in the centre

Solution Ii macro are placed at the center andstandard cells

If
are present at the opposite corners then there will be
and the path is timing critical this can
detouring
if
leading to timing failure
His Macros are power hungary blocks so that standardcell
around the macros
may not get the appropriate voltages
due to the IR drop hence we avoid macro placement at
the center
 Lower
Technology mode

Is Macro can be placed at centre and the Ir drop can be

by
avoided adding decapcells

ID In lower Technologynodes the internal layer of macros

uses less no
of metal layers so that the layer used
at the core don't detour which does not lead to timing
failure
Iii At higher technology node the supply voltage will behigher
so we need additional power mesh over the macro But in
lower technology node the supplyvoltage is less so we
don't need additional power mesh for macros

ioa the
gag for
posts

macros 09
connectionof
standard cells
gag
gag

C
ShapeApproach
4th Minimum channel length shouldbe maintained
Priority
between the macros

total no of macropins x pitching

Distance between
the macros Total no ofmetal layers
2

Reference metallayer
is the least layer so we wanted to with
Initially m go
the least layer which is presentbetween the macros

A offset distance is calculated

I
from metal pitch only
considered
a the offset is
full MetalAch usually between the
as the distante
tracks

Total spacing Spacingbetween themacros EndCap Welltap

boundary boundary
formula
 us

5thpriority Atleastone setof metal layers are needed exceptthe

top two metal routing layers

Apart from this after floorplan we dopowerplan so there

needs to be a proper power mesh collection fromtop

routing layer to the layer which would

bottom routing

be done in future so atleastthere mustbe atleast oneset of UDD

pair present tween the macros
Vss

If thestandard cell is present between the macros and if the

metal layers between the macros is not present then this will
lead to IR drop
To avoidsuch IR drop we need atleast one routing layer
from Un toNss pair from Top to bottom metallayers

6th There should not be criss cross connection

priority any
between the macros to avoid congestion
 7thpriority we will maintain the orientation between the
macho from 0 to 1800 to avoid the disorientationof
ofpolylayer
IEEE e ______

1800 900 82700

I 00 Rotation
Rotation

the polylayer but

There is minimum width which we need
for
due to the 902700 rotation of Macro the minimum Y
ratio of thepoly layer is voilated

8thparity
D Placement of endlapcells Ranting blockage Halo
around the macros

A Halo and Softblockages are same in terms of blocking the

placement of standard cells The only difference is that the

halo can move along with the standard cells whileshifting
the location but soft blockage cannot
Halo Placement
associated with macro
Halo are nothing but placement blockage To
the halo will move accordingly
we move
macro
so if the edge of the macro and to avoidthe
congestion on
avoid the the macro to avoid the placement
bare DRC halo is put
a
on

standard cells
of

Routing blockage

Routingblockages is used to prevent the route in a particular

area
for specific metal layer for all signal Pianets

If the internal layer of macro is made from ma m andmy layer

then to avoid the shortsbetween macro internallayers and
routing layers of lore we place routing block over the macro

hence
The manufacturing
of Ic's happens layer by layerprocess
this is one ofthe reasons routing blockage is placedabove
the macros to avoidshorts
 10th
Priority Macropin should beplaced towards thecore area

The reason is macro is connected to thestandard cells andthe

majority of the logic connections is within core area so macro

pins are placed towards core area

If there is communication with respect to ports to

any
pin thenthose pins going to place
memory we are towards
the ports

10th Avoid notcheswhile placingthe macros

priority
 Ipriosity the placementstatus of macros is termed as
fixed status The tool cannot change this If the tool
changes this then my
channel
spacing is not thatsufficient

I fined in
Placement statuses place
fix
hisSoft in Unplaced

Macros are allinged to manufacturing grid and as a user

we are going to allingthe macros with the manufacturing gui

a Snap floorplan block is the tool command which will help to
snap your macros to
your manufacturing grid
 After the area is fixed we are trying to create rows
because now is the standard
legal site placing the
for
cells

Row height is the multiples of standard cell heightbecause

some standard cells will be multiheighted
of
4 If we are doing from chiptop level then the firstthing
we will get is port def and we will go with portdef
first for easier flyline analysis
So to read the def file the command is

Mead def filename

common command forreading anydef file whether its
ofstandard cells or macro def or partdef
Go
Sourcingthe file
in DEFformat on
a
If we forgetthe Syntax of
read def then in the tool shell

will departall the

mad I def This
correct s ax relatedto it
 status fined In further stages during
Applying for macros
optimization we are not giving tool chance to move
any
the macros even I am
by
If tool is trying to move the memories then during the
plan
power it may lead to opens wort to memories

set db get db insts if base tell class core's place status fixed

There are
four status for macroplacement s

a Unplaced b Placed c
fined d Soft
fixed
L
Thestandard Celland You are
macro is not placed on explicitlyfixing
the core then the the status
category comes
under Unplaced of macro

status
L
I Can move themacroswithin
the rangeof20am

If any standard cells needs to be placed hear the ports

status
then we can use soft
fix for macros
 Parteffinity buffers
Mean the ports the porteffinity buffers are placed these
are added so that the signal strength is not lost

output
port
Input port
Buffers
Buffers

Placement status is as fixedstatus

of output port Buffers placed
These are placed hear to the port
Command
for adding port effinity Buffers
add io buffers typecell port status

Austin whatare information neededthe buffers to place the parts

Answers
a Portname
b Pastdirection

ports on which metal layer it is placed

for
c Reference

d Location Edge
A Tracks are used as a reference
for Parts
Attribute Ii getdb getdb is used when we wanted to
s

know which attribute is presentinitially

setdb want to change its attribute

If we

then we will use set db

Tf we are trying to putthe ports byourself then we need a

create tracks usingthe
reference point so we first
command

Is create tracks Referenia

forports
dis then we want to have poet name
Hi then want the
we
edge in which the
needs to beplaced
port

Now shouldhave
post this part
whenever we are a
choosing
a communication possibility with lowermetal layers
equal
andupper metal layers If we are usingthe top or bottom
metal layer the connection of ports then we mayhave
for
to drop large no of vias for the connection with the
m 5Mt
other parts chips
f
So mostof the time wechoose Mpmoorms
mt
 Question How to decide which metal layer is horizontal or
vertical

Answers ismo will beharviontal becauseinitially p welland

n well both are hoviontal

in whenever one metal is horizontal then another metal will be

vertical in that manner we can detect horizontal Vertical

we can place the ports based on the tracks or basedon

the micron distance

Danity floatplane
as in Care area widthmustbe in multiple ofplacement
heightmustbe the multiplesof cellheight
grid
ii Core area and die area mustbe clearly
differentiated o

Iis Marro Sanity checks

a No overlap between Macros
b Status should be
of macro
fired
D Halo must be checked whether its placed or not
d End cap is present or not if it is a base Drc issues
e Routing blockage is present or not
Iii Sanity checks with respect to final floorplan s

a Entire chip has well tap coverage or not

ease
l t
I l

so so
g
eas l Minimumdistancebetween wee
tapsmustbe below sopgicrons

When the macro is

large enough then
the well tarps
cannot be placed with equal uniformity

Two case will arise Case 1 cased

Well taps placed in Case 1 is valid because it is still

in case 4 the
maintai
minimum
ing
the minimum distance which is to be needed but
distance between well taps is
not maintained

b There should not be any overlap between EndCap

and well tap cells
 in_f
a Minimum width violation is present or not
b Parteffinity buffer is present or not
c Ports are allinged to tracks or not

d unplacedports
e
Multiple ports for same tracks I lead to short

etc
for checking min space violation
Commands unplaced ports
check pin assignment

Command
for checking overlap between macros
check place
between the macros so that
sanity check
Command
for
minimum internal distance has been followed or not
check welltap
 Questions Before starting the floorplan what is the proffered
initial density initial utilization
Solutions close to 50 551

If you are given a def and the density is given as 50 551

good to go face the
then we are otherwise we will
congestion 161 65

Question what is the significance

of floorplan LEF 4 DEF
Solutions is Floorplan LEF DEF of a child is given to the
parentblock

used
These are
for physical synthesis
Floorplan LEF and DEF will be given to caliber to
check base doc

101 It is also given to IR team

for IR Cri'd Checks
POWER LANNI IG

VDD
Due to resistance the signal Power current is decreasing CIRdrop

Capacitance a Width ofmetallayer

For better distribution power network across
the core area
of
the metal layer should have lessResistance more
Capacitance

But as the metal layerthickness decreases then u have

more resistance and less capacitance which is not
the ideal case
for powernetwork

To compensate the capacitance of the power network

we provide multiple n
metal layers for increasing
the capacitance

spited

current
distribution
 As we frombottom to top s
go
a Data tracks is decreasing
a Paver tracks is increasing

staples are nothing but small parts of metals

Resistance is more
8 0 Power staples

in staples that is
y tf j space is
forsignalrouting
left
the reason we
don't connect it D8 BE

back to back
Mil stripes
mio stripes
Ma staple d Since the Resistance
of
Ms staple sothey are not connected
back to back
Ma staple
Mo staple
ms stripe
To connect metal stripes metal nias isused s
a
Single cat
b Multi cat was Resistance is lessdue to
parallelconnectionofstripes
Actually in a
given power mesh the supply voltage
Upp 0 65 Volts
Uss O volts

6 But in
reality
UDD 0 64 0 63 0 62

Iss 0.0 1 o 02

Challenges are more in lower technology so more no

of metal layer are used

Command for timing Check atfloorplan stage

report design pre place

 Powerplay
Sanity checks for
a Nias
Missing
b Check
for opens
c Check
forshorts
level DRC's
di mo base level DAC Sent to power team
Lin m mi metal to check the robustness
mesh
ofpower
is created
db
file
Given to caliber tool

to check the base level

DRC

How to check tether the content

of UPF is
correct or not

Solution CL P Conformal low Power Check

The UPF is taken as input and it will check whether the

all the syntaxes are correct not and whether one

or

and one ground is or not

power supple supply defined
whether values have been assigned it or not
 HYSICAL CELLS
I
well tap cells are placed at regular intervals in standard cell now
and distance betweentwotap cell is given in the designrulemanual

given by foundary
Thesecells are added in the design to avoid Latchupissue

These cells are added beforethe global placement sothat it uniformly

covers all standard cells in the design
Well tap cells are added at pre placementstage

add well taps interval cellname

Provided Typeofthe cell

by
TSMC in the library and
boundary
uponthe
Based a drivestrength
technology nodethe internal

changes
well taps at
8 8 As Regular Intervals
a welltapscannotbe
added where macros Welltaps are added all
F
I E
ÉBb faga.iq

MMM W W overthe designtoavoid

are using morespacing Catch
up
Well
tapscannotbeplaced
Latch
up phenomenon

i
Hi Tieu
purpose cells whose output is constanthigh or low
These are special

The inputs needs to connected to the the transistor andthere

gate of
are only two types of input logic 1 and logic 0 but we do not
connect them tothegate of transistor due to Voltage
fluctu tions
directly
which can damagethe transistor so we used tie highand

Tie low which is connected to Upp andus

of Ciaosrespectively
the tool adds during placement
stage its well andgood
otherwise
If
user has to add after post route stage

d why Tie cells are inserted

And Thegate oxide is verythin and it very sensitive to voltage

fluctuations If the gate oxide is directly connected to PG
network the
gateoxidemayget damaged due to voltage fluctuation
in power supply To overcome this problem tie cells areused

Fight Tiehigh Cell Fig 11 Tielowcell

ii Filtered
youhave completed placement and
routing there are usuallygaps
Once

left in the layout where you do not have anystandard all present
It is notpossible to abutevery cell available as that would cause
routing issues due to high congestion So if yousay youhave
70 utilization then you can expect 30 ofthe area as unfilled

If you do DRC Check now base

layer DRC you tanexpect to see
spacing violation like N well minimumspacing
notmet This
need NWELL
where
filter cells come in For a clean layout you
continuity

Filler cells are the cells with no logical functionality but it

continues the base layers like Filter cellscome with smallest
tile width in the standard cell
library amongother sizes
which can
fill any gap if your placement followed the placement
grid
A Standard all
fillers are added pastplacement to check forBase
Drc Metal
fills are added after postroute
v7 Deeptells
charge storing device madeof the
Decap cells are basically a Capacitors

and ad to support the instant current requirements in thepower

delivery network
in
the instant largecurrentrequirements
There are various reasons
for adequate measures have taken to
the circuit and if there are no occur
droop or ground bonnie may
handle this requirement power
These droop or bounce will affect the instantpowersupply
power ground
and ultimately the delay standard cell maygetaffected Tosupport
of of delap
the power delivery network fromsuchsuddenpower requirements
cells are inserted throughout the design

De capcells are added at preplacementstage

Decap cells
Fig

6 BoundaryCells Endcap ells For Proper Ending of Rows

which are added to the ends
Boundary cells consist ofend capcells
ofthe cell rows and around the boundaries ofobjectssuch as
core area hard macros Voltage areas which fill the emptyspace
between horizontal andvertical end cells
cap
These cells are positioned in design toguard against manufacturing
damage to aregular cell gate that is located close tothe
border

A Endcap cells are avoiding the boundary's baselayer DRC

IN well andImplantlayer

Endcaps are added at floorplan Stage

Splitt command to endthe rows whereverEndcap is

So there standard cells be taced

found if are no vows no can

Endcap are also used as the reference

for rows
J i
C
 I is a process of placing thestandardcells withinthe Core
Placement

boundary in an optimal location The tool tries to place the

stand
and cell in such a that design should haveminimalCongestion
way
And the besttiming

H Pnrtool provides various switches so thatusers can optimize the

pacement in a better in terms oftiming congestion area
way
andpower as
per their requirements

rent Steps
Pre placement
Lii Initial Placement Coarse placement Mahal placement
legalization
HENS
0 Iterations
for Congestion Timing DRV andPowerOptimization
Ci Multibit flop conversion
Hii Scan chain reordering

I Tie cell insertion

Pre placement

Before Starting the actual placement of the standard cells present

in the synthesized nettist we need to place various physical
cells like End lap well tap Io buffers AntennaDiodes
only
and spare cells
 2 Initial Placement coarse placement
global placement

Before starting the placement we have to providecorrect

optimization settings like bound regioncreation path
groups
ite
pre plugin

After providing all these placementsettings we can call the

placement commands place optdesign

Figs layoutdiagram NANDgate

 I placement s

During
Coarse placement the tool determines an approximate
location
foreachcell according to timing congestion
connectivity

theplacement
The placed cells don't
fall on
grid andmight
overlap with eachother

Legalization

During legalization the tool moves the cells to legallocations

on the placement and eliminate overlap between
grid any
the cells
in the location cause the
these small
c hanges
During legalization to new timing
connections to change possibly leading
lengths of
Violation
 Lacement w r A timing

0 After Placement we to place standardcells in more optimize

try
based unis andThis
way
WNS worst negativeSlack
TNS Total negative Slack

to Reg to Reg paths in a design which

that there are
Let us
say
are violating

Path I 200ps Slack

Path 2 D Loops
Path 3 50ps
Path 4 hoops
Path 5 15ps
Path 6 75ps
Path 7 tops
Then in the above case
Path 1 is having the worstnegative
slack
TNS
4 Adding all negative slacks will give

So to summarize
Was 200ps
This 1200 too 50 t 100 t 15 75 10 650ps
0 The tool tries to wills and on fining the WNS
first fix
in turn TNS gets reduced

optimizations donebythe tool Plan ment Stage

Timing
I ut Swapping Usually there are 4types in a standard
cell having same logic These are

1 HUT in SVT in LVT N ULI AfterPaget

These cells are having delays depending on their doping

U lui's are concentra
having ion
the highestdoping and requires
less time to turn ON

Same HUT SVT D LVT UL VT PropagationDelay

Size HV TL SVT L LVT C U LVT
Leakage power

low it decreases the transition time and sopropagation delay

decreases
Y'D Up Increasingthedriver strength
sizing

Standard cells having higher drivestrength have higher E

ratio cells comes with
varying drive strength

0.25 to 32 Drive strength

I 0.25 to 0.75 low drivestrength
Don't Use
til 24 to 32
high
devicestrength

A In Higher the drive strength more area is used in thelayout

3 Inserting buffer Inverter Pair

long
distance
routing huge RC leading to RCdelays
means
A good alternative is to use
buffer repeater I idling the
line into several paces

Buffer is inserted in between the data path launch and

of
Capture
flop to break the net

to somedelay but this

This buffer addition contributes
in delay
delay is compensated by the reduction
which we receive breaking the net
by
 Cloning
a Cell Cloning is a method of optimization that decreases the
load of a very heavily loaded cell by replicating the cell

is done identical cell to the

Replication
by connecting an
same inputs as the original d Cloningclones the
all to divide the fanout load to improve timing
I IDF
FF IFz

i
IDF
FF

7 I D FE
FF DI

FF

M
beginning
logic restructing means to rearrange logic to meet timing
constraints on critical paths designof
to a
AND NOT HAND
 Vi Pin Swapping
Pin swapping optimization examines the slacks on the inputs
of the gates on worst timing paths and optimizes the
timing by swapping nets attached to the inputpins so the net
with the least amount of slack is put on fastest path
through the gate without changing the structure oflogic

Interchanging the
datapaths tothepins 7377
j In Gizahighesttiming arc
is taken as a celldelay

There are
generallyfourpath groups In Reg In out

a Rg Rg
b
Reg out
e Input Reg
d Input output

In out Combinational circuits Registers are inside

the blocks he in out path contains the ports between
the input output parts Nologic Inbetween
 CONG EST I N

no ofInstances are placed in smaller Area

Congestion
If more
then numberof routing tracks available is less than therequired
tracks
Available Required
Tracks Tracks

The tool deports Congestion based upon horizontal Overflow and

vertical overflow

Horizontal Overflow Verticaloverflow C OI

G cell This horizontal vertical Overflow is calculated based

on G cell
0 The tool will reportcongestion basedon G cells Each G cell is
basedon that thetool reportscongestion
having some tracks
MD MS
Gell
Biffy any
ma É rffpins Buffer

If each ball is having totracks and12metal layersthan the

total no oftracks available is 1200 doubt

LocalCongestion
Congestion
GlobalCongestion

Congestionwith respect to each G cell is local congestionandadding

these becomes Global Congestion TracksAvailable
all of
RequiredTracks
5 it Is a
Gcell
s 6 F
4 is
 Due to there is aformation of hotspot
congestion

Maxhotspotlocal hotspot 50
Globalhotspot 100

Congestion depends on

1Celldensity If there is more no of standardcell in a given G Cell

is Pin density when there are more no of pins than required

in a particular G cell the tool reports congestion due
to the increase in pin density
Iii Placement
ofstandard cell near to theedgeof macro
Bad floorplan
 ULT I BIT FLIP FLOP CONVERSION

bit are converted to multibit because

Single flip flop
flip advantages due to its architecture over SBFF
flop
Matt has
many
Internal structure of Multi Bit Flipflop

The Soc implementation using multibit flip

conversion results in lesser
of clocks sinks as seen clocktree synthesis tool
member
Hence
by
their usage results in lesspower consumption clocks in
all the
by
a clocknet
flip flops as overall capacitance driven by
gets reduced
This should also reduce clock skew in sequentialgates as the clock
paths are balanced in a whole multi bit cello

The SoC implementationusing multi bit flip flop shouldresult in

smallerSoC area as the total numbers of clock buffersshould
reduce resulting in lesser congestion
3LOCKAGI
Routing blockage

Routingblockages is used to prevent the route in a particular

area
forspecificmetal layer for all signal Panets
If the internal layer of macro is madefrom ma m andmy layer
then to avoid the shortsbetween macro internallayers and
routing layers of lore we place routing blockage over themacro

hence
The manufacturing
of Ic's happens layer by layerprocess
this is one ofthe reasons whyrouting blockage is placedabove
the macros to avoidshorts

i Placementblockage
Blockages are specific locations where placing of cells are prevented or
blocked

a Hard Placement blockageWill not allow

anystandard cell to
place in that region We will put placement blockage
only
where the bell taps or End Caps cell is not
present
to avoid the DRC Violation
 So only after adding the well taps I Endcap cells whatever
the space is left we applyplacement blockage to that
region

b Softy aye
This placement blockage won't allow anyof combinational cells
or sequential cells Only placement investor is
of buffer
allowed

c Partial blockage
In a particular region we are partially blocking some area
and some of the area placement is allowed
for the
placement of standard cells

ex S

I Softblockage will not resolve congestion issue

in hardblockages notresolve it

M Partial blockages Congestion is improved to someextent

in certaincases
inPadding Restrictingthe placementof standard cells near to one of
the required standard cells Better form of
placement blockage
is known as padding

a Instance
padding
Padding which done on the entire hierarchy of cells is called
instance padding

b Cellpadding
a whenever we are finding a problem withrespect to oneparticular cell
then we
go for cell padding

D In the cell name example AOI cell then all the AOI
for
cell will get the constraint

Questions which site paddingneedsto be done

Answer top 1bottom Left1 Right
If we are specifying onlyleft the this command do cell
padding only on left side

1XjT
instance

padding
 In standard cell padding is done oneside
first on
Hi then routing blockage is applied over the macro

So we have only threetechniques to avoid congestion padding

partial placementblockages spreadingcells

Routing blockagewithrespect to Drc

Tf due to the two differentmetal layers there is a shortinthe
design then we can applythe routing blockage in that area

for one ofthe metal layers to avoidshort

are mean

lil Cornerpads
É
ITEMthMI

415 Boundary
Pads Figg

Iii Powerpads rue

Scands If
from library
theists
And
if the
cen which iscoming
standardcell is notworking
as intended in the RTL design we need one method tocheck
this unintended function of the cell
Now to test what they have is inside the flop

To Mowwheneverthey want to
By Dee
s test the functionality then
SE
they will enable scan enable
elk BY to 1
Sian D flipflop

when the select line is't then the SI willget enabled

and this keen input passes through the pin
if of
the flop then the flipflop is workingcorrectly Thismode
is known as test mode o

o we are externally giving SI inputs So there is two types

of netlist
is Mormal Metlist
ScanEnable Neth'st
 Inputpins of a scan enableflop

Imjin ftp.nutein
SE ScanEnable Scan output Sto
clock
SI ScanInput

The clock is seperate in the scan flops and metused

during the scan chain operation For SI so transmission

scan clock is used

Scanchain
whenever we have of scanInserted flops we pass
a series

some testvector at the input of scanchain and the

if
output is same then the flop is workingcorrectly
flip
the scan Input Vector SI is not same as scan output
If
50 then we need to break the chain from the last flip
Backtracing
flop
whenever they create scanchain this mustbe present in some
that area itself is known as scan def and once
area
the scan of is providedby the DFT they are considering
it as a input a PD
Modes in mmmc
file fume mode scancapture
scan mode scan shift
Testmode
6_dtechniqe Timingfires

I Regioncoration
whenever we are seeing a hierarchal split in design which
is contributing to timing failure with huge slack then
a

we choose user defined technique calledregion

a Region

whenever we want to place one specific hierarchy in

one particular region and other hierarchy cells are also
allowed
if we have enough space in thatregion
 b Fence
Whenever we
want onespecific hierarchy in one particular

region restrict the placementof other hierarchies we

use fence

c Guide
Guide is a technique which is to placestandard
cells which belong to one hierarchy in one specific
region and allowing tool to relocate standard cells
to otherregion to have bettertiming
 using fence the mandatory thing is the
whenever we are

area must be sufficient the standardcells It is should

for
not be more should not beless
Pathgroup
Pathgroup is a user defined technique which will be used
when we have a stout point end point near to eachother
but we observe there are detourednets and alsoscope for
data optimization
D a
D a

clk clk

a tf locationwise of the cell hierarchy is at same location

but observesome timing fail in these groups then we go
forcreation ofpathgroups

Basic path 1 2
groups Reg LReg highestpriority
2 Reg2 as 2ndhighest priority z
3 In
Reg Equal priority
4 Reg out
11 weight
age
5 In out
 India Bangladesh

Pakistan

yfjGÉÉÉMt

Path is failing between India Pakistan Bangladesh For example

India Pak s topaths are failing

Ind Bangladesh s 8opaths are failing
Hi Pakistan topaths
Bangladesh are failing

If the total design has too paths and all are Reg Reg so
initially if we are not creating any path group all
will have equal weightage

If we create a user
path group for 80paths then these
80paths will be excluded the Thenthere
from design
will be 620paths remaining and we are creating user
name
defined path group with a separate
 Now after creatingthe pathgroup have
for example we

India pakistan India Bangladesh pathsboth are failing

by 100ps then the priority will be given to
India Bangladesh becauseof path grouping

Question In which cases creation

we
gofor path group
Anne I Detoured Mets

whenever we are seeing a logical split or hierarchical split

then we
go for region creation

whenever that my start point I End point are very

we see
near to each other then if there is a detoured path
we
go for path grouping
from to adjustment waight
slack
group path name effort

create group type

boundaryanstrainy
path Reg2 Reg
means priority high how medium
Effort 011,21
weight wrtnumbers
Is meaning nextpage slackadjustment rays
Slack Adjustment
slack that are telling the tool better
adjustment means
you for
additional Slack
optimisation
byadding
Ciii Incremental Placement
D Magnetic Placement
d Scan chain reordering

achecksoften Placement

a setup check
DRU'so

Ciii congestion report

IvagneticPlacement
for a complexfloorplan or to improve
To improve the Congestion
the timing
for the design we can use magnetic placement
to specify fixed object as magnet and have tool placed
all the standard cells connected to the magnetobjectclose
to it
WHENS
The process
of buffering the highfanout to balance the
load because design has too many loads then it
if
affects delay and transition time We know that delay
of load is directly proportional to the delay By
buffering the high fan out nets the load can be
balanced and this process is called HFNS
 Example of HighFan out Mets Reset preset ScanEnable

HENS r E
D
D
D
D

HENS does not need skew balancing buts cis needs

any
balancing The buffers which are added in HENS don't
equal rise time and time Hens mostlyhappens fromInputtoReg
fall
Scan chain
reordering
It is the process of reconnecting the scan chains in a design to
optimize
for routing by reordering the Sian connection which
improve timing and congestion

Since logicsynthethis arbitarily connectthe scan chain we need

to perform Kan reorder after placement so that the scan
chain routing will be optimal
Based on
timing and congestion the tool optimally places standard
cells while doing so
if scan chains are detached it canbreak
the chain ordering t which is done a scan insertion tool like
by
DFT Compiler
fromSynopsys and can wander to optimize it
and it maintains the numbers offlops in a chain

a Reordered scanchain in rumplesdesign

Conjestion
Fffects
may take the
During placement the optimization scan chain difficult
to route due to congestion Hence the tool will reorder
the chain to reduce congestion
TimingEffect
This sometime increases the hold time problems in the chain
mayhave to be inserted into the
To overcomethese buffers
scan path
Incremental Placement

For example if there are 20 Reg Reg paths outof which

have 10 paths having
we ve slack Remaining topaths

having violations
has still
path from1 to
Data 10
path I 200ps
path 2 180ps Scope to fire Sowe ask tool
to put more these
path 3 160ps effort on

path 4 150ps paths to theviolations

fir
path 5 140ps
path 6 130ps a The input db is placementdb
path 7 120ps and we enable the switch
path 8 110ps to was
fin
path 9 loops
path to 90ps
0 So the zoo value will come to hoops but the

TMS won't be optimized much o

th
Runtime
o
3 time Required for placement
Checks Placement
after Stage
I check legalization
I Check PG connections
for all thecells
Iii Checkcongestion reports
W there should not be wits violations
Timing OOR any
VI DRVs
Lui Check total utilization ofdesignafterplacement

Modes
Understanding different

Is Functional Mode

Pjajnnn.sn
s
nsw
UK SE

I we are talking about scan inserted flip flops we are

having 2 mines inside a scan flip flop
 To send the data functional clock is used
your
1
In scan mode scan clocks are used to sendthe data whenever

scan clock is enabled the scan enable signal becomes I

Whenever SE becomes I so will will betravelling to SI of2ndmax

so the entire data path is disabled

D
Wha
Ak SE

In scan shift mode sincethe datapath is notinvolved so combinational

delay won'tbepresent

Scan
Capture
Tuk qt Taib t Tsetup E Tak
Tak q t tsetup L Tak Setup Equation

holdEquation Tambo
Tak w I Tak
Siang
 MhistMode s MBis t Memorybuild in selftest

Since macro pins are completty hardcoded IP's so mux logic

cannot be introduced in such designs to test the macros

So to test these blocks some logic is introduced in the design

to test the functionality ofmemory

this logic is by RTL atsynthesis Memorieshave multipl

introduced

clocks one
for testing and other is forcheckingthefunctionality
So in taBistmode the testclock is to
going frommy memory
Register The tool will report mem to Reg path for setup
violation

So this analysis will be for testing notfor the functionality

check
If the timing is failing in mem to Regpath that
means the is not working as expected if the
memory
is not as expected then this lead todesign
memory working may
failure

So in 19Bistmode also setup and hold Analysis is done

ECK IEEE SYNTHESIS
 cc opt design steps

dieting
this step
During CCOpt will build
only
a DRV aware clocktree

ant will not balance the clocks

lil Balancing
Copt will balance the design as
per skewgroup constraint

Hi Routing the clocktrees

During this step kept will route all the clock tree netsusing
nano route engine

In Post conditioning
This step is used to clean
any minor degradation afterthe
clock routing due to signalIntegrity
 In placement stage when the optimization is complete the
the slack is met when the clock is ideal

But in Cts stage the real clock comes into picture and
skew is introduced in the design

meet
To theslack since the clock nets are already detailed
routed so we need to do the datapath optimisation
to meet the slack this step is known as post TS

Again after post cts the setup hold slack is met

But in routing the physical connection is done to the cells
due to this the picture andthere
net delay comes into
are setup hold violations in the datapaths to avoid this

again the data path is optimized in postroute stage

Till postroute stage the timing analysis is donebased

on GBA but in Sta the timing Analysis is done
in PBA mode
CTS definition
Is is Tprocess of building clock tree to have minimal
skew and minimal latency

Clock Block level clockpart

source chip level PLL

The step of Clocktree shouldbe to reach all the

first
flops
Our next priority should be to make the clock reach
the source at the earliest minimum latency
point
The time taken the clock from the
Latency
by
clock definition point to the sink pin of farthest
flop is called Latency Maxinsertiondelay

A latency and Insertiondelay both are same

Reports generated after CTS it will show as latency

and in it will show as min insertion delay
log files
and max insertion delay
 outraging
top too A
Et
AKEAKEAKE
B
oo
C

Insertion delay A 3ns Min Insertion

ofB 6ns Max Insertion
c 4ns

Min Insertion Delay The time taken by the clock to

reach to the nearest flop is called minimum
Insertion delay

Max Insertion delay The time taken the clock to

by
reach to the farthest flop is called max insertion
delay

SkeeofAIB Insertion delay A Insertion Delay B

ar

Difference in latency of two flops

Sy groupclocka is defined in sole the tool is going

to define group which is known
a as skew
group
same clock
Its a
group of flopssharing
 Gasparyan
WTF
FF
our
id
qg
i
if
oooh oooh

q
our FF FF
oar
is if if if
if if if if if if

Glohalskent The difference between clock arrival time

and nearest flop which belongs to the
for farthest flop
skew is called
Same
group global skew

Global skew Max insertiondelay Min insertion delay

Local Skew Its a difference in clock arrival timebetween

the launch flop andcapture flopfor a valid timingpath

4 If the data path is easting between the flopsthen

consecutive

there will be a skew

 glob

Out of the
two skews the tool will always try give more
importance to local skew than global skew because it
always corresponds to a valid in a design
timing path
So inside a skewgroup

Ii First the tool well build the clocktree then the clock
will ensure that the it should have minimum insertion
delay between the flops

I Mow after this the tool will

try to have skew balancing
in all the paths

Source Delay Sourcelatency

from the clock origin point to clock definition

The
delay
point of the design
Network latency
Insertiondelay Networklatency is defined as the delay from
the clock definition point to the clock pin of the
register

Ie Jitter is the short term variation of a signal

with respect to its ideal position in time
or
Jitter is the variation of the clock period from
to It can 1 jettervalue
edge edge vary
In multiple clock domains
Asynchronousclocks if these clocks
do not have a common base period thenthey
are called a asynchronous clocks

Generated clocks Generated clocks are the clocks that

are generated from other clocks
by a circuit within
the design such as divider multiplier circuit
 In the design whatever skew we have we are going to
is going to be added in the clock period

Negativeskew s the clock period is

So in case of
going to decrease
Positive skew the clockperiod is going
to increase

Inputs CTS Placementdb

Specfile

We putsome constraints while building a clocktree to build

a better quality
of CTS These constraints are given as an

input for the Cts and are stored in Specfile

Inshortspecfile contains all the specifications which is given

to the tool for building clock tree
Contents in Spec user defined constraints
file
Is Primary Delay Corner
Due to Ocu different standard cells are having differenttypes

of delays due to different Put corners

So for setup check ss process is involvedand for hold

is taken
ff recess corner
If we arenotgiving any constraint the tool cannotgo
with proper tree structure hence we specify the
primary delay corner which can be used by the tool
to build the clock tree for different setup and hold
conditions
loops

90ps

We give setup as more priority so

for setup ss low't lowT
metalwires R Ccworst
High for more delay worst

Setup corner is Functional mode

it ss process
iii low Votage
10 Low temperature
v Cworst
vi cc worst
 afferent Combinations are s

i process SS ff tt
Put corners
2 Voltage low high typical
3 Temperature low high typical
4 RC ofmetal Cworst Rebest
J
best RC
worst Rc corner
Coupling Capacitorofmetal Coworst Ccbest
modes functional mode Scan
Operating Shift Scan Capturedmodes
Testmode

In the hold Case the tool will do report timing so this

will report the timing in othermodes and corners then
we come to know about the other dominant corners

XBut best practice in many designs the primary delay

as
corner will be slow process low 4 low Temperature

2 Skew Target Since we want the clock to propagate with

minimal skew and minimal latency then we need to
specify the skew targets for
our design

3
Lucy target
4 Preffered Metallayer
D Since the toggle rate of clock nets are high so this can
lead to EM violation hencemetal with more width
is chosen So this contains the top proffered metallayers
and bottom metal layer which is used to build clocktree

Exceptthe top two Power Ground connections below 4nets

are used to make the clock trees

I Forexample Mil Top metalroutinglayer Mio Pgconnections

I m
g mo Mo my Proffered metal layer

NDR Rules
Route Rules
forpuffer clocknets
For defining the route rules we are diversifying cts nets

into three types

Top 3W 35

Trunk 2W 25
IN its
leaf

a clocknets will always have

MDRrules at V

Defaultrules means that the

spacing width which is already

defined in the Techlef
 Max Transition Limit
Weneed some extra pessimism inclocknets fordefine transition
limit in our specfile This transition limit is different
from the transition limit values mentioned in the sdofile

MafanoutImet
Man Capacitate
listof Buffers Inverters to be usedfor cis
a Buffer 618,10 Drivestrength
4 Inverters 8,10
Only LVT cells are used for cts

Max netlength
Largernet length leads to transition violation in the design
so to avoid the transition violation max netlength is
specified in the spec
file

I CTSEnceptions NoTDon
listof Id with drive strengths
Idg incurknets
I Toavoid the crosstalk issue in the nets proper shielding
shouldbepresentbetween thenets This is done by adding UssIUD
between the nets
 4 But in general is proffered because Upp requirespower
Uss

supply which will lead to

additional powerconsumption

Spec file is generated

bythe tool and given as an input
to CTS So it is considered both as a inputfile
and as an output file

In CTS
specfile isgenerated Userdefined Specfile
the tool constraint is
by
commandsmputadded
this content is written in
preplugin files

A Iii This cointent will be

file appended to your clock
tree spec file
CTSEXCEPTIONIS

I Monstoppins gpus
Monstops pins trace through the endpoints that are normally
considered as endpoints
ofclocktree
Enampf
The clock
pin of sequential cells duringgenerated clocks
an implicit stop pins clock divider circuit
Clock cells
a pins of It or
sq

D Q D A

DANK D

Through pin

Endude Pins
Ended e pins are clock tree endpoints that are excluded

tea timing calculation andoptimization

from clock
The tool consider exclude pins only while optimizingDRC's

Enamplet
Mon clock input pin of sequential cell
a Multiplexer select Pin
Ciii Float Pins
Float Pins clock pins that havespecial insertion
are

delay requirements and balancing is done according to the

delay

This is same syncpin but internal clock latency ofthe

as

pin is taken into consideration while building the clock

thee To adjust the clock arrival for specific endpoints
with respect to all other endpoints

A Clock entry pin of Macros

Ms hoops Macro
X
in

2ns flop
iv Stopping
Stoppins are the endpoints of check tree that are used
delay balancing In Cts the tool uses stop pins in
for
calculations and optimization for both DRC and clocktree

timing

The optimization is done upto the stop pin The

only
clock signal should not propagate after reaching the
stop sync The pin needs to beconsidered
the clock tree
for building

IQ Pins
clock
TaTa Ito Ty to Ito ti
Its data
So in the above don'tneed clock to propagate
case we
if the data is not present Er after Tr

D For stopping the clock we have to use the Enablesignal

Enable ON clock propagates further
If
Enable OFF clock propagation is stopped
One of the method to reduce dynamicpower is using
integrated clockgating cells
 There are basically two of Clock
gating
types
is Clockgating ANDgate
using
Clockgating clockgating
using Integrated
1 Clock
gating using AND gate
To stop the clock when data is notthere we need some
additional element which will control clockpropagation
in a way such that dock propagates only when data
is present
Data a output
F
ALL
Ehale AND

problem with clockgating using gate is that the

The AND

circuit might come with glitch

in clock
gating with Integrated Clockgating cells
To avoid we need some solution therefore integrated
glitch
clock gating comes into picture

The integrated clockgating cell is made upof latch

and AND Cell
Integrated clock cell use enablesignal fromthedesign
So due to the introduction Ica's there is one more
of
timing path that comes into picture that is
Reg Cas

Data Enable D d
And
gate
oops
clock
 A Ica's are added both near to the clock definition
pointand near to the leaf cells
amitant to Ica
zyreg Path

Report
check for ska
in check
for latency
Iii check for fanouts
civ Max transition
e Man Capacitance

Mi EM Violations
Vii Fired Place Unplaced Softfire 20microns

Status ofclock
network cells
checking forglobalroutes

both nets data nets is not done simuntaen

Routing of clock
thusly because the MDR rules is applied on the data nets
so they won't be able to judge which nets should be

proffered first
 If the data nets are given more preference then the clock
nets will get detoured Hence clock routing is performed in
CTS itself

FunctionalMode 2 Testmode 3 ScanShift Scan

Capture

Priority Order

Question Why the run time of postroute is greater as compared

to post cts
Answert Both past cts and fastroute do data path
optimization but in postroute the routing of standardcells
are done so it
post route the tool is to resolve
trying
the DRC issues as well as performing data
path optimization

During routing the tool more priority to data

maygive
nets and may reroute the clock net which will lead
to different skew andlatency values hence we keep a don't
touch attribute to the clock nets
Sanity check for Cts

I Thereshould not be
any open's andshorts in clock
nets

going to fire the status ofclock tree

because are
you
There should not be min spacing violationbetween
any
the surrounding nets NDR's

Imingcheckfor

Setup check

holdcheck
In Cts the real clock comes into picture and hold is
checked with respect to clock edges
Notdependent
of clock period
 305T CTS
O
D
DI D D A

DD ok alk
D D D

Due to skew in the clock tree again the timingoptimization

needs to be done on the data path This is done in

post cts
Techniques to improve setup

Utswapping higherUt
to Lowery
till Upsizing
id Buffer Insertion Breaking the net
is cloning
01 logic Restructuring disadvantages leads to congestion
Xi Pin Swapping

Forholdt
LowerUt to higher Vt
Uswapping
BufferInsertion Near tothe end point ofCapture flop
We are adding near to the Capture flop because
we are connecting in between the flops there
if may
be many fanout connected to the data nets
 Adding buffer may effect
other timing paths
D a
toooo D o which are connected
Fanouls to it
elk elk

Ciii Downsizing higher derivestrength to lower drive strength

CLOCK PUSHING CLOCK PULLING

n ni n t paths
In 1 n path inti paly
s
kazoo gooooo Appar Gooooo Nooooogooooogooooo

FF FF F
Fez Fg

gooooo gooooo Tgooooo Magar Woomer T gooooo gooooo

whenever we using useful skew or if we want to

are

push the clock then mandatorily you have to check

net as well as a 1 margin
for your margins

Clock
pushing clock is late
coming
clockpulling clock is coming early
A clock pushing in a path will impactsetup in nti

D clock pulling in m path will impact hold in n 1

Checks
after Post Cts IsSetup Reports Setup holdboth
IS hold Reports will be checked
on user definedpath
groups
Ciii DRV's
Question
If Wms is optimized having too much
we are
TNS then what
type of technique will be used
Answers We will give postcis dob
for incremental
optimization
Incremental optimization works on reducing WNs Ultimatty

your TNS gets

reduced

I If the initial utilisation beforethe designplanning

is 56 then what will be the utilization ratio at

post cis db
Answer Utilization at postCis db Initial Utilization 4

postroutedb Initial Utilization 8

At CTS Stage Datanets routes trial route

Early
global
Powernets Global detailed route
Clocktreenets Global detailed route

NDR's is present in top PGnets andclock nets

To haveleast resistance andhigh Capacitance
 UT Gi

The chip is divided into small box

A These small box are called cell and the size of cell
g g
depends on the algorithm the tool uses
 Each
gall has a
finite number ofhorizontal and
vertical tracks

Global routing assignsnets to specific but

galls
it does not define the specific tracks for each of
them

A the router connects two different from

global gulls
the centre point ofeach
grill
A Routing is the process ofcreating physical connections
based on logical
connectivity

Routing Operation Stages

Ii Global Routing
Track Assignment
En Detailed
Routing
Search and Repair J are one simultaneously

Grouting
In global routing tool identifies the shortest rentablepaths
is not DRC aware I will not consider Drc while routing
Hi while doing the global routing the tool tries to assign
layers to the nets

Ei
while doing the congestion calculation it tries to
calculate the number in each So
of overflows layer global
routing is congestion aware

Iv During global routing the tool is also aware about

placement blockages and routing blockages

Global Routing Detailed Routing

Track assignment

Assigns each net to a specific track and actual metaltraces

are laid down it
by
Track assignment operates on the entire desi at once
ATA does not check or follow physical Dre rules

Detailed Routing
Tries to
fire all Drc violations after track assignment
a size small area known as bbox
using fined

Detail route traverses the whole design box by box

untill entire route pass is complete

Search and Repair

A Searchand Repairfines remaining DRCViolations through
multipleloops using progressively larger boxes over
from detail routing

loop2 loop3 loop4

loop
 DRC violations are addressed another pass
Remaining by
using a larger bby
The larger box potentially gives more routing resources
to clear violation

Challenges faced during Routing

I In routing phase the clocknets pgnets are alreadyrouted so

less no tracks are available which can lead to shorts
of
Cil For example a net is being routed and while routing thetool
cannotfind a legal
locations which lead to opens
may
Iii Usually the tool tries to avoid Drc's in the design whichmaylead
to detouring ofnets andmay lead to timing
fail
Detouring
a p
Dp

Mk Mk

Checks
after Routing
I setup holdtiming checks in comparison to postcis and
Routing

ID Dru's a Maxfanout b Max transition a MaxCapacitance

Hit Noise
glitchreport
 POST ROUTI
At routing stage the Datanets are detailed routed due to which
RC Delay the net comes into picture which again degrades
of
the timing of design

I So to fix the setup hold timing again optimization needs

to beperformed in the datapath This is done in
Postroute stage

Optimizationques

Setup optimization hold optimization

Ii Utswapping Ut swapping flowertohigherK
upsizing Lii Downsizing
Lin Buffer Addition HisBuffer Addition
Iv Cloning Near to the endof Capture
e logic Restructing flop
Wi Pin Swapping

question In post route Stage what

you will fix first
a Setup b hold c Dru's

Answers Dru's Hold setup

finingorder
4 ITWhen
are fining the Drv's this well fix many
setup holds that is the reason we are fixing Dru's

nets at later stages then

b
If fixing Dru's in clock
we are
we know that clocknets are high fanoutnets and

fining Dru's in one particular net will effect the timing

of other nets connected to it which may lead to huge
setup and hold
violations at later Stages

I Hold
we are derate in thedata path and we have only
trying add
a

three techniques to dothis the same amount is added in setup

and
you have more no oftechniques to fix the hold
b For a design
if the hold slack is violated the ship won't
function but there is setup violation the chip can
if
be made to work reducing the frequency
by
In timing reports what things we checks
a Setup b hold c Dru's d net
Crosstalk Noise delay clock

e Minimum Pulse width Violation clocknet

 S GN O F EC O
In sign off we nutrients a
pissimism
both on timing
closure and physical verification

A Physical connections to the nets are done in routing stage these

nets have Rand C Values So to extract these RCdelays wit lot

of accuracy we are relying on the signoff tool calledQuarter

OR Stark for spef generation which ordains RC delaysofnets
SPEF Standard parasitic Efraction format

postrouteAb

Starke quantusRC

We will get different SPEFbased

spof
on different RC Corners
 Unannotated net
Checks
after spef generation repost
I Unannotated nets Sometimes
during routing due to lackofrouting
resourcesthe nets are notrouted completely there is Open So
the tool is not able to extract accurate RC values of nets

The tool will try

to give the Rand C Valuesof not onlytill
the pointwhere routing has stopped

is all such unrouted nets or partiallyroutednets

Therefore

will reported under Unannotated nets

of SPEF generation
Significance
Is larger number of Unannotated netsshows that routing has
been done properly
y the tool So spef file containing large
no of annotated bets does not give accurateresults in Sta

Iiis During EM Analysis the tool needs to knowthe accurate

value ofRand C value net because R C values are one of
of
the important factors in Eta violation

Timing Sta
SIGN OFI
Physicalverification
 SIGN OFF TIMING STA
Inputs a Postroutedb
b SPEEfile

PrimeTime
Tools Is Synopsys
Tempus Cadence

in Setup
Outputs 120ps
Ii hold 60ps

Hii Noisereport 30ps

Ayam Hiv Min Pulse width Report
X DRVreport Gops 70ps Ipf
Bumpy Waveform Report 20ps
hi Unannotated nets
report
Ix Glitch Report sops

In Signoff we are checking timing with respect of PBAmode

havinghigher accuracy ascompared to GBA
PBAmode is Runtimeof

BA is more
 STATIC TIMING ANALYSIS

Setuptime

It is the minimum amount oftime

for which data should
be stable at the input before the activeedgeof the
clock
Hold Time
Holdtime is the minimum time which the data should
for
be stable at the input at the active edge of the clock
has arrived
Latency

latency is defined as the amount

oftimetaken by the clock
signal in travelling from its source to the sinks
Insertion Delay
to reach the farthest flop is
Time taken
by the clock
known as Max Insertion Delay

Jitter
Clock the deviation
is a clockedge from its ideal
jitter of
position in time
Types
oflatency
ounce latency the time taken
Source latency is defined as

by the clock signal in transversing from clock source

Network Latency Network latency is defined as the time
taken the clock signal in travelling from clock
by
definition point to the sink of the clock

Skew

ositive Skew
If the Capture clock comes late than the
launch clock then it is called the skew

Negative Skew If the Capture clock comes early than launch

clock it is called ve skew
Uncertainty
Check
Uncertainty is the time difference between the arrivals
of clock signals at the registers in one clock domain on
between domains

TUncertainty Skew Jitter t clock Margin Moise Ocu

Types of timing paths

1 Input pin part to Register In Reg

ii Register to Register Reg Reg
iii register to Output past Reg out
Iv Input In out
pin port to outputpinport
v Reg Cas
 Constraints
Setting Input output Delay

Sourcelatency

Create clock period 10 EgetportsA

set clock latency source Max 3 Egetports dKJ

Network latency

set clock latency source max2 Egetparts UK preCTS

set propagated clock getposts AT post cts

Setting Input Delay

Set wiped delay max 0.6 clock Uk getparts A

set output delay max 08 dock UK Egets parts B
 Timing Fines

Setup Hold
i
Upsizing Is Downsizing
Ut swapping Hut Lutlulut Gi UtswappingKut Hut Higheste

Buffer addition Breaking net Cis BufferAddition Near to

us Conning capture flop
e Pin
swapping
vis logic restructing

ImingException
Falsepath
False path refers to a timing path in timing Analysis is
not done on that particularhats it will never get captured
in a limited time frame whenexcited

Set path startpoint to Endpoint

false from
in Multicyclepath
where the
A multicycle path is flop to floppath
combi ational
logic delay in between the flops is permissible to
take more than one clock Cycle
Iii If cycle pa
Timingpath that is designed to take halfclock cycle
both
of the clock edges for the data to propagate from
the startpoint to the end point

Recovery and removal Checks

Is Recovery and removal analysis are done on asynchronoussignals
like resets

Is Recovery time
It is the minimum required time to the neat active edge
after the reset
Removal time
It is the minimum required time after which reset can
be released
G BA and PBA

GBI
In GBA mode the tool computes the path delay based worst
the instances
case timing arcs
of all
A GBA take less runtime as compared to PBA
 PBI
In path based timing analysis the tool considers each path inisolation
other paths which eliminates impossible combination
from of
worst stew and worstarrivals and similar combination
of effects
such as crosstalk and CRPR

As a result path basedtiming analysis reduces pessimism and

increases
accuracy
at the cost
of more runtime

leport timing Primetime Synopsys

Thereporttiming commands
report thetiming paths in the current design
that haveworstslack These are the paths that violate the timing
constraints the large amounts or paths with positive slack that comes
by
closest to causing timing violation
DEach pathhas a startpointand an endpoint Data is launched a
by
clockedge at the path start
point propagatedthrough combinationallogic
in thepath and then captured at the path endpoint another
clock edge The startpoint can be a registerclock pin
by
or an input
post The endpoint can be a register data inputpin or an output
port
command without options reports the
By default thereporttiming single
constraint violation
paths in the design with the worstmaxdelay setup
to consider constraints other than max delay use the delay type
option

To control the numberof paths reported use the nworst option which
specifies the maximum number of worstpaths reported per endpoint

The max paths option whichspecifies overall maximum number paths

of
by
reported the command

IING Reports
To invoke path based analysis use the pbamode option In pathbased
timing analysis the tool path in isolation fromother
considers each

paths
 u

Éo___

oom
 MINIMUM PULSE WIDTH CHECK

aMinimum pulse widthchecks are done to ensure that width ofthe

clock signal is wide enough the cell's internal operation
to i e to
for
stable output you need to ensure
complete
get a
that the clock signal at the clock pin ofthe flop is at least
of certain minimum width

a Minimum pulse width is the interval between the rising edge of

the signal crossing 50 ofUop and the falling edge of the
signal crossing 501of Unis
Command to report Minimum Pulse width violation
report timing check type pulse width
ON CHIP VARIATION

variationwithin a die
is termed as localvariation
 So inside a wafer there is a variation in each dia and
also there is variation in characteristics of transistors even
inside even inside a single IC along with the die

Sof variation

Profess 1 temperature
Voltage

ystematic onSystematic
Ambient Juridion
variations Variations temp Temp
Internal Variation
SupplyVoltage
voltage
variation

ProcessVariation
In processvariation there are two types of variation one is
systematic Variation and other is non systematic Variation

Systematic Variation come due to optical proximity correctioncord

or Mechanical Policing which are predictable
chemical in
nature and can be modeled in PVT Variations

Yon Systematic Variations come from the Random dopant Fluctuation

RDF line Edge Roughness Len or due to oxide thickness variation
highly unpredictable and cannot be
Otu which are modeled
easily
 I
lugs Vin Vds Uaf
Meg
So drain current depends on Tun s mobility
of
electrons

Eon Permittivity ofsiliconoxide

tox oxide thickness
w width transistor
of
gate lenght

To if any of these factors mentioned above varies during

fabrication process It will affect the drain current
going to vary
The
delay of a standard cell is

A photolithography process is a non ideal process and

it is hardto the exact on the silicon
very print layout
wafer

layout 7 pay iffy

actual layout
in Ideal us
condition

So in conclusion there are many factors and high Chances

of variation while
fabrication of a chip and these can
lead the vary the delay of the standard cells
WageVariation
one is due to the variation in external supply voltage and
other is internal Voltage Variation inside the Chip

25 Variations in supply Voltage

variations due to IR drop

The external but

volley variations is taken care in the PvtMethod
there could occur IR drop in your power delivery
which lead to variation in available voltage to operate
a
may
cell

Distance between the power pads andstandard cells could notbe

the same all So there will be variation
standardcells
for
of available Upp for the standard cells depending on the
design Delay of a cell is dependent on the available Upp
Upp is less delay will be more
If
UDD T
t Delay
Temperature Variations
There is ambient temperature on which the Chip is operating
and another temperature is junction temperature of the
transistors junction temperature is the sumof ambient
temperature
plus the temperature raised due to power
dissipation
of Chip
Junction Temperature is
always much greater than the ambient
temperature and the Characteristics
of any transistors majorly
depend on the junction temperature Ambienttemperature
can be taken care in Put but the junction
tempe ature
variations we need to take for
care in our

Sometimes there is also the formation of local hotspots base

on the placement density and power requirements
of cells
which affects the temperature of the junction and
ultimately lead to the variation in current and delayof
cells

Chip ariations
To take care of Ocu we need to addsome pessimism in
the timing of standard cells we basically apply Ix
of additional delay to all standard cells which is
called OCU derate
Ocu berate factors
A fixed derate factor is applied on throughout the design so
in that case any variation occurs will not cause failure of
the Chip But it added too much of timing pessimism
which leads to difficulties in the timing closure especially in the
lower nodes

Set timing derate o g early

set timing donate 1 I late

Issues in OCU
Fixed timing derate is used all the cells in the Ocu is
over pessimistic In reality for
there is cancellation Random
a
of
variation effect

So thelower technology node we want to resolve this issue

for
And so the concept of Advance on chip variation AOU
has involved which does notused the fired denates

In AOCU derate is applied on each cell based on path depth

and distance of the cell in the timing path and it also
varies with cell type anddrivestrength
ofthe cell
box
Distance is
defined by a bounding for netsandcells

D
LF c
Ho Mo r
Distance

y
logicdepth
 g
Distance
If the distance increases systematic variation would

increase and to mitigate the variation we need to use higherderate

value So the distance derate values increases
along with

Pathdepth
In the case of distance is fined andpath depthincreases systemal
variation would be constant but the random variation would tend
to cancel each other Therefore the pathdepthincreases the derate
factor would
decreases

teletypes
The dirate is based on the celltype as an ANDgate and or
gate doesnotexibit thesame variation Derate value also varies
with drive strength of the cell like ANDI and ANDY will have
drive derate values

AOcuderate values depend upon ID 2D look uptables

Depth
I 2 3 4 5 10 50 100
1000 1.099 1.055 1.053
2000 1.099 1.055 1.054

3000 1.100 1.056 1.055

4000 1.102 1057 1.055

EE sooo 1105 1.061 1.059
6000 1.107 1.070 1.06

I 7000 1.109 1.071 16062

IssuesinAo_
AON does not
perform very well below tomm technology node
and to improve that we need to improve the timing
pessimism further Distance and Depth basedderate factor used
in AOCU is good for technology nodes above to nm
but the belownode we need it toimprove it further
for
To address these issues Parametric on ChipVarition Poco

Poco
In Pev instead of applying the specific derate factor to
A cell cell
delay is calculated based on delayvariation
o the cell
of
In Poco it is assumed that the normal delayvalue of a

cell follows the normal distributed curve

central value

it

310 20 20 35
I Y I
7
95
2 995

DOCU
Analysis
Docu uses nominal delayvalues k instead
ofusing the
min or max value of delay to modelthe randomvariations
 using the nominal delay valued
and
Timing Analysis is
A done
delay variation o in thefollowing ways

Tool takes the valueof o from the timing or an

the
library
external Poco coefficient value c
file
containing

Each aretime is then calculated statically asthetotal

the variation
of nominal
delay and
fix the tool then calculates the delayofthepath
by
statistally combiningthese arc delay and perform
setup andhold timing analysis

PInputda
Is using single
POCu coefficient c

An external
file containing the delaycoefficientvalues C for each
heiarchial cell ordesign
library cell
There is only one valueof C for eachtiming arc ofthe
cell irrespective of the input transition or outputload
The cell
delay variation o is calculated based on Cas
follows
The delay variation o Ct Nominaldelay
 Poor Calculations

Delay of a Cell Nominal Delay44 I Powcoefficient T

where C POW Coefficient

N Number
of standard deviation

Prime time POW Analysis flows

Verilog library
SDC Parasitic RC

variation setup
Read POW Input andenable PoW Analysis

Timing Analysis
Subtraction
Apply statiscal Addition min
Max calculation

Generate N Sigma Conner timing reports

stageditayrepart
 Comparison between poor and AOcu

AOCU POCO
Is Random Variation modeled andsystematic variation
Random

through the depth based derate modeled through a delay

and systematic variation is variation coefficient o which is
modeled
through distancebased specific to eachcell
derate

I less accurate co relation More accurate correlation between

between GBA and PBA GrBA andPBA

Iii Transition variation andcell Transition Variation and cell

check variation notsupported check variation is supported in
LVFformat

Numericals
0 2 O 4
D a

I
Launcher
Wtf
µ O3 2 0 4

Tak 2ns Late donate I Ins

Tak q 0.2 ns derate 09ns
Early
Tsetup 0.2ns
T hold O Ins
 Setup Analysis
while calculating the setup Analysis we need to take late
derate along launch
path and early derate along
Capture path
Arrival time
Arrival time includes addition of cells wire delays
along the launch path

Arrival time A T

Wired delay lateiterate Ak to go latederate wire 2delay a

late derate inverter delay Late derate there 3delay
late derate

Arrival time A T o 1 Xl 1 02 11 o2 11 3 1 Dt Coax

Arrival Time A T 4.29nsec

Required time

Required time Rt Tak Tsetup Ewire delays a earlyderate

Tall delays earlydonate
RT 2 0.2 Co 3 x o g 2 10.9 0.4 0.9 4.23ns

Setup Slack RT A T
4.23 4.29
0006 C ve Slack
Holdanalysis
hold analysis we need to take
While calculating the
derates the launch and late derate early
along path along
the Capture path

Arrival time
wire 1 delay early derate tide early
q
derate wire 2delay
derate inverter delay early derate were 3delay
early derate
early
Arrival time 0.1 0.9 0.2 0.9 0.2 0.9 3 0.9
0.4 9 3 51 nseconds

Required time

Required time IR D Thold Twire delays latederate thtcellderate

a late derate

Required Time R T 0.1 to 3 11 2 1.1 0.4 1.1

3 07 nseconds

told Stark AT RT 3.51 3 07

o 44 nseconds tue Slack
Case
2Withonto o 2 o t
p a

ight Ight
m O3 2 0.4

Tak 2ns Late donate I Ins

09ns
Tak q Early date
0.2ns
Tsetup 0.2ns
T hold O Ins

Setup Analysis
AT were 1 talk to a inv delay wire 3
AT O I 0 2 02 3 0 4 3.9nseconds

RT Tax W Tsetup Twire delays Tell delays

RT 2 0.2 0.3 2 0.4 4 5mseconds
Setup Slack RT A T
4.5 39 O G nee

HoldAnalysis
AT were I talk qt inv delay wire 3
A T O 1 0 2 to 2 3 0.4 3.9ns

RT Thold Twindelays Tall delays

RT 0.1 to 3 2 0.4 2 8ns

Hold Slack A T RT
I In seconds
 GRPRICII
RPR Clock Re
convergence
removal Pessimism
CPPR Clock Path pessimism removal

condition arise where have to use

During Timing Analysis a youanother
Max
delay for one timing path and min delay for
timing path

Due to the common path we cannot take Maxdelay mindelay

at the sametime For example common to Data and Clockpath

Removing common clock buffer delay between launch path

capture path is CPPR and CRPR
Numerical

D a D a
delay
Tsetup 0.35ns
FF 5.2ns Ftz
TIM
BE BE
A
Iga M
woop
ihr
ak Thold 0.25ns

Ins 0.86
 Set timing derate early 09
set timing derate late 1.2

Solution
getup slack RT LA
AT 1.2ns to 8 5.2
RT 10 1.2 086 0.35 setup

Setupstalk 11.71 7.2

4.51

Hold Slack LAT RT

A T 1.2ns to 8ns 5.2ns
RT 1.2ns t 086 0.25 Thad

Hold Slack 7.2 2.31

4.89nsec

Derate Value 0.9 1.1

Using PPR and derates
Setup Stalk RT A T

RT Lo 10 86 0.9 0.35 1 1 1.211.1 0.9 PPR

AT II 2 113 008 11 t 52 1.1

Hold Slack A T RT
R'T o 8 11 0.25 1.1 1.2 1.2 0.9 ppr
AT 12 0.9 t 10.8 0.9 5 2 0.9
 Question
why do we need to go with STA if the timing is already
clean in Postroute stage

get accurate valuesof Rand

C
Answer After SPEF generation we
which our Pnr tool was not able to determine and
maybe
maybe degradation in the
due to this RCdelays there
the timing path Hence we static
go for timing Analysis

Signofftools can generate tool based Eco's forthe current existing

violations
ECO EngineeringChangeOrder

Inputs is routedb
Post
SPEF
Kii STA Reports

ECO EngineeringChangeOrder

output is Setup Eco files

td format
in Hold ECO files

inDRy'secofiley
Thiscontainsglitch bumpyWaveform
noise Ecofiles
ECOFlows routedb
new post
Jostroute dis's
SPEF
1ststage
Sta
Reporting W
Reports

Éco
Tempus flow
2nd ECO til files with
Stage
fines
Generating tool
based Elo's Restorepostroutelab Restoringthe dbwithInno
vous
ICcompiler Pnrtool

Delete filter cells

AfterPostrouteoptimizationthefiller
Source Eco cells are added inthedesignThis
files cellsneededtoberemovedfrom
fillerroute
post dbforsourcingtheEcofile
weneedthelegallocations for Legalization
standardcellswhich
wasintroduced
aftersourcingtheEcofiles

gotdisturbedaftersourcingthe
Whatevernets
ecoMaute Ecofiledue toinstancesintroductionthenets
are
routedagainin Ecoroutestage

Addfilter cells

Savictb

Spefgeneration postroutedb
new
 If the tool not able to fix the timing
generated Elo is
then we have to with manualEco's Generally I 2
go
iteration is done with tool Eco still
if degradation intiming
is observed we with manualEco's
go
ManualEco
Manual Ecomean's user have to write the til script to
fire the violations ability to report the timing

Tempus Primetime Tool

Generates Eco files

i size cell cell name Fusion Compiler

in eco update cell instance name celltype Innovous

either source the tech file restoring the

db or
you can by
a

b can do it in the Pnr stage

you
Runtime a Mo of Sienarias
STA Runtime lokpaths are
failing
20hrs aptn
Eso 30 32hrs count
filegeneration a instance

the session I 2hrs

Restoring
PNR Implementation 6 8hr meanwhile we
3days will do PV Checks
I ECO Cycle 2
full
PHYSICAL verification
Inputs in Pastroute db
Iii Ruledeckfile
OASIS GDS II
YI

Runtime
Physical verification caliber
Lhs

Output lil DRC

metallayer Base layer
DRC DRC

II ERC
Ciii Antenna Violation
In Metal Go violations
C Lus
Rule deck Rule deck is given from foundry It is a
file file
set of written in standard verification rule format
Code

It guides the tool to extract the devices and the connectivity

layer information to identifythe layers in used
ofIC's It
contains

file and to match it with the location of layer in Gns

Rule deck also contains device structure definitions

Restore the same post route db in which we were implementing Eco

flow
NERI
ERC involves checking a design for all electrical connection
ERC Will check
Unconnected
Inputandshorted output
Gate should not connect directly to supply Must beconnected
TIE
through high and TIE low cells
Iii VDDLuss errors to be connected to
The wellgeometries med

power ground and if the PG connection is notcomplete

as if the pins are not defined the whole layout can

repost error like MWELL notconnected to Uno

 Schematicchecks
Linus Layout Vs

Mo ofdevices in schematic layout

devices in schematic
Type of layout
Kill Moofnets in schematic layout

Typicalerrors during Lus checks

lil Shorts opens
Component mismatch Componentmismatch can happen if
component of different types areused Luiinsteadof Srt
Ciii Missing component tf some expected componentis leftout
from layout
Iv Parameter mismatch Allcomponent has its own properties LUS
tool is configured to compare these properties withsome
tolerance tolerance is not met then it will
if give
parameter mismatch

US layoutnetlist
Spice netlist generatedfromspicetool

4 Overlap whenAND gate is overlapped with buffer toolcannot

understand which all should behere iftonsiders
considered

it asbuffer if spice netlistwell showANDgateandlayoutnettist

shows a buffer it will lead to Los
fait
 design_ckDRc
nothing but physicalcheckof
A Design rule checke is metal width
pitch and spacing requirement different layers with respect
for
to different manufacturing process

Bares
it Violation with to oxide diffusion OD
ftp.ggt
spacing
Area
Enclosure
Overlaps Overlaps with N well

Iii Violation with respect to polyonide Po

Area Enample ODwidth

Pitch
OD Area
Width
spacing
Enclosure
Minimum distance that should be maintained

from boundary to poly

a cut Polyoxide Cpo
width
b butted Bpo spiffing
polyonide
I 4 Trim polyoxide Teo
Liii Violation lost to PODE
Poly on Onide Edge
s

width
Area

Violation wet to CPO DE Connected Poly on oxide

Edge

At floorplan stage we are checking for Denarules

there with
respect to memory the above violation will be reported and in
post route stage with respect to standard cell we have may
these type
ofviolations
 Physical Verification

ptre t
US ERC I

ÉTMÉntt maiden HtqÉsD

Goviolation

MetalDRIs
From me to the top routing layer Fos ex Mai if we are

having any Dre with respect to metal layers

Shorts opens min cut min step Violations cut enclosure vialoops

Finingthe Metal Dress

a In case of shorts we will delete the nets andthen we will

reroute it again

89Short
i

b In case of opens stretch or move the metal layer to empty

tracks
stretchmetal to empty
metal tracks
 ESDViolation Base layer DRC
Based on the the chiptop level decides howmany
tolerance level

ESD cellshas to be present and its respectivelocations

DESD Cells are used to avoid damage from the accumulation of

static charges

D TSMC also gives some

guidlines in and around
these cells

regarding spacing and overlaps

Soif some overlap issue is present with respect to ESD cells this will
be reported in ESD violations

ESD cells and Blok level

4 If chiptop level has given some DEF for
Engineer forget to source this DEF then tool will report error
regarding ESD coverage

ESD P Clamp N Clamp Maro all

fulfill samepurpose
Latch Up Violations Base DRC

Generally well tap coverage and latch up violations are fined at

floorplan stage but if the well tap does not have a fixed
floorplan stage then it will again show latchup
Status at

violation at post route stage

in there are missing well tape so this

If a particular
region
will be reported under batch up violation

Go Violations Metal Drc

This violation is with respect to internal structure ofStandard
cell pins

Sometimes
in order to the min the pin
fill area requirements
dimension is not a straight line So the pin dimensionmay
be in CShape I Shape or reverse C Shape

r b
formation of metalloop
So in this this mutual couplingof Pins
case during fabrication
this might effect the intended functionality of cell
 Dueto the's type of metal loopformation capacitance ofeach
pin will effect the pinsof other standard cells
Spreading the cell can resolve metal G violation

LEC Tools Formality Conformality

Logic Equivalence Check

Inputs to LEC a Golden Netlist Synthesized Netlist

b Revised Netlist Recent Netlist after Each
stage

Alsoknown as layout netlist

Lutputs of LEC
A Mismatch Instance Name report LEC Fait

Ill Passing Instance name report LEC Pass

o o

ye FE
Inverter Buffer
Mismatch Instant.es LEC fail
of

In LEC the tool matches thetwo given netlist with respect toinputs
andoutputs logico orlogic 1
 Stages at which LEC isdone
Reason
forperforming Lec
Post Timing optimization
Synthesis
Ii At placement Data path optimization
Hill Past Cts Data Path and Clock optimizations
v1 Past Routes Datapath optimization

X After Eco Manual Eco's

All the time synthesized netlist is considerd as

golden netlist

your netlist
Question a Functional Eco is introduced in which
If
will
your golden netlist
aFunctional Eco Synthesized netlist will be
mygolden
netlist Given Synthesis team
by

Again after doing the Eco the postroute is done and db is

saved while saving the db you will generate netlist that
will be revised netlist
my
 POWER CHECKS

Inputs I DEF DesignExchange format

TWI Timing window
file
Lili SPEF
Liv Apache Power library

Runtime
Redhawk EM IR Checks
2hrs

output I Vector based IR

report
in vectorless IR report

IR drop IR drop can be defined as the Voltage drop in natal

wires constituting power grid before reaching the Uddpins
of cells
Emigration
Electromigration is the movement
of atoms based on the flow of
current through a material If the currentdensity is highenough
the heat dissipated within the material will be repeteadly break
atoms
from the structure andmove them This will createboth
vacancies vacancies and deposits The vacancies can
grow andeventually
break the circuit connections resulting in open circuits while
the deposits can and eventually close the circuit connections
grow
resulting in short circuit
 so due to EMmetal layers can haveshorts andopens in the design

of metal layers is causedby divergence in atomic flux

Damage
when amount metal leaving and entering a given volume are
ofassociated
unequal the accumulation
on loss materialsresults
of
in damage This results in two types ofinequalities

Atoms Voids Interconnect

Depletion
of failure
hillocks Shorts
Hi Deposition
ofmetals

0 Due to chemical mechanical polishing camp effects which

reduces the thickness ofwires a thinner wire be able
hold a large current density than a wider one
may

In lowernets Resistances M and Capacitance H due to that

D leadsto EM
there is currentdensity which
high
Methods to reduce EM
Rules
By Applying NDR
d
Applying NDR rules mean increasing the width of metal layer
which intern increases the capacitance of the net
therefore electron density is reduced in the nets leading
to
voids hillocks

Always EM will be reported to specific nets

 ANTENNA EFFECT
The antenna effect occurs mainly occurs due to the excessive
accumulation
of charges on a metal interconnect
connected to
agate of transistor during plasma etthing
of the metal interconnect The amount
of accumulated
charge depends on the area ofmetal interconnect connected
to thegate The excessive accumulated Charges getdischarged
through the thin gate on de and it cause permanent
damage to the gate oxide

a The
first method is to reduce the amount
ofchargeaccumulation
and this can be acheived
reducing the area of metal
by
gate oftransistor
interconnect connected to

b the second method is to increase the gate area so the

ratio becomes lesser than the permitted metal
ghettos
to gate area ratio
c The third method is to provide an alternative path to
get discharged
the accumulated charges on the ofthe transistor which is
gate
addition
ofan antenna Diode

Antenna Ratio
Antenna Ratio is theratio ofthe metal area connected tothe
gate
to thetotal gate area

Antenna Checks Physical verification

Antenna Rule

file CALIBER
Antenna Check
results
Design
gaffease

N JumperInsertion
Best to break thelengthy metal into small pieces and
way
using jumpers route them through other metal layers This
process is called jumper insertion ofmetal hopping
Iii Adding antenna diodes Ireversedbiased zener diode

Ciii Laya hopping

In layer hopping transistor uses less no of metal layers
and skippingthese metallayers means lessstaticcharge
 CROSSTALK

Crosstalk noise refers to unintentional coupling

ofactivity
between two

or more signals which can either effect the functionality or

the timing ofthedevises

The effected signal is called victim

The affecting
signal are called aggressors
A net can be victim as well as aggressor
in Crosstalkglitch
Typesofcrosstalk Victim is steady aggressor
is switching

Ciii Crosstalk Delta Delay

Victim and aggressor both
are switchin
 Gosa glitch
I

Aggressor
Do 0

mm Im Iit
GlitchMagnitudes
Magnitude depends on
Ii coupling capacitor between Aggressor victim
Slew of aggressor
tin Victim not ground Capacitor
N Victim net driving strength
Overshoot

victim

Aggressor
AFall glitch

Rise
glitch

Nana
Crosstalk delta
delay
Negative crosstalk delays
when Aggressor and victim are switching in same direction
abath
Aggressor
Do 0

Cotai mtg tcg

Hmm I grit
mm Victim
ig
o IG
fuk delay

Positive Crosstalk
Delays
d
o
Aggressor

Ciotat mtg tcg

Hmm I grit
mm
Victim
o ig
1 Icg
fastadelay
This scenario occurs when aggressor and victim both are
switching
in opposite direction
A The crosstalk can delay the delay ofthe victim only if
the switching windows of aggressor and victim nets
overlap
Crosstalk SetupAnalysis

Setup Equation

Launch Clockpath
Dataggh
Tsetup Jimmy t Capture path

Delay Delay

Worstcrosstalk scenario
forsetup
delay on launchand data path
Positive crosstalk

Negative crosstalk delay on Capture path

Note path crosstalk contributions are consideredfor

The common
both launch and Capture clock paths during setup Analysis

Worstcrosstalk scenario
for hold
Launch Clock path Datapath delay Thold Capture Path Delay

Worst crosstalkscenario for hold

Negative crosstalk impact on launch and data path

Positive crosstalk delay an Capture path

The crosstalk impact onthe common portion the clock

Note
of
tree is not considerd the hold an s
for
 LATCH UP

Latch up issue can be defined as a formation

of a directpath
fromVan to Gnd terminal in the design which will cause
a huge current flow between Uop andgroundterminal

Latchap formation
CMos circuit two parasites BIT
Inside a
get formed and
and connected in such a
way that
these BIT form a PNPN
device

Both the Bit's are connected to eachother in such a that

way
they form aPillPN device The baseof PNP BST is connected
to the collector ofNPN BIT andbase NPN BIT is connected
of
to collector
ofNPN BIT

APNPN device is normally in off state andthere are minimal

current or no current flowthrough it But once the PNPN
 device is
get triggered by its gate signal a large currentstarts
to flow through it and it continues to flow even if the
gate terminal is removed

summary
latch
up is a phenomenon of activating the parasitic Bit's in a

Chaos circuit which forms a low impedance path between

the power and ground terminals

This lowimpedance path draws a large current and heats

up the IC Integrated Chip which cause permanent damage to
IC

TEMP IN VERSION

Normal Case Worstsetup timingcritical corner

Slow process Minimum Voltage high temperature

Temperature Inversion worstsetuptiming critical corner s

Slow process MinimumVoltage low Temperature

Drain Current Id Lunch Was Utn

E
where u is mobility and Ut has threshold Voltage
 uniting
Id a µ
Id Th y 3h
Ith
Temp
1 J UTA

i
to the phenomenon

ofelectrons decreases
of

leading o so 100 1so 7

temperature Cc
to larger delays

In this case Vas Uth is constant because in largertechnology

mode Vans 7 vth

HiTemptnversion
In lower technology nodes Vas has a lower value and

Vas Vin is not constant anymore

Sowith increase in temperature x'decreases and Vas Un

increases therefore In increases leading to less delay This
phenomenon is known as Temperature Inversion
 IME Borrowing
WTime borrowing is the property of latch by virtue ofwhich
a latch can borrow time
a path ending at from next
path in pipeline such that the overall time of two paths
remains the same The time borrowed
by latch fromnest
stage in pipeline is then subtracted from the next path
time

Time borrowing
property of latches is due to the fact that
latches are level sensitive hence
they can capture data
times than a singletime the entire
over a
range of
duration time over which they are transparent Ifthey
of
capture data when they are transparent the same pointof
time can launch the data
for the next stage

Example Time borrowingusing negative triggered latch

 MET A STABILITI
W Metastability is a phenomenon of unstable equilibrium in

digital electronics in whichthe sequential element is not

able to resolve the state of the inputsignal hence the output
goes into unresolved state of an unbound interval oftime

when data transitions close

always this happens
Almost
very
to active edge ofthe clock hence violating setup and hold
requirements

Sincedata makestransition close to active edge ofclock

the flop is not able to capture data completty The flop
starts to capture the data and output also starts to
transition But before output has changed its states the
 Butinput is cut off from the output also starts to transition
before output has changed its state the input is cut off
the output as clock edge has arrived The output is left
from
hanging between o and state
smallinterval
for
0 Thismetastable state can lead to system failure
 LOCK UP LATCH

lock up latch play an important role in time fixing problem especially

hold timing closure A lock up latch is a transparent
for
latch used to avoid largeskew and mitigate the problem in
closing hold due to large uncommon clock path

lock
up
latches are used two scan flopshaving large
in between
hold failure probability due to uncommon clock path so that
there is no issue in
closing timing in a scan chain across
domains in scan shift mode

From timing lockuplatches can be the bestsolution

prospective
to avoid large uncommon path between the clocks of
two flops

lock up latch insertion duringscan sticking

a Concatenation
of Scan chains of different Clockdomains
There is aneed of concatenation of scan chainsof different
domains lock in order to mitigate
up latch is
clock inserted
large clock skew and uncommon path
Scanchain I
I
Yahn
Simms I
 but to eachother
lil Flops within same domain are
far apart
when flops are sitting
far apart the same clock
but within
domain so to avoid
large clock skew and uncommon path
lock up latch is inserted in between

Figs lock
up latch connecting far apartflops within the
same clock domain

0 Issues due to lock up latch insertion

a lock uplatches on the path act as breakpoints across which

flops cannot be recorded

b Due to lock up latch on scan
path tool is not able to
improve the chain length byreordering in efficient
Manner

there is a lock chain

1 Whenever
up latch in the Chain the scan
is broken into smaller segments These segments in turn
have their own start and end points which are fined
and cannot be reordered This results in longer scanchain
wire length
d Poor seem chain
reordering substantially increases the length
of scan chain andhence the congestion which unnecessary
increases
the Capacitance offlops outputs i e more wading of
of A pin which leads to more chippower dissipation

DOUBLE PATTERNINI
The fabrication MOSFET's
i's done using light of Wavelength 193mm
of
in a process called optical lithography Now as we
move lower Technology nodes i e channel below 30 nm the
process can loose its accuracy The quality is lost dueto
the diffraction of light around the corners and edgesofthe
mask since the features are so small compared to the
wavelength oflight The result in uneven edges ofthe mask
since the features are too smaller as compared to the
Wavelen th
of light This results in uneven edges shorts or the
complete absence
of metal to be etched this is where
double
patterning comes into picture

In this method densepatterns

of metals
single mask
in a are

split into 2 different mask that can be interleaved to

get the original pattern as desired and the masks are
colors to the metals
identified by
assigning

Since the masks are fabricated seperatty this can be corrected

This better resolution and higher layout
way we can
get
density
 atom pompom

ibis pjak idgaf ia.gg

iaghga ibook

gig's
intparaara

Maska Task I
Result

HEIRARCHICAL BLOCK

Etangeneration Primetime
This ETMs are generated
by Tempus
Once the placement is done this placement db is given to
Primetime Tempus to generate ETMs
 The tool will generate ETMs which contains theenactinternal delaysof
Childblock

A Inter logic Module ILM's are same like ETMs but this
model is
for Chiplevel
Person I childblock Person 2 Parent
Block

stage Floorplanning is
complete but Person I has to

give floorplan LEF to person2

É Now whenperson 2 is
doing floorplan it mustindu
the floorplan LEF received from
person 1

Stage Person 1 will Complete ETMs will beshared to

Placementand will generate ETMs PlacementLEF parent block for accurate
Etty
Primetime the input Regand Reg out
using for given
Placement db
delays
 Stage 3
Person I will run CTS
Sothis stagecontains our max So clock latencyinformat
insertion delay min insertion ion is needed for building
delay and Clock delay values CTS in parent block

Childblock contains information

clock
my latency
latency information This
Clock
insertion delay is embedded in
makeflow

ay
On post cts we generate EtMs Ms For parent block
Because due heed to notethe while doingpostCTS
irate timing information EtMs

Challenges in hierarchial blocks

a Parent block owner will

get
lesstime to fix violation
INNOVUS COMMANDS
INNOVUS commands at floorplan stage:

1) create_floorplan -box_size {die_box io_box core_box}

The create_floorplan command initializes the floorplan and calls the
add_tracks command to create new routing tracks.

2) create_row -area {x1 y1 x2 y2}

Create rows in the specified rectangle

3) create_tracks -direction -layer -num -start -step

Creates non uniform and customized tracks in the selected design area
-direction — specifies tracks direction as a string
-start —starting co-ordinate to create the track
-layer —specifies the routing layer used for the tracks, more than 1 layer
can specified
-step —specifies the spacing between the tracks
-num —specifies the number of tracks to create for the grid

4) delete_tracks -direction -layer

Delete the set of tracks in the database for a given metal layer.

5) edit_pin -pin_name -location -edge -layer -snap {track} -spacing

Modifies the properties of pins, such as pin spreading, pin location,
width and depth etc

6) init_design
To load the netlist file
7) read_def
Load a DEF file containing the floorplan saved by any tool.
Load the DEF file containing the scan chain information so that the
placement can do scan chain reorder.

8) snap_floorplan {-all | -selected }

Snap floorplan command is used to snap blocks, I/O Pads, standard
cells to the FINFET grid.

9) check_place
Checks FIXED and PLACED cells for violations, adds violations markers
to the display area, and generates the violation report.

10) add_io_buffers
Adds buffers/inverters to the I/O pins and places the buffers/inverters
near the I/O pins.

11) check_pin_assignment
Sanity checks with respect to port placement like spacing, allignment
with tracks, allingment with proper metal layer etc.

12) legalize_pins -keep_layer -keep_order

This command moves a pin to the nearest legal location. Moves a pin
from its existing location in the following cases: /
a) Pin overlap with any other object or pin.
b) If the pin is not in the non preffered layer, a non reserved layer, or the
metal layer.
c) If the pin is not on the routing track.
d) If the pin does not honor corner mask settings.
-keep_layer — Maintains the pin layer while legalizing the pins.
-keep_order — Maintains the pin order while legalizing the pins.

13) create_route_blockage
Creates an area which prevents which prevents routing of specified
metal layer, signal routes and hierarchical instances.
{-insts name} - blockage over a particular instance
{-layers layer name} -blockage over particular layer
{-rects {x1 y1 x2 y2} … { } } - specifies the rectangular area of the
blockage
{polygon {x1 y1 x2 y2} …{ } } -specifies the polygon area of the blockage
{-except_pg_nets} - applies routing blockage to all the nets except PG
nets

14) create_place_blockage
Creates a placement blockage for the specified area.
-rects {x1 y1 x2 y2} -area of the blockage
-all_macros -keeps the placement blockage around all macro
-type -hard/soft/{-partial -density -exclude_flops}/macro only
a) hard -niether standard cell nor macros may be placed in the blockage
b) soft - allows only buffers, inverters, isolation cells, clock gates, tie
cells and level shifters.
c) partial -creates a placement blockage that has a maximum density as
specified (sometime excludes flops and latches too)
d) macro_only - enable proto_design command to keep macros out of
the placement blockage
-inst instance name - specifies the name of instances in which
placement blockage has to be applied.

15) add_endcaps
Places physical only end cap cells at the end of site rows. add_endcaps
is always done after floorplan and before add_well_taps
{-rect x1 y1 x2 y2} — boundary box.
{-core_boundary_only} —specifies that endcaps cells are placed within
the core boundary.
{-power_domain power domain name} —specifies the power domain
name in which the endcaps are inserted.

16) add_well_taps
Add physical only well tap cells. Well tap cells are physical only filler
cells that are required by some technology libraries to limit the
resistance between power and ground connections.
{-area x1 y1 x2 y2} -specifies the co ordinates of all row in which well tap
needed to be placed
{-cell_interval microns} -specifies the maximum distance from the center
of one well tap to the other well tap
{-checker_board} —places the well tap in checker board pattern

17) add_decaps
Adds decoupling capacitance to the end of design.
[-place_status] -keep the place status of macro as fixed or placed
[-area lllx lly urx ury | -exclude _areas { {lax lly urx ury} … { } ] -defines the
entire area in which decaps are to be added
[-pg_net net name] —add decaps to the specified power rail.

18) check_floorplan -report_density

Checks the quality of the floorplan to detect potential problems before
the design is passed on to other tools.
{-outfile filename} - outputs detailed information for the specified
blocks.
{-report_density} - Reports target utilization( (TU) and effective utilization
(EU) for the entire design, fences and regions.

19) create_place_halo
Adds a halo to the block. A halo is an area that prevents the placement
of standard cells within the specified halo distance from the edge of a
hard macro to avoid congestion.
{-all_blocks} — add halo around all hard macros, black boxes and
commited partitions.
{-all_io_pads} —add halo around all IO Pads.
{-cell name} —Add halo around all instances of cell.
Sanity check after Powerplan:

1) check_connectivity
Detects conditions such as opens, unconnected, wires(geometric
antennas), unconnected pins, loops, partial routing and unrouted nets
and generates violation marker in the design window; reports violations.
{-out_file filename} specifies the report file for connectivity violation data

2)check_power_vias
This command checks missing powergrid vias.
{-area {x1 y1 x2 y2}} specifies the co-ordinates of the area to be checked
{-report filename } specifies the name of output file for the report.
{-what_if_report filename } write out the violations data into an ECO file
that can be used directly as an input for what if rail analysis

3) check_drc
Checks for the DRC Violations and creates violation markers in the
design database that can be seen on the GUI and browsed with the
violation browser.
{-area {x1 y1 x2 y2} … {} } checks DRC within the specified area
{-out_file filename} specifies the report file that contains DRC violations
information.

4) add_rings -around {each_block} -layer {layer1 layer2} -offset {a b c d}

-spacing {value} -width {value}
Create rings for the specified nets around the core boundary or selected
blocks.

5) add_stripes -area
Creates power strips within the specified area.
6) update_power_vias
Adds power vias to the design or perform one of the following actions to
existing power vias:
a) Modies the power vias
b) Deletes the power vias
c) Fixes the vias that violate LEF minimum cut rule
INNOVUS command Placement:

1) set_cell_padding
Add cell padding to the specified instance
{-cells leaf cell name}
{-padding right | left | top |bottom}

2) set_inst_padding
creates cell padding for entire hierarchy of instances.
{-inst instance name}
{-padding number of sites | [-right_side numofsites] [-left_side
numofsites] [-top_side numofsites] [-bottom_side numofsites]

3)create_group
Command for creating fence, region, guide, cluster
{-name group_name} Name of the created group
{-type fence/region/guide/cluster} specifies the type of group to create
{-density value} specifies the placement density percentage
{-rects {x1 y1 x2 y2}……{ } } specifies the coordinates of the rectangle for
fence, region and guide

4)group_path
Creates group path in the design, and identifies them with the path
group name.
{-name path group name } specifies the name of path group
{-from fromlist} List of pins, instances at the start of path
{-through throughlist } list of pins, instances where the paths go through
{-to to list } list of pins, instances where the path ends

5) place_connected
Magnetic placement
{-attractor_pin pinlist} specifies hard macros/IOs/fixed standard cells for
attracting standard cells.
{-attractor macrolist } places only standard cells connected with
specified pins of attractor close to attractor.
{-sequential all_connected} pulls sequential cells connected close to the
attractor.

6) place_opt_design
Executes pre-CTS with both placement and pre CTS optimization.
{-expanded_views} prints timing information for each active view at the
end of the command.
{-incremental} specifies the “place_opt_design” to run incremental
mode
{-num_paths numofpaths} specifies the number of paths to be reported
in the timing report.
{-report_dir directoryname} specifies the output directory in which the
timing/DRV reports will be saved.
{report_prefix outfilename} specifies the file name that is generated at
the end of place_opt_design.

NOTE - place_opt_design is made from two commands which were

used separately place_design and opt_design -pre_cts.

7) opt_design
Performs timing optimization before or after the clock tree is built, or
after routing and generates timing reports.
{-drv} — corrects max_cap and max_trans violations, if we want to
correct fanout_load we have to first specify opt_fix_load attribute before
you specify opt_design.

{-expanded_views} generates detailed view-specific timing reports at

the reports at the ends of opt_design command.

{-hold} corrects hold violations.

{-hold_vioaltion_report filename} generates the following report files for
the remaining violation that remain after hold fixing.

{-incremental} performs setup optimization incrementally on the violated

paths until they cannot be optimized more. Both WNS and TNS are
optimized.

{-post_cts} performs timing optimization o design whose clock tree has

been created.

{-post_route} performs timing optimaztion on the design whose routing

is complete.

{-pre_cts} performs timing optimization on the place design, before the

clock tree is built.

{-report_dir directoryname} reports are generated in the given directory.

{-setup} corrects setup violations for the post_route optimization flow.

When -hold parameter is given, a combined setup and hold optimization
is performed.

8) report_congestion
Reports the average congestion and the local hotspot score.
{-hotspot} reports the local hotspot score. It reports the local and total
hotspot area.
{-overflow} reports horizontal and vertical overflow.
{-3d} honors 3d congestion map.

9) set_db opt_multi_bit_flop_opt true

To enable multi bit flip flop conversion

10) set_db opt_power_effort medium/high

To enable leakage power optimization.
INNOVUS Commands CTS stage:

1) ccopt_design
Performs clock concurrent optimization (CCOpt) on the current loaded
design in Innovus.
{-check _cts_config} checks that all the prerequites for running the
clock tree synthesis are fulfilled without actual doing CTS.

2) create_clock_tree_spec
Create a clock tree network with associated skew groups and other
clock tree synthesis (CTS) configuration setting such as ignore pins,
case analysis, max trans etc.
{-out_file filename} writes this clock tree specification script file in
Stylus UI format.
{-views} specifies the TCL list of analysis view names.

3) delete_clock_tree_spec
This command deletes all the skew group definitions and other clock
tree synthesis configuration information.
INNOVUS command Routing Stage:

1) route_design
Runs routing per postroute via or wire optimization using the nanoroute
router. Using without any arguments runs global and detailed routing.

{-placement_check} -checks for placement violation before routing.

{-track_opt} perform timing optimization after track assignment.
{-via_opt} optimizes vias after routing

2) opt_design -post_route
Performs timing optimization after post route.

3) time_design -report_dir filename

Runs early global route, extraction and timing analysis, and generates
detailed timing reports. The generated timing reports are saved in the
directory that you specified using -report_dir
PrimeTime Commands:

1) {-from / -rise_from / -fall_from fromlist }

-from
Reports only paths that start from the specified list of pins, ports, nets,
to cell instances; po from start point clocked by the named clocks.
-rise_from
Same as -from option except that the path must start with rising
transition
-fall_from
Same as -rise_from option, except that the path must start with a falling
transition.

2) {-to / -rise_to / -fall_to }

Reports only paths that end at the specified list of pins, ports, nets, or
cell instance; or at endpoints clocked by the named clocks.

3) {-exclude excludelist}
Excludes all paths in which the data goes from, through, or to the
specified list of pins, ports, nets or cell instances. Use of -exclude
option can lead to longer runtimes. To reduce the runtime impact, use
-from and -through.

4) {-through / -rise_through / -fall_through }

For ex. report_timing -from -A1 -through {B1 B2} -through C1 -to D1

Reports only paths in which the data goes through the named pins,
ports, cell instances, or nets. This option can be used multiple times in a
command.
If advanced analysis through transparent latches in enabled
(timing_enable_through_paths set to true), and the pins specified in the
last -through options are latch loop breakers.

5) {-delay_type delaytype}
Specifies the type of path delay constraint to consider for finding and
sorting paths with worst slacks.

-max - max delay (setup constraint)

This option is considered as the default option.
-min - hold constraint
-min_max - both min and max delay

6) {-nworst paths per endpoint}

Reports up to the specified number of worst path per endpoint. By
default the value is 1.

If you are setting the value greater than the default value, then the tool
does the following things:

a) Implicitly sets -max_paths equal to the -nworst setting if the

max_path option is not used in the command, so that at least one set of
multiple paths to an endpoint can be reported.

b) Implicitly sets -slack_lesser_than 0.0 if the slack_lesser than and

-slack_greater_than options are not used in the command, so that only
violating paths are violated.

7) {-max_paths max path count}

Reports up to the specified maximum total number of paths.

If -group option is specified, the total number of paths reported is at

most the specified number of paths per path group.
If -group is not specified, the total number of paths reported is at most
the specified number of paths among all path group.

The default max_paths_count is equal to the -nworst setting, or the

-slack_lesser_than and -slack_greater_than options are not specified.
Difference between -max_paths and -nworst:

• The -nworst option controls the maximum number of paths reported

per endpoint.
• -max_paths options controls the overall total maximum number of
paths reported.

• The -max_paths setting should be at least as larger than the -nworst

setting, so by default the tool implicitly sets -max_paths to the same
value as -nworst setting, so by default the tool implicitly sets-
max_paths to the same value as -nworst if the -max_paths option is
not specified.

8) {-group groupname}
Reports only paths that belongs to the specified path groups.

Paths groups are created by create_clock and group_path commands.

Without -group command the tool will report the WNS of the whole
design.

report_timing -group [get_path_groups]

Reports the single worst path in each path group.

9) {-slack_lesser_than maximumslack}
Reports only paths with slack less than the specified maximum_slack
value

10) {-slack_greater_than minimumslack}

Reports only commands with slack greater than the minimum_slack
value.

11) {-pba_mode none / path / exhaustive / ml_exhaustive}

Specifies one of the following path-based timing analysis reports
-none(default)
Disables path-based analysis and enables ordinary graph-based
analysis. This is the fastest mode.
-path
Performs path based analysis on paths after they have been gathered by
GBA, performing more accurate timing results for those paths.
-exhaustive
Performs an exahaustive path_based analysis to determine the truly
worst case paths in the design. This can be used along with
-start_end_pair.
-ml_exhaustive
Performs Machine learning based exhaustive path-based analysis.

12) {-start_end_type from_to_type}

Restricts the report to one of four classes of paths based on the type of
startpoint and endpoint.
reg_to_reg - register to register
reg_to_out - register to output port
In_to_reg - input to register
In_to_out - Input port to Output port

13) {-don_merge_duplicates}
Prevents the merging of duplicate paths across multiple scenarios in
DMSA.
By default, when the same path is reported in more than one scenario,
the tool reports only the single most critical instances of the path from
all scenarios.

14) {-path_type format}

Specifies the type of path information displayed in the timing report,
using one of the following format keywords:
-summary
Displays the path startpoint, path endpoint, and slack.
-end
Displays the path endpoint, path delay, required time, and slack.
-short
Displays a report like the default full report but omits the intermediate
points between the startpoint and endpoint.
-full (default)
Displays the full data path, including all intermediate points and their
incremental points between start and endpoint.
-full_clock
Displays a full report with the addition of the clock source to the launch
and capture points.
-full_clock_explained
Displays a full_clock report with the addition of the clock path points
between primary clock source and its related generated clock source
point.

15) {-nets}
Shows the nets in the timing path.

16) {-transition_time}
Shows the transition time (slew) in the path report for each driver and
load pin, appearing as an additional column labeled “Trans”.

17) {-crosstalk_delta}
Reports the annotated delta delay values at cell input pins in a column
labeled “Delta”. The delta delay values are computed during crosstalk
and Signal Integrity analysis.

18) {-derate}
Shows derating factors in a column labeled “Derate”. Specifying this
option automatically sets the -input_pins option, so that different net
and cell derating values are reported.

19) {-variation}
Includes parametric on-chip variation (POCV) in the report in columns
labeled “Mean” and “Sensit”. POCV analysis is enabled by setting the
timing_pocvm_enable_analysis variable to true.

20) {-physical}
Reports the X-Y co-ordinates for each path element in a column labeled
“location”.

21) {-voltage}
Reports the supply group or the supply net name for each path element
in a column labeled “voltage” allowing you to debug voltage levels in
multi voltage designs.

22) {-sort_by slack / group}

If there is nothing the default option is slack.If “group” option is enabled
the paths are sorted according to the group.