DFT 2006.06 SG 00 Intro

DFT Compiler 1
2006.06
Synopsys Customer Education Services
2006 Synopsys, Inc. All Rights Reserved Synopsys 30-I-011-SSG-009
2 i-
Facilities
Building Hours
Restrooms
Meals
Messages
Smoking
Recycling
Phones
Emergency EXIT
Please turn off cell phones and pagers
3 i-
Workshop Prerequisites
You should have experience in the following areas:
Digital IC design
Verilog or VHDL
UNIX and X-Windows
A Unix based text editor

4 i-
The Power of Tcl
3 workshops
at 3 skill levels
The Power of Tcl
3 workshops
at 3 skill levels
Curriculum Flow
Design Compiler 1
PrimeTime:
Debugging Constraints
Physical Compiler 1
DFT Compiler 1
PrimeTime 1
PrimeTime:
Signal Integrity
ATPG with TetraMAX
Astro 1 Astro XTalk
The Power of Tcl
3 workshops
at 3 skill levels
IC Compiler 1
5 i-
Target Audience
SoC Design and Test engineers who need
to identify and fix DFT violations in their
RTL or gate-level designs, insert scan into
multi-million gate SoCs, and export design
files to ATPG and P&R tools.
6 i-
Introductions
Name
Company
Job Responsibilities
EDA Experience
Main Goal(s) and Expectations for this Course
7 i-
Galaxy Design Platform
Design Services
Physical Compiler
IC Compiler, Astro

JupiterXT

Star-RCXT
Hercules
Proteus
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Design Compiler
D
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W
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M
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Test Synthesis
DFT Compiler, DBIST, DFT MAX
Unified DFT synthesis, verification and
test signoff
Significant test cost reduction
ATPG
TetraMAX
ATPG, DSMTest, TenX

Leading-edge ATPG with comprehensive
support for delay related defects
Synopsys Manufacturing Test Solution
8 i-
1-Pass Test Suite: Environment Overview
TetraMAX Environment
RTL Source
Boundary
Scan Netlist
BSDL
Test Vectors
Design Compiler/Physical Compiler Environment
DFT Compiler
1-Pass Test Synthesis
Setup Info
STIL File
Scan Design
(Gates)
TetraMAX ATPG
Sequential Fault Simulator
Bridging Faults
IDDQ
Transition Delay
Path Delay
BSD Compiler
IEEE-1149.1
9 i-
DFT Compiler
TM
1-Pass Scan Synthesis
RTL Rule Checking: In-depth testability analysis
at RT Level:
Helps designers write test-friendly RTL
AutoFix: Automatic correction of scan DRC violations:
Removes unpredictability from back-end design process
DFT synthesis
Scan Synthesis: Transparent scan implementation:
Seamlessly optimize all design constraints timing, area, power
and test (logical and physical domain)
Hierarchical Scan Synthesis: Leverage existing flows
and test models to gain multi-million gate capacity and
improved performance (logical and physical domain)
10 i-
Top-Down Scan Insertion Flow
DFT Check
Test-Ready Compile
Timing, Area
Read RTL Design
Violations? Create Test Protocol
Constraints
Met?
DFT Check
Specify Scan Paths
Preview
Coverage
Insert Scan Paths
Read Design and
Test Protocol Violations?
Violations?
Handoff Design
Unmapped
DFT Flow
Mapped
DFT Flow
Start
End
11 i-
Test-Ready Flow
Scan-inserted
Design
Testability
Reports
RTL
Source
DFT Compiler
DFT synthesis, test drc, test
coverage preview
DFT Compiler Test-Ready or Unmapped Flow
Start point is RTL
(unmapped) design
IDEAL starting point
1-Pass Scan synthesis
achieved by taking RTL
directly to a scan
synthesized design
12 i-
Mapped Flow
Scan-inserted
Design
Testability
Reports
Gate-Level
Source
DFT Compiler
coverage preview
DFT Compiler Mapped Flow
Start point is gate-level
(mapped) design with
no scan circuitry yet
DFT Compiler performs
scan cell replacement
and scan chain
synthesis
13 i-
Existing Scan Flow
Scan-inserted
Design
Testability
Reports
Gate-Level
Source
DFT Compiler
coverage preview
DFT Compiler Existing Scan Flow
Start point is gate-level
design that already
includes scan cells and
chains
DFT Compiler performs
scan chain extraction &
test DRCs in
preparation for
TetraMAX ATPG
14 i-
Bottom-Up Scan Insertion Flow
DFT Check
Specify Scan Paths
Preview
Coverage
Insert Scan Paths
Read Block and
Test Protocol Violations?
Violations?
Handoff Block
Block
DFT Flow
RTL DFT Flow
DFT Check
Specify Scan Paths
Preview
Coverage
Insert Scan Paths
Read Block and
Test Protocol
Violations?
Violations?
Handoff Block
Block
DFT Flow
RTL DFT Flow

Top-Level DFT
15 i-
Methods for High Capacity Scan Synthesis
Unified Design Rule Checking
(UDRC):
Uses TetraMAX DRC for
consistency and faster runtime
Rapid Scan Synthesis (RSS):
Avoids test uniquification and
just stitches the scan chains
Test Models, Interface Logic
Models (ILMs) with Test Models:
Highly reduced scan models of
gate-level designs
XG Mode
New infrastructure increases
capacity and reduces runtime
DFT Compiler
UDRC
RSS
Test Models
ILMs
DC
DC-XG
16 i-
Workshop Goal
Use DFT Compiler to check RTL and mapped
designs for DFT violations, insert scan chains
into very large multi-million gate designs in
either logical or physical flows, and export all
the required files for downstream tools.
17 i-
Agenda
Understanding Scan Testing
1
DFTC User Interfaces
2
DFT for Clocks and Resets
4
Creating Test Protocols
3
DAY
1
18 i-
Workshop Objectives: Day 1
Define the test protocol for a design
Perform DFT checks at both the RTL and
gate-levels
State common clocking and reset/set design
constructs that cause typical DFT violations
Automatically fix certain DFT violations at the
gate-level using AutoFix
19 i-
Agenda
DFT for Buses/Tristates
5
Top-Down Scan Insertion
6
Exporting Design Files
7
DAY
2
High Capacity DFT Flows
8
20 i-
How to fix Internal/External Buses for DFT
Insert scan to achieve well-balanced top-level scan
chains and other scan design requirements
Write a script to perform all the steps in the DFT flow,
including exporting all the required files for ATPG and
Place & Route
Customize the test initialization sequence, if needed
Modify a bottom-up scan insertion script for full
gate-level designs to use Test Models/ILMs with RSS
and run it
Preview top-level chain balance using test
models/ILMs after block level scan insertion and
revise block level scan architecture as needed to
improve top-level scan chain balance
21 i-
Agenda
DFT MAX
10
Conclusion
12
Customer Support
CS
DAY
3
New Features
9
Clock Gating
11
22 i-
Overview of new features in 2005.09 and 2006.06
XG mode
Introduction to DFT MAX
DFT Power Compiler interoperability

23 i-
Lab Exercise Caution
Recommendation
Definition of
Acronyms
For Further Reference
Under the Hood
Information
Group Exercise
Question
Icons Used in this Workshop
!
24 i-
Test Automation Docs are on SolvNet!
https://solvnet.synopsys.com/dow_retrieve/Y-2006.06/ni/test.html
Documentation on the Web:
https://solvnet.synopsys.com/dow_search

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DFT Compiler 1

ATPG, DSMTest, TenX

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