Unit Ii
Unit Ii
Unit Ii
F(A,B,C)=π(0,3,6,7)
F(A,B,C,D)=π(3,5,7,8,10,11,12,13)
x x’
x x’
x x’
NAND and NOR Implementation
NAND and NOR Implementation
NAND and NOR Implementation
NAND and NOR Implementation
⚫Implement the following function with NAND
and NOR gates.
F(x,y,z) = ∑(0,6) = ∏(1,2,3,4,5,7)
⚫Solution:
Sum of products by combining 1’s using k-Map.
F = x’y’z’ + xyz’
F’ = (x+y+z) . (x’+y’+z)
Product of sums by combining 0’s using k-Map.
F = (x+y’) . (x’+y) . z’
F’ = x’y + xy’ + z
Two-Level Implementation
⚫The implementation of a function in a standard
form (SOP & POS) is said to be a Two-level
implementation.
⚫The Sum-Of-Products (SOP) expression is
implemented with a group of AND gates, one
for each AND term. The output of the AND
gates are connected to the inputs of a single
OR gate.
⚫The Product-Of-Sums (POS) expression is
implemented with a group of OR gates, one
for each OR term. The output of the OR gates
are connected to the inputs of a single AND
gate.
Two-Level Implementation
Two-Level Implementation
Other Two-Level Implementations
⚫Some NAND or NOR gates (but not all)
allow the possibility of a wire connection
between the outputs of two gates to provide
a specific logic function. This type of logic is
called “wired logic”.
⚫Open-collector TTL NAND gates, when tied
together, perform the wired-AND logic.
⚫The wired-AND gate is not a physical gate
but only a symbol to designate the function
obtained from the indicated wired
connection.
Other Two-Level Implementations