Lecture 5-Logic Gates and Ciruits
Lecture 5-Logic Gates and Ciruits
Lecture 5-Logic Gates and Ciruits
Summary
Positive Logic HIGH=1 (i. e +5V)
LOW=0 (i.e. 0V)
Negative Logic HIGH=0 (i. e 0V)
LOW=1 (i.e. +5V)
Negative and positive logic are used Digital but
positive Logic is more common.
Part 4:Logic gates and circuits
NOT/INVERT
This is the inversion operator, it is written as a bar
over its argument.
• It is written “NOT”. Thus the inverse of A
is Ā or NOT A
• Analog representation of not operator
INPUT OUTPUT
Switch open(Low) Lamp ON(High)
Switch close(High) Lamp OFF(Low)
Part 4:Logic gates and circuits
AND Operator
This is an operator denoted by x or. The sign
can be omitted similarly to ordinary algebra;
A x B, A.B or AB has similar meaning. A.B
may be read as A and B. A and B is high if
both A and B is high otherwise LOW.
Part 4:Logic gates and circuits
S1 S2 INPUT Output
S1 S2
Open(Low) Open(Low) Lamp OFF(Low)
Open(Low) Open(Low) Lamp OFF(Low)
Close(High) Close(High) Lamp OFF(Low)
Logic operator OR
It is written as +, A+B is read as A or B; this is high if either A
or B is high or both are high.
INPUT Output
S1
S1 S2
Open(Low) Open(Low) Lamp OFF(Low)
Open(Low) Close(High) Lamp ON(High)
Close(High) Close(Low) Lamp ON(High)
S2
LOGIC GATES
These are basic elements that build up a digital. This is a circuit. This
is a circuit that is able to operate on number of binary inputs in
order to perform particular logic function. Types of gates that are
available are NOT, AND, OR, NAND, NOR, Exclusive-OR and
Exclusive-NOR.
By definition
Gate is a digital circuit with one or more inputs but only one
output.
Part 4:Logic gates and circuits
Inverter
This is agate that forms basic function called inversion or
complementation, a bubble (0) appearing is a symbol for an
inversion. NOT gate is denoted by a bar sign (-), NOT gate is
a gate with one input and one output, and the output is high
only when the input is LOW.
AND gate
This is a gate that performs logical multiplication
function. Is a logic gate with two or more input and
one output; the output this gate is high when all
the inputs are high. This gate is denoted by a
period (.), x or combination of inputs without all
those two notation.
Circuit symbol and truth table for two inputs AND gate
Part 4:Logic gates and circuits
The OR Gate
This is a gate with two or more input and only one
output; the output of an OR gate is LOW only when
all of its inputs are LOW. This performs Logical
addition function and it is denoted by (+) sign.
Circuit symbol and truth table for the two inputs OR gate
Part 4:Logic gates and circuits
EXCLUSIVE-OR Gate
The Ex-OR is an abbreviation for the Exclusive –OR
gate, In this gate the output is high when there is
odd number of one (1) at the input.
EXCLUSIVE-OR Gate
IC available for Ex-OR gate are those having two
inputs and one output but more than two inputs Ex-
OR can be implemented by using the combination of
other Logic gates. Truth table for 3 input Ex-OR gate
Part 4:Logic gates and circuits
EXCLUSIVE-NOR Gate
Ex-NOR is an abbreviation for Exclusive NOR. The
complemented output of Exclusive OR gate is the output of
Exclusive-NOR gate.
Universal Gates
NOR and NAND gates have the property that they
individually can be used to hardware-implement a logic
circuit corresponding to any given Boolean expression. That
is, it is possible to use either only NAND gates or only NOR
gates to implement any Boolean expression. This is so
because a combination of NAND gates or a combination of
NOR gates can be used to perform functions of any of the
basic logic gates. It is for this reason that NAND and NOR
gates are universal gates.
Part 4:Logic gates and circuits
INHIBIT GATE
There are many situations in digital circuit design where the
passage of a logic signal needs to be either enabled or inhibited
depending upon certain other control inputs. INHIBIT here means
that the gate produces a certain fixed logic level at the output
irrespective of changes in the input logic level. To illustrate this
behavior take NOR gate with one input tied at logic level one, the
output will always be one irrespective of the other inputs. The
inhibit behavior is available in an integrated circuit of AND gate,
which is an AND gate with one input negated by an inverter. The
negated input acts to inhibit the gate.
Part 4:Logic gates and circuits
INHIBIT GATE
Circuit symbol and truth table of a four-input INHIBIT gate
Part 4:Logic gates and circuits
Has five terms including four AND terms and the OR term that
combines the first-level AND terms.
Part 4:Logic gates and circuits
Rule 3: Anything ORed with a 0 is equal to itself (A + 0= A), because one input is always 0, if and if Therefore, X is
equal to whatever the logic level of A is (X = A). A = 0, X = 0. A = 1, X = 1, (A + 0 = A).
Rule 4: Anything ORed with a 1 is equal to 1, because one input to the OR gate is always 1, the output is always 1,
no matter what A is(X = 1). (A + 1 = 1)
Part 4:Logic gates and circuits
Rule 7: Anything ANDed with its own complement equals 0. Because the
inputs are complements of each other, one of them is always 0. With a zero at
the input, the output is always 0 (X = 0).
Part 4:Logic gates and circuits
Rule 8: Anything ORed with its own complement equals 1. Because the inputs
are complements of each other, one of them is always 1. With a 1 at the input,
the output is always 1 (X = 1).
Rule 9: A variable that is complemented twice will return to its original logic
level. When a variable is complemented once, it changes to the opposite logic
level. When it is complemented a second time, it changes back to its original
logic level ( = A).
Part 4:Logic gates and circuits
Rule 10: B=A + B and = + B This rule differs from the others because it
involves two variables. It is useful because, when an equation is in this form,
one or more variables in the second term can be eliminated. The validity of
these two equations is proven in Table below. In each case, equivalence is
demonstrated by showing that the truth table derived from the expression
on the left side of the equation matches.
Proof or rule 10
Part 4:Logic gates and circuits
Review questions
1. How many gates are required to implement the following Boolean
equations?
a) X = (A + B)C
b) Y = AC + BC
c) Z = (ABC + CD)E
1. Which Boolean law is used to transform each of the following
equations?
a) B + (D + E) = (B + D) + E
b) CAB = BCA
c) (B + C)(A + D) = BA + BD + CA + CD
Part 4:Logic gates and circuits
De Morgan’s Theorem
De Morgan’s theorem is stated as follows:
Duality Theorem
Duality theorem state that starting with a Boolean relation, you can
derive another Boolean relation by:
Changing OR sign to and sign Changing AND sign to OR sign
Complementing any zero(0) or one(1) as appearing to the expression
A+0=A
A.1= A
For example distributive Law
A (B+C) = AB+AC
A+ (BC) = (A+B). (A+C)
A+BC= (A+B). (A+C)
Part 4:Logic gates and circuits
Sum of Products(SOP)
Is a group of product terms ORed together. Some of
examples are
1. ABC +AB̅ C̅
2. XY + XYZ̅ + YZ
3. P̅ Q +QR̅ + PQR
Each of these sum of product expressions consist of two or
more product terms(AND) that are ORed together.
Part 4:Logic gates and circuits
Example
Solution
1. Y=AC + AB + BC
=AC (B + B̅ ) + AB(C+ C̅ ) +BC (A+A̅ ) From rule 8
=ABC +AB̅ C + ABC + ABC̅ + ABC + A̅ BC
=ABC + AB̅ C + ABC̅ + A̅ BC
∴ Y= ABC + AB̅ C + ABC̅ + A̅ BC
2. Y= A+ AB +BC
=A (B + B̅ ) (C+ C̅ ) + AB(C+C̅ ) + BC (A+A̅ )
= (AB + AB̅ ) (C+C̅ ) + ABC + ABC̅ + ABC + A̅ BC
= ABC + ABC̅ + AB̅ C + AB̅ C̅ + ABC + ABC̅ + ABC + A̅ BC
= ABC + ABC̅ + AB̅ C + AB̅ C̅ + ABC + ABC̅ + ABC + A̅ BC
=ABC + ABC̅ + AB̅ C + AB̅ C̅ + A̅ BC
Part 4:Logic gates and circuits
3. X= (A+B)(B+C)(A+C)
= ((A+ B) + CC̅ ) + ((B+C) + AA̅ ) + ((A+C) +
BB̅ )
= (A+B+C) (A+B+C̅ ) (A+B+C) (A̅ +B+C)
(A+B+C) (A+B̅ +C)
= (A+B+C) (A+B+C̅) (A̅+B+C) (A+B̅+C)
Part 4:Logic gates and circuits
Truth table
F = x̅ y z + x y̅ z + x y z̅ + x y z
= m3 + m5 + m6 + m7
F (x, y, z) = Σ (3, 5, 6, 7)
The inverse of the function can be expressed as a sum (OR) of its 0-minterms.
F̅ (list of variables) = Σ (list of 0-minterm indices)
F̅ = x̅ y̅ z̅ + x̅ y̅ z + x̅ y z̅ + x y̅ z̅
= m0 + m 1 + m 2 + m 4
Or
F̅ (x, y, z) = Σ (0, 1, 2, 4)
Part 4:Logic gates and circuits
MAXTERM
This is a sum(OR) of variables, in which variables assigned logic
one (0) remain as they are while the variables assigned logic zero
(1) are complemented.
Any Boolean function can be expressed as a product (AND) of its 0-
maxterms.
It is denoted by Mi, where 0 ≤ i < 2n and n=number of terms
1-maxterms = maxterms for which the function F = 1.
0-maxterms = maxterms for which the function F = 0.
F (list of variables) = Π (list of 0-maxterm indices)
Part 4:Logic gates and circuits
Truth table
F (x, y, z) = Π (0, 1, 2, 4)
F(list of variables) = Π (list of 1-maxterm indices)
F̅ = (x+ y̅ +z̅ ) • (x̅ +y+ z̅ ) • (x̅ +y̅ +z) • (x̅ +y̅ +z̅ )
= M3•M5 •M6 •M7
Or
F̅ (x, y, z) = Π (3, 5, 6, 7)
To convert from one canonical form to its other equivalent
form, interchange the symbols Σ and Π, and list the index
numbers that were excluded from the original form.
Part 4:Logic gates and circuits
KARNOUGH MAP(K-MAP)
Is a graphical tool used to simplify logic equation or to convert truth
table to its corresponding logic circuit in a simple orderly process.
Although this K-map can be used to any number of variable but its
practical usefulness is limited to five or six variables.
Or
Is the graphical tool that shows the output level of boolean equation for
each input variable combination.
Part 4:Logic gates and circuits
In K-map
• Output level is placed in a separate cell
• K-map is used to simply up to six
variables(practically)
Cell-is a square covered by single miniterm in a
SOP K-map or single maxterm in POS K-map
Determination of cells
= 2n
Part 4:Logic gates and circuits
Drawing a K-map(Mapping)
K-map can be drawn from the following
1) Drawing a K-map from SOP
2) Drawing K-map from POS
3) Drawing K-map from Truth
table
Part 4:Logic gates and circuits
5) A̅ + AB̅ + ABC̅
6) BC + A̅ C̅
C C
AB 0 1 AB 0 1
00 0 1 00 0 0
01 1 0 01 0 1
11 1 1 11 0 0
10 0 0 10 1 1
Part 4:Logic gates and circuits
CD
AB 00 01 11 10
00 0 1 1 0
01 1 0 0 1
11 1 1 1 0
10 0 0 0 0
Part 4:Logic gates and circuits
CD
AB 00 01 11 10
00 0 0 0 0
01 0 0 0 1
11 1 0 1 1
10 0 0 0 0
Part 4:Logic gates and circuits
5) A̅ + AB̅ + ABC̅
This is not in the standard form to convert it to
standard from
A̅ (B + B̅ )(C + C̅ ) +AB̅ (C + C̅ ) + ABC̅
C
= A̅ B̅ C̅ + A̅ B̅ C + A̅ BC + A̅ BC̅ +
AB 0 1
AB̅ C + AB̅ C̅ + ABC̅
00 0 1
01 1 0
11 1 1
10 0 0
Part 4:Logic gates and circuits
6) BC + A̅ C̅
This is in non-standard form so to convert it to standard:
BC(A+A̅ ) + A̅ C̅ (B + B̅ )
C
ABC + A̅ BC + A̅ BC̅ + A̅ B̅ C̅
AB 0 1
00 0 1
01 1 0
11 1 1
10 0 0
Part 4:Logic gates and circuits
CD
AB 00 01 11 10
00 1 1 0 0
01 0 0 0 0
11 1 1 0 0
10 1 1 1 1
Part 4:Logic gates and circuits
Solution
1) (A̅ + B̅ + C + D) (A̅ + B + C̅ + D̅) (A+ B + C̅ + D)
(A̅ + B̅ + C̅ + D̅) (A+ B + C̅ + D̅)
CD
AB 00 01 11 10
00 1 1 0 0
01 1 1 1 1
11 0 1 0 1
10 1 1 0 1
Part 4:Logic gates and circuits
CD
AB 00 01 11 10
00 0 0 1 1
01 1 1 1 0
11 1 1 1 1
10 1 1 1 0
Part 4:Logic gates and circuits
AB 0 1
00 0 0
01 0 0
11 1 0
10 1 1
Part 4:Logic gates and circuits
Looping
Is the process in which the square that contains one are
grouped together
Looping group of two (pairs)
X=A̅ B C̅ +ABC̅ X=A̅ BC̅ + A̅ BC
Part 4:Logic gates and circuits
Examples
Use K-map to minimize the following:
1) B̅ C̅ D̅ + A̅ BC̅ D̅ + ABC̅ D̅ + A̅ B̅ CD + AB̅ CD + A̅ B̅ CD̅
+ A̅ BCD̅ + A̅ B̅ C̅ D + AB̅ CD̅
2) A̅ BC̅ D̅ + A̅ BC̅ D + ABC̅ D̅ +ABC̅ D + AB̅ C̅ D + A̅ B̅ CD̅
3) AB̅ C + A̅ B̅ C + A̅ B C + AB̅ C̅ + A̅ B̅ C̅
4) F(A,B,C,D)=∑m(0,1,4,8,9,10)
Part 4:Logic gates and circuits
Solution
1) B̅ C̅ D̅ + A̅ BC̅ D̅ + ABC̅ D̅ + A̅ B̅ CD + AB̅ CD + A̅ B̅ CD̅
+ A̅ BCD̅ + A̅ B̅ C̅ D + AB̅ CD̅
In standard form the expression can be written
as
AB̅ C̅ D̅ + A̅ B̅ C̅ D̅ + A̅ BC̅ D̅ + ABC̅ D̅ + A̅ B̅ CD +AB̅ CD
+ A̅ B̅ CD̅ + A̅ BCD̅ + ABCD̅ + AB̅ CD̅
Part 4:Logic gates and circuits
K-map D̅ B̅ C
CD
AB 00 01 11 10
00 1 0 1 1
01 1 0 0 1
11 1 0 0 1
10 1 0 1 1
=D̅ + B̅ C
Part 4:Logic gates and circuits
3) AB̅ C + A̅ B̅ C + A̅ B C + AB̅ C̅ + A̅ B̅ C̅
K-map
C B̅
AB 0 1
00 1 1
01 1
A̅C
11
10 1 1
=B̅ + A̅C
Part 4:Logic gates and circuits
4) F(A,B,C,D)=∑m(0,1,4,8,9,10)
CD
AB 00 01 11 10
00 1 1 0 0
01 1 0 0 0
11 0 0 0
10 1 1 0 1