SN54HC595

SN74HC595
www.ti.com SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009

8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

Check for Samples: SN54HC595 SN74HC595

1FEATURES SN54HC595...J OR W PACKAGE

• 8-Bit Serial-In, Parallel-Out Shift SN74HC595...D, DB, DW, N, NS, OR PW PACKAGE
• Wide Operating Voltage Range of 2 V to 6 V (TOP VIEW)

• High-Current 3-State Outputs Can Drive Up To QB 1 16 VCC

15 LSTTL Loads QC 2 15 QA
• Low Power Consumption: 80-μA (Max) ICC QD 3 14 SER
• tpd = 13 ns (Typ) QE 4 13 OE
• ±6-mA Output Drive at 5 V QF 5 12 RCLK
QG 6 11 SRCLK
• Low Input Current: 1 μA (Max)
QH 7 10 SRCLR
• Shift Register Has Direct Clear
GND 8 9 QH′
DESCRIPTION
The 'HC595 devices contain an 8-bit serial-in, SN54HC595...FK PACKAGE
(TOP VIEW)
parallel-out shift register that feeds an 8-bit D-type

VCC
storage register. The storage register has parallel

QC

NC
QB

QA
3-state outputs. Separate clocks are provided for both
the shift and storage register. The shift register has a
3 2 1 20 1 9
direct overriding clear (SRCLR) input, serial (SER) QD 4 18 SER
input, and serial outputs for cascading. When the QE 5 17 OE
output-enable (OE) input is high, the outputs are in NC 6 16 NC
the high-impedance state. QF 7 15 RCLK
Both the shift register clock (SRCLK) and storage QG 8 14 SRCLK
register clock (RCLK) are positive-edge triggered. If 9 10 11 12 1 3
both clocks are connected together, the shift register
QH
GND
NC

SRCLR
always is one clock pulse ahead of the storage Q H'
register.

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 1982–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN54HC595
SN74HC595
SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 www.ti.com

ORDERING INFORMATION (1)

(2)
TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
PDIP − N Tube of 25 SN74HC595N SN74HC595N
Tube of 40 SN74HC595D
SOIC − D Reel of 2500 SN74HC595DR HC595
Reel of 250 SN74HC595DT
Tube of 40 SN74HC595DW
–40°C to 85°C SOIC − DW HC595
Reel of 2000 SN74HC595DWR
SOP − NS Reel of 2000 SN74HC595NSR HC595
SSOP − DB Reel of 2000 SN74HC595DBR HC595
Tube of 90 SN74HC595PW
TSSOP – PW HC595
Reel of 2000 SN74HC595PWR
CDIP − J Tube of 25 SNJ54HC595J SNJ54HC595J
–55°C to 125°C CFP − W Tube of 150 SNJ54HC595W SNJ54HC595W
LCCC − FK Tube of 55 SNJ54HC595FK SNJ54HC595FK

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Table 1. FUNCTION TABLE

INPUTS
FUNCTION
SER SRCLK SRCLR RCLK OE
X X X X H Outputs QA−QH are disabled.
X X X X L Outputs QA−QH are enabled.
X X L X X Shift register is cleared.
First stage of the shift register goes low.
L ↑ H X X
Other stages store the data of previous stage, respectively.
First stage of the shift register goes high.
H ↑ H X X
Other stages store the data of previous stage, respectively.
X X X ↑ X Shift-register data is stored in the storage register.

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 SN54HC595
SN74HC595
www.ti.com SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009

LOGIC DIAGRAM (POSITIVE LOGIC)

13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
SER 1D 3R 15
C1 C3 QA
R 3S

2S
2R 3R 1
C2 C3 QB
R 3S

2S
2R 3R 2
C2 C3 QC
R 3S

2S
2R 3R 3
C2 C3 QD
R 3S

2S
2R 3R 4
C2 C3 QE
R 3S

2S
2R 3R 5
C2 C3 QF
R 3S

2S
2R 3R 6
C2 C3 QG
R 3S

2S
2R 3R 7
C2 C3 QH
R 3S
9
QH′
Pin numbers shown are for the D, DB, DW, J, N, NS, PW, and W packages.

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SN74HC595
SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 www.ti.com

TIMING DIAGRAM

SRCLK

SER

RCLK

SRCLR

OE

QA

QB

QC

QD

QE

QF

QG

QH

QH’

NOTE: implies that the output is in 3-State mode.

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 SN54HC595
SN74HC595
www.ti.com SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range −0.5 V to 7 V
IIK Input clamp current (2) VI < 0 or VI > VCC ±20 mA
(2)
IOK Output clamp current VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±35 mA
Continuous current through VCC or GND ±70 mA
D package 73°C/W
DB package 82°C/W
DW package 57°C/W
θJA Package thermal impedance (3)
N package 67°C/W
NS package 64°C/W
PW package 108°C/W
Tstg Storage temperature range −65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.

RECOMMENDED OPERATING CONDITIONS (1)

SN54HC595 SN74HC595
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 6 V 1.8 1.8
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
Δt/Δv Input transition rise/fall time (2) VCC = 4.5 V 500 500 ns
VCC = 6 V 400 400
TA Operating free-air temperature –55 125 –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from
induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

Copyright © 1982–2009, Texas Instruments Incorporated Submit Documentation Feedback 5

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SN54HC595
SN74HC595
SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 www.ti.com

ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54HC595 SN74HC595
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 1.9 1.998 1.9 1.9
IOH = −20 μA 4.5 V 4.4 4.499 4.4 4.4
6V 5.9 5.999 5.9 5.9
VOH VI = VIH or VIL QH′, IOH = −4 mA 3.98 4.3 3.7 3.84 V
4.5 V
QA−QH, IOH = −6 mA 3.98 4.3 3.7 3.84
QH′, IOH = −5.2 mA 5.48 5.8 5.2 5.34
6V
QA−QH, IOH = −7.8 mA 5.48 5.8 5.2 5.34
2V 0.002 0.1 0.1 0.1
IOL = 20 μA 4.5 V 0.001 0.1 0.1 0.1
6V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL QH′, IOL = 4 mA 0.17 0.26 0.4 0.33 V
4.5 V
QA−QH, IOL = 6 mA 0.17 0.26 0.4 0.33
QH′, IOL = 5.2 mA 0.15 0.26 0.4 0.33
6V
QA−QH, IOL = 7.8 mA 0.15 0.26 0.4 0.33
II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA
IOZ VO = VCC or 0, QA−QH 6V ±0.01 ±0.5 ±10 ±5 µA
ICC VI = VCC or 0, IO = 0 6V 8 160 80 µA
2V
Ci 3 10 10 10 pF
to 6 V

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 SN54HC595
SN74HC595
www.ti.com SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009

TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54HC595 SN74HC595
VCC UNIT
MIN MAX MIN MAX MIN MAX
2V 6 4.2 5
fclock Clock frequency 4.5 V 31 21 25 MHz
6V 36 25 29
2V 80 120 100
SRCLK or RCLK high or low 4.5 V 16 24 20
6V 14 20 17
tw Pulse duration ns
2V 80 120 100
SRCLR low 4.5 V 16 24 20
6V 14 20 17
2V 100 150 125
SER before SRCLK↑ 4.5 V 20 30 25
6V 17 25 21
2V 75 113 94
SRCLK↑ before RCLK↑ (1) 4.5 V 15 23 19
6V 13 19 16
tsu Setup time ns
2V 50 75 65
SRCLR low before RCLK↑ 4.5 V 10 15 13
6V 9 13 11
2V 50 75 60
SRCLR high (inactive) before SRCLK↑ 4.5 V 10 15 12
6V 9 13 11
2V 0 0 0
th Hold time, SER after SRCLK↑ 4.5 V 0 0 0 ns
6V 0 0 0

(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.

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SN74HC595
SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 www.ti.com

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted)
FROM TO TA = 25°C SN54HC595 SN74HC595
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
2V 6 26 4.2 5
fmax 4.5 V 31 38 21 25 MHz
6V 36 42 25 29
2V 50 160 240 200
SRCLK QH′ 4.5 V 17 32 48 40
6V 14 27 41 34
tpd ns
2V 50 150 225 187
RCLK QA−QH 4.5 V 17 30 45 37
6V 14 26 38 32
2V 51 175 261 219
tPHL SRCLR QH′ 4.5 V 18 35 52 44 ns
6V 15 30 44 37
2V 40 150 255 187
ten OE QA−QH 4.5 V 15 30 45 37 ns
6V 13 26 38 32
2V 42 200 300 250
tdis OE QA−QH 4.5 V 23 40 60 50 ns
6V 20 34 51 43
2V 28 60 90 75
QA−QH 4.5 V 8 12 18 15
6V 6 10 15 13
tt ns
2V 28 75 110 95
QH′ 4.5 V 8 15 22 19
6V 6 13 19 16

SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted)
FROM TO TA = 25°C SN54HC595 SN74HC595
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
2V 60 200 300 250
tpd RCLK QA−QH 4.5 V 22 40 60 50 ns
6V 19 34 51 43
2V 70 200 298 250
ten OE QA−QH 4.5 V 23 40 60 50 ns
6V 19 34 51 43
2V 45 210 315 265
tt QA−QH 4.5 V 17 42 63 53 ns
6V 13 36 53 45

OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 400 pF

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 SN54HC595
SN74HC595
www.ti.com SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009

PARAMETER MEASUREMENT INFORMATION

VCC
PARAMETER RL CL S1 S2

S1 tPZH 50 pF Open Closed

Test ten 1 kΩ or
From Output Point RL tPZL 150 pF Closed Open
Under Test tPHZ Open Closed
CL tdis 1 kΩ 50 pF
(see Note A) S2 tPLZ Closed Open

50 pF
tpd or tt or Open Open
150 pF
LOAD CIRCUIT

VCC
Reference 50%
VCC Input
High-Level 0V
50% 50%
Pulse tsu th
0V
tw Data VCC
90% 90%
Input 50% 50%
Low-Level VCC 10% 10% 0 V
Pulse 50% 50% tr tf
0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATIONS SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VCC Output
VCC
Input 50% 50% Control
50% 50%
(Low-Level
0V 0V
Enabling)
tPLH tPHL
tPZL tPLZ
In-Phase VOH Output ≈VCC ≈VCC
90% 90%
Output 50% 50% Waveform 1 50%
10% 10% V 10%
OL (See Note B) VOL
tr tf
tPHL tPLH tPZH tPHZ
VOH Output VOH
90% 90% 90%
Out-of- 50% 50% Waveform 2 50%
Phase 10% 10%
VOL (See Note B) ≈0 V
Output tf tr
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A. CL includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
F. t PLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

Copyright © 1982–2009, Texas Instruments Incorporated Submit Documentation Feedback 9

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 PACKAGE OPTION ADDENDUM

www.ti.com 31-Jan-2015

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

5962-86816012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
86816012A
SNJ54HC
595FK
5962-8681601EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8681601EA
SNJ54HC595J
5962-8681601VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8681601VE
A
SNV54HC595J
5962-8681601VFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8681601VF
A
SNV54HC595W
SN54HC595J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC595J

SN74HC595D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

& no Sb/Br)
SN74HC595DBR ACTIVE SSOP DB 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DE4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DRE4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DRG3 ACTIVE SOIC D 16 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DRG4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 31-Jan-2015

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74HC595DT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DTE4 ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DWR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595N ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU | CU SN N / A for Pkg Type -40 to 85 SN74HC595N
(RoHS)
SN74HC595NE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC595N
(RoHS)
SN74HC595NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595PW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SN74HC595PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC595
& no Sb/Br)
SNJ54HC595FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
86816012A
SNJ54HC
595FK
SNJ54HC595J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8681601EA
SNJ54HC595J

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 31-Jan-2015

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SNJ54HC595W OBSOLETE 16 TBD Call TI Call TI -55 to 125

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC595, SN54HC595-SP, SN74HC595 :

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

www.ti.com 31-Jan-2015

• Catalog: SN74HC595, SN54HC595

• Enhanced Product: SN74HC595-EP, SN74HC595-EP
• Military: SN54HC595
• Space: SN54HC595-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Apr-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC595DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74HC595DR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC595DRG3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC595DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC595DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC595DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
SN74HC595DWRG4 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
SN74HC595PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Apr-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC595DBR SSOP DB 16 2000 367.0 367.0 38.0
SN74HC595DR SOIC D 16 2500 364.0 364.0 27.0
SN74HC595DRG3 SOIC D 16 2500 364.0 364.0 27.0
SN74HC595DRG4 SOIC D 16 2500 367.0 367.0 38.0
SN74HC595DRG4 SOIC D 16 2500 333.2 345.9 28.6
SN74HC595DWR SOIC DW 16 2000 367.0 367.0 38.0
SN74HC595DWRG4 SOIC DW 16 2000 367.0 367.0 38.0
SN74HC595PWR TSSOP PW 16 2000 367.0 367.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

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