MS51PC0AE
MS51PC0AE
MS51PC0AE
1T 8051
8-bit Microcontroller
NuMicro® Family
MS51 32K Series
MS51FC0AE
MS51XC0BE
MS51EC0AE
MS51TC0AE
MS51PC0AE
Datasheet
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
TABLE OF CONTENTS
1 GENERAL DESCRIPTION .............................................................................. 7
2 FEATURES ...................................................................................................... 8
3 PARTS INFORMATION ................................................................................. 12
3.1 Package Type .............................................................................................................. 12
3.2 MS51 Series Selection Guide.................................................................................... 12
3.3 MS51 Series Selection Code ..................................................................................... 13
4 PIN CONFIGURATION .................................................................................. 14
4.1 MS51 32KB Series Multi Function Pin Diagram ..................................................... 14
4.1.1 QFN 33-pin Package Pin Diagram ............................................................................. 14
4.1.2 LQFP 32-pin Package Pin Diagram ........................................................................... 15
4.1.3 TSSOP 28-pin Package Pin Diagram ........................................................................ 16
4.1.4 TSSOP 20-pin Package Pin Diagram ........................................................................ 16
4.1.5 QFN 20-pin Package Pin Diagram ............................................................................. 17
4.2 MS51 32KB Series Pin Description .......................................................................... 18
5 BLOCK DIAGRAM ......................................................................................... 22
5.1 MS51 32K Series Block Diagram.............................................................................. 22
6 FUNCTIONAL DESCRIPTION ....................................................................... 23
6.1 Memory Organization.................................................................................................. 23
6.1.1 Overview .......................................................................................................................... 23
MS51 SERIES DATASHEET
LIST OF FIGURES
Figure 4.1-1 Pin Assignment of LQFP-32 Package ....................................................................... 14
Figure 4.1-2 Pin Assignment of LQFP-32 Package ....................................................................... 15
Figure 4.1-3 Pin Assignment of TSSOP28 Package ..................................................................... 16
Figure 4.1-4 Pin Assignment of TSSOP20 Package ..................................................................... 16
Figure 4.1-5 Pin Assignment of QFN20 Package .......................................................................... 17
Figure 5.1-1 Functional Block Diagram .......................................................................................... 22
Figure 6.2-1 CONFIG0 Any Reset Reloading ................................................................................ 25
Figure 6.2-2 CONFIG2 Power-On Reset Reloading ...................................................................... 27
Figure 6.3-1 Clock System Block Diagram .................................................................................... 29
Figure 6.6-1 Timer 2 Block Diagram .............................................................................................. 36
Figure 6.6-2 Timer 3 Block Diagram .............................................................................................. 37
Figure 6.9-1 Self Wake-Up Timer Block Diagram .......................................................................... 41
Figure 6.11-1 SC Controller Block Diagram ................................................................................... 43
Figure 6.13-1 SPI Block Diagram................................................................................................... 46
Figure 6.13-2 SPI Multi-Master, Multi-Slave Interconnection ........................................................ 47
Figure 6.13-3 SPI Single-Master, Single-Slave Interconnection .................................................... 47
®
Figure 7.1-1 NuMicro MS51 Power supply circuit ........................................................................ 50
®
Figure 7.2-1 NuMicro MS51 Peripheral interface circuit .............................................................. 51
Figure 8.6-1 Soldering profile from J-STD-020C ........................................................................... 74
Figure 9.1-1 QFN-33 Package Dimension ..................................................................................... 75
Figure 9.2-1 LQFP-32 Package Dimension ................................................................................... 76
List of Tables
Table 6.7-1 PWM Pin Define And Enable Control Register ........................................................... 39
Table 6.8-1 Watchdog Timer-out Interval Under Different Pre-scalars.......................................... 40
Table 6.11-1 Smart Card or UART Pin Define And Enable Control Register ................................ 44
Table 8.1-1 General operating conditions ...................................................................................... 52
Table 8.2-1 Current consumption in Normal Run mode ................................................................ 53
Table 8.2-2 Current consumption in Idle mode .............................................................................. 54
Table 8.2-3 Chip Current Consumption in Power down mode ...................................................... 54
Table 8.2-4 Low-power mode wakeup timings .............................................................................. 55
Table 8.2-5 I/O input characteristics .............................................................................................. 56
Table 8.2-6 I/O output characteristics ............................................................................................ 57
Table 8.2-7 nRESET Input Characteristics .................................................................................... 58
Table 8.3-1 16 MHz Internal High Speed RC Oscillator(HIRC) characteristics ............................ 59
Table 8.3-2 24MHz Internal High Speed RC Oscillator(HIRC) characteristics .............................. 60
Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator .......................................... 61
Table 8.3-4 External 4~24 MHz High Speed Clock Input Signal ................................................... 62
Table 8.3-5 10 kHz Internal Low Speed RC Oscillator(LIRC) characteristics ............................... 63
Table 8.3-6 I/O AC characteristics ................................................................................................. 64
Table 8.4-1 Reset and power control unit ...................................................................................... 65
Table 8.4-2 Minimum Brown-out Detect Pulse Width .................................................................... 66
Table 8.4-3 ADC characteristics .................................................................................................... 67
Table 8.5-1 Flash memory characteristics ..................................................................................... 69
MS51 SERIES DATASHEET
1 GENERAL DESCRIPTION
The MS51 is an embedded Flash type, 8-bit high performance 1T 8051-based microcontroller. The
instruction set is fully compatible with the standard 80C51 and performance enhanced.
The MS51 contains a up to 32 Kbytes of main Flash called APROM, in which the contents of User
Code resides. The MS51 Flash supports In-Application-Programming (IAP) function, which enables
on-chip firmware updates. IAP also makes it possible to configure any block of User Code array to be
used as non-volatile data storage, which is written by IAP and read by IAP or MOVC instruction. There
is an additional Flash called LDROM, in which the Boot Code normally resides for carrying out In-
System-Programming (ISP). The LDROM size is configurable with a maximum of 4 Kbytes. To
facilitate programming and verification, the Flash allows to be programmed and read electronically by
parallel Writer or In-Circuit-Programming (ICP). Once the code is confirmed, user can lock the code for
security.
The MS51 32KB series provides rich peripherals including 256 bytes of SRAM, 2 Kbytes of auxiliary
RAM (XRAM), Up to 29 general purpose I/O, two 16-bit Timers/Counters 0/1, one 16-bit Timer2 with
three-channel input capture module, one Watchdog Timer (WDT), one Self Wake-up Timer (WKT),
one 16-bit auto-reload Timer3 for general purpose or baud rate generator, two UARTs with frame error
2
detection and automatic address recognition, three ISO 7816-3 interfaces, one SPI, one I C, six basic
PWM output channels, six enhanced PWM output channels, eight-channel shared pin interrupt for all
I/O, and one 12-bit ADC. The peripherals are equipped with 24 sources with 4-level-priority interrupts
capability.
The MS51 32KB series is equipped with three clock sources and supports switching on-the-fly via
software. The three clock sources include external clock input, 10 kHz internal oscillator, and one 16
MHz internal precise oscillator that is factory trimmed to ±1% at room temperature. The MS51
provides additional power monitoring detection such as power-on reset and 4-level brown-out
detection, which stabilizes the power-on/off sequence for a high reliability system design.
The MS51 microcontroller operation consumes a very low power with two economic power modes to
reduce power consumption - Idle and Power-down mode, which are software selectable. Idle mode
turns off the CPU clock but allows continuing peripheral operation. Power-down mode stops the whole
system clock for minimum power consumption. The system clock of the MS51 can also be slowed
down by software clock divider, which allows for a flexibility between execution performance and
power consumption.
2 FEATURES
Brown-out Detector (BOD) 4-level selection, with brown-out interrupt and reset option.
(4.4V / 3.7V / 2.7V / 2.2V)
Low Voltage Reset (LVR) LVR with 2.0V threshold voltage level
Memories
MS51 SERIES DATASHEET
Clocks
Timers
Analog Interfaces
Communication Interfaces
2
1 sets of I C devices
Master/Slave mode
Bidirectional data transfer between masters and slaves
2
IC 7-bit addressing mode
Standard mode (100 kbps) and Fast mode (400 kbps).
2
Supports 8-bit time-out counter requesting the I C interrupt if
2
the I C bus hangs up and timer-out counter overflows
Supports hold time programmable
MS51 SERIES DATASHEET
3 PARTS INFORMATION
ADC(12-Bit)
Part Number
SRAM (KB)
Flash (KB)
Package
Timer/
UART
PWM
SPI
I2C
I/O
Note:
1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
2. ISO 7816-3 configurable as UART function, GPIO defined as UART2 ~ UART4
3. Detailed package information please refer to Chapter 9
4. This document is only for 32KB flash size part number product
4 PIN CONFIGURATION
Users can find pin configuaration informations by using NuTool - PinConfigure. The NuTool -
®
PinConfigure contains all Nuvoton NuMicro Family chip series with all part number, and helps users
configure GPIO multi-function correctly and handily.
23
22
21
20
19
18
17
8
nRESET / P2.0
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
VDD
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5
P3.2 / PWM3_CH0
P3.1 / PWM2_CH1
P3.5 / SPI0_SS
24
23
22
21
20
19
18
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3 27 14 P2.3 / ADC_CH11 / PWM1_CH0 / UART4_TXD
8
nRESET / P2.0
VSS
VDD
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6 2 27 P3.0 / ADC_CH1 / OSCIN / INT0 / UART2_TXD / SPI0_MOSI
TSSOP28
ADC_CH13 / I2C0_SCL / STADC / P1.3 7 22 P0.5 / ADC_CH4 / IC6 / PWM0_CH2 / T0 / UART3_TXD / PWM2_CH0
UART4_TXD / PWM1_CH0 / ADC_CH11 / P2.3 9 20 P0.3 / ADC_CH6 / IC5 / PWM0_CH5 / UART2_TXD / PWM3_CH1
PWM1_CH0 / UART3_TXD / IC0 / PWM0_CH0 / P1.2 13 16 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
PWM1_CH1 / UART3_RXD / PWM0_CH1 / IC1 / CLKO / ADC_CH7 / P1.1 14 15 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5 1 20 P0.4 / ADC_CH5 / IC3 / PWM0_CH3 / STADC / UART2_RXD / PWM2_CH1
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0 5 16 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7 6 15 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5 10 11 P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
MS51 SERIES DATASHEET
14
13
12
11
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3 16 10 P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0
Top transparent view
PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4 17 9 P1.3 / STADC / I2C0_SCL / ADC_CH13
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5 18 QFN20 8 P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
UART0_TXD / ADC_CH3 / P0.6 19 7 P1.5 / PWM0_CH5 / SPI0_SS / IC7 / UART3_TXD / PWM3_CH1
33 VSS
UART0_RXD / ADC_CH2 / P0.7 20 6 VDD
1
5
nRESET / P2.0
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
Pin Number
MS51PC0AE
MS51XC0BE MS51FC0AE MS51EC0AE LQFP 32
Symbol Multi-Function Description[1]
QFN 20 TSSOP20 TSSOP28 MS51TC0AE
QFN 33
P0.6 Port 0 bit 6.
19 2 23 30 ADC_CH3 ADC input channel 3.
UART0_TXD UART0 transmit data output.
P0.7 Port 0 bit 7.
20 3 24 31 ADC_CH2 ADC input channel 2.
UART0_RXD UART0 transmit data output.
P1.0 Port 1 bit 0.
PWM0_CH2 PWM0 output channel 2.
PWM2_CH0 PWM2 output channel 0.
12 15 15 22
IC2 Input capture channel 2.
SPI0_CLK SPI0 clock.
UART1_TXD UART1 receive input.
P1.1 Port 1 bit 1
ADC_CH7 ADC input channel 7.
PWM0_CH1 PWM0 output channel 1.
PWM1_CH1 PWM1 output channel 1.
11 14 14 21
IC1 Input capture channel 1.
UART3_RXD UART3 receive input.
SC1_DAT Smart Card 1 data pin.
CLKO System clock output.
P1.2 Port 1 bit 2.
PWM0_CH0 PWM0 output channel 0.
PWM1_CH0 PWM1 output channel 0.
10 13 13 20
IC0 Input capture channel 0.
UART3_TXD UART3 transmit data output.
SC1_CLK Smart Card 1 clock pin.
P1.3 Port 1 bit 3.
ADC_CH13 ADC input channel 13.
9 12 7 12 2
I2C0_SCL I C0 clock.
Pin Number
MS51PC0AE
MS51XC0BE MS51FC0AE MS51EC0AE LQFP 32
Symbol Multi-Function Description[1]
QFN 20 TSSOP20 TSSOP28 MS51TC0AE
QFN 33
SPI0_CLK SPI0 clock.
UART2_RXD UART2 receive input.
SC0_DAT Smart Card 0 data pin
INT1 External interrupt 1 input.
Port 2 bit 0 input pin available when RPD
P2.0
(CONFIG0.2) is programmed as 0.
It is a Schmitt trigger input pin for hardware
device reset. A low on this pin resets the device.
1 4 26 1 nRESET pin has an internal pull-up resistor
nRESET allowing power-on reset by simply connecting
an external capacitor to VSS.
Note: It is recommended to use 10 kΩ pull-up
resistor and 10 uF capacitor on nRESET pin.
P2.1 Port 2 bit 1.
- - 11 16 ADC_CH9 ADC input channel 9.
PWM2_CH0 PWM2 output channel 0.
P2.2 Port 2 bit 2.
ADC_CH10 ADC input channel 10.
- - 10 15 PWM1_CH1 PWM1 output channel 1.
UART4_RXD UART4 receive input.
SC2_DAT6 Smart card 2 data pin
P2.3 Port 2 bit 3.
ADC_CH11 ADC input channel 11.
- - 9 14 PWM1_CH0 PWM1 output channel 0.
UART4_TXD UART4 transmit data output.
SC2_CLK6 Smart card 2 clock pin
P2.4 Port 2 bit 4.
ADC_CH12 ADC input channel 12.
- - 8 13
External count input to Timer/Counter 0 or its
T0
toggle output.
MS51 SERIES DATASHEET
Pin Number
MS51PC0AE
MS51XC0BE MS51FC0AE MS51EC0AE LQFP 32
Symbol Multi-Function Description[1]
QFN 20 TSSOP20 TSSOP28 MS51TC0AE
QFN 33
PWM3_CH1 PWM3 output channel 0.
UART3_RXD UART3 receive input.
SC1_DAT Smart card 0 data pin
P3.5 Port 3 bit 5.
- - 12 17
SPI0_SS SPI0 slave select input.
P3.6 Port 3 bit 6.
- - - 9
UART1_TXD UART1 transmit data output.
P3.7 Port 3 bit 7.
- - - 10
UART1_RXD UART1 receive input.
Note:
1. All I/O pins can be configured as a interrupt pin. This feature is not listed in multi-function description.
2. UART0_TXD and UART0_RXD pins are software exchangeable by UART0PX (AUXR1.2).
3. [I2C] alternate function remapping option. I2C pins is software switched by I2CPX (I2CON.0).
4. [STADC] alternate function remapping option. STADC pin is software switched by STADCPX(ADCCON1.6).
5. PIOx register decides which pins are PWM or GPIO.
6. UART2_TXD and UART2_RXD pin is defined by AUXR2 register. UART3_TXD, UART3_RXD, UART4_TXD
and UART4_RXD pin defined by AUXR3 register.
5 BLOCK DIAGRAM
T0
Memory 32 KB APROM Timer 0/1
Flash T1
Access
Max. 4KB Timer 2
3 ICAP0~2
LDROM Flash with
Input Capture
Max. Bytes
Data Flash
Timer 3
(page: 128B) Digital
Self Wake-up Peripheral
256 bytes Timer
Internal RAM
Watchdog Timer
2 Kbytes XRAM
(Auxiliary RAM)
Serial Ports UART0/1_TX
8 (UART 0/1) UART0/1_RX
P0[7:0] P0
8-bit Internal Bus
8 UART2/3/4 UART2/3/4_TX
GPIO P1[7:0] P1 (ISO 7816-3 port) UART2/3/4_RX
6 P2 I2C0_SDA
P2[5:0] I2C0 I2C0_SCL
8 SPI0_MOSI
P3[7:0] P3 SPI0_MISO
SPI0 SPI0_SS
SPI0_SCK
MS51 SERIES DATASHEET
8 6
Any Port GPIO Interrupt PWM0CH0~5
PWM0/1/2/3 6
PWM1/2/3CH0~1
FB0
INT0
External Interrupt 15
INT1 AIN0~7, 9~15Analog
12-bit ADC STADC
Peripheral
System Clock
16/24 MHz Internal
RC Oscillator
XIN 4-24 MHz Clock Divider
(HIRC) System Clock
Oscillator Circuit 10 kHz Internal RC
XOUT (HXT) Oscillator Source
(LIRC)
6 FUNCTIONAL DESCRIPTION
6.1.1 Overview
A standard 80C51 based microcontroller divides the memory into two different sections, Program
Memory and Data Memory. The Program Memory is used to store the instruction codes, whereas the
Data Memory is used to store data or variations during the program execution.
The Data Memory occupies a separate address space from Program Memory. In MS51, there are 256
bytes of internal scratch-pad RAM. For many applications those need more internal RAM, the MS51
provides another on-chip 2 Kbytes of RAM, which is called XRAM, accessed by MOVX instruction.
The whole embedded Flash, functioning as Program Memory, is divided into three blocks: Application
ROM (APROM) normally for User Code, Loader ROM (LDROM) normally for Boot Code, and CONFIG
bytes for hardware initialization. Actually, APROM and LDROM function in the same way but have
different size. Each block is accumulated page by page and the page size is 128 bytes. The Flash
control unit supports Erase, Program, and Read modes. The external writer tools though specific I/O
pins, In-Application-Programming (IAP), or In-System-Programming (ISP) can both perform these
modes.
CONFIG0
7 6 5 4 3 2 1 0
CONFIG0 7 6 5 4 3 2 1 0
CBS - OCDPWM OCDEN - RPD LOCK -
CHPCON 7 6 5 4 3 2 1 0
SWRST IAPFF - - - - BS IAPEN
CONFIG1
7 6 5 4 3 2 1 0
- - - - - LDSIZE[2:0]
- - - - - R/W
CONFIG2
7 6 5 4 3 2 1 0
BODCON0 7 6 5 4 3 2 1 0
BODEN BOV[2:0] BOF BORST BORF BOS
CONFIG4
7 6 5 4 3 2 1 0
WDTEN[3:0] - - - -
R/W - - - -
3:0 - Reserved
MS51 SERIES DATASHEET
FECLK
10
The POF is recommended to be cleared to 0 via software to check if a cold reset or warm reset
performed after the next reset occurs. If a cold reset caused by power off and on, POF will be set 1
again. If the reset is a warm reset caused by other reset sources, POF will remain 0. User may take a
different course to check other reset flags and deal with the warm reset event. For detailed electrical
characteristics.
POR: 0001_0000b
PCON 87H, All pages
Others: 000U _0000b
7 6 5 4 3 2 1 0
POR,CCCC XC0X b
BODCON0 A3H, Page 0, TA protected BOD, UUUU XU1X b
Others,UUUU XUUX b
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
POR 0000_0111 b
WDCON AAH, Page 0, TA protected WDT 0000_1UUU b
Others 0000_UUUU b
7 6 5 4 3 2 1 0
6.6 Timer
6.6.1.1 Overview
Timer/Counter 0 and 1 on MS51 are two 16-bit Timers/Counters. Each of them has two 8-bit registers
those form the 16-bit counting register. For Timer/Counter 0 they are TH0, the upper 8-bit register, and
TL0, the lower 8-bit register. Similarly Timer/Counter 1 has two 8-bit registers, TH1 and TL1. TCON
and TMOD can configure modes of Timer/Counter 0 and 1.
The Timer or Counter function is selected by the C/T̅ bit in TMOD. Each Timer/Counter has its own
selection bit. TMOD.2 selects the function for Timer/Counter 0 and TMOD.6 selects the function for
Timer/Counter 1.
When configured as a “Timer”, the timer counts the system clock cycles. The timer clock is 1/12 of the
system clock (FSYS) for standard 8051 capability or direct the system clock for enhancement, which is
selected by T0M (CKCON.3) bit for Timer 0 and T1M (CKCON.4) bit for Timer 1. In the “Counter”
mode, the countering register increases on the falling edge of the external input pin T0. If the sampled
value is high in one clock cycle and low in the next, a valid 1-to-0 transition is recognized on T0 or T1
pin.
The Timers 0 and 1 can be configured to automatically to toggle output whenever a timer overflow
occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer
toggle outputs. This function is enabled by control bits T0OE and T1OE in the CKCON register, and
apply to Timer 0 and Timer 1 respectively. The port outputs will be logic 1 prior to the first timer
̅ bit should be cleared
overflow when this mode is turned on. In order for this mode to function, the C/T
selecting the system clock as the clock source for the timer.
Note that the TH0 (TH1) and TL0 (TL1) are accessed separately. It is strongly recommended that in
mode 0 or 1, user should stop Timer temporally by clearing TR0 (TR1) bit before reading from or
writing to TH0 (TH1) and TL0 (TL1). The free-running reading or writing may cause unpredictable
result.
C0L C0H
CAPF0
CAPF1 CMPCR
CAPF2 Clear
Clear Timer 2 (T2MOD.2)
CAPCR[1] Counter
(T2MOD.3)
Clear Timer 2
00
CAPF0
CAPF1
01
10
=
CAPF2 11 LDEN[1]
LDTS[1:0] (T2MOD.7)
(T2MOD[1:0])
RCMP2L RCMP2H
Timer 2 Module
[1] Once CAPCR and LDEN are both set, an input capture event only clears TH2 and TL2 without reloading RCMP2H and RCMP2L contents.
MS51 SERIES DATASHEET
6.6.3 Timer 3
6.6.3.1 Overview
Timer 3 is implemented simply as a 16-bit auto-reload, up-counting timer. The user can select the pre-
scale with T3PS[2:0] (T3CON[2:0]) and fill the reload value into RH3 and RL3 registers to determine
its overflow rate. User then can set TR3 (T3CON.3) to start counting. When the counter rolls over
FFFFH, TF3 (T3CON.4) is set as 1 and a reload is generated and causes the contents of the RH3 and
RL3 registers to be reloaded into the internal 16-bit counter. If ET3 (EIE1.1) is set as 1, Timer 3
interrupt service routine will be served. TF3 is auto-cleared by hardware after entering its interrupt
service routine.
Timer 3 can also be the baud rate clock source of both UARTs.
Timer 3
FSYS Pre-scalar Overflow TF3
Internal 16-bit Counter Timer 3 Interrupt
(1/1~1/128) (T3CON.4)
TR3
(T3CON.3)
T3PS[2:0]
(T3CON[2:0]) 0 7 0 7
RL3 RH3
6.7.1 Overview
The PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It can
used on motor driving, fan control, backlight brightness tuning, LED light dimming, or simulating as a
simple digital to analog converter output through a low pass filter circuit.
The MS51 PWM0 is especially designed for motor control by providing three pairs, maximum 16-bit
resolution of PWM0 output with programmable period and duty. The architecture makes user easy to
drive the one-phase or three-phase brushless DC motor (BLDC), or three-phase AC induction motor.
Each of six PWM can be configured as one of independent mode, complementary mode, or
synchronous mode. If the complementary mode is used, a programmable dead-time insertion is
available to protect MOS turn-on simultaneously. The PWM waveform can be edge-aligned or center-
aligned with variable interrupt points.
The MS51 PWM1/2/3 provide individual configurable period and duty. maximum 16-bit resolution
output. Each of two PWM1/2/3 can be configured as one of independent mode, complementary mode,
or synchronous mode.The PWM1/2/3 waveform can be edge-aligned or center-aligned with variable
interrupt points.
PWM output pin define and enable control register table.
Control register 1 Control register2
Output
PWM Channel
Pin SFR Byte Name Bit name Value SFR Byte Name Bit name Value
6.8.1 Overview
The MS51 provides one Watchdog Timer (WDT). It can be configured as a time-out reset timer to
reset whole device. Once the device runs in an abnormal status or hangs up by outward interference,
a WDT reset recover the system. It provides a system monitor, which improves the reliability of the
system. Therefore, WDT is especially useful for system that is susceptible to noise, power glitches, or
electrostatic discharge. The WDT also can be configured as a general purpose timer, of which the
periodic interrupt serves as an event timer or a durational system supervisor in a monitoring system,
which is able to operate during Idle or Power-down mode. WDTEN[3:0] (CONFIG4[7:4]) initialize the
WDT to operate as a time-out reset timer or a general purpose timer.
1
The Watchdog time-out interval is determined by the formula × 64 , where
FLIRC × clock dividerscalar
FLIRC is the frequency of internal 10 kHz oscillator. The following table shows an example of the
Watchdog time-out interval with different pre-scales.
0 0 0 1/1 6.40 ms
0 0 1 1/4 25.60 ms
0 1 0 1/8 51.20 ms
0 1 1 1/16 102.40 ms
1 0 0 1/32 204.80 ms
1 0 1 1/64 409.60 ms
1 1 0 1/128 819.20 ms
MS51 SERIES DATASHEET
1 1 1 1/256 1.638 s
Since the limitation of the maxima vaule of WDT timer delay. To up MS51 from idle mode or power
down mode suggest use WKT function see Chapter 6.9 Self Wake-Up Timer (WKT).
6.9.1 Overview
The MS51 has a dedicated Self Wake-up Timer (WKT), which serves for a periodic wake-up timer in
low power mode or for general purpose timer. WKT remains counting in Idle or Power-down mode.
When WKT is being used as a wake-up timer, a start of WKT can occur just prior to entering a power
management mode. WKT has one clock source, internal 10 kHz. Note that the system clock frequency
must be twice over WKT clock. If WKT starts counting, the selected clock source will remain active
once the device enters Idle or Power-down mode. Note that the selected clock source of WKT will not
automatically enabled along with WKT configuration. User should manually enable the selected clock
source and waiting for stability to ensure a proper operation.
The WKT is implemented simply as a 8-bit auto-reload, up-counting timer with pre-scale 1/1 to 1/2048
selected by WKPS[2:0] (WKCON[2:0]). User fills the reload value into RWK register to determine its
overflow rate. The WKTR (WKCON.3) can be set to start counting. When the counter rolls over FFH,
WKTF (WKCON.4) is set as 1 and a reload is generated and causes the contents of the RWK register
to be reloaded into the internal 8-bit counter. If EWKT (EIE1.2) is set as 1, WKT interrupt service
routine will be served.
WKPS[2:0]
WKTR (WKCON[2:0]) 0 15
(WKCON.3) RWK
6.10.1 Overview
The MS51 includes two enhanced full duplex serial ports enhanced with automatic address
recognition and framing error detection. As control bits of these two serial ports are implemented the
same. Generally speaking, in the following contents, there will not be any reference to serial port 1, but
only to serial port 0.
Each serial port supports one synchronous communication mode, Mode 0, and three modes of full
duplex UART (Universal Asynchronous Receiver and Transmitter), Mode 1, 2, and 3. This means it
can transmit and receive simultaneously. The serial port is also receiving-buffered, meaning it can
commence reception of a second byte before a previously received byte has been read from the
register. The receiving and transmitting registers are both accessed at SBUF. Writing to SBUF loads
the transmitting register, and reading SBUF accesses a physically separate receiving register. There
are four operation modes in serial port. In all four modes, transmission initiates by any instruction that
uses SBUF as a destination register.
MS51 SERIES DATASHEET
6.11.1 Overview
The MS51 32K SERIES provides ISO 7816-3 Interface controller (SC controller) with asynchronous
protocal based on ISO/IEC 7816-3 standard. Software controls GPIO pins as the smartcard reset
function and card detection function. This controller also provides UART emulation for high precision
baud rate communication.
RX_IN TX_OUT
RX Shift TX/RX TX Shift
Register Control Unit Register
ISO-7816-3 T = 0, T = 1 compliant
Programmable transmission clock frequency
P0.3 01
UART2_TXD SC0_CLK AUXR2[7:6] UART2TXP
P3.0 10
P0.4 01
UART2_RXD SC0_DAT AUXR2[5:4] UART2RXP
P1.7 10
SFR Define
URAT Pin SC Pin Pin Name
SFR Byte Name SFR Bit Name Value
P1.2 01
P0.5 11
P1.1 01
P3.4 11
Table 6.11-1 Smart Card or UART Pin Define And Enable Control Register
MS51 SERIES DATASHEET
2
6.12 Inter-Integrated Circuit (I C)
6.12.1 Overview
2
The MS51 provides two Inter-Integrated Circuit (I C) bus to serves as an serial interface between the
2
microcontrollers and the I C devices such as EEPROM, LCD module, temperature sensor, and so on.
2
The I C bus used two wires design (a serial data line I2C0_SDA and a serial clock line I2C0_SCL) to
transfer information between devices.
2
The I C bus uses bi-directional data transfer between masters and slaves. There is no central master
and the multi-master system is allowed by arbitration between simultaneously transmitting masters.
The serial clock synchronization allows devices with different bit rates to communicate via one serial
2
bus. The I C bus supports four transfer modes including master transmitter, master receiver, slave
2
receiver, and slave transmitter. The I C interface only supports 7-bit addressing mode. A special mode
2
General Call is also available. The I C can meet both standard (up to 100kbps) and fast (up to 400k
bps) speeds.
6.13.1 Overview
The MS51 provides two Serial Peripheral Interface (SPI) block to support high-speed serial
communication. SPI is a full-duplex, high-speed, synchronous communication bus between
microcontrollers or other peripheral devices such as serial EEPROM, LCD driver, or D/A converter. It
provides either Master or Slave mode, high-speed rate up to FSYS/2, transfer complete and write
collision flag. For a multi-master system, SPI supports Master Mode Fault to protect a multi-master
conflict.
FSYS
S
Divider M MISO
/2, /4, /8, /16 MSB LSB
Write Data Buffer M MOSI
CLOCK
SPR1
SPR0
SS
DISMODF
SSOE
SPIEN
MSTR
MSTR
DISMODF
SPIOVF
WCOL
MODF
SPIF
LSBFE
SPIEN
MSTR
SSOE
CPHA
CPOL
SPR1
SPR0
Internal
SPI Interrupt Data Bus
Figure 6.13-1 shows SPI block diagram. It provides an overview of SPI architecture in this device. The
main blocks of SPI are the SPI control register logic, SPI status logic, clock rate control logic, and pin
control logic. For a serial data transfer or receiving, The SPI block exists a write data buffer, a shift out
register and a read data buffer. It is double buffered in the receiving and transmit directions. Transmit
data can be written to the shifter until when the previous transfer is not complete. Receiving logic
consists of parallel read data buffer so the shift register is free to accept a second data, as the first
received data will be transferred to the read data buffer.
The four pins of SPI interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift
̅̅̅̅). The MOSI pin is used to transfer a 8-bit data in series from the
Clock (SPCLK), and Slave Select (SS
Master to the Slave. Therefore, MOSI is an output pin for Master device and an input for Slave.
Respectively, the MISO is used to receive a serial data from the Slave to the Master.
The SPCLK pin is the clock output in Master mode, but is the clock input in Slave mode. The shift
clock is used to synchronize the data movement both in and out of the devices through their MOSI and
MISO pins. The shift clock is driven by the Master mode device for eight clock cycles. Eight clocks
exchange one byte data on the serial lines. For the shift clock is always produced out of the Master
device, the system should never exist more than one device in Master mode for avoiding device
conflict.
Each Slave peripheral is selected by one Slave Select pin (SS ̅̅̅̅). The signal should stay low for any
̅̅̅̅
Slave access. When SS is driven high, the Slave device will be inactivated. If the system is multi-
slave, there should be only one Slave device selected at the same time. In the Master mode MCU, the
̅̅̅̅
SS pin does not function and it can be configured as a general purpose I/O. However, ̅̅̅̅
SS can be used
as Master Mode Fault detection via software setting if multi-master environment exists. The MS51 also
provides auto-activating function to toggle ̅̅̅̅
SS between each byte-transfer.
Master/Slave Master/Slave
MCU1 MCU2
MISO MISO
MOSI MOSI
SPCLK SPCLK
SS SS
0 0
I/O 1 1 I/O
PORT 2 2 PORT
3 3
SO
SCK
SO
SO
SCK
SCK
SS
SS
SS
SI
SI
SI
Figure 6.13-2 shows a typical interconnection of SPI devices. The bus generally connects devices
together through three signal wires, MOSI to MOSI, MISO to MISO, and SPCLK to SPCLK. The
Master devices select the individual Slave devices by using four pins of a parallel port to control the
four ̅̅̅̅
SS pins. MCU1 and MCU2 play either Master or Slave mode. The ̅̅̅̅ SS should be configured as
Master Mode Fault detection to avoid multi-master conflict.
MOSI MOSI
SPI clock
generator SS SS
*
Master MCU GND Slave MCU
* SS configuration follows DISMODF and SSOE bits.
Figure 6.13-3 shows the simplest SPI system interconnection, single-master and signal-slave. During
a transfer, the Master shifts data out to the Slave via MOSI line. While simultaneously, the Master
shifts data in from the Slave via MISO line. The two shift registers in the Master MCU and the Slave
MCU can be considered as one 16-bit circular shift register. Therefore, while a transfer data pushed
from Master into Slave, the data in Slave will also be pulled in Master device respectively. The transfer
effectively exchanges the data, which was in the SPI shift registers of the two MCUs.
By default, SPI data is transferred MSB first. If the LSBFE (SPCR.5) is set, SPI data shifts LSB first.
This bit does not affect the position of the MSB and LSB in the data register. Note that all the following
description and figures are under the condition of LSBFE logic 0. MSB is transmitted and received
first.
There are three SPI registers to support its operations, including SPI control register (SPCR), SPI
status register (SPSR), and SPI data register (SPDR). These registers provide control, status, data
storage functions, and clock rate selection. The following registers relate to SPI function.
MS51 SERIES DATASHEET
6.14.1 Overview
The MS51 32K SERIES is embedded with a 12-bit SAR ADC. The ADC (analog-to-digital converter)
allows conversion of an analog input signal to a 12-bit binary representation of that signal. The MS51
32K SERIES is selected as 8-channel inputs in single end mode. The internal band-gap voltage 1.22
V also can be the internal ADC input. The analog input, multiplexed into one sample and hold circuit,
charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the
converter. The converter then generates a digital result of this analog level via successive
approximation and stores the result in the result registers. The ADC controller also supports
continuous conversion and storage result data into XRAM.
7 APPLICATION CIRCUIT
EXT_PWR
10uF+0.1uF
MS51
Series
as close to the EXT_PWR as possible
VDD
VSS
EXT_VSS 0.1uF
as close to VDD as possible
®
Figure 7.1-1 NuMicro MS51 Power supply circuit
MS51 SERIES DATASHEET
DVCC
SPI_SS CS
DVCC VDD SPI
SPI_CLK CLK
ICE / ICP SPI_MISO MISO Device
VSS
Interface SPI_MOSI MOSI
100K 100K
VDD
100 * ICE_DAT
100 * ICE_CLK
DVCC
nRESET DVCC
VSS
10K
nRESET
Reset
Circuit 10 uF
RS 232 Transceiver
PC COM Port
Note 1: It is recommended to add 100 ohm series resistor between ICE_DAT/ICE_CLK and writer pin to filter the disturb of noise on the circuit.
Note 2: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin.
Note 3: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
®
Figure 7.2-1 NuMicro MS51 Peripheral interface circuit
8 ELECTRICAL CHARACTERISTICS
Please refer to the relative Datasheet for detailed information about the MS51 electrical
characteristics.
1.17 1.30 TA = 25 °C
VBG Band-gap voltage[2] 1.22
1.14 1.33 TA = -40°C ~105 °C,
Note:
1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3V between V DD and
AVDD can be tolerated during power-on and power-off operation .
2. Based on characterization, tested in production.
24 MHz(HIRC)[1]
3.6
@5.5V
24 MHz(HIRC)[1]
3.2 4.2 4.6 4.8
@3.3V
24 MHz(HIRC)[1]
2.9
@2.4V
Normal run mode,
IDD_RUN executed from Flash, all 16 MHz (HIRC) [1] mA
3.3
peripherals disable @5.5V
Notes:
1. This value base on HIRC enable, LIRC enable
2. This value base on HIRC disable, LIRC enable
3. LVR17 enabled, POR enable and BOD enable.
4. Based on characterization, not tested in production unless otherwise specified.
24 MHz(HIRC)[1]
2.8
@5.5V
24 MHz(HIRC)[1]
2.4 2.9 3.2 3.8
@3.3V
24 MHz(HIRC)[1]
2.2
@2.4V
Idle mode, executed from
IDD_IDLE Flash, all peripherals 16 MHz (HIRC)[1] mA
disable 2.2
@5.5V
16 MHz (HIRC)[1]
1.9 2.5 2.6 3.2
@3.3V
16 MHz (HIRC)[1]
1.8
@2.4V
Notes:
1. This value base on HIRC enable, LIRC enable
2. This value base on HIRC disable, LIRC enable
3. LVR17 enabled, POR enable and BOD enable.
4. Based on characterization, not tested in production unless otherwise specified.
Typ[1] Max[2]
Symbol Test Conditions Unit
TA = 25 °C TA = -40 °C TA = 25 °C TA = 105 °C
MS51 SERIES DATASHEET
Notes:
1. AVDD = VDD = 3.3V unless otherwise specified, LVR17 disabled, POR disabled and BOD disabled.
2. Based on characterization, not tested in production unless otherwise specified.
3. Based on characterization, tested in production.
Notes:
1. Measured on a wakeup phase with a 16 MHz HIRC oscillator.
2. Based on test during characterization, not tested in production.
3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first.
Notes:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher than
the maximum value, if positive current is injected on adjacent pins
VDD = 5.5 V
-7.4 - -7.5 µA
VIN =(VDD-0.4) V
VDD = 3.3 V
-7.3 - -7.5 µA
Source current for quasi- VIN =(VDD-0.4) V
bidirectional mode and high
level VDD = 2.4 V
-7.3 - -7.5 µA
VIN =(VDD-0.4) V
VDD = 5.5 V
-57.2 - -58.3 µA
VIN = 2.4 V
ISR[1] [2]
VDD = 5.5 V
-9 - -9.6 mA
VIN =(VDD-0.4) V
VDD = 3.3 V
-6 - -6.6 mA
VIN =(VDD-0.4) V
Source current for push-pull
mode and high level
VDD = 2.7 V
-4.2 - -4.9 mA
VIN =(VDD-0.4) V
VDD = 5.5 V
-18 - -20 mA
VIN = 2.4 V
VDD = 5.5 V
18 - 20 mA
VIN = 0.4 V
VDD = 2.4 V
9.7 - 11 mA
VIN = 0.4 V
Notes:
1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not
exceed ΣIDD and ΣISS.
45 - 60 VDD = 5.5 V
RRST[1] Internal nRESET pull up resistor KΩ
45 - 65 VDD = 2.4 V
Notes:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.
TA = 25 °C,
Oscillator frequnecy - 16[1] - MHz
VDD = 3.3
TA = 25 °C,
-1[3] - 1[3] %
VDD = 3.3V
FHRC
Frequency drift over temperarure and TA = -20 C ~ +105 °C,
-2[4] - 2[4] %
volatge VDD = 2.4 ~ 5.5V
Notes:
1. Default setting value for the product
2. Based on reload value.
3. Based on characterization, tested in production.
4. Guaranteed by characterization result, not tested in production.
5. Guaranteed by design.
TA = 25 °C,
Oscillator frequnecy - 24[1] - MHz
VDD = 3.3
TA = 25 °C,
-1[3] - 1[3] %
VDD = 3.3V
FHRC
Frequency drift over temperarure and TA = -20C ~ +85 °C,
-2[4] - 2[4] %
volatge VDD = 2.4 ~ 5.5V
Notes:
1. Default setting value for the product
2. Based on reload value.
3. Based on characterization, tested in production.
4. Guaranteed by characterization result, not tested in production.
5. Guaranteed by design.
8.3.2 External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
Notes:
Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator
8.3.3 External 4~24 MHz High Speed Clock Input Signal Characteristics
For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions
External
clock source
XT1_IN
tCLCL
tCLCH
MS51 SERIES DATASHEET
90%
VIH
tCLCX
VIL 10%
tCHCL tCHCX
Notes:
1. Guaranteed by characterization, not tested in production.
Table 8.3-4 External 4~24 MHz High Speed Clock Input Signal
TA = 25 °C,
-10[1] - 10[1] %
FLRC VDD = 5V
Frequency drift over temperarure
and volatge
TA=-40~105°C
-35[2] - 35[2] %
Without software calibration
Notes:
1. Guaranteed by characterization, tested in production.
2. Guaranteed by characterization, not tested in production.
3. Guaranteed by design.
Notes:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
3. The maximum frequency is defined by .
VBOD BOD brown-out detect voltage 4.25 4.4 4.55 BOV[1:0] = [0,0]
Notes:
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
VDD
RVDDR RVDDF
VBOD
VLVR
VPOR
Time
0 Normal mode
Any clock source Typ. 1μs
(LPBOD[1:0] = [0,0])
LIRC 2 (1/FLIRC)
NR Resolution 12 Bit
FADC = 1/TADC
FADC[1] ADC conversion rate - - 500 kHz
TADC = TSMP +TCONV
4095
4094
4093
4092
6
ADC
output 5
Actual transfer curve
code
4
2 DNL
1 1 LSB
4095
Analog input voltage
Offset Error
EO
(LSB)
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
MS51 SERIES DATASHEET
Notes:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles.
3. Guaranteed by design.
Notes:
1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
Note:
1. Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be
exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage
supply pin.
θJA[*1]
Thermal resistance junction-ambient
30 - ℃/Watt
28-pin TSSOP(4.4x9.7 mm)
Note:
1. Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions
Notes:
MS51 SERIES DATASHEET
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
Pacakge[1] MSL
Note:
1. Determined according to IPC/JEDEC J-STD-020
Note:
1. Determined according to J-STD-020C
9 PACKAGE DIMENSIONS
10 ABBREVIATIONS
11 REVISION HISTORY
Date Revision Description
Section 4.2 Added notes about the hardware reference design for
ICE_DAT, ICE_CLK and nRESET pins
2020.04.08 1.02
Modified P3.6 and P3.7 description in Pin Description table,
Figure 4.1-1 and Figure 4.1-2
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.