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    Comp B 60 DLDA Ex3 Shashank Rai

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    shashank rai
    This document describes building even and odd parity generators using logic gates. It defines parity bits as extra bits added to binary messages to make the total number of 1s either even or odd. An even parity generator ensures an even number of 1s, while an odd parity generator ensures an odd number of 1s. Truth tables, K-maps, boolean expressions, and circuit diagrams are used to design 3-bit even and odd parity generators in a digital circuit simulator. The experiment aims to describe parity code generation and give examples of even and odd parity codes.

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    Comp B 60 DLDA Ex3 Shashank Rai

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    shashank rai
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    This document describes building even and odd parity generators using logic gates. It defines parity bits as extra bits added to binary messages to make the total number of 1s either even or odd. An even parity generator ensures an even number of 1s, while an odd parity generator ensures an odd number of 1s. Truth tables, K-maps, boolean expressions, and circuit diagrams are used to design 3-bit even and odd parity generators in a digital circuit simulator. The experiment aims to describe parity code generation and give examples of even and odd parity codes.

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    This document describes building even and odd parity generators using logic gates. It defines parity bits as extra bits added to binary messages to make the total number of 1s either even or odd. An even parity generator ensures an even number of 1s, while an odd parity generator ensures an odd number of 1s. Truth tables, K-maps, boolean expressions, and circuit diagrams are used to design 3-bit even and odd parity generators in a digital circuit simulator. The experiment aims to describe parity code generation and give examples of even and odd parity codes.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    13 views4 pages

    Comp B 60 DLDA Ex3 Shashank Rai

    Uploaded by

    shashank rai
    This document describes building even and odd parity generators using logic gates. It defines parity bits as extra bits added to binary messages to make the total number of 1s either even or odd. An even parity generator ensures an even number of 1s, while an odd parity generator ensures an odd number of 1s. Truth tables, K-maps, boolean expressions, and circuit diagrams are used to design 3-bit even and odd parity generators in a digital circuit simulator. The experiment aims to describe parity code generation and give examples of even and odd parity codes.

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    Experiment 03: Build Even & Odd parity Generator

    Learning Objectives: Illustrate the function of basic logic gates using universal gates & build even &
    odd parity Generator
    Instruments: Circuit Verse digital circuit simulator

    Theory:

    ⮚ What is a Parity Bit?

    A parity bit is an extra bit in any binary message to make the total number of 1’s either odd or
    even. We need to add the parity bit to a signal. This is done by the Parity generator. This parity
    inclusive binary message then transmits from transmitter to receiver end.
    ❖ Even parity mechanism: The target is to make the total number of 1s even. For example, if
    you have a message signal “010”, you can clearly see that it has just one 1. So we add a parity
    bit to make it two 1s. Now the number of 1s is even.
    ❖ Odd parity mechanism: Here, the target is the make the total number of 1s odd. For example,
    consider the same message signal from above. “010”. The parity bit here will be….complete
    the sentence. 0! That’s right. There’s already an odd number of 1s in the message signal.

    While transmitting the data over long distances, there is a possibility of one of the bits changing due
    to electrical noise or some spurious event. To detect such errors, a parity generator/checker pair is
    used, generator at transmitting end and checker at receiving end. The parity of a binary number
    indicates the number of 1’s in it. If the number of 1’s in the word is odd, it is said to have an odd
    parity and if the number of 1’s in it are even, it is said to have an even parity. For e.g. the binary
    number 1010101 is said to have an even parity whereas the number 1011011 is said to have an odd
    parity. At the generating end, a parity bit is attached to a number to make it in an odd or an even
    parity number as desired. At the receiving end, the number with its parity bit is checked to see if the
    parity is maintained. Parity checker shown in the fig. given below is useful in detecting the single bit
    errors. For odd parity, P=1 and for even parity of the number along with the parity bit P=0. The truth
    table is shown next to the circuit diagram.
    Observation Tables:

    Truth Table:
    1. 3 Bit Even Parity Generator

    ⮚ Truth Table

    ⮚ K-map

    ⮚ Boolean Expression

    ⮚ Circuit Diagram
    2. 3 Bit odd Parity Generator

    ⮚ Truth Table

    ⮚ K-map

    ⮚ Boolean Expression
    ⮚ Circuit Diagram

    Learning Outcomes: Students will able to


    LO3.1 Describe the process of parity code generation
    LO3.2 Give Examples for even parity and odd parity
    LO3.3 Derive a code word from the data bits by introducing parity bits

    Course Outcome: After completion of this experiment the students will be able build different number
    systems forms and Illustrate the design of Combinational circuits

    Conclusion: In this experiment we have learnt how to construct 3 bit odd and even parity
    generator with help of gates. We have also simplified in form of expression and K map
    variable and drawn circuit diagram with help of Circuitverse tools.

    NAME: SHASHANK RAI


    CLASS: COMP B
    ROLL NO: 60

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