TCET/FRM/IP-02/18 Term Work Index Sheet

Revision: B
(To be filled up on regular basis)

Marks
Sr. Signature
Name DOP DOC Obtained
No. of Faculty
(100)
Basic Experiments

1 Utilize logic gates to realize Boolean expressions 28/9/21 5/10/21 95

Make use of universal gates to implement Basic
2 05/10/21 12/10/21 90
gates
3 Build parity generator and detector 12/10/21 27/10/21 95

Design & Development Experiment

4 Build Basis Gates Using Circuit verse 12/10/21 27/10/21 95

Build binary to gray code and gray code to binary
5 27/10/21 10/11/21 95
converter
Construct arithmetic circuits i) Half adder ii) Full
6 27/10/21 10/11/21 95
adder
Construct arithmetic i) Half subtractor ii) Full
7 10/11/21 17/11/21 95
subtractor.
8 Construct 4:1 multiplexer using ICs 17/11/21 26/11/21 90

9 Construction of 2-bit magnitude Comparator 17/11/21 26/11/21 90

Case Study

Case study on k-map using 5 bit Variable

10 10/11/21 17/11/21 95
Formative Assessment / Seminar / Remedial work /
Assignments

11 FORMATIVE ASSESSMENT 1 01/10/21 08/10/21 80/100

12 FORMATIVE ASSESSMENT 2 29/10/21 08/11/21 50/50

13 FORMATIVE ASSESSMENT 3 15/11/21 26/11/21 50/50

14

15

17

18
DOP – Date of Performance. DOC – Date of Completion

Provisional Certificate

This is to Certify provisionally that Mr. SHASHANK RAI Class COMP B Roll no 60 Course BE has successfully

completed the term work requirements in the Subject DIGITAL LOGIC DESIGN & ANALYSIS during the academic
Year 2021-2022.

Signature of faculty Signature of HOD Signature of Dean (Academic)

Date: Date: Date:
 LAB EVALUATION SHEET

Cycle-1 Roll No.:60

Experiment/Tutorial No.:
Performance
Pa ra me te rs We i g ht a g e Category Excel- Very Below
Good Average
lent Good Average Score
(3) (2)
(5) (4) (1)


Technical Knowledge Prerequisites (2)
(Preparedness and Execution)
30 Skills in performing experiment (2)
Learning (1)


Technical Documentation Format (1)
(Developing skills for Journal
Writing and Maintenance of Lab 30 Contents as per Format (2)
Notebook) Quality (2)


Level of Interaction Level of Understanding (2)
(Developing Expression
Power) 10 Questions & Answers (2)
Application (1)


Behavioral Attitude (1)
(Attitude Towards Learning)
10 Regularity (2)
Team Work / Group Activity(2)


Compliance (Attainment Course Objective Attainment (3)
of Objectives / 20
Outcomes) Learning Objective Attainment (2)

Total 100

Signature of Subject Teacher

LAB EVALUATION SHEET

Cycle-2 Roll No.:60
Experiment/Tutorial No.:
Performance
Pa ra me te rs W e i g h ta g e Category Excel- Very Below
Good Average
lent Good Average Score
(3) (2)
(5) (4) (1)


Technical Knowledge (TK) Prerequisites (2)
(Preparedness and Execution) Skills in performing experiment (2)
30
Learning (1)


Technical Documentation (TD) Format (1)
(Developing skills for Journal
Writing and Maintenance of Lab 30 Contents as per Format (2)
Notebook) Quality (2)


Level of Interaction (LI) Level of Understanding (2)
(Developing Expression
Power) 10 Questions & Answers (2)
Application (1)


Behavioral (B) Attitude (1)
(Attitude Towards Learning)
10 Regularity (2)
Team Work / Group Activity(2)


Compliance (C) Course Objective Attainment (3)
(Attainment of Objectives 20 Learning Objective Attainment (2)
/ Outcomes)

Total 100

Signature of Subject Teacher

Evaluation Index Sheet
Sr. No Cycle Expt. No. TK TD LI B C Total
1 Cycle-1 1 to 5 30 24 10 10 20 94
2 Cycle-2 6 to 10 30 24 10 10 20 94
Total 60 48 20 20 40 188
Average 30 24 10 10 20 94

Signature of Subject Teacher

 Experiment 01 - Utilize logic gates to realize Boolean expressions
Learning Objectives: To Minimize the Boolean algebra and design it using logic gates

Instruments: CircuitVerse Digital Circuit Simulator

Theory: A logic gate is an idealized model of computation or physical electronic device

implementing a Boolean function, a logical operation performed on one or more binary inputs that
produces a single binary output. There are three different categories of logic gates:

● Basic logic gates: AND gate, OR gate and NOT gate

● Universal logic gates: NAND gate and NOR gate
● Exclusive logic gates: XOR gate and XNOR gate

➢ AND gate: It is a basic logic gate which is denoted by cross (x) or dot (.) symbol in a logical
expression. This gate behaves like the following truth table:

A B A.B

0 0 0

0 1 0

1 0 0

1 1 1

In a logical circuit, AND gate is represented by the following symbol and manner:
➢ OR gate: It is a basic logic gate which is denoted by the plus (+) symbol in a logical
expression. This gate behaves like the following truth table:

A B A+B

0 0 0

0 1 1

1 0 1

1 1 1

In a logical circuit, OR gate is represented by the following symbol and manner:

➢ NOT gate: It is a basic logic gate denoted by dash (‘) or bar(x̄ ) above the representingvariable
in a logical expression. The gate behaves like the following truth table:

X x̄or X’

0 1

1 0

In a logical circuit, NOT gate is represented by the following symbol and manner:
➢ NAND gate: It is a universal logic gate denoted by A.B in a logical expression. This gate’s
circuit is used in burglar alarms. It is basically a combination of an AND gate and NOT
gate. It follows the given truth table:

A B A.B

0 0 1

0 1 1

1 0 1

1 1 0

In a logical circuit, NAND gate is represented by the following symbols and manner:

➢ NOR gate: It is a universal logic gate denoted by A + B in a logical expression. It is

basically a combination of an OR gate and NOT gate. It follows the given truth table:

A B A+B

0 0 1

0 1 0

1 0 0

1 1 0

In a logical circuit, NOR gate is represented by the following symbols and manner:
 ➢ XOR gate: It is a special type of logic gate denoted by A⊕B in a logical expression. Prime
example of logic of XOR gate is in staircase wiring or lights which can be operated via
more than one switch. It follows the given truth table:

A B A⊕B

0 0 0

0 1 1

1 0 1

1 1 0

In a logical circuit, XOR gate is represented by the following symbols and manner:

➢ XNOR gate: : It is a special type or logic gate denoted by A⊕B in a logical expression. It is basically a
combination of XNOR gate and NOT gate. It follows the given truth table:

A B A⊕B

0 0 1

0 1 0

1 0 0

1 1 1

In a logical circuit, XNOR gate is represented by the following symbols and manner:
 Exercise:
⮚ Solve Booleans Expressions Using Logic Gates

1) AB+BC+(B+C)
Let Y= AB+BC+B+C
= B(A+C+A)+C
=B(1)+C ….A+1=1
=B+C …..B.1=B

2) A+B(A+C)+AC
Let Y=A+B(A+C)+AC
= A+AB+BC+AC
=A(1+B+C)+BC
=A(1)+BC ….A+1=1
=A+BC …. A.1=A
 3) XY’(Z+YZ’)+Z’
Let Y=XY’(Z+YZ’)+Z’
=XY’Z+XY’YZ’+Z’ …….(Distributive law)
=XY’Z+X(0)Z’+Z’ ……Y.Y’=0
=XY’Z+0+Z’ ……A.0=0
=XY’Z+Z’ ………A+0=A

Applications:
1. Logic gates are used to detect exceeds of temperature or pressure and produce command
signals for the system to take required actions.
2. Allows or disallows the transmission of data through a channel.
3. Gates are also used in digital measuring instruments and in alarm circuits.
4. Logic gates are used in microcontrollers, microprocessors, electronic and electrical project
circuits, burglar alarms and embedded system applications.

Learning Outcomes: Students will able to

LO1.1 Define the various logic gates.
LO1.2 Relate the truth table of various logic gates with the output obtained.
LO1.3 Evaluate a Boolean expression using logic gates.

Course Outcome: After completion of this experiment the students will be able to solve Boolean
expressions as well as students will solve questions based on the given truth table or equations.

Conclusion: In this experiment, we explored the functions of the logic gates and learned how to
implement them in an online simulator. We learned how to simplify problem statements and tested
the output circuits using the simulator functions which ensured the results corresponded with the
truth table.
NAME: SHASHANK RAI
CLASS: COMP B
ROLL NO: 60
 Experiment 02: Make use of universal gates to implement Basic gates
Learning Objectives: Illustrate the function of basic logic gates using universal gates
Instruments: Circuit verse digital circuit simulator

Theory:
NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate. So its
output is complement of the output of an AND gate. This gate can have minimum two inputs,
output is always one. By using only NAND gates, we can realize all logic functions: AND, OR,
NOT, X-OR, X-NOR, NOR. So this gate is also called universal gate.

NAND gates as NOT gate

NAND gates as AND gate

NAND gates as OR gate

NOR gates as NOT gate

NOR gates as AND gate

 NOR gates as OR gate

Observation Tables:

Make use of universal NAND gates to implement Basic gates

1) Y=AB’+CD’+A’B

Make use of universal NOR gates to implement Basic gates

2) Y=A’B+AC’+BC
=(A’C)B+AC’
=(A’.C’)B+AC’
 =AC’(B+1)
=AC’
= (A’+C)’

Learning Outcomes: Students will able to

LO2.1 Define the De Morgan’s theorems
LO2.2 Use the De Morgan’s theorem to derive a Boolean expression with universal gates

Course Outcome: After completion of this experiment the students will be able to solve Boolean
expressions with exclusive OR, NOR,X-NOR,XOR gate.

Conclusion:
In this experiment we have learnt how to create basic logic universal gates like NAND and
NOR. We solved two equations manually and implemented circuit using Verse simulator.

NAME: SHASHANK RAI

CLASS: COMP B
ROLL NO : 60
 Experiment 03: Build Even & Odd parity Generator
Learning Objectives: Illustrate the function of basic logic gates using universal gates & build even &
odd parity Generator
Instruments: Circuit Verse digital circuit simulator

Theory:

⮚ What is a Parity Bit?

A parity bit is an extra bit in any binary message to make the total number of 1’s either odd or
even. We need to add the parity bit to a signal. This is done by the Parity generator. This parity
inclusive binary message then transmits from transmitter to receiver end.
❖ Even parity mechanism: The target is to make the total number of 1s even. For example, if
you have a message signal “010”, you can clearly see that it has just one 1. So we add a parity
bit to make it two 1s. Now the number of 1s is even.
❖ Odd parity mechanism: Here, the target is the make the total number of 1s odd. For example,
consider the same message signal from above. “010”. The parity bit here will be….complete
the sentence. 0! That’s right. There’s already an odd number of 1s in the message signal.

While transmitting the data over long distances, there is a possibility of one of the bits changing due
to electrical noise or some spurious event. To detect such errors, a parity generator/checker pair is
used, generator at transmitting end and checker at receiving end. The parity of a binary number
indicates the number of 1’s in it. If the number of 1’s in the word is odd, it is said to have an odd
parity and if the number of 1’s in it are even, it is said to have an even parity. For e.g. the binary
number 1010101 is said to have an even parity whereas the number 1011011 is said to have an odd
parity. At the generating end, a parity bit is attached to a number to make it in an odd or an even
parity number as desired. At the receiving end, the number with its parity bit is checked to see if the
parity is maintained. Parity checker shown in the fig. given below is useful in detecting the single bit
errors. For odd parity, P=1 and for even parity of the number along with the parity bit P=0. The truth
table is shown next to the circuit diagram.
Observation Tables:

Truth Table:
1. 3 Bit Even Parity Generator

⮚ Truth Table

⮚ K-map

⮚ Boolean Expression

⮚ Circuit Diagram
2. 3 Bit odd Parity Generator

⮚ Truth Table

⮚ K-map

⮚ Boolean Expression
 ⮚ Circuit Diagram

Learning Outcomes: Students will able to

LO3.1 Describe the process of parity code generation
LO3.2 Give Examples for even parity and odd parity
LO3.3 Derive a code word from the data bits by introducing parity bits

Course Outcome: After completion of this experiment the students will be able build different number
systems forms and Illustrate the design of Combinational circuits

Conclusion: In this experiment we have learnt how to construct 3 bit odd and even parity
generator with help of gates. We have also simplified in form of expression and K map
variable and drawn circuit diagram with help of Circuitverse tools.

NAME: SHASHANK RAI

CLASS: COMP B
ROLL NO: 60
 Experiment 04 – Build basic gates using Circuit Verse Simulator
Learning Objectives: To Minimize the Boolean algebra and design it using logic gates&Illustrate the function
of basic gates using universal gates i.e. AND, OR, NOT, EX-OR, EX- NOR, NAND, and OR gates.

Instruments: CircuitVerse Digital Circuit Simulator

Theory: In digital system there are only few operations performed irrespective of the
complexities of the system. The basic operations & universal gates. The operation of these
basic gates is as follows:-

● Basic logic gates: AND gate, OR gate and NOT gate

● Universal logic gates: NAND gate and NOR gate
● Exclusive logic gates: XOR gate and XNOR gate

➢ AND gate: It is a basic logic gate which is denoted by cross (x) or dot (.) symbol in a logical
expression. This gate behaves like the following truth table:

A B A.B

0 0 0

0 1 0

1 0 0

1 1 1

In a logical circuit, AND gate is represented by the following symbol and manner:
➢ OR gate: It is a basic logic gate which is denoted by the plus (+) symbol in a logical
expression. This gate behaves like the following truth table:

A B A+B

0 0 0

0 1 1

1 0 1

1 1 1

In a logical circuit, OR gate is represented by the following symbol and manner:

➢ NOT gate: It is a basic logic gate denoted by dash (‘) or bar(x̄ ) above the representingvariable in a
logical expression. The gate behaves like the following truth table:

X x̄or X’

0 1

1 0

In a logical circuit, NOT gate is represented by the following symbol and manner:
➢ NAND gate: It is a universal logic gate denoted by A.B in a logical expression. This gate’s
circuit is used in burglar alarms. It is basically a combination of an AND gate and NOT
gate. It follows the given truth table:

A B A.B

0 0 1

0 1 1

1 0 1

1 1 0

In a logical circuit, NAND gate is represented by the following symbols and manner:

➢ NOR gate: It is a universal logic gate denoted by A + B in a logical expression. It is

basically a combination of an OR gate and NOT gate. It follows the given truth table:

A B A+B

0 0 1

0 1 0

1 0 0

1 1 0

In a logical circuit, NOR gate is represented by the following symbols and manner:
 ➢ XOR gate: It is a special type of logic gate denoted by A⊕B in a logical expression. Prime
example of logic of XOR gate is in staircase wiring or lights which can be operated via
more than one switch. It follows the given truth table:

A B A⊕B

0 0 0

0 1 1

1 0 1

1 1 0

In a logical circuit, XOR gate is represented by the following symbols and manner:

➢ XNOR gate: : It is a special type or logic gate denoted by A⊕B in a logical expression. It is basically a
combination of XNOR gate and NOT gate. It follows the given truth table:

A B A⊕B

0 0 1

0 1 0

1 0 0

1 1 1

In a logical circuit, XNOR gate is represented by the following symbols and manner:
 Exercise:
⮚ Solve Booleans Expressions & draw circuit diagram using simulator:
1) Y=A’BC’+A’C+A’B’C’+A’C’
=A’.(BC’+B’C’)+A’(C+C’)
=A’.[C’(B+B’)]+A’(1) ….X+X’=1
=A’.[C’(1)]+A’ ……X.1=X
=A’[C’+1]
= A’ ……X+1=1

2) Y=(A.B.C).[A.B+C’.(B.C+A.C)]
=(A.B.C).[A.B+C’.C(B+A)]
=(A.B.C).[A.B+0(B+A)] …..X.X’=0
=(A.B.C).[A.B+0] ……..X.0=0
=(A.B.C).(A.B) ….X+0=0
=(A.A).(B.B).C
=A.B.C …..X.X=X
 3) Y=(A+B’)+(A+C)
=A+B’+A+C
=(A+A)+B’+C
=A+B’+C …..X+X=X

Learning Outcomes: Students will able to

LO1.1 Define the various logic gates.
LO1.2 Relate the truth table of various logic gates with the output obtained.
LO1.3 Evaluate a Boolean expression using logic gates.

Course Outcome: After completion of this experiment the students will be able to solve Boolean
expressions.

Conclusion: In this experiment, we have learnt to construct basic gates circuit Verse simulator. We
have also solved Boolean expression.
NAME: SHASHANK RAI
CLASS: COMP B
ROLL NO: 60
 Experiment 05: Build binary to gray code and gray code to binary converter.

Learning Objectives: Illustrate the process of code conversion.

Instruments: CircuitVerse digital circuit simulator

Theory:
In computers, we need to convert binary to gray and gray to binary. The conversion of this can be
done by using two rules namely binary to gray conversion and gray to binary conversion. In the first
conversion, the MSB of the gray code is constantly equivalent to the MSB of the binary code.
Additional bits of the gray code’s output can get using EX-OR logic gate concept to the binary
codes at that present index as well as the earlier index. Here MSB is nothing but the most
significant bit. In the first conversion, the MSB of the binary code is constantly equivalent to the
MSB of the particular binary code. Additional bits of the binary code’s output can get using EX-
OR logic gate concept by verifying gray codes at that present index. If the present gray code bit is
zero then after that copy earlier binary code, as well copy reverse of earlier binary code bit.

Truth Table:
1. Binary to GCD Conversion
4 bit Message truth table:
K-map:-

Boolean Equation: -
Circuit Diagram :

2. Gray Code to Binary Conversion

4 bit Message truth table:

 K-map:-

Boolean Equation: -
Circuit Diagram:

Learning Objectives: Students will be able to:

LO5.1 Define K-Map with proper example and diagrams

LO5.2 Explain Model and simulate a Gray Code to Binary Conversion Logic Circuit
LO5.3 Explain Binary to Gray Code Conversion Logic Circuit with truth table

Course Outcome:
After completion of this experiment the students will be able to understand the K-map for Gray Code to
Binary Conversion Logic Circuit & Binary to Gray Code Conversion Logic Circuit with truth table.

Conclusion:
We understood in this experiment conversion of BCD to gray code and gray code to BCD with help of truth
table and by solving the Boolean equation , K map and circuit diagram.

NAME: SHASHANK RAI

CLASS: COMP B
ROLL NO: 60
 Experiment 06: Construct arithmetic circuits Half adder & Full adder

Learning Objectives: Illustrate the working half adder, Full adder circuits.

Instruments: CircuitVerse digital circuit simulator

Theory:
1. HALF Adder:
The half adder circuit has two inputs: A and B, which add two input digits and generates a carry and
a sum. It adds two binary digits where the input bits are termed as augend and addend and the result
will be two outputs one is the sum and the other is carry. To perform the sum operation, XOR is
applied to both the inputs, and AND gate is applied to both inputs to produce carry. By using a half
adder, you can design simple addition with the help of logic gates.

Block diagram:

Half Adder Truth Table:

K-map(Sum,carry):
Circuit Diagarm:

2. FULL Adder:
The full adder circuit has three inputs: A and C, which add three input numbers and generates a carry
and sum. Whereas in the full adder circuit, it adds 3 one-bit numbers, where two of the three bits can
be referred to as operands and the other is termed as bit carried in. The produced output is 2-bit output
and these can be referred to as output carry and sum.

Block diagram:

Full Adder Truth Table:

K-map(Sum,Carry –out):

Circuit Diagram:

Learning Outcomes: Students will able to

LO6.1 Define the half adder, Full adder with truth table
LO6.2 Explain Working of half adder, Full adder with circuit diagram

Course Outcome: After completion of this experiment the students will be able to solve half adder & full
adder circuit.

Conclusion:
We learned what half and full adder circuits are and how they can be constructed using logic gates. We
learned their truth tables and solved for k-maps which helped in designing the logic circuit.

NAME: SHASHANK RAI

CLASS: COMP B
ROLL NO: 60
Experiment 07: Construct arithmetic circuits Half subtractor & Full subtractor

Learning Objectives: Illustrate the working half subtractor and Full subtractor circuits.

Instruments: Circuitverse digital circuit simulator

Theory:

1. Half Subtractor: The half subtractor is also a building block for subtracting two
binary numbers. It has two inputs and two outputs. This circuit is used two subtract
two single bit binary numbers A and B. The Difference and borrow are two output
states of half subtractor.

Block diagram:

Half Subtractor (Truth Table):

K-map:

Circuit Diagarm:

2. Full Subtractor: The Half Subtractor is used to subtract only two numbers. To
overcome this problem, a full subtractor was designed. The full subtractor is used to
subtract three 1-bit numbers A, B, and Bin, which are minuend, subtrahend, and
borrow, respectively. The full subtractor has three input states and two output states
i.e., diff and borrow.

Block diagram:
Full Subtractor Truth Table:

K-map:
Circuit Diagram:

Learning Outcomes: Students will able to

LO6.1 Define the half subtractor and Full subtractor with truth table
LO6.2 Explain Working of half subtractor and Full subtractor with circuit diagram

Course Outcome: After completion of this experiment the students will be able to solve half subtractor &
full subtractor circuit.
Conclusion: In this experiment we have learnt construction of Half subtractor and Full
subtractor with help of different types of logic gates and circuit construction was done on
circuit verses simulator and we have also defined truth table and K map.

NAME: SHASHANK RAI

CLASS: COMP B
ROLL NO: 60
 Experiment 08: Construct 4:1 multiplexer using circuit verse

Learning Objectives: Illustrate the working 4:1 multiplexer using circuit verse

Instruments: Circuit Verses

Theory:
In the 4×1 multiplexer, there is a total of four inputs, i.e., I0, I1, I2, and I3, 2 selection lines, i.e.,
S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are present at the
selection lines S0 and S1, one of these 4 inputs are connected to the output. The block diagram and
the truth table of the 4×1 multiplexer are given below.
1. Block Diagram:

2. Truth table:

3. Equation:
 4. Diagram Using Mux:

Learning Outcomes: Students will able to

LO8.1 Define Full adder with truth table
LO8.2 Explain Working of Full adder using mux circuit diagram

Course Outcome: After completion of this experiment the students will be able to solve 4:1 multiplexer
using ICs

Conclusion: In this lab you learned how to design a adder and I learnt from this that full adder,
1-bit binary numbers to gives outputs, sum out and carry out.

NAME: SHASHANK RAI

CLASS: COMPB
ROLL NO: 60
 Experiment 09: Construction of 2-bit magnitude Comparator.

Learning Objectives: Magnitude digital Comparator is a combinational circuit that compares two
digital or binary numbers in order to find out whether one binary number is equal, less than or
greater than the other binary number.

Tools/Software Required: Circuit verses

Theory: A magnitude digital Comparator is a combinational circuit that compares two digital or
binary numbers in order to find out whether one binary number is equal, less than or greater than
the other binary number. We logically design a circuit for which we will have two inputs one for A
and other for B and have three output terminals, one for A > B condition, one for A = B condition
and one for A < B condition.

A comparator used to compare two bits is called a single bit comparator. It consists of two inputs
each for two single bit numbers and three outputs to generate less than, equal to and greater than
between two binary numbers.

Comparator of 2 bit: - Table and Circuit

A comparator used to compare two binary numbers each of two bits is called a 2-bit Magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to and greater than
between two binary numbers.

The truth table for a 2-bit comparator:

K-map for each output and equation:
1. A>B:

2. A=B:

3. A<B:
 Circuit Diagram:

Learning Outcomes: Students will able to

LO10.1 What is 2-bit magnitude comparators
LO10.2 Explain Working of 2 bit magnitude comparators with circuit diagram & output

Course Outcome: After completion of this experiment the students will be able to solve 2 bit magnitude
comparators with circuit diagram.

Conclusion: From this experiment we understood the concept of 2-bit magnitude

Comparator. We have analyse the truth table of for a 2-bit comparator and also k – map for
each output A=B , A<B and A>B . we also learnt the equation and drawn the circuit diagram
for 2 bit magnitude Comparator. We will be able to Explain Working of 2 bit magnitude
comparators with circuit diagram & output and solve 2 bit magnitude comparators with
circuit diagram.

NAME: SHASHANK RAI

CLASS: COMP B
ROLL NO: 60
 Experiment 10: Case study on K-map using 5 Variable

Learning Objectives: To understand k-map & if more than 4 input then how to draw k-map table.

Tools/Software Required:

Theory:

Karnaugh Map or K-Map is an alternative way to write truth table and is used for the simplification
of Boolean Expressions. So far, we are familiar with 3 variable K-Map & 4 variable K-Map. Now,
let us discuss the 5-variable K-Map in detail.
Any Boolean Expression or Function comprising of 5 variables can be solved using the 5 variable
K-Map. Such a 5 variable K-Map must contain 2 = 32 cells . Let the 5-variable Boolean function
be represented as :
f ( P Q R S T) where P, Q, R, S, T are the variables and P is the most significant bit variable and T
is the least significant bit variable.
The structure of such a K-Map for SOP expression is given below :

The cell no. written corresponding to each cell can be understood from the example described here:
Here for variable P=0, we have Q = 0, R = 1, S = 1, T = 1 i.e. (PQRST)=(00111) . In decimal form,
this is equivalent to 7. So, for the cell shown above the corresponding cell no. = 7. In a similar
manner, we can write cell numbers corresponding to every cell as shown in the above figure.
Now let us discuss how to use a 5 variable K-Map to minimize a Boolean Function.

Rules to be followed :
1. If a function is given in compact canonical SOP(Sum of Products) form, then we write “1”
corresponding to each minterm ( provided in the question ) in the corresponding cell
numbers. For e.g.:
For ∑m(0, 1, 5, 7, 30, 31) we will write “1” corresponding to cell numbers (0, 1, 5, 7, 30 and 31).
2. If a function is given in compact canonical POS(Product of Sums) form, then we write “0”
corresponding to each maxterm ( provided in the question ) in the corresponding cell
numbers. For e.g.:
For ∏M(0, 1, 5, 7, 30, 31) we will write “0” corresponding to cell numbers (0, 1, 5, 7, 30 and 31).
Steps to be followed :
1. Make the largest possible size subcube covering all the marked 1’s in case of SOP or all
marked 0’s in case of POS in the K-Map. It is important to note that each subcube can only
contain terms in powers of 2 . Also a subcube 2 cells is possible if and only if in that
subcube for every cell we satisfy that “m” number of cells are adjacent cells .
2. All Essential Prime Implicants (EPIs) must be present in the minimal expressions.
I. Solving SOP function –
For clear understanding, let us solve the example of SOP function minimization of 5 Variable K-
Map using the following expression :
∑m(0, 2, 4, 7, 8, 10, 12, 16, 18, 20, 23, 24, 25, 26, 27, 28)
In the above K-Map we have 4 subcubes:

 Subcube 1: The one marked in red comprises of cells ( 0, 4, 8, 12, 16, 20, 24, 28)

 Subcube 2: The one marked in blue comprises of cells (7, 23)

 Subcube 3: The one marked in pink comprises of cells ( 0, 2, 8, 10, 16, 18, 24, 26)

 Subcube 4: The one marked in yellow comprises of cells (24, 25, 26, 27)
Now, while writing the minimal expression of each of the subcubes we will search for the literal
that is common to all the cells present in that subcube.

 Subcube 1: 𝑆̅. 𝑇

 Subcube 2: 𝑄 RST

 Subcube 3: 𝑅 . 𝑇

 Subcube 4: PQ𝑅 .
Finally, the minimal expression of the given Boolean Function can be expressed as follows :

f(P Q R S T) = 𝑆̅. 𝑇+ 𝑄 R S T + 𝑅 . 𝑇+ P Q 𝑅 .
II. Solving POS function –
Now, let us solve the example of POS function minimization of 5 Variable K-Map using the
following expression :
∏M(0, 2, 4, 7, 8, 10, 12, 16, 18, 20, 23, 24, 25, 26, 27, 28)
In the above K-Map we have 4 subcubes:

 Subcube 1: The one marked in red comprises of cells ( 0, 4, 8, 12, 16, 20, 24, 28)

 Subcube 2: The one marked in blue comprises of cells (7, 23)

 Subcube 3: The one marked in pink comprises of cells ( 0, 2, 8, 10, 16, 18, 24, 26)

 Subcube 4: The one marked in yellow comprises of cells (24, 25, 26, 27)
Now, while writing the minimal expression of each of the subcubes we will search for the literal
that is common to all the cells present in that subcube.

 Subcube 1: S + T

 Subcube 2: Q + 𝑅 + 𝑆̅ + 𝑇

 Subcube 3: R + T

 Subcube 4: 𝑃+ 𝑄 + R
Finally, the minimal expression of the given Boolean Function can be expressed as follows :

f(P Q R S T) = (S + T)(Q + 𝑅 + 𝑆̅ + 𝑇)( R + T)( 𝑃+ 𝑄 + R)

NOTE:

1. For the 5 variable K-Map, the Range of the cell numbers will be from 0 to 2 -1 i.e., 0 to 31.
2. The above-mentioned term “Adjacent Cells” means that “any two cells which differ in only
1 variable”.
Applications:

Provide a means for:-

- Finding optimum or near optimum

  SOP and POS standard forms

 Two-level AND/OR and OR/AND circuits

- For functions with small number of variables
- Visualizing concepts related to manipulating Boolean expressions, and
- Demonstrating concepts used by computer-aided design programs to simplify large circuits

Conclusion:

1. Karnaugh maps are used to simplify real world logic requirements so that they can be
implemented using a minimum number of logic gates. The k- map simplification technique
is simpler and less error – prone compared to the method of solving the logical expression
using Boolean laws.
2. It prevents the need to remember each and every Boolean algebraic theorem.
3. Although 5 and 6 variables are solvable but their complexity is as good as solving the
expression algebraically.

NAME: SHASHANK RAI

CLASS: COMP B

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