DS34C86T
DS34C86T
DS34C86T
May 1998
DS34C86T
Quad CMOS Differential Line Receiver
General Description Features
The DS34C86T is a quad differential line receiver designed n CMOS design for low power
to meet the RS-422, RS-423, and Federal Standards 1020 n ± 0.2V sensitivity over the input common mode voltage
and 1030 for balanced and unbalanced digital data transmis- range
sion, while retaining the low power characteristics of CMOS. n Typical propagation delays: 19 ns
The DS34C86T has an input sensitivity of 200 mV over the n Typical input hysteresis: 60 mV
common mode input voltage range of ± 7V. Hysteresis is pro- n Inputs won’t load line when VCC = 0V
vided to improve noise margin and discourage output insta- n Meets the requirements of EIA standard RS-422
bility for slowly changing input waveforms. n TRI-STATE outputs for system bus compatibility
The DS34C86T features internal pull-up and pull-down resis- n Available in surface mount
tors which prevent output oscillation on unused channels. n Open input Failsafe feature, output high for open input
Separate enable pins allow independent control of receiver
pairs. The TRI-STATE ® outputs have 6 mA source and sink
capability. The DS34C86T is pin compatible with the
DS3486.
Logic Diagram
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Top View
Order Number DS34C86TM, and DS34C86TN
See NS Package Number M16A and N16E
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AC Electrical Characteristics (Note 3) (Continued)
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Test and Switching Waveforms (Continued)
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AC Test Circuits and Switching Time Waveforms (Continued)
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tPLZ tPHZ
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tPZH tPZL
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FIGURE 5. Propagation Delay TRI-STATE Control Unit to Output for “LS-Type” Load
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Physical Dimensions inches (millimeters) unless otherwise noted
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DS34C86T Quad CMOS Differential Line Receiver
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.