SC452 Dual Phase Single Chip IMVP 6 Vcor

NOT RECOMMENDED FOR NEW DESIGN SC452
Dual-Phase Single Chip

IMVP-6 Vcore Power Supply
POWER MANAGEMENT
Description Features
The SC452 is a single chip high-performance PWM con- Dual-Phase Solution with Integrated Drivers
troller designed to power advanced IMVP-6™ processors. Hysteretic Control for Fast Transient Response
On-chip support is provided for all of the IMVP-6 require- Combi-Sense Provides Loss-Less Current Sensing
ments, including Active Voltage Positioning, Geyserville-3 Dynamic Current Sharing
VID transitions, VID-controlled Deeper Sleep voltage set- Active Voltage Positioning
ting, PSI# and DPRSL control, fast/slow C4 exit, and de- True Differential Remote (die) Sensing
fault Boot voltage. On-Chip Support for all IMVP-6 Power Management
Features
The SC452 implements hysteretic control technology VID Programmed Deeper Sleep Voltage
which provides the fastest possible transient response Fast/Slow C4E Break-Event Support
while avoiding the stability issues inherent to classical Clock Enable (CLKEN#) Output
PWM controllers. Semtech’s proprietary Combi-Sense®
IG ED
Delayed Power Good Signal with Blanking
technology provides a loss-less current sensing scheme Programmable Soft-Start and DAC Slew Control
which is extremely robust and easy to lay out. Eliminat- Programmable OCP Threshold
ES D
ing the sense resistors reduces costs and PCB area, plus Supports all Ceramic Decoupling Solutions
N
D EN
increases system efficiency. Integrated SmartDriver™ 44 pin MLP (7x7)
technology initially turns on the high side driver with ‘soft’ Lead-free Package
drive to reduce ringing, EMI, and capacitive turn-on of the
M
low side MOSFET, while also increasing overall efficiency.
EW M
Hysteretic operation adaptively reduces the SC452

N O
switching frequency at light loads. Combined with an

Applications
R EC
automatic “power-save” mode which prevents negative

current flow in the low-side FET, system efficiency is sig- IMVP-6/6+ Notebook PCs
nificantly enhanced during light loading conditions. The Embedded Applications
FO T R
SC452 changes from dual-phase to single-phase opera- Graphics and Other Processor Cores
tion whenever PSI# asserts, providing optimal efficiency
across the entire power range.
O
N
A 7-bit DAC, accurate to 0.85%, sets the output voltage

reference, and implements the 0.300V to 1.500V range
required by the processor. The DAC slew rate is externally
programmed to minimize transient currents and audible
noise. True differential remote sensing provides accu-
rate point-of-load regulation at the processor die. Other
features include programmable soft-start, open-drain
IMVP6_PWRGD and CLKEN# outputs, dynamic current
sharing, over-voltage and programmable over-current pro-
tection. The SC452 is available in a space-saving 44 pin
MLP package.
February 22, 2006 1 www.semtech.com

© 2006 Semtech Corp.
POWER MANAGEMENT
Typical Application Circuit
+VDC
+V5S
1
+VDC C2 1 C1 2
9
8
7
6
5
9
8
7
6
5
CR1
1μF MBR0530 R1 1
0.1μF/25V Q2 1 1
2 2 Q1 C4
1 10.0 D D C3 C5 1.4V@
R2
BST1 1 2 BSTRCD1 4 4
10μF
48A
VPR1 0 25V 10μF +VCC_Core
10μF
1 25V
1 25V
3
2
1
2
1
3
C7 2 2 2
1
R3 C6
N FO
R4
1nF 1 2
100 1uF
2 100k L1 R6
2 R5 2 5 4
1 2 CS1P 1 2 1 2
NOT RECOMMENDED FOR NEW DESIGN

O R
TG1 16.2k C8 10nF 3 6
9
8
7
6
5
9
8
7
6
5
DRN1 0.0005
1
BG1 Q4
VR_ON Q3 1 C9 C10
43 VPN1
ISH D D
To ICH7 DPRSLPVR CR2
T
1 4 4
C11 MBRS14OL
44
42
41
40
39
38
37
36
35
34
2
VPN1
VIN1
TG1
DRN1
BG1
V5_1
ISH1
BST1
100pF 330μF
DPRSL
DPRSTP#
EN
3
2
1
3
2
1
2
2
330μF
R NE
2
CLKEN#1 1 CLKEN#1 CS1+ 33
R7 32
100k R9 VREF 2 VREF CS1- CS1N
HYS 3 HYS CS2- 31 CS2N
10K 30
CLSET 4 CLSET CS2+
R12
EC W
U1 Note: Route CS1x, CS2x, DRPx and FBx
1 8
ERROUT 29 as differential pairs.
10K R10 54.9k R8 5 VID6 ERROUT
28 2 7
6 VCCA VCCA 1 Note: Terminate droop
VID5 27
7 AGND 3 6 feedback to sense
2 1 VID4 SC452 26
8 DAC DAC 2 C15 resistors with Kelvin
VID3 25 4 5
1nF C12 9 SS SS connections.
VID2 24
10 DRP+ R11 1k
VID1 23 1 1 0.1μF
11 DRP-
VID0 R22
C14 10k 2
O D
1 +VDC
C13
1 No_Pop
CRC
PWRGD
CLKEN# 1 1μF 1
DRN2
VPN2
BST2
VID6 C16
V5_2
GND
VID6
VIN2
C17
PSI#
C18
BG2
TG2
1nF
FB+
FB-
VID5 VID5 2
M E
VID4 2
9
8
7
6
5
9
8
7
6
5
VID4 100pF
2
VID3 VID3 10nF 10pF

45
1
VPN2 13
14
15
16
17
18
19
20
21
22
12
VID2 2 2 1
VID2
VID1
Q5 Q6 1
C20
VID1 2 D D C21
VID0 C19
VID0 4 4
To ICH7
M SI
10μF
or CPU 10μF 25V 10μF
25V 25V
3
2
1
2
1
3
2 2 2
IMVP PG
PSI# DRP+
EN G
DRP-
VCC SENSE R13 10 FB+

1 2
GND SENSE FB- 1nF 4 0.5μH 5
C22 R17
R14 10 2 1
2 1 6 3
9
8
7
6
5
9
8
7
6
5
10K L2 0.0005
1
1 2 CS2P 1 2 Q8
Q7 1
C26
1
R16 16.2k C25 10nF D D
D
CR3
1 2 4 4 C27
MBRS140L
TG2 R18 100k
2 C24 2 2
C23 BG2 330μF
3
2
1
3
2
1
ED
DRN2
2
1 1 1
2
10nF 10nF 1 C29
1 C28 1μF 1
2
R19 C30
N
2
100 2 100pF
VPR2
2
United States Patent No. 6,441,597
R20
+VDC BST2 1 2 BSTRCD2
0 1
MBR0530
CR4 +V5S
2
1
C31
1
0.1μF/25V C32
2
1μF
2
SC452
SC452
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not implied.
Parameter Condition Min Max Units
Supply Voltages VCCA V5_1, V5_2 -0.3 6.5 V
Static -0.3 30 V
BST1, BST2 to PGND
Transient <100ns -0.3 34 V
BST1, BST2 to DRN1, DRN2 -0.3 6 V
DRN1, DRN2 to PGND Static -2 25 V
Transient <100ns -5 29 V
IG ED
TG1, TG2 to PGND DRN 1, 2-0.3 BST1, 2+0.3 V
ES D
BG1, BG2 to PGND -0.3 V5_1, 2+0.3 V
N
VIN1, VIN2 to PGND
VPN1, VPN2 to PGND

D EN -0.3
-0.3
25
VIN1, 2+0.3
V
V
M
PGND to AGND -0.3 0.3 V
EW M
All other pins to AGND -0.3 VCCA+0.3 V

N O
Thermal Resistance Junction to Ambient θJA 29

21 o
C/W
R EC
o
Operating Junction Temperature Range TJ -40 125 C
FO T R
o
Storage Temperature Range TSTG -65 150 C
o
Peak IR Reflow (10-40sec) TIRreflow 260 C
O
ESD Rating (Human Body Model) VESD 2 kV

N
Electrical Characteristics
Unless otherwise specified, VccA = V5_1 = V5_2 =5 V. -40<TJ<+125°C.
Parameter Condition Min Typ Max Units
Supplies (VccA, V5_1, V5_2)
VccA,V5_1, V5_2
4.5 5.0 5.5 V
Operating Range
VBAT Operating Range 4.5 24 V
VccA, V5_2 UVLO Rising 4.25 4.4 4.5 V
Hysteresis Falling 50 150 250 mV
VccA Current Disabled 10 μA
In UVLO 0.6 1.0 mA
Operating (Static) 5 10 15 mA
© 2006 Semtech Corp. 3 United States Patent No. 6,441,597

SC452
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Supplies (VccA, V5_1, V5_2) (Cont.)
VccA Operating Current Operating (Deeper Sleep) 8 12 mA
V5_1 Current Disabled 10 μA
In UVLO 10 μA
Operating, Static, TG1 Low 0.3 0.9 1.2 mA
V5_2 Current Disabled 10 μA
In ULVO 120 200 μA
IG ED
Operating, Static, TG2 Low 0.3 0.9 1.2 mA
ES D
Vin1 and Vin2 Current Static TG when respective TG Low 500 μA
N
D EN Static TG when respective TG High
When in Powersave
900
0
μA
μA
M
(EN, VID[6:0],
Logic Inputs (EN, VID[6:0], DPRSLP,
DPRSL, PSI #)
DPRSTP#, PSI#)
EW M
Enable Threshold 0.8 2.0 V

N O
VID[6:0], DRPSLP, DPRSTP, PSI#

VID[6:0], DPRSL, PSI # Threshold 0.45 0.65 V
R EC
Threshold
Input Impedance 40 kΩ
FO T R
85°C)
Reference (DAC, SS, VREF), (0 < TJ <125°C)
DAC Error + Internal Offset 1.5000V - 0.7625V -0.85 +0.85 %

O
0.75V - 0.50V -7 7 mV
N
0.4875 - 0.30V
0.50 - 0.30V -14 14 mV
DAC Sink/Source Ability 0.3V < DAC <1.5V |50| μA
SS Slew Current Start-Up 8 12 16 μA
Operating 102 120 138 μA
Slow DPRSLP Exit

x/6 x/5 x/4
(x = operating ISS)
Discharge (SS = 0.5V) 15 mA
SS Discharge Threshold 50 100 mV
Boot Voltage 1.176 1.2 1.224 V
Boot Delay(1) 10 30 100 us
VREF Accuracy 1.97 2.00 2.03 V
VREF Sink/Source Ability |1.5| mA

SC452
POWER MANAGEMENT
Remote Sense (FB+, FB-)
Input Impedance 14 kΩ
Bandwidth(1) 2 MHz
Droop (DRP+, DRP-)
Input Bias Current ±1 μA
Gain DRP+ = 1.5V, DRP- = 1.48V 9.5 10 10.5 V/V
Droop Input Offset (25°C only) -0.4 0 0.4 mV
IG ED
0 to 85°C
-85°C -0.5 0 0.5 mV
ES D
Maximum Input Signal(1) 20 mV
N
Bandwidth(1)
Error Amplifier (ERROUT)

D EN 0.8 MHz
M
Gain 19
EW M
Bandwidth(1) 2 MHz
N O
R EC
Current Sensing (CS1+, CS1-, CS2+, CS2-, ISH)
CS1, 2 + CS1, 2 Bias Currents CS+ = CS- = 1.5V ±1 μA

FO T R
CS Gain for Switchingg 2.7

5.4 3.0
6.0 3.3
6.6 V/V
Maximum Input Signal(1) 450 mV

O
CS Bandwidth(1) 2 MHz
N
Zero-Crossing Detector Offset -6 6 mV
Low Pass Filter Corner

50 80 125 kHz
Frequency(1)

SC452
POWER MANAGEMENT
Current Sensing (CS1+, CS1-, CS2+, CS2-, ISH) (Cont.)
Current Sharing Open Loop Gain 20

40 30
60 45
90
Current Sharing Range (% relative to VHYS) 26

52 40
80 54
108 %
Current Sharing Offset -3.0 +3.0 mV
Current Sharing Disable

Voltage on ISH pin -0.9 -0.35 V
Threshold Relative to VccA
Hysteresis Setting (HYS, CLSET)
IG ED
HYS, CLSET Input Bias Current ±1
I500I μA
nA
ES D
HYS Error (internal HYS difference from Dual Phase -18
-24 -20 -16
-22 %
N
D EN
TG Hi to TG lo as a percentage of HYS = 1V
voltage applied at HYS pin) Single Phase ±36 ±40 ±44 %
CLSET Voltage (internal hysteresis TG High 160 200 240 mV

M
setting relative to voltage applied at
TG Low 128 160 192 mV
EW M
CLSET pin) CLSET = 1.2V

N O
Single Phase TG Low 90 120 150 mV

R EC
Powergood (CLKEN#, PWRGD)
CLKEN#, PWRGD
Leakage 1 μA
FO T R
High Impedance
On Resistance CLKEN#, PWRGD = 0.1V 100 Ω

O
PWRGD Start-Up Delay 3 6.5 10 ms

N
Fixed Over-Voltage Protection Threshold 1.75 1.8 1.85 V
Power Good Window Upper Threshold FB Rising Relative DAC +160 +200 +240 mV
Power Good Window Lower Threshold FB Falling Relative DAC -360 -300 -240 mV
Power Good Window Lower Hysteresis FB Rising Relative DAC 30 50 90

70 mV

SC452
POWER MANAGEMENT
Parameter Condition Min Typ Max Unit
High-Side Driver (TG1, TG2, BST1, BST2, DRN1, DRN2)
Peak Current(1,2) 1.75 2.0 2.25 A
On Resistance RTG_UP, DRN < 0.5V, 25°C 4.1 5.8 7.5 Ω
Ω
RTG_UP, DRN < 0.5V,
3.48 5.8 9.24
-40 to 125°C
RTG_UP, DRN > 0.5V, 25°C 0.9 1.3 1.7 Ω
Ω
RTG_UP, DRN > 0.5V,
0.76 1.3 2.1
-40 to 125°C
IG ED
RTG_DN , 25°C 0.42 0.6 0.78 Ω
ES D
RTG_DN , -40 to 125°C 0.34 0.6 1.01
N
Rise Time (1,2)
Fall Time (1,2)

D EN CTG = 3nF
CTG = 3nF
17
9
22
12
27
15
ns
ns
M
From Hysteretic Comparator
EW M
Propagation Delay (1,2) 30 45 60 ns

Inputs to Driver Output
N O
Shoot-Thru Protection Delay (1) 10 20 30 ns

R EC
Low-Side Driver (BG1, BG2, V5_1, V5_2, PGND1, PGND2)

FO T R
Peak Current(1, 2) 3.5 4.0 4.5 A
On Resistance RBG_UP at 25°C 0.9 1.3 1.7 Ω
Ω
O
RBG_UP at -40 to 125°C 0.76 1.3 2.1
Ω
N
RBG_DN at 25°C 0.35 0.5 0.65
RBG_DN at -40 to 125°C 0.28 0.5 0.86 Ω
Rise Time(1, 2) CBG = 3nF 5 7 9 ns
Fall Time(1, 2) CBG = 3nF 2.5 3.5 4.5 ns
VPN (VPN1, VPN2, VIN1, VIN2)
Tri-State Leakage -600 600 nA
On Resistance Source 100 200 400 Ω
Sink 100 200 400 Ω
Propagation Delay(1, 2) From Hysteretic Comparator

30 45 60 ns
Inputs to Driver Output

SC452
POWER MANAGEMENT
Pin Configuration Ordering Information
DPRSTP#
Device(2) Package(1) Temp Range (TJ)(3)
DPRSL
BST1
DRN1
VPNI
V5_1
VIN1
BG1
TG1
ISH
EN
SC452IMLTRT MLP-44 -40°C to +125°C
44 43 42 41 40 39 38 37 36 35 34
CLKEN# 1
33 CS1+ SC452EVB Evaluation Board
VREF 2
32 CS1 -
Notes:
31 CS2 - 1) Only available in tape and reel packaging. A reel contains 3000
HYS 3
CLSET 4
30 CS2+ devices.
VID6 5 29 ERROUT 2) This device is ESD sensitive. Use of standard ESD handling precau-
PGND tions is required.
VID5 6
28 VCCA
PAD
VID4 7
27 AGND
3) Lead-free package compliant with J-STD-020B. Qualified to support
IG ED
maximum IR Reflow temperature of 260°C for 30 seconds. This prod-
VID3 8
26 DAC uct is fully WEEE and RoHS compliant.
VID2 9
ES D
25 SS
VID1 10
N
24 DRP+
VID0 11
12 13 14 15 16 17 D EN
18 19 20 21 22
23 DRP -
M
DRN2
VPN2
BST2
V5_2
PWRGD
VIN2
BG2
TG2
PSI#
FB+
FB-
EW M
N O
R EC
f id
Pin Descriptions
FO T R
Pin #
Pin# Pin
PinName
Name Pin Description
Pin Description
1 CLKEN# Start Clock Indicator - open drain output. Active low.

O
N
2 VREF Internal reference voltage (2V). Bypass to AGND with a TBD pF capacitor.
1nF capacitor.
3 HYS Core comparator hysteresis. A resistor divider on this pin sets the hysteresis voltage.
4 CLSET Current Limit Set. A resistor divider on this pin sets the OCP threshold.
5 VID6 VID MSB.
6 VID5
7 VID4
8 VID3
9 VID2
10 VID1
11 VID0 VID LSB.
12 IMVP6_PWRGD IMVP6 Power Good - open drain output.

SC452
POWER MANAGEMENT
Pin Descriptions (Cont.)
PinPin#
# Pin
PinName
Name PinDescription
Pin Description
Virtual Phase Node for Phase 2. Connect an RC between this pin and the output sense
13 VPN2
point to enable Combi-Sense operation.
Input power to the DC-DC converter. Used as supply reference for internal Phase 2
14 VIN2
Combi-Sense circuitry.
Phase 2 Bootstrap pin. A capacitor is connected between BST and DRN to develop the
15 BST2
floating voltage for the high-side MOSFET.
16 TG2 Phase 2 output drive for the top (switching) MOSFET.
This pin connects to the junction of the Phase 2 switching and synchronous MOSFETs .
IG ED
17 DRN2
This pin can be subjected to a -2V minimum relative to PGND without affecting operation.
18 BG2 Phase 2 output drive signal for the bottom (synchronous) MOSFET.
ES D
N
D EN
19 V5_2 Input supply for Phase 2 low-side gate drive. Connect to 5V.
20 PSI# Platform PSI-2 control signal.

M
21 FB+ Remote die sense of core voltage. Connect to VCC_SENSE at the CPU socket.
EW M
22 FB- Remote GND sense. Connect to VSS_SENSE at the CPU socket.

N O
23 DRP- Inverting input to droop amplifier.

R EC
24 DRP+ Non-inverting input to droop amplifier.

FO T R
25 SS Soft-start. An external cap at this pin defines the soft-start ramp.
26 DAC DAC output. An external cap at this pin defines VID transition timing.
O
27 AGND Analog ground.

N
28 VCCA IC supply. Connect to 5V.
29 ERROUT Error Amplifier Compensation Pin.
30 CS2+ Non-inverting input to Phase 2 Combi-Sense amplifier.
31 CS2- Inverting input to Phase 2 Combi-Sense amplifier.
32 CS1- Inverting input to Phase 1 Combi-Sense amplifier.
33 CS1+ Non-inverting input to Phase 1 Combi-Sense amplifier.
34 ISH Used for compensation of the ISHARE amplifier.
35 DPRSTP# DPRSTP# control pin for fast/slow C4E event. Active high.
36 EN Enable control. Active High.
37 V5_1 Input supply for Phase 1 low-side gate drive. Connect to 5V.

SC452
POWER MANAGEMENT
Pin Descriptions (Cont.)
Pin##
Pin PinName
Pin Name Pin Description
Pin Description
38 BG1 Phase 1 output drive signal for the bottom (synchronous) MOSFET.
This pin connects to the junction of the Phase 1 switching and synchronous
39 DRN1 MOSFETs . This pin can be subjected to a -2V minimum relative to PGND without
affecting operation.
40 TG1 Phase 1 output drive for the top (switching) MOSFET.
Phase 1 Bootstrap pin. A capacitor is connected between BST and DRN to

41 BST1
develop the floating voltage for the high-side MOSFET.
Input power to the DC-DC converter. Used as supply reference for internal Phase 1
IG ED
42 VIN1
Combi-Sense circuitry.
Virtual Phase Node for Phase 1. Connect an RC between this pin and the output sense
ES D
43 VPN1
point to enable Combi-Sense operation.
N
44 DPRSL
D EN
Deeper Sleep control pin. Active high.
M
PAD PGND Power Ground for Drivers 1 and 2. Pad must be soldered to Power Ground plane.
EW M
N O
R EC
FO T R
O
N

SC452
POWER MANAGEMENT
Block Diagram
DAC
VID +
[6:0] DAC ERROUT
-
SS ERROR AMP
FB- -
HYSTERETIC COMPARATOR
FB+ + CO
+ CO1
DRP+ + -
-
DRP- CO2
I-limit
IG ED
SELECT
Hys hi
SELECT
ES D
CURRENT SENSE AMP Hys_lo
CS1
CS1+ +
N
+
D EN
CO
CS1- - - CO
LP
FILTER DPRSLP
SELECT PHASE
PHASE
CONTROL
PSI#
M
SELECT CONTROL
LP
FILTER
CS1 DPRSTP
-
CS2+
EW M
+
CS2
- +
CS2- CS2
N O
CURRENT SENSE AMP -

CL hi
+
R EC
CS1 + CL lo I-limit
CO
CS2 -
ISH
FO T R
REFERENCE +
EN & VREF
UVLO -
CL_hi
O
CLSET VID [6:0] PWRGD CLKEN#

LOGIC
CL_lo DAC
N
3ms
START UP PWRGD
HYS_hi TIME
HYS DRIVERS 1,2
HYS_lo VIN 1,2

VPN 1,2
EN EN PGNDN
BST 1,2
VccA TG 1,2
CROSS
VccA CONDUCTION DRN 1,2
PROTECTION
CO 1 or
CO 2
AGND VS 1,2
CS 1 or ZERO BG 1,2
CS 2 CROSSING
PGND 1,2

SC452
POWER MANAGEMENT
Applications Information
INTRODUCTION: Thus, customers can choose the amount of cost and per-
formance they need for any given design.
The SC452 is a new generation of hysteretic converter
which combines the best features of Semtech’s hyster- The SC452 also provides a full range of features.
etic converter technology with the benefits of Semtech’s
patented Combi-Sense technology. The SC452 provides a All IMVP-6/6+ functions are implemented:
complete solution to Intel’s IMVP-6 requirements.
¨ EN
In the SC452, the ripple for the hysteretic switching con- ¨ CLKEN#
trol is provided by Combi-Sense current feedback. This ¨ IMVP-6 PWRGD
provides several advantages over plain voltage-mode hys- ¨ DPRSLPVR
teretic converters, and other topologies such as constant ¨ DPRSTP#
IG ED
on-time which switch on voltage ripple. ¨ PSI#
¨ Geyserville-3 VID changes
• No minimum amount of output ripple is required so ¨ Fast-C4 Exit
ES D
there are no controller-induced limits on capacitor value ¨ All ‘1s’ soft-OFF state
N
or ESR.
D EN
• No current sense resistors are required, resulting in
• A 2.00V voltage reference is provided
M
higher converter efficiency. • Separate hysteresis and current limit settings
EW M
• The large signal magnitude afforded by Combi-Sense • A full suite of protection features is provided:
N O
(4-5 times that of inductor DCR current sensing) makes

R EC
the layout much less sensitive to noise. ¨ Over-current protection (OCP)

¨ Fixed and DAC-referenced over-voltage
• Full differential feedback of the output voltage from the protection (OVP)
FO T R
CPU die is enabled. ¨ Over-temperature protection (OTP)

¨ Undervoltage detection via PWRGD
Because the basic control is hysteretic, the SC452 pro-
O
vides the fastest possible transient response without All protection features are latching, and are either reset by
N
switching at very high frequencies. This results in higher recycling power or toggling the EN signal.
efficiency with less expensive parts because switching
losses are reduced. Only the Combi-Sense ripple is used THEORY OF OPERATION
for the regulation loop, so the load-line accuracy is not af-
fected by tolerances in RDS(ON) or inductor DCR. Howev- Voltage Regulation:
er, because of the large signal magnitude, the DC is kept
for the current limiting and current sharing functions. Referring to the block diagram on the preceding page, the
hysteretic comparator is the heart of the converter. The
Load-line control is provided by a dedicated droop ampli- “+” input corresponds roughly to the CMPREF node of our
fier with uncommitted inputs. This provides users with older generations of IC; the “-” input is similar to CMP. In
maximum flexibility, as the droop source can be any of the order to regulate, the hysteretic comparator needs the fol-
following: lowing information:
• PCB copper trace • DAC (reference) voltage

• Inductor DCR • Droop voltage proportional to IOUT
• Sense resistor • Feedback voltage
• Hysteresis voltage
• Hysteresis ripple

SC452
POWER MANAGEMENT
Applications Information (Cont.)
CMPREF receives the reference, voltage feedback and Current Limit Regulation:
droop information. The reference is produced by the in-
tegrated seven-bit DAC. The feedback voltage is received In Current Limit, the voltage hysteretic converter is over-
by the full differential amplifier from the CPU socket. The ridden by the current limit hysteretic comparator, and the
droop amplifier reduces the voltage at the “+” node of the TG pulse is terminated when the output of the current
differential amplifier as the output current increases to sense amplifier reaches the CL_hi threshold and BG is
produce the required linear load line. A third amplifier, terminated at the CL_lo threshold. These thresholds are
labeled the “Error Amplifier”, multiplies the difference set from the CLSET resistor divider:
between the “ideal” voltage (DAC minus droop) and the
actual voltage (FB+ minus FB-) for faster response. This CL_hi = 0.33 * V(clset)
signal is the reference for the hysteretic comparator. CL_lo = 0.20 * V(clset)
IG ED
CMP has the ripple signal derived from the Combi-Sense Current limit pulses continue until 32 pulses after the
inputs plus the hysteresis signal. The DC is stripped from voltage droops to the PWRGD low threshold; then the con-
the ripple signals by the combination of low-pass filter and troller latches off. This current limit algorithm has been
ES D
summing amplifiers. Phase 2 has a current sharing in- used in several generations of IMVP controllers and have
N
D EN
put derived from an averaged difference between the two
phases. The ripple inputs are fed to a summing block via
a multiplexer which is synchronized to the active phase
been proven to be extremely robust.
M
with the select output. The hysteresis signal is added at Start-Up and Shut-Down Sequences:
EW M
the summing block. The hysteresis voltage is set directly

by the resistor divider from the 2V REF output. For the SC452 to start up, VCCA, V5_1, and V5_2 must
N O
reach their under-voltage lockout (UVLO) thresholds (4.4V

R EC
The figure on Page 14 illustrates the basic switching con- typ.) then the EN signal goes high. The DAC drives 12μA
trol. Starting with the Select line (top plot, green trace) on (typ.) into the soft-start capacitor on the SS pin. The SS
Phase 2, and both CO signals low. Accordingly, both bot- and DAC pins rise slowly until the BOOT voltage (1.2V, fixed
FO T R
tom gate (BG) signals are on and the inductor currents in internally) is reached. The controller remains at BOOT
both phases are discharging as shown by the Phase 1 (or- voltage for ~30μs. At the end of the BOOT interval, the
ange) and Phase 2 (blue) ripple signals in the lower plot. VID(6:0) lines are considered valid and CLKEN# is driven
O
low. The controller will slew at a 120μA rate to the VID-de-

N
When CMP discharges to CMPREF, the select line toggles, fined value. Approximately 6ms after the voltage hits the
CO1 turns on, and subtracts V(hys_hi) from CMP. CO1 PWRGD threshold, IMVP-6_PWRGD goes high, and start-
remains high until CMP again charges to CMPREF. Then, up is complete.
CO1 switches low, adding V(hys_lo) to CMP. This state is
held until CMP again discharges to CMPREF. Then, the In a normal shutdown, the EN signal is driven low, the
select line toggles, CO2 turns on, and the cycle repeats. TG and BG signals are driven low, tri-stating the power
chains. An approximately 100Ω resistor on the FB+ signal
In Dual Phase mode, V(hys_lo) is zero; C0 of the initial discharges Vcore slowly and prevents normal amounts of
phase remains low while the alternate phase is in control, leakage from pulling Vcore high. The DAC and other in-
so BG of the initial phase remains on through the alter- ternal circuitry is shut down, entering a very low power
nate cycle and, as a result, the second phase will termi- (<10μA typical) state. A UVLO will also result in this type
nate at approximately -V(hys). During single phase opera- of shutdown.
tion, V(hys_lo) = -V(hys).

SC452
POWER MANAGEMENT
* D:\Products\SC452\Model_04Jun04\SC452_CBM_Top-level.sch
Date/Time run: 06/04/04 16:18:36 Temperature: 27.0
(A) SC452_CBM_Top-level.dat (active)
6.0V
IC SIGNALS
4.0V CO2
CO1
2.0V Phase 1
IG ED
elect Phase 2
0V
ES D
V(HS27.HS19:select)/2 V(HS27.CO1)/4 +3 V(HS27.CO2)/4+4
N
D EN
LOG SIGNALS
1.10V
CMPREF
M
CMP
EW M
1.05V
N O
Ripple - Phase 1 Ripple - Phase 2

R EC
1.00V
Vdac
SEL>> Vcore
FO T R
0.96V
220us 221us 222us 223us 224us
V(DAC) V(Vcore) V(CS2+)-V(CS2-)+1V V(CS1+)-V(CS1-) +1V V(HS27.CMPREF)-0.55V
V(HS27.CMP)-0.55V
Time
O
Date: June 04, 2004 Page 1 Time: 17:13:48

N

SC452
POWER MANAGEMENT
SC452
VID DPRSL PSI# Status Load
Mode
tSFT_START_VCC
VR_ON -12% 1 0 Deeper Sleep Icc < 3A 1-phase

VBOOT VVID
tBOOT
VCC_CORE
tBOOT-VID-TR
1 1 Deeper Sleep Icc > 3A 1-phase
CPU_UP tCPU_UP
-12%
VCCP Active; Med. 9A < Icc

0 0 1-phase
Power Potential <16A
VCCP_UP
tVCCP_UP
CLK_ENABLE#
IG ED
Active; Full
0 1 Icc > 15A 2-phase
Power Potential
tCPU_PWRGD
IMVP6_PWRGD
ES D
N
D EN
Response to Power Control Inputs:
Figure A - Power On Sequencing Timing Diagram Besides the EN signal, described on Page 13, the SC452
M
reacts to the other control signals in the following man-
EW M
VR_ON
ner:
N O
The SC452 always operates with discontinuous mode

R EC
IMVP6_PWRGD
tPWRDOWN1 power saving enabled, always saving power at light load
regardless of the status of DPRSL or PSI#. PSI# signal is
MCH_PWRGD used to indicate the expected max level of currents de-
FO T R
manded from IMVP6. In essence, as DPRSTP# (DPRSLPVR)

CPU-UP indicates a voltage demand, PSI# indicates a current de-
mand. PSI# signal can be asserted during active (LFM to
O
VCCP-UP HFM) execution. The purpose is to command the voltage

N
regulator to maximize its efficiency through the widest

tPWRDOWN2
range of current loads, (i.e., DeeperSleep to HFM).
VCC_CORE
VCCP
PSI# transitions no longer occurs during Deeper Sleep
mode. While in active mode, it is expected that PSI# sig-
VCC_MCH nal toggle occurs at the same Vcc-core voltage level VID.
The reason to have same VID voltage requirement is that
the superimposed charge current required to charge the
output decoupling to a new level of voltage can overcome
Figure B - Power Off Sequencing Timing Diagram single phase mode of operation (if used), during positive
dv/dt events (such as Enhanced Intel SpeedStep® or
Deeper Sleep exit).

SC452
POWER MANAGEMENT
In active mode, enhanced Intel SpeedStep transitions can A +/-0.85% 7-bit digital-to-analog converter (DAC) serves
occur. SC452 can recognize a step-up in voltage transi- as the programmable reference source of the Core Com-
tion and revert operation to full power mode to supply the parator. Programming is accomplished by logic voltage
bulk capacitor charge currents superimposed on the pro- levels applied to the DAC inputs. The VID code vs. The
cessor active mode current. During Deeper Sleep, PSI# DAC output is shown in the tables below. There are 7 volt-
indicates a very low current state. Regulator can enter age identification pins on mobile processor. These signals
asynchronous mode of operation. In rare occasions, if the can be used to support automatic selection of Vcc_core
PSI# is deasserted during Deeper Sleep, this is an indica- voltages.
tion of a high leakage component that may not benefit
They are needed to cleanly support voltage specification
from asynchronous operation.
variations on current and future processors. VID [6:0]
are defined in the table below. The VID [6:0] signals are
In the Deeper Sleep state, SC452 recognizes Deeper
0V to Vccp CMOS level inputs. These signals are not to
IG ED
Sleep exit state and its associated voltage transitions and
be pulled up externally as this will damage the proces-
reverts operation to full power mode to allow for the bulk
sor.
capacitor charge currents to superimpose with the pro-
ES D
cessor active mode current.
N
D EN
M
EW M
N O
R EC
FO T R
O
N

SC452
POWER MANAGEMENT
Table 1. Table 2.
VID vs. VCC_CORE Voltage (Active Mode) VID vs. VCC_CORE Voltage
(Active Mode/Deeper Sleep Dual Mode Region)
VID VDAC VID VDAC VID VDAC VID VDAC
6 5 4 3 2 1 0 V 6 5 4 3 2 1 0 V 6 5 4 3 2 1 0 V 6 5 4 3 2 1 0 V
0 0 0 0 0 0 0 1.5000 0 0 1 0 1 0 0 1.2500 0 1 0 1 0 0 0 1.0000 0 1 1 1 1 0 0 0.7500
0 0 0 0 0 0 1 1.4875 0 0 1 0 1 0 1 1.2375 0 1 0 1 0 0 1 0.9875 0 1 1 1 1 0 1 0.7375
0 0 0 0 0 1 0 1.4750 0 0 1 0 1 1 0 1.2250 0 1 0 1 0 1 0 0.9750 0 1 1 1 1 1 0 0.7250
IG ED
0 0 0 0 0 1 1 1.4625 0 0 1 0 1 1 1 1.2125 0 1 0 1 0 1 1 0.9625 0 1 1 1 1 1 1 0.7125
0 0 0 0 1 0 0 1.4500 0 0 1 1 0 0 0 1.2000 0 1 0 1 1 0 0 0.9500 1 0 0 0 0 0 0 0.7000
ES D
N
0 0 0 0 1 0 1 1.4375 0 0 1 1 0 0 1 1.1875 0 1 0 1 1 0 1 0.9375 1 0 0 0 0 0 1 0.6875
D EN
0 0 0 0 1 1 0 1.4250 0 0 1 1 0 1 0 1.1750 0 1 0 1 1 1 0 0.9250 1 0 0 0 0 1 0 0.6750
M
0 0 0 0 1 1 1 1.4125 0 0 1 1 0 1 1 1.1625 0 1 0 1 1 1 1 0.9125 1 0 0 0 0 1 1 0.6625
EW M
0 0 0 1 0 0 0 1.4000 0 0 1 1 1 0 0 1.1500 0 1 1 0 0 0 0 0.9000 1 0 0 0 1 0 0 0.6500

N O
0 0 0 1 0 0 1 1.3875 0 0 1 1 1 0 1 1.1375 0 1 1 0 0 0 1 0.8875 1 0 0 0 1 0 1 0.6375

R EC
0 0 0 1 0 1 0 1.3750 0 0 1 1 1 1 0 1.1250 0 1 1 0 0 1 0 0.8750 1 0 0 0 1 1 0 0.6250

FO T R
0 0 0 1 0 1 1 1.3625 0 0 1 1 1 1 1 1.1125 0 1 1 0 0 1 1 0.8625 1 0 0 0 1 1 1 0.6125
0 0 0 1 1 0 0 1.3500 0 1 0 0 0 0 0 1.1100 0 1 1 0 1 0 0 0.8500 1 0 0 1 0 0 0 0.6000

O
0 0 0 1 1 0 1 1.3375 0 1 0 0 0 0 1 1.0875 0 1 1 0 1 0 1 0.8375 1 0 0 1 0 0 1 0.5875

N
0 0 0 1 1 1 0 1.3250 0 1 0 0 0 1 0 1.0750 0 1 1 0 1 1 0 0.8250 1 0 0 1 0 1 0 0.5750
0 0 0 1 1 1 1 1.3125 0 1 0 0 0 1 1 1.0625 0 1 1 0 1 1 1 0.8125 1 0 0 1 0 1 1 0.5625
0 0 1 0 0 0 0 1.3000 0 1 0 0 1 0 0 1.0500 0 1 1 1 0 0 0 0.8000 1 0 0 1 1 0 0 0.5500
0 0 1 0 0 0 1 1.2875 0 1 0 0 1 0 1 1.0375 0 1 1 1 0 0 1 0.7875 1 0 0 1 1 0 1 0.5375
0 0 1 0 0 1 0 1.2750 0 1 0 0 1 1 0 1.0250 0 1 1 1 0 1 0 0.7750 1 0 0 1 1 1 0 0.5250
0 0 1 0 0 1 1 1.2625 0 1 0 0 1 1 1 1.0125 0 1 1 1 0 1 1 0.7625 1 0 0 1 1 1 1 0.5125
1 0 1 0 0 0 0 0.5000
Table 1 - reflects VID codes to be used in Active state. The voltages represent- Table 2 - reflects VID codes to be used for both Active and Deeper Sleep
ed cover HFM through LFM. states.

SC452
POWER MANAGEMENT
Table 3. DAC Slew Rate Control:
VID vs. VCC_CORE Voltage (Deeper Sleep/
Extended Deeper Sleep Dual Mode Region) The DAC has integrated slew-rate control with multiple
current settings to charge and discharge the soft-start ca-
pacitor. The slowest setting is used for soft-start, a medi-
VID VDAC VID VDAC
um setting for slow C4-exit (DPRSLVR=’1’, DPRSTP#=’1’)
6 5 4 3 2 1 0 V 6 5 4 3 2 1 0 V and a fast setting for all other VID transitions.
1 0 1 0 0 0 1 0.4875 1 0 1 1 0 1 0 0.3750
Power Supply Protection:
1 0 1 0 0 1 0 0.4750 1 0 1 1 0 1 1 0.3625
A UVLO circuit consists of a comparator that monitors the
1 0 1 0 0 1 1 0.4625 1 0 1 1 1 0 0 0.3500 input supply voltage level, 5V. The SC452 is in UVLO mode
IG ED
1 0 1 0 1 0 0 0.4500 1 0 1 1 1 0 1 0.3375
when its supply voltage has not ramped above the upper
threshold or has dropped below the lower threshold. The
1 0 1 0 1 0 1 0.4375 1 0 1 1 1 1 0 0.3250 output of the UVLO comparator, gated with the ENABLE
ES D
signal, turns on or off the internal bias, enables or dis-
N
1 0 1 0 1 1 0 0.4250 1 0 1 1 1 1 1 0.3125
D EN
able the SC452 output, and initiates or resets the soft-
1 0 1 0 1 1 1 0.4125 1 1 0 0 0 0 0 0.3000 start timer. If an UVLO occurs, a fault is set and SC452 is
disabled until the system has shut down (and reapplied
M
1 0 1 1 0 0 0 0.4000 1 1 1 1 1 1 1 OFF power), or the enable input signal to the SC452 has tog-
EW M
gled states.
1 0 1 1 0 0 1 0.3875
N O
R EC
Table 3 - reflects VID codes likely to represent Deeper Sleep and extended ver- The OVP circuit of SC452 monitors the processor core
sions of Deeper Sleep State.
VCC_CORE voltage for an over-voltage condition. If the FB
voltage is 200mV greater than the DAC-Droop (i.e., out of
FO T R
DAC Operation Below 0.3000V: the power good window), the SC452 will latch off and hold
the low-side driver on permanently. Either the Power or
The SC452 responds to DAC codes corresponding to EN must be recycled to clear the latch. The latch is dis-
O
voltage values below 0.3V by producing voltages less abled during soft-start and VID/DeeperSleep transitions.
N
than 0.3V; however, the tolerance of these signals is not For safety, the latch is enabled if the FB voltage exceeds
specified or guaranteed. In the case of the ‘111 1111’ 1.8V even during VID/DeeperSleep transitions.
VID code, the SC452 holds BGx and TGx low, preventing
switching from occurring. In addition, a ~50Ω FET con- The device will be disabled and latched off when the inter-
nected from VCORE to GND is turned on to prevent system nal junction temperature reaches approximately 160°C.
leakage from charging up the VCORE rail. Either the Power or EN must be recycled to clear the
latch.

SC452
POWER MANAGEMENT
Design Procedure
(Based on SC452 R2 calculation with DCR Droop and R-Droop
Method. In this design procedure, we are going to use the speci-
fications required by the Intel’s IMVP VI Napa Platform T&L (Yonah)
Processor):
Important requirements and design constants are de-

fined below:
3
3 3.1415926 , k 103, M 106, mil 10
12, 9, 6
p 10 n 10 P 10
20 V
IG ED
V INMAX
V INMIN 10 V
19 V
ES D
V INNOM
N

V HFM_NL
I LKGMAX
1.2875
1.6 A
V
D EN Figure 1 - Hysteretic Converter Response
M

to a Positive Transient
I HFM_FL 36 A
EW M
R IMVP 2.1
mV The first condition is easy to see; if the ESR is too high,
N O
A the transient response will fail.

VHFM_FL VHFM_NL RIMVP IHFM_FL
R EC
In the second condition, because the hysteretic converter

responds in < 100ns, the capacitor does not droop very
FO T R
The required droop per phase at full load is:

far before the inductor current starts ramping up. (This
VDP R IMVP IHFM_FL is not true of control schemes where time constants in
the error amplifier cause delays.) Once the inductor cur-
O
rent starts to rise, the increasing DV of the capacitor is

STEP 1: Output Inductor and Capacitor Selection
N
offset by reduced DV from the ESR, so DV is constant. If

the DV due to the charge taken from the capacitor be-
Output capacitance and ESR values are a function of
fore the inductor current reaches the load current (see
transient requirements and output inductor value. Fig-
the shaded area above) is less than VIMVP, then the
ure 1 illustrates the response of a hysteretic converter
transient response will pass.
to a positive transient: In a hysteretic converter with
adaptive voltage positioning, like the SC452, two condi-
Since HFM (High Frequency Mode) has the most severe
tions determine if you meet the positive transient re-
requirements, the other modes will be satisfied by a de-
quirements since there are no transient specifications
sign optimized for HFM. The maximum ESR requirement
in IMVP IV:
to meet the transient requirement is:
A : ESRMAX d RIMVP
C : ESRMAX RIMVP
B : VIMVP t deltaV C OUT

3
ESR MAX 2.1000 u 10 :

SC452
POWER MANAGEMENT
For the second condition, we need to know the inductor This value of inductance is required up to maximum load.
value, which is a function of the highest desired switching Inductors with a “swinging choke” characteristic, where the
frequency. The maximum frequency occurs at the high- zero current value of inductance is much less than the full
est input voltage. As a reasonable compromise between load current inductance can be used, as long as the above
efficiency and component size, a maximum switching restriction is met. Then, the worst-case (low input voltage)
frequency of 300kHz or less per phase is desired. Since response time (the time for the current to reach the new
we are analyzing the minimum inductance for one phase, transient value) is:
the ripple voltage will actually be twice the amount of the 1
specified output ripple, since the ripple voltage from each L1 IHFM_FL ILKGMAX
2
phase will tend to cancel. Please consult the data for your dT
specific processor. Note: The desired ripple amount comes VINMIN VHFM_NL
from Intel’s IMVP-6 Rev 0.5 specs.
IG ED
VHFM_NL 9
dMIN dT 927.8623 10 s
ES D
VINMAX
N
FS 250kHz
D EN Add ~200ns for the propagation delay from a change at
the output to the MOSFET switch turning on in reaction
due to the minimum on time requirement of the IC. Since
M
VRIPPLE 10m V the shaded area is triangular, the total charge taken out
EW M
of the capacitor = (dI / dt) / 2. Q = C / dV = (dI / dt) / 2,

The current share accuracy is achieved by Semtech’s pro- therefore;
N O
prietary Combi-Sense technology and no longer a function

R EC
of the current sense resistor values.

VINMAX VHFM_NL ESRMAX
D. LMIN 7
FO T R
dMIN
FS 2VRIPPLE F. C IHFM_FL ILKGMAX dT 2 10 sec
MINP
2 VDP
Ω
3
O
ESR MAX 2.1000 10

N
9 6
LMIN 361.3852 10 H CMINP 256.6036 10 F
Selected L = 470nH as the next closest value. Selected COUT = 330µF x 6 to meet transient requirements.
This condition applies only to the positive transient.
Load Step:
0.47 μH
Load Release:
L1
0.47 μH
The worst-case for the transient load release to happen is
L2 when one phase has just reached the maximum hysteresis,
(i.e., it has just turned off the high-side switch). At this point,
the second phase will be declining (approximately) through
the nominal voltage, (i.e., its low-side switch will be on).

SC452
POWER MANAGEMENT
J?
L1 Rcs1 Rcu1 IRIPPLE 13A
BG1 Rds_ON1
See STEP 6 for how to derive the ripple current.

36A
ESR_eq 1.6A
Rcu1_rt
R_LOAD
IHFM_FL IRIPPLE
It0_1
J? L2 Rcs2 Rcu2 Cout_eq
2 2
Rds_ON2
BG2
IHFM_FL
Rcu2_rt
It0_2
2
IG ED
0
It0_1 24.5000 10 A
ES D
0
Figure 2 - Load Release Behavior of Dual It0_2 18.0000 10 A
N
Phase Buck Converter
D EN COUT 330 10
6
F
M
Load is stepping from 36A to 1.6A:
6m Ω
EW M
VTRANS_MIN RIMVP IHFM_FL ILKGMAX 10 m V RESR

N O
R EC
VTRANS_MIN 0.082 V We assume for the worst-case condition, at t = 0, one in-

ductor is sitting at its maximum, while the other is sitting at
The diagram below shows the response of the converter. its nominal. After t = 0, both inductors discharge at a rate
FO T R
The control circuit quickly turns off TG and turns on both equal to VFL / L. (without the consideration of the secondary
bottom gates to discharge the inductors as quickly as order effect, such as, Rds_on drop, current sense resistor
possible. The stored energy, once losses in the ESR and
O
and miscellaneous trace drop).

FET RDS is subtracted, is transferred into the output ca-
N
pacitors. What happens in terms of energy: The energy released

TG1
from both inductors during load step down will be dissi-
pated through the following means:
BG1
VHFM_FL t
IL1 IL1 ( t) It0_1
L1
OA VHFM_FL t
IL2
IL2 ( t) It0_2
L2
OA t 0 50n s 10μ s
t= 0
ICAP ( t) IL1 ( t) IL2 ( t) ILKGMAX
Figure 3 - Waveforms of Figure 2

SC452
POWER MANAGEMENT
Since both inductors are discharging at the same time Using Panasonic SPCAP, specified as 330µF at 2.0V with
and the same rate, there are two terms contributing to the 6mΩ ESR, we see that 6 caps are sufficient for the ESR re-
increase of the voltage on the output capacitors. First is quirements, and also meet the capacitance requirement.
due to the ESR of the output capacitor. Second is due to
the added charge contributed by the inductor currents. STEP 2: Droop Calculation
RESR SC452 offers 2 droop methods: Method I — Current Sense

VESR ( t N) ICAP ( t) Resistor Droop, Method II — DCR Resistive Droop.
G: N 1
ICAP ( t) t
dVCAP ( t N) Method I: Current Sense Resistor Droop
H: COUT N 2
In an SC452 design, setting the IMVP gain is through the
IG ED
I: VTOTAL ( t N) VESR ( t N) dVCAP ( t N) use of the droop amplifier. This IMVP gain is used to meet
the IMVP load line specification.
ES D
The goal here is to use minimum amount of N x COUT to meet The IMVP load line is defined as the High Frequency Mode
N
the transient requirement, with some headroom to allow
for component tolerance. D EN at no-load voltage, minus the High Frequency Mode at
full-load voltage, divided by the maximum (High Frequency
M
Mode) load current. Since SC452 provides remote sens-
ing for the core voltage, we no longer need to adjust for
EW M
0.15
the trace loss at full load (such adjustment was needed
N O
for IMVP4 and 4+ core controllers, such as SC450 and

SC451).
R EC
0.1
V TRANS_MIN
6 V HFM_FL 1.195V
FO T R
V TOTAL t
0.05
V ESR t 6
0.5m Ω
dV CAP t 6
RCS1
O
0.5m Ω
N
RCS2
0.05
6 6 6 6 5
0 2 10 4 10 6 10 8 10 1 10
0.0000 10
0 t
10.0000 10
6 In order to provide the droop required by IMVP VI applica-
tion, we will use the Block Diagram on Page 11 to determine
the component values. The reference designators that
Figure 4 - Simulated (Load Release) are used in this worksheet are from the SC452 evaluation
Transient Response board schematic.

SC452
POWER MANAGEMENT
L2 R cs2
R c s = R c s1 || R cs 2 RCS1 RCS2
RCS
C ou t
L1 +V cc_co re
RCS1 RCS2
L -R
R cs1
VDP_CS RCS IHFM_FL

R 29 R 30
2.5 k Ω
2 .5k 2.5k
2.5 k Ω
R 37
0Ω
R29 R30
G ain = 1 0 V /V
R 35 DRP
We can calculate the value of R35 by using the equation
TBD
as follows:
R33
0Ω
IG ED
VDP_R35
C alculated a s
show n be lo w R35 R29 R30
VDP_CS VDP_R35
ES D
Figure 5 - Current Sense Resistive Droop Method
N
D EN
Since Rsense, R29, R30, R37 and R33 are pre-determined
to the values shown on the above diagram, we will need to
R35 26.2500 10 Ω
3
M
calculate the value of R35 to give us the correct droop.
EW M
Selected R35 = 26.5kΩ as the next closest value.

According to the IMVP-VI droop requirement:
N O
R EC
m V
R IMVP 2.1 METHOD II: DCR Droop Method
A
FO T R
L1
DRN1 L-R Rsense +Vcc_ core Cout
the required droop at full load is therefore, 0Ω

O
R28
3 R31
18.2kΩ
TH3
V DP 92. 4000 10 V 36.0 kΩ

33kΩ
N
Calculated C 60
R32 R37
from Step 10 39nF
Since the droop amplifier has a gain of 10V/V, the actual L2
47kΩ 0Ω
voltage appears across R35 is only VDP_R35: DRN2 L-R Rsense Gain = 10 V/V
0Ω R32
47kΩ
DRP
R35
V R36 TBD.
GDP_AMP 10 R34
18.2kΩ
TH4
V 36.0kΩ C61 33kΩ
39nF
R32
Calculated 47kΩ
R33
from Step 10
R32 0Ω
VDP 47kΩ
VDP_R35
GDP_AMP Droop Section of the SC452. R35 is the only variable
which is calculated as shown below
Since at full load, the voltage drop across the current sense Figure 6 - Inductive DCR Droop Method
resistor is VDP_CS.

SC452
POWER MANAGEMENT
Using Inductive DCR droop method will also require the The RC filter time constant is set by C60 and parallel
external compensation for the temperature coefficient combination of R31 and R28, TH3, R32 and R35.
of the DCR resistance. We will cover the entire thermal
design in STEP 10. Here we are only interested in deriv- In order to calculate R35 and C60, use the following
ing the correct value of the droop resistor R35. simplified diagram for Phase 1,
DC Voltage Between Two Terminals is:
To simplify the design process, here we will use the nomi- VDCR = ( I FULL_LOAD / 2 ) x RDCR
nal DCR resistance value published in the inductor L1 Rsense
vendor’s datasheet. L-R 0: +Vcc_core Cout
RDCR
As shown in Figure 6 (Page 23), by moving the regulation I FULL_LOAD / 2

Req = Parallel
point before the output inductor (at the DRN1 and DRN2 Combination of Resistors
shown in the box
node), droop becomes equal to the average voltage drop
IG ED
R32
47k:
across the output inductor’s DCR as well as any distrib- DRN1
uted resistance. The DCR droop is simply a RC low-pass TH3

33k:
ES D
Voltage
filter placed across the output inductor. This filter must Between these
two terminals is
C60 IR35 R35
TBD
Gain = 10 V/V
DRP_AMP
N
Droop
have the same time constant that the output inductor Veq
D EN
R28
18.2k: Requirement =
2.1mV/A
and its DCR have. If the DCR value of the inductor is R32
Droop
Requirement =
R31 47k:
0.21mV/A
very low, then care must be given to include any distrib-
M
36k:
Hence, V R35 = (0.21 mV/A) x Full Load Current
uted/parasitic impedances on the board. Second Phase Connects
Here With Identical
Component Values
EW M
In the SC452 evaluation design, this low pass filter is Considering One of the Two Phases of the SC452. The Second Phase Circuit will be exactly identical contributing the
N O
remaining 50% of the full load current
represented by combination of R31, R28, TH3, C60, R32

R EC
and R35 (for phase 1) and R34, R36, TH4, C61, R32
and R35 (for phase 2). For phase 1, resistor combina- Figure 7 - Inductive DCR Droop Method (Simplifed
tion R28, TH3 and R32, R35 are used to scale the mag- Diagram)
FO T R
nitude of the droop. The output of this low pass filter is

summed together with that of the phase 2 and then fed According to the IMVP VI droop requirement,:
mV
directly into the droop amplifier. The effects of this filter
R IMVP 2.1
O
on the frequency response is minimal and can be ignored.

N
A
3
92.4000 u 10
From Step 1 we have the inductor and DCR value as:
VDP V
9
L1 470.0000 u 10 H
Since the droop amplifier has a gain of 10V/V, the
9
actual voltage appears across R35 is only VR35
L2 470.0000 u 10 H
VR35
VDP
GDP_AMP
DCR: = 1.2 • m • Ω
10.0000 u 10
The time constant of the output inductor is given by, 0
GDP_AMP
W
L1
DCR
6
W 391.6667 u 10 s

SC452
POWER MANAGEMENT
Consider Phase 1 Consider Phase 2
Since
Sinceat fulldroop
the load, amplifi
the voltage drop
er has across
a gain ofthe DCR is
10V/V, the Since the components and current are identical for phase
VDCR,
actual voltage appears across R35 is only VR35 2 we get the same expression for voltage across R35,
VDP VR35_2 IR35_2 R35

VR35
GDP_AMP IR35_1 IR35_2 equal to IR35
IHFM_FL Total voltage across R35 is given as:

VDCR DCR
2
VR35 VR35_1 VR35_2
IG ED
We
R31can 16 k Ω the value of R35 as follows:
calculate
Substituting equations A,B,C, D, E, F, G into H and simplify-
ES D
ing we get the following final expression for R35:
•k•Ω
N
R
We31:can
16 calculate
D EN
the value of R35 as follows:
18.2 k Ω
M
R28 TH3 R28 2R32 TH3 R28 R31 2 R32 R31
EW M
R35_DCR
2 VDCR TH3 R28
33 k Ω
TH3 R28 R31
N O
TH3 VR35
R EC
47 k Ω
31.6633 10 Ω
R32
3
FO T R
R35_DCR
TH3 R28 R35 2R32 1

1 1 1
O
Req Rcombination
TH3 R28 R35 2R32 R32 R32 R35_DCR R31 R28 TH3
N
So,
11.1125 10 Ω
3
Rcombination
Req
Veq VDCR
Req R31
3
C60
Now, Rcombination
Veq 9
IR35 C60 35.2457 10 F
2 R32 R35
VR35_1 IR35_1 R35

SC452
POWER MANAGEMENT
We use the standard resistor value of 32K for R35 in the Cinput 66 μF
case of DCR droop method. For C60 and C61, we use
standard capacitor value of 7nF. 1
L in
2
STEP 3: Calculate Input RMS Current (for input capaci- 2 FS C input
tor selection)
In order to calculate the worst case input RMS current, the 9

L in 6.14 10 H
layout is important. If the input capacitors for both phases
are very close together, the following formula is accurate So effective is this that it takes less than 7nH to separate
and provides the lowest input capacitance. the phases from each other. This is about 1.5/inch of 250
mil wide trace. If the phases are separated, the following
IG ED
n 2
formula is more accurate:
ES D
VHFM_FL POUT PIN
IIN_DC
N
D PIN
VINMIN
D EN 85% VINMIN
M
POUT IHFM_FL VHFM_FL 0
IIN_DC 5.1328 10 A
EW M
N O
0
POUT 43.6284 10 W
R EC
2
I HFM_FL 2
I RMS2 n I IN_DC D n I IN_DC 1 D
The simplified expression is given as: n
FO T R
2
1 2 n 2 3 0
I RMS 2 9.2970 10 A
O
IRMS1 ( D) D IHFM_FL IRIPPLE ( D)

n 2
12 n D
N
IRMS1 7.93 A
Selection:
In this case, 6 x 22µF/25V POSCaps (1.5A ripple current CI_RMS_POSCAP 1.5A

--> 8 X 22µF/25V POSCaps
rating) are marginal. A seventh POScap is required if full (1.5A ripple current rating) (4 per phase).
load must be sustained indefinitely at VINMIN. Five 10µF/
25V/1210 (2A ripple current rating) ceramic capacitors CI RMS MLCC 2A --> 6 X 10µF/25V MLCC
will work down to VINMIN. (2A ripple current rating) (3 per phase).
If the input capacitors and high side FETs are separated by

a very short distance, the input capacitors and the board
inductance will form an LC filter. Surprisingly, little induc-
tance is required for the pole to be lower than the switching
frequency. In the case of using 6 x 22µF POSCaps, three
near each phase:

SC452
POWER MANAGEMENT
0.0012 Ω
STEP 4: Combi-Sense Component Values
Calculation R IND
VHFM_NL RIMVP IHFM_FL

Vin dNOM
Rds_on
Lout
VINNOM
Vout
PHASE
DCR
Ccombi RSENSE dNOM RHS_FET 1 dNOM RLS_FET RIND
VPN
Cout
Rcombi
Ω
3
RSENSE 3.7658 10
CS1P CS1N
L1 4
IG ED
Figure 8 - The Equivalent Circuit of 1.2481 10 s
Combi-Sense During On-Time R SENSE
ES D
Lout
In Figures 8 and 9 RCOMBI is the parallel combination of
N
D EN
Vout
R4 and R7. R4 is the gain setting resistor and R7 with R4
DCR
Ccombi sets RCOMBI.
VPN
M
Cout
Rcombi
10 Ω
Rds_on 3
EW M
R7 7.5
CS1P CS1N
N O
100 10 Ω
3
R4
R EC
Figure 9 - The Equivalent Circuit of Note: We assume R7 and R4 to be 7.5k and 100k respectively.
FO T R
Combi-Sense During Off-Time One can vary R4 to have desired gain and the signal for combi-
sense. If thermal compensation is required please refer Step
The equivalent combi-sense resistance is then given by the 10.
O
following
The equations:
equivalent Comb-Sense resistance is then given by 1
N
R COMBI
the following equations: 1 1
1.25 Ω
0.008 R7 R4
R HS_FE T ---> 2 X IRF7821 per phase @
2
6.9767 10 Ω
3
75°C, per datasheet effective Rds-on at 75°C is 1.25 x RCOMBI
8mΩ
L1
1.2 Ω
0.004
R LS _FET --->2 X IRF7832 per phase @ 75°C, CCOMBI
2 RSENSE R7
per datasheet effective Rds-on at 75°C is 1.2 x 4mΩ.
9
CCOMBI 16.6408 10 F
From the above calculation, we determined the values for

the Combi-Sense components: R7, R4, R23, R20, C8 and
C17 ----> where R7 = R23 = 7.5kΩ, 11.5KΩ R4 = R20 =
100KΩ C8 = C17 = 12nF.

SC452
POWER MANAGEMENT
STEP 5: Hysteresis (Frequency) Setting Using the Taylor Series we can expand the right hand
side.
The next step is to calculate the desired hysteresis voltage
level for a fixed switching frequency. Since SC452 is a If we consider only the first term of the Taylor series the
hysteretic converter with the benefits of Combi-Sense equation is greatly simplified with about a 20% error in
technology, the ripple for the hysteretic switching control is the final value. If first 3 terms are considered the equation
provided by the Combi-Sense current feedback. will give virtually zero error,
The ripple inputs are fed to a summer via a multiplexer Ton Vcombi ( Ton)
which is synchronized to the active phase with the select Vhys_low
Rcombi Ccombi Vin Vout
ouput. The hysteresis signal is added at the summer. The
hystersisis voltage is set directly by the resistor divider from
IG ED
the 2V REF output. Ton
Vcombi ( Ton) ( Vin Vout) Vhys_low
Rcombi Ccombi
ES D
From the circuit in Figure 8 on Page 27, we can write the
N
following equation for Combi-Sense operation during on
time (high side MOSFETs are on),
Vin Vout Vcombi ( t)
D EN
Rcombi Ccombi
dVcombi ( t)
For more accuracy we have to consider more than the
first term of the Taylor series for the hysteretic frequency
M
prediction.
dt
EW M
We can simplify the above equation as follows:

N O
The Feedback
1 1
R EC
dt dVcombi
Rcombi Ccombi Vin Vout Vcombi ( t( t) ) The feedback voltage essentially contains two components,
the voltage across the output capacitor and the voltage
FO T R
across the ESR of the output capacitor,

Since we are interested in the end point for this waveform
we simplify the equation with t = tON.
O
1
Vfb( t) i esr i dt
N
Cout
Hence, the solution for the above equation is:
Ton In the above equation, i is the output inductor current

ln [ ( Vin Vout) Vcombi ( t) ] Vini ripple defined by the equation below for on-time,
Rcombi Ccombi
In the above equation Vini is the initial value of voltage

Vin Vout
across the capacitor. Let us assume it to be equal to i( t) t
Vhys_low voltage. This is a fair assumption because of the 2Lout
architecture of the hysteretic comparator. We can rewrite
the above equation as follows:
Again we are interested in the end point where t = tON, so
the above equation simplifies to,
Ton
ln [ ( Vin Vout) Vcombi ( t) ] Vhys_low 2
Rcombi Ccombi Vin Vout 1 Ton
Vfb( Ton) Ton esr
2 Lout Cout 2

SC452
POWER MANAGEMENT
The Droop Example Showing Variation with VHYS_LOW Voltage:
The droop circuit is the simple inductor sense feedback for LOUT 0.47 μ H
the SC452 with a gain of 0.00021.
6
Vin Vout C OUT 330.0000 10 F
Vdrp( Ton) Ton 0.00021
2 Lout
COMBI RCOMBI CCOMBI
Equations 1, 2 and 3 can be used to obtain the final expres-

6
sion for the on-time for SC452 architechture. COMBI 116.0988 10 s
IG ED
0.0126 Ω
Final Expresssion
R calc 6 ESR MAX
2 Vcombi ( Ton) 10 Vdrp( Ton) Vfb( Ton) 12
ES D
N
following final result for tON, D EN
Substituting 1, 2 and 3 in the above equation we get the RCALC is a constant obtained from equation 4 above. It
enables better presentation of the solution of equation 4
M
as follows:
3 2 2 0.0252 6 e sr
EW M
To n To n
L ou t Co u t Rco mb i Cco mb i 2 L ou t L ou t d NOM
Fs V HYS_LO
N O
Ton V HYS_LO
R EC
2 Vhys_low 0 2
2L OUT COMBI R calc 2L OUT COMBI R calc 3
4 2V HYS _LO
FO T R
L OUT COMBI L OUT COMBI L OUT C OUT 6

Ton V HYS _LO
3
Since the converter is operating in continuous conduction 2
L OUT C OUT 6
mode we can write the expression for Frequency in terms
O
of tON only. Finding the expresssion for tOFF is a similar pro- 399.7341 10
3 4 10
5
cedure as we have for tON but for CCM mode

N
5
3.5 10
we need not care. 5

3 10
Where, 2.5 10
5
(Hz)
Fs V HYS _LO 5
2 10
D
Fs 1.5 10
5
Ton
5
1 10
4
Vout Iout Rdrop 5 10
D 3
Vin 46.8798 10 0
0.005 0.01 0.015 0.02 0.025 0.03 0.035
0.005 V HYS _LO 0.04
(V )
Figure 10 - Hysteresis Setting vs.

Switching Frequency

SC452
POWER MANAGEMENT
STEP 6: Current Limit Calculation In current limit, the voltage hysteretic converter is over-rid-
den by the current limit hysteretic comparator, and the TG
Setting the threshold for current limit is a relatively straight- pulse is terminated when the output of the current sense
forward process. To do this we must calculate the peak amplifier reaches the CL_hi threshold and BG terminated
current based on the maximum DC value plus the worst- at the CL_lo threshold. These thresholds are set from the
case ripple current. Because the SC452 has a current-limit CLSET resistor divider:
comparator for each phase, the following calculations apply
for a single phase. CL_hi 0.33 V( clset )
Worst-case ripple occurs at the highest input voltage. Since
CL_lo 0.20 V( clset )
ripple is also inversely proportional to inductance, it is rec-
ommended that the minimum inductance value be used Current limit pulses continue until 32 pulses after the volt-
IG ED
based on the manufacturer’s specified tolerance: age droops to the PWRGD low threshold; then the controller
latches off.
ES D
3 L T OL 20%
N
D EN
d MIN 64. 3750 10 ICLIM 28.1233A
Ω
3
RSENSE 3.7658 10
M
V INMAX V HFM_NL d MIN
I RIPPLE_MAX
Per phase current limit is set by ICLIM, Rsense (Combi-Sense),
EW M
L MIN F S
current sense amplifier gain in current limit mode and CL-
N O
SET gain, therefore the dual phase current limit is set by

0.3760 μH
R EC
LMIN the following equation:
V 1 V
GaCS_CL 2 GaCLSET
FO T R
I RIPP LE _MA X 13. 3333A

V 3 V
To calculate the maximum DC value of current we must
O
make an adjustment for the dynamic current-sharing tol- RSENSE ICLIM GaCS_CL
erance. We then add the maximum DC current and the VCLSET
N
GaCLSET
maximum ripple value to obtain peak current.
3
I_SHR TOL 5% ICC_MAX IHFM_FL VCLSET 635.4477 10 V
1 IRIPPLE_MAX
IPEAK ICC_MAX 1 I_SHR TOL We calculate R14 and R13 based on the VCLSET voltage,
2 2
100 10 Ω
3 VCLSET R14
IPEAK 25.5667A R14 R13
2V VCLSET
It is recommended that the current limit be set at 110%
of the peak value to allow for inductor current overshoot
R13 46568.2149Ω
during load transients:
ICLIM 1.10 IPEAK ICLIM 28.1233A We use 46.5K for R13 and 100K for R14.

SC452
POWER MANAGEMENT
STEP 7: OVP 1. Start-Up:
12 μ A
dV
No calculations are necessary for Over Voltage Protection. iSS_STARTUP iSS_STARTUP CSS
dt
The OVP circuit of SC452 monitors the processor core
Vcc_core voltage for an over-voltage condition. If the FB
dV VHFM_NL dt 3m s
voltage is 200mV greater than the DAC_Droop (i.e., out of
the powergood window), the SC452 will latch off and hold
iSS_STARTUP dt 9
the low-side driver on permanently. Either the Power or EN CSS CSS 27.9612 10 F
must be recycled to clear the latch. The latch is disabled dV
120 μ A
during soft-start and VID/DeeperSleep transitions. For
safety, the latch is enabled if the FB voltage exceeds 1.8V iSS_GVIII
even during VID/DeeperSleep transition.
IG ED
2. During GV-III Transition:
STEP 8: Thermal Protection
dV
ES D
iSS_GVIII CSS
SC452 will be disabled and latched off when the internal
N
dt
D EN
junction temperature reaches approximately 160°C. Either
the Power or EN must be recycled to clear this fault. Slew_Rate GVIII 3.2
mV
μ s
M
STEP 9: Soft-Start/DAC Slew Control dV
EW M
Slew_Rate GVIII
dt
N O
The soft-start cap C12 in the SC452 eval board design

serves two purposes: 1) define the soft-start ramp 2)
R EC
define the DAC slew rate during DeeperSleep and VID 3. During fast C4 exit:
transition. During VID/DeeperSleep transitions, the SS
1
FO T R
current is normally 120µA. During start-up, the SS current C S S_GVIII i S S_GVIII

is normally 12µA. Slew_Rate GVIII
9
O
Resistance of the node is set to provide a fixed gain of C S S_GVIII 37. 5000 10 F
10; as a result, only 0.21mW of resistance is required to
N
120 μ A
produce the Intel-defined load line of 2.1mV/A.
dV
iSS_C4E iSS_C4E CSS
According to Intel’s IMVP-VI Timing Requirements, the dt
maximum t_SFT_START_CC is specified at 3ms(max). And
the slew rate for CPU_UP due to, dV mV
μ s
Slew_Rate C4E Slew_Rate C4E 10
dt
1) GV-III VID change is 3.2mV/μsec
2) Deeper Sleep exit is specified at 10mV/μsec 1
C S S_C4 i S S_C4E
Slew_Rate C4E
We will be doing three soft-start exercises based on the

9
above three conditions: C S S_C 4 12. 0000 10 F
Taking into consideration of component tolerance, we use

Css = 10nF to meet all three requirements.
STEP 10: DCR Droop Thermal Compensation

Note: (contact your local Semtech Representative for details)

SC452
POWER MANAGEMENT
Component Manufacturer Series or Part Number
International Rectifier
IRF7821, IRF6602,
Fairchild Semiconductor
High Side MOSFET, HSFET SSC3002S,
Siliconix
Si4860DY,Si4410BDY
Infenion Technologies
Fairchild Semiconductor
Low Side MOSFET, LSFET Depends on Application
Siliconix
Infenion Technologies
Boost Capacitor, Cbst Various X5R or better
IG ED
Boost Diode, Dbst Various Schottky, 200mA or greater
ES D
N
Output Inductor, L Panasonic / NEC TOKIN 0.5μH
Decoupling Capacitors D EN
Various X5R or better
M
Current Sense Resistor IRC, Panasonic ERJ-M1WTJ
EW M
Output Bulk Capacitors Panasonic / NEC-TOKIN SPCAP 330μF, max ESR 6mΩ
N O
R EC
FO T R
Company Contact
Web: http://www.irf.com/product-info/
O
Phone: (310) 726-8000

N
Web: http://www.panasonic.com/pic/ecg/
Panasonic
Phone: (201) 348-7522
Web: http://www.irctt.com
IRC
Phone: (888) 472-4376
Web: http://www.kernet.com/
Kernet
Phone: (864) 963-6300
Web: http://www.sanyovideo.com/
Sanyo
Phone: (619) 661-6835
Web: http://www.component.tdk.com/components/components.html
TDK
Phone: (847) 390-4373
Web: http://www.vishay.com/brands/dale
Vishay/Dale
Phone: (402) 564-3131
Web: http://www.vishay.com/brands/siliconix
Vishay/Siliconix
Phone: (800) 554-5565

SC452
POWER MANAGEMENT
Typical Characteristics
High Frequency Line and Load Regulation Low Frequency Line and Load Regulation
VOUT = 1.2875V, IOUT = 0A to 36A (Spec bounds @ 25C) VOUT = 0.8375V, IOUT = 0A to 9.5A (Spec bounds @ 25C)
1.320 0.855
0.850
1.300
0.845
0.840
1.280
0.835 20Vin ( 40C)

20Vin ( 40C)
10Vin (-40C)
10Vin (-40C)
20Vin (25C)
1.260 20Vin (25C) 0.830 10Vin (25C)
10Vin (25C) V (V)
OUT
20Vin (125C)
V (V) 20Vin (125C)
OUT
0.825 10Vin (125C)
10Vin (125C)
Spec Nom.
1.240 Spec Nom.
Spec Min.
Spec Min. 0.820 Spec Max.
Spec Max.
0.815
1.220
0.810
IG ED
1.200
0.805
0.800
1.180 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 32.0 34.0 36.0
ES D
I (A)
OUT
I (A)
OUT
N
Deeper Sleep Line and Load Regulation
VOUT = 0.7625V, IOUT = 0A to 3.5A (Spec bounds @ 25C) D EN SC452 High Frequency Mode Output Power Efficiency
VOUT=1.2875V, IOUT=2A to 36A
M
0.780 95.0%
EW M
90.0%
0.775
N O
85.0%
0.770
80.0%
R EC
20V Input ( 40C)

0.765
10V Input (-40C) 20Vin ( 40C)
20V Input (25C) 75.0% 10Vin (-40C)
10V Input (25C) EFF (%) 20Vin (25C)
VOUT (V) 0.760 20V Input (125C) 10Vin (25C)
10V Input (125C) 70.0% 20Vin (125C)
Spec Nom.
FO T R
10Vin (125C)
Spec Min.
0.755
Spec Max.
65.0%
0.750
60.0%
O
0.745 55.0%
N
0.740 50.0%
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 32.0 34.0 36.0
I (A) I (A)
OUT OUT
SC452 Low Frequency Mode Output Power Efficiency SC452 Deeper Sleep (C4) Mode Output Power Efficiency
VOUT=0.8375V, IOUT=1A to 9.5A VOUT=0.7625V, IOUT=0.25A to 3.5A
95.0%
100.0%
90.0%
95.0%
85.0% 90.0%
80.0% 85.0%
20Vin ( 40C) 80.0% 20Vin ( 40C)

75.0% 10Vin (-40C) 10Vin (-40C)
EFF (%) 20Vin (25C) EFF (%) 20Vin (25C)
10Vin (25C) 75.0%
10Vin (25C)
70.0% 20Vin (125C) 20Vin (125C)
10Vin (125C) 10Vin (125C)
70.0%
65.0%
65.0%
60.0%
60.0%
55.0% 55.0%
50.0%
50.0%
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5
I (A)
I (A) OUT
OUT

SC452
POWER MANAGEMENT
Typical Characteristics (Cont.)
Phase 1 vs. Phase 2 Current Share Balance
(specified at IOUT > 50% load)
50.0%
45.0%
40.0%
35.0%
30.0% 20Vin -40C

10Vin -40C
20Vin 25C
EFF (%)
25.0% 10Vin 25C
20Vin 125C
10Vin 125C
20.0% 5% Limit
15.0%
10.0%
5.0%
IG ED
0.0%
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 32.0 34.0 36.0
IOUT (A)
ES D
N
D EN
M
EW M
N O
R EC
FO T R
O
N

SC452
POWER MANAGEMENT
Typical Characteristics (Cont.)
IG ED
ES D
N
D EN
M
EW M
N O
R EC
FO T R
O
N

SC452
POWER MANAGEMENT
Outline Drawing - MLP-44
A D B
DIMENSIONS
INCHES MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
A .031 - .040 0.80 - 1.00
A1 .000 - .002 0.00 - 0.05
A2 - (.008) - - (0.20) -
PIN 1 b
INDICATOR .007 .010 .012 0.18 0.25 0.30
E D .271 .275 .279 6.90 7.00 7.10
(LASER MARK)
D1 .197 .203 .207 5.00 5.15 5.25
E .271 .275 .279 6.90 7.00 7.10
E1 .197 .203 .207 5.00 5.15 5.25
l
e .020 BSC 0.50 BSC
IG ED
L .017 .021 .025 0.45 0.55 0.65
tia
N 44 44
aaa .003 0.08
bbb .004 0.10
A2
ES D
A SEATING
N
D EN
aaa C en PLANE
A1 C
D1
M
LxN
EW M
id
E/2
N O
R C
E1
nf O RE
2
1
F o
N
T
bxN
bbb C A B
O
e
C
NOTES: D/2
N
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

SC452
POWER MANAGEMENT
Land Pattern - MLP-44
DIMENSIONS
DIM INCHES MILLIMETERS
C (.268) (6.80)
G .228 5.80
(C) K Z H .207 5.25
G
K .207 5.25
P .021 0.50
IG ED
X .011 0.30
Y .039 1.00
Z .307 7.80
Y
ES D
N
D EN
X
P
M
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
EW M
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR

COMPANY'S MANUFACTURING GUIDELINES ARE MET.
N O
2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD

SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
R EC
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR

FUNCTIONAL PERFORMANCE OF THE DEVICE.
FO T R
O
N
Contact Information
Taiwan Branch Tel: 886-2-2748-3380 Semtech Switzerland GmbH Tel: 81-3-6408-0950
Fax: 886-2-2748-3390 Japan Branch Fax: 81-3-6408-0951
Korea Branch Tel: 82-2-527-4377 Semtech Limited (U.K.) Tel: 44-1794-527-600

Fax: 82-2-527-4376 Fax: 44-1794-527-601
Shanghai Office Tel: 86-21-6391-0830 Semtech France SARL Tel: 33-(0)169-28-22-00

Fax: 86-21-6391-0831 Fax: 33-(0)169-28-12-98
Semtech International AG is a wholly-owned subsidiary of Semtech Germany GmbH Tel: 49-(0)8161-140-123

Semtech Corporation, which has its headquarters in the Fax: 49-(0)8161-140-124
U.S.A.
www.semtech.com

SC452 Dual Phase Single Chip IMVP 6 Vcor

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SC452 Dual Phase Single Chip IMVP 6 Vcor

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NOT RECOMMENDED FOR NEW DESIGN SC452

Dual-Phase Single Chip

Hysteretic operation adaptively reduces the SC452

switching frequency at light loads. Combined with an

automatic “power-save” mode which prevents negative

A 7-bit DAC, accurate to 0.85%, sets the output voltage

February 22, 2006 1 www.semtech.com

NOT RECOMMENDED FOR NEW DESIGN

VID3 VID3 10nF 10pF

VCC SENSE R13 10 FB+

Parameter Condition Min Max Units

Supply Voltages VCCA V5_1, V5_2 -0.3 6.5 V

BST1, BST2 to DRN1, DRN2 -0.3 6 V

DRN1, DRN2 to PGND Static -2 25 V

VPN1, VPN2 to PGND

All other pins to AGND -0.3 VCCA+0.3 V

Thermal Resistance Junction to Ambient θJA 29

ESD Rating (Human Body Model) VESD 2 kV

Parameter Condition Min Typ Max Units

Supplies (VccA, V5_1, V5_2)

VBAT Operating Range 4.5 24 V

VccA, V5_2 UVLO Rising 4.25 4.4 4.5 V

Hysteresis Falling 50 150 250 mV

VccA Current Disabled 10 μA

In UVLO 0.6 1.0 mA

© 2006 Semtech Corp. 3 United States Patent No. 6,441,597

Supplies (VccA, V5_1, V5_2) (Cont.)

VccA Operating Current Operating (Deeper Sleep) 8 12 mA

V5_1 Current Disabled 10 μA

Operating, Static, TG1 Low 0.3 0.9 1.2 mA

V5_2 Current Disabled 10 μA

In ULVO 120 200 μA

Enable Threshold 0.8 2.0 V

VID[6:0], DRPSLP, DPRSTP, PSI#

DAC Error + Internal Offset 1.5000V - 0.7625V -0.85 +0.85 %

DAC Sink/Source Ability 0.3V < DAC <1.5V |50| μA

SS Slew Current Start-Up 8 12 16 μA

Operating 102 120 138 μA

Slow DPRSLP Exit

Discharge (SS = 0.5V) 15 mA

SS Discharge Threshold 50 100 mV

Boot Voltage 1.176 1.2 1.224 V

Boot Delay(1) 10 30 100 us

VREF Accuracy 1.97 2.00 2.03 V

VREF Sink/Source Ability |1.5| mA

© 2006 Semtech Corp. 4 United States Patent No. 6,441,597

Remote Sense (FB+, FB-)

Droop (DRP+, DRP-)

Input Bias Current ±1 μA

Gain DRP+ = 1.5V, DRP- = 1.48V 9.5 10 10.5 V/V

Droop Input Offset (25°C only) -0.4 0 0.4 mV

Error Amplifier (ERROUT)

Current Sensing (CS1+, CS1-, CS2+, CS2-, ISH)

CS1, 2 + CS1, 2 Bias Currents CS+ = CS- = 1.5V ±1 μA

CS Gain for Switchingg 2.7

Maximum Input Signal(1) 450 mV

Zero-Crossing Detector Offset -6 6 mV

Low Pass Filter Corner

© 2006 Semtech Corp. 5 United States Patent No. 6,441,597

Current Sensing (CS1+, CS1-, CS2+, CS2-, ISH) (Cont.)