Application note

1903
JULY 2006

Advanced IGBT Driver

APPLICATION MANUAL

Alain Calmels
Product Engineer (Power Modules)
Microsemi® Power Module Products
33700 Merignac, France

Introduction -Optimize turn-on and turn-off

operation for switching losses
To simplify the design of high power, high reduction by selecting the appropriate
performance applications, MICROSEMI gate resistances (RG(on) , RG(off)).
introduced a new advanced Dual IGBT -Prevent cross conduction by the
Driver. input signal dead time calculation.
Dedicated to drive high Power IGBT -Eliminate gate rigging in case of
modules (up to 300A, 1200V, 50 kHz) in paralleled IGBT modules operation.
phase leg operation (as shown on Fig. 1), -Understand the short circuit
this circuit provides multiple functions to protection operation including fault
optimize IGBT performance. output and reset in case of short
This application note describes some circuit detection.
techniques to: -Explain mounting procedure.
-Verify the driver capacity by the
total gate charge calculation.
+5VDigital
DUAL DRIVER CIRCUIT VC1
+VBUS
V1
IN1
SHORTCIRCUIT
1nF PROTECT
1K

BUFFER FAULT VCEsat

Memorisation 2R 5W
0V1 Gon1 0VBUS

IN2 Goff1
GND HIGH
+5V TOP 0V1
0.5R 5W POW ER
IGBT
DRIVER
1K

BUFFER
0V1
CIRCUIT 1R 10W
1nF

BUFFER LOGIC
2.7K

SOFT TURN OFF

And And
P WM G ENERAT O R

INTERLOCK UVLO
-V1
RESET
GND DRIVE VC2 OUT
+5VDigital
V2
2.7K

FAULT SHORTCIRCUIT
Memorisation PROTECT
FAULT 2R 5W
OUT
VCEsat 0V2 Gon2
BUFFER 1nF
1nF

Goff2
GND 1K
0.5R 5W
BOTTOM 0V2
0V2
HIGH
POW ER
GND GND +5V DRIVER
+15V IGBT
1R 10W
S UPPLY (1A)

+ +

47MF ISOLATED DC/DC

15V AUX.

SOFT TURN OFF

CONVERTERS And
UVLO
-V2
0/15V
GND
0VBUS

Figure 1 Typical Phase Leg Operation

Description: Due to the compact design, this circuit is

Among other functions, this high speed easy to mount on a PC board close to the
circuit integrates galvanic isolation of logic power module in order to minimize parasitic
level inputs signals, positive and negative elements.
isolated auxiliary power supplies and short Isolated screw-on spacers guarantee good
circuit protection by VCE(sat) monitoring. vibration withstand capability.

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 Application note
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JULY 2006

Pin Description
Sym bol Function D escription
+15V Supply V oltage Positive power-supply voltage Input. All internal Aux. Power supplies
are made from this V oltage including isolated secondary supplies.
T he range of this voltage is 14.5V to 15.5V ( decoupling capacitor required)
0/15V Power G round Internally connected to the G N D pin and the primary ground plane,
T his pin must be connected to the Supply voltage Reference
H1 Channel 1 Input Channel 1 Input signal has a Schmitt T rigger Characteristics to provide improved
signal noise immunity. Logic H igh (5V ) turn-on the IG B T
In addition Low impedance ( typical 1K and 1nF) guarantees good noise immunity
A parallel 5V zener diode increase the Electrostatic D ischarge Protection
H2 Channel 2 Input Channel 2 Input signal has a Schmitt T rigger Characteristics to provide improved
signal noise immunity. Logic H igh (5V ) turn-on the IG B T
In addition Low impedance ( typical 1K and 1nF) guarantees good noise immunity
A parallel 5V zener diode increase the Electrostatic D ischarge Protection
Reset Fault Reset Input A logic H igh input for at least 20µ s, resets fault output high and enable
O utputs 1 and 2 to follow the respective Input level
FAU LT OU T Fault O utput Fault change from H igh Logic level ( 2,7K connected to +5V internal)
to a logic Low following the voltage on V C1 or V C2 exceed 6.3V .
Channel 1 and Channel 2 Fault outputs are open collectors connected together
in a "wire O R" forming a single FAU LT O U T pin.
GND Input Signal Ground D igital input ground pin should be connected to the low noise ground
plane for optimum performances.

V C1 Collector D esat Channel 1 D esaturation V oltage Input.W hen the voltage on V C1 exceeds 6.3V while
the IG B T is O N , FAU LT O U T is changed from 5V to a Logic Low State
and T urn-off the IG B T until Reset is brought hight
G on1 T urn-on G ate O utput 1 Separate T urn-on and T urn-off gate D rive O utputs in order to Set T urn-on and
T urn-off switching speed independently from each other.
G off1 T urn-off G ate O utput 1 T hose pins are connected through a resistor to the gate of IG BT
with short wire length ( see "G ate resistors calculation")
0V 1 Common O utput T his pin is directly connected to the Emetter of the IG BT or throught a resistor
Supply V oltage to minimize G ate ringing in case of paralleling operations
0V 2 Common O utput T his pin is directly connected to the Emetter of the IG BT or throught a resistor
Supply V oltage to minimize G ate ringing in case of paralleling operations
G off2 T urn-off G ate O utput 2 Separate T urn-on and T urn-off gate D rive O utput in order to Set T urn-on and
T urn-off switching speed independently from each other.
G on2 T urn-on G ate O utput 2 T hose pins are connected through a resistor to the gate of IG BT
with short wire length ( see "G ate Resistors Calculation" )
V C2 Collector D esat Channel 2 D esaturation V oltage Input.W hen the voltage on V C2 exceeds 6.3V while
the IG B T is O N , FAU LT O U T is changed from 5V to a Logic Low State
and T urn off the IG BT until Reset is brought hight

Table 1 Pin Function and Description - Separate sink & Source outputs for turn-on
and turn-off switching optimisation.
Features: - Single VDD=15V supply required.
- Common mode rejection higher than 10 - Secondary auxiliary power supplies under
kV/µs for very high noise immunity. voltage lockout with hysteresis.
- 2500V galvanic isolation between primary The +15V bias voltage ensures low IGBT
and secondary and between the two saturation voltage while the –5V guarantees
secondary. fast turn-off and good noise immunity, even
- 5V logic level with Schmidt trigger input. in an electrically noisy environnement.
- Low speed over current cut off (coupled
with short circuit protection) to limit over
voltage.

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 Application note
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switching frequency, the higher the driver

consumption is.
1- Drive Power Calculation This effective gate capacitor may be
calculated by the relation:
To determine if the IGBT driver is well
suited for the application the main parameter
Qg
C
(@ 15V )
= with VGE=15V
is the total gate charge of the IGBT (Qg).
Most of power semiconductor data sheet
EFF
V GE
Application:
specify the IGBT total gate charge with the The Total Gate charge Curve ( see
corresponding gate voltage applied. APTGF300A120 data sheet for example)
gives a Qg of 2200µC @ VGE=15V.
In this application note we will also examine By the formula the effective capacitor can
some simple methods to determine the Total be calculated:
Gate charge.
CEFF = 146 nF.
1-1 Effective Gate Capacitor
Determination So the “Frequency vs. Effective Gate
Capacitance” curve (see Fig. 2) allows
During each turn-on and turn off operation verifying if the driver is well suited to the
the driver must charge and discharge the application. In our example, the frequency at
effective gate capacitor, so the higher the 25°C is close to 40 kHz.
Frequency Vs Gate effective Capacitor
110
100

90
Tamb=25°C
80
Tamb=70°C
70
F RQ (Khz)

60

50
40
30
20

10
0
0 25 50 75 100 125 150 175 200 225 250 275 300
CEFF (nF)

Figure 2 Switching Frequency vs. Effective Gate Capacitance

The driving power per channel and the

consumption in the primary auxiliary power (Normally the power necessary to charge a
supply are: capacitor is ½ CV2f, but in this case, during
a switching period the driver must charge
and discharge the effective capacitance,
(W ) = C EFF × ( ∆V Gate) × F RQ
2
P perchannel resulting in twice the power).

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 Application note
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The maximum steady state power

1-2 Example of phase leg dissipation of the driver is close to 1.2W
operation (due to biasing the device).
So the total primary power consumption
The total amplitude generated by the IGBT (gate driver supply voltage=15V) is:
driver is 20V (15V positive, -5V negative).
So the power per channel at 40 kHz and PTOTAL(primary) =7.2W
146nF is: @ Frq=40 kHz and CEFF=146nF
P = 2.3W
Additional losses like gate driver’s DC/DC The maximum switching frequency is also
converter efficiency must also be added (it dependent on the ambient temperature.
represents around 30% of total losses). The following Figure 3 “Switching
Frequency vs. Ambient Temperature” gives
the derating to observe.

Maximum
Switching Frequency Vs Ambiant Temperature
60
APTGF300A120(Ceff=150nF)
PHASE LEG OPERATION
50

40
Absolute
Frq (KHz)

Max. Rating
30
Typical

20

10

0
-50 -25 0 25 50 75 85 100
Tamb (°C)

Figure 3 Switching Frequency vs. Ambient Temperature

1-3 Total gate Charge

Measurement And
Qg ( nC ) = C EFF ( nF ) × VoltageRise(V )
- In general the effective capacitance (CEFF)
is close to the input capacitance value (Cies)
The difference is more particularly due the
increased by a factor 5.
the Miller plateau effect (as shown in Fig. 4)
C EFF
≅ 5 × C ies corresponding to the flat portion of the
curve.

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 Application note
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1-4 Measurement methodology

16
If a more accurate value is needed, the
VDRV following method based on the Gate current
14
measurement is very simple (see Fig. 5).
Important: The gate charge is increasing
VGS, Gate-To-Source Voltage (V)

12
with the IGBT Collector voltage amplitude.
So it is important to apply the same collector
10
Miller Plateau voltage as in the final application.
VCE

8
A digital oscilloscope combined with
“Integral” math function analysis on the
6
Gate current waveform gives the gate charge
value by the formula:
4 Q = idt

2
The measurement gives: Q = 2400nAs
QG
Q
0
C EFF
=
20
= 120nF
Qg, Total Gate Charge (nC) By comparison, the total gate charge for VGE
Figure 4 Typical Gate Charge Curves = 0 to 15V is:
Q G
@ 15V = 1800nC

G a t e C h a r g e M e a s u r e m e n t (n A s )

∆
-0V -

-0nAs-

-0A-

T im e ( 1 µ S / D iv )

Figure 5 Gate Charge Measurement

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 Application note
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JULY 2006

Turn-on speed of an IGBT can be increased

2- Gate Resistors Calculation only up to a level compatible with the
reverse recovery of a free wheeling rectifier.
The choice of the turn-on and turn-off gate Too fast turn-on could also cause
resistors is critical in order to optimise the oscillations in the collector current. On the
IGBT switching losses without exceeding other hand, turn-off time must be as short as
the current capability of the driver. possible to reduce power loss.
For theses reasons (and others like EMI
The typical values of Ron and Roff are limitation), the APTRG8A120 integrates
given in Table 2, “Typical External Gon and Goff output connections in order to
Components Values”. adjust separately the Ron and Roff gate
resistors.
Typical External Components Values
APT - Modul Technology Ron Roff Total gate charge Frequency up to R return Additional
SP6 package IGBT (ohms) (ohms) (nC) @15V (Khz) ** (ohms) Diode *
600V
APTGF350A60 NPT 6.8 6.8 1320 50 0
APTGT300A60 Trench/Fieldstop 4.7 4.7 2150 20 0
APTGT600A60 Trench/Fieldstop 2.2 2.2 4300 10 0

1200V
APTGF150A120 NPT 10 10 850 50 0
APTGT150A120 Trench/Fieldstop 10 10 700 20 0
APTGT200A120 Trench/Fieldstop 6.8 6.8 950 20 0
APTGF300A120 NPT 3.9 3.9 2250 25 0
APTGT400A120 Trench/Fieldstop 3.3 3.3 1850 20 0

1700V
APTGT150A170 Trench/Fieldstop 6.8 6.8 850 20 0 X
APTGT300A170 Trench/Fieldstop 3.3 3.3 1700 20 0 X

Caution : A dead time must be observed between H1 and H2 input signals ( see" dead time" Chapter)
* : This external diode ( STTH112U from STM for example) must be connected between VC pins and
IGBT collector to increase voltage capability
** : due to the driver and/or the power module switching frequency limitation ( Tamb = 85°C, Tcase module = 80°C)

Table 2 Typical External Component Values ∆VG 20

RG = = = 2.5Ω
2-1 Gate resistors Minimum
ON min
I PEAKon
8
Value Calculation
∆VG 20
A minimum gate resistor value must be RG = = = 1.33Ω
observed to avoid IGBT Driver damage.
OFF min
I PEAKoff
15
The peak current is limited at 8A during In fact the IGBT gate model integrates a
turn-on and 15A during turn-off. series resistance, so in practice:
To calculate the minimum “ON” and “OFF”
gate resistors (see Fig. 6 and Fig. 7), it RGONmin=2
should be considered that the APTRG8A120
is turned-on at +15V and turned-off at –5V And RGOFFmin=1
therefore the gate voltage amplitude is 20V
during every switching procedure.

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 Application note
1903
JULY 2006

Also the wire length between the driver and

the power module must be as short as
possible.
Parasitic elements in the drive loop (like
emitter inductance) clearly alter the
performance. In general IGBT power
modules integrate a Kelvin emitter sense
terminal to minimize this drive loop effect.

3- Dead Time and Drive Interlock

In case of phase leg operation, a dead

time must be applied between the two
Figure 6 Turn-On Operation input signals (H1 and H2) to ensure the
complete turn-off of the active IGBT
switch before turn-on of the opposite
switch.
If not, then short cross conductions
appear which increase the losses and
may destroy the IGBTs. Generally those
cross conductions are short enough to
disappear before the end of the necessary
VCE(sat) detection blanking time, so the
short circuit protection will not be
activated.

Figure 7 Turn-Off Operation 3-1 Minimum dead Time

Calculation
2-2 Gate Resistors Power
Determination The dead time is the difference between
the maximum total turn-off delay time
and minimum total turn-on delay time
(see Fig. 8 and Fig. 9 “Tdon and Tdoff
Note that most of the drive losses are measurements”).
dissipated in the external gate resistors This includes driver, gate resistors and
independently of the resistors values. IGBT delay times.
In the previous example (primary power
Note that the driver data sheet gives the
consumption calculation in phase leg
operation) the Ron and Roff power will be: “Propagation Delay Difference Between
P=2.3/2 = 1.15 W any Two Drivers” (PDD) which
In order to have good safety margin we simplifies this calculation.
propose:
Rgon, Rgoff = PR02 series (2W
metal layer)
Low inductance metal layer resistors are
recommended.

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 Application note
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So the equation of the Minimum dead time becomes (ns):

DTmin= (RGoff.Cies(max)log2+TdoffIGBT+Toff)
-(RGon.Cies(min)log2+TdonIGBT+Ton)+PDD
3-2 APTGF300A120 Calculation
With Example
Cies = Input Capacitance
Rgoff = Turn-off gate resistor With Rgon=Rgoff= 2R and RE (emitter
Rgon= Turn-on gate resistor resistor) = 0R

DTmin (nS) = (41 + 500 + 30) – (30 +

Dead Time Calculation
- 5V -
90%
70 + 50) + 350 = 771 ns
1
1 - H (Input Driver Signal)
2 - Output Collector Current (A)
Recommended Dead Time: 1µs
-0-
2
3-3 Drive Interlock
This function prevents two IGBT’s in
the same leg from being turned on at the
10%
same time as shown in Table 3,
“Operation Table”.
-0-
TOTAL TDON
4- Suppression of gate ringing by R
Figure 8 Total Tdon Measurement for Dead return
Time Calculation

90% Dead Time Calculation When IGBT module paralleling is necessary

- 5V - it is best to use a common gate drive.
Using different driver circuits introduces
additional variation in turn-on and turn-off
1
time and possible imbalance between each
-0- power module.
1 - H (Input Driver Signal)
To avoid gate ringing during the switching
2 - Output Collector Current transient (collector voltage transition), an
2 additional resistor may be connected
10% between emitter sense connection and the
-0-
common supply (0V) of the driver.
TOTAL TDOFF

Figure 9 Total Tdoff Measurement for Dead

Time Calculation

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 Application note
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Operation Table
Inputs Secondary UVLO Desat Condition Detected
H1 H2 Channel 1 Channel 2 Channel 1 Channel 2 Reset Fault Output OUT G1 OUT G2
Low Low X X X X Not Active High Low Low
High Low X X X X Not Active High High Low
Low High X X X X Not Active High Low High
High High X X X X Not Active High Low/High * High/Low *
X X Active X X X Not active High Low X
X X X Active X X Not active High X Low
X X X X Yes X Low Low ** Low ** X
X X X X X Yes Low Low ** X Low**
X X X X Yes X High High** X X
X X X X X Yes High High** X X

* : in all of the cases only one of the two outputs may be High at the same time, generally the first
channel high will keep hight Output level but un case of sychonise input signal the reponse
time of each internal component will determind the high level channel and could not be garanty.
** : The fault condition is memorized until Reset input is brought low, then a logic hight for at least
20µS reset fault output and enable Inputs. A period of time ( 100 mS minimum) must be observe between
each reset pulse in order to avoid the destruction of Power IGBT by over heating.
Table 3 Operation Table In case of discrete semiconductors never
forget that parasitic elements like
This additional “return” resistor inductance in the drive loop clearly alter
combined with the traditional gate the circuit performance and will increase
resistor permits driving each power switching losses.
device gate input in a differential mode
that helps to eliminate the effects of Note that separate distributed resistors
possible oscillations (see Fig. 10, (Ron, Roff and Rreturn) must be
“Paralleling of Power Modules Block matched for best synchronization.
Diagram”). A bi-directional tranzorb should also be
added to protect the IGBT gate from
Generally the power modules integrate over voltage spikes (Z1, Z2 in Fig. 10).
emitter sense connections that reduce the
driving loop effects.

Figure 10 Paralleling of Power Module Block Diagram

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 Application note
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5- Protections corresponding driver output is slowly

turned off as shown in Fig. 11 and the
5-1 Short circuit protection by fault output immediately activated. The
VCEsat monitoring fault conditions are stored until a logic
high signal for at least 20µs is applied to
Each driver provides a short circuit the reset input.
protection by VCEsat monitoring. The total driver reaction time in case of
If the drive senses that the voltage across short circuit is 5µs, with a short circuit
the IGBT (at ON state only and from the duration that will not exceed 6µs.
VC pins) is greater than 6.3V, the short
circuit conditions has been detected, the

Figure 11 Short Circuit Protection Operation the IGBT breakdown voltage (BVCES)
like the Vc pins maximum voltage
The fault outputs of each channel are (1200V).
connected together in a “Wired OR”
forming a single fault output pin. This is See Fig. 1 “Phase Leg Operation Block
an open collector with an integrated pull Diagram”.
up resistor of 2.7K.
The other side of this pull up resistor is Note that in normal operation (no fault)
connected to the internal 5V supply. the reset input may be high or low
without any action inside the driver.
In order to increase the immunity it is A period of 100ms must be considered
recommended to add an external pull-up as a minimum between each reset signal
resistor close to the digital components. to prevent the destruction of the IGBT
Due to the switching over-voltage spikes by over heating.
(in spite of decoupling capacitors) or
following a short circuit (in spite of slow
turn-off) a safety margin must be
observed between the VBUS voltage and

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 Application note
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6- Mounting Instructions
For 1700V applications an additional
fast diode (STTH112U from STM for The IGBT driver is dedicated to be mounted
example) must be connected between the on a PC Board and fixed with 4x M3 screws
Vc pins and the IGBT collector. in order to increase the vibration withstand
capability.
The recommended diameters for drill holes
5-2 Secondary Auxiliary power
are 1 mm for the 18x 0.6mm square @2.54
supplies under voltage
mm raster gold plated connectors.
To minimize parasitic elements, the driver
The APTRG8A120 under-voltage
and other external components must be as
lockout (UVLO) feature is designed to close as possible to the IGBT Power
prevent against insufficient IGBT gate module.
voltage. For this reason the PC Board will be fixed
The IGBT saturation voltage is increased on the same support as the module (the heat
significantly when the gate voltage sink generally).
amplitude is under 13V and dramatically See Fig. 12 “Recommended Layout and
when below 11V. Mounting”.
In this case the conduction losses are so In the case of SP6 power module, keep a
important that they may damage the distance of at least 5cm between the 2.8mm
IGBT by over heating. fast-on connectors and the spacer, which
supports the PCB, to avoid mechanical
The UVLO will turn off the output if the
stress.
secondary power supply voltage falls See “SP6 Mounting Instructions”
below 12.3V (typical) with a hysteresis application note APT0601.
of 0.4V minimum to prevent erratic Note that the screw-on spacers are totally
operation. isolated from the rest of the circuit and are
also isolated from each other.

Figure 12 Recommended Layout and Mounting

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 Application note
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The parameters can be summarized by

Conclusion the following checklist:
-Total Gate charge (Qg)
The APTRG8A120 Drivers Circuit -Input capacitance (CIES)
simplifies the power systems design by -Turn-on and Turn-off delay times
offering most of the functions necessary (Tdon, Tdoff)
to set up and protect power IGBTs. -Turn-on and Turn-off times (Ton,
This application note describes how to Toff)
use this circuit to obtain the best -Breakdown Voltage (BVCES)
performance. -Maximum switching Frequency
We also demonstrate that IGBT (Frq )
operating parameters must be considered
to design a reliable power system.

References
1
Ralph McArthur “Making Use of Gate Charge Information in MOSFET and IGBT Data
Sheets” Application Note APT0103 Advanced Power Technology.
2
“Use Gate Charge to Design the Gate Drive Circuit” AN944 International Rectifier
3
Jonathan Dodge, P.E., John Hess “IGBT Tutorial” Application note APT0201
Advanced Power Technology.
4
Serge Bontemps Product Manager “Parallel Connection of IGBT and MOSFET Power
Modules” Application Note APT0405 Advanced Power Technology.

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