La-L241pr10 Warlock TGL Uma 041

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : Warlock TGL
PCB NO : DA6002E0000
TGL-U+MEC1515
1
PCB 2X2 LA-L241P REV0 M/B 1 S (UMA) - Realtek Codec 1
2021-04-07
TGL CPU QS TGL CPU Base-U REV : 1.0 (A00)
A
UC1 UC1
SA0000DRS1L SA0000DXG2L
QS_I3@ PENTIUM@
@ : Un-pop Component
S IC A31 FH8069004531502 QVBG B1 3G S S IC A31 FH8069004531802 QVBK B1 2G S UMA@ : not Support external Graphic card
rn
UC1
SA0000DRR1L UC1
SA0000DXH2L
N3@/V3@ : Inspiron/Vostro
QS_I5@ MSFT@/NMSFT@ : MSFT SKU / Normal SKU
tu
CELERON@
S IC A31 FH8069004530601 QVBD B1 2.4G S
S IC A31 FH8069004531901 QVBS B1 1.8G S
G3@ : Support G3 sharing SPI topology
UC1
SA0000DRG1L
CNV@ : Support CNVi function
TGL CPU R3 S5LID@/LID@ : Support S5 LID power up Function/Normal LID close
ck
2 2
QS_I7@
S IC A31 FH8069004529905 QVBA B1 2.8G S
UC1
SA0000DTV2L
ES_I3@/ES_I5A@/ES_I5B@/QS_I7@ : TGL-U QS Sample
R3_I3@
STG@ : C10_gate control VCCSTG
I2CTCH@/USBTCH@ : Touch Screen support I2C signal / USB signal
lo
S IC FH8069004531602 SRK08 B1 3G A31 !
UC1
BASE@/PREM@ : Pentium,Celeron/i3,i5,i7
SA0000E4U3L I2CPAD@/PS2PAD@ : EC use I2C touch PAD signal(or PS2)
ar
R3_I34C@ JP@/JUMP@/PJP@ : JUMP
S IC FH8069004531606 SRK8S B1 2G A31!
100@/1000@ : 10/100 LAN / Giga-LAN
W
UC1
PRO@/ICPRO@ : only LCDVDD protection/Hinge up protection Support
SA0000DTU2L
EMI@/ESD@/RF@ : EMI, ESD and RF Component
R3_I5@
S IC FH8069004531301 SRK05 B1 2.4G A31 !
@EMI@/@ESD@/@RF@ : EMI, ESD and RF Un-POP Component
3
UC1
SA0000DTT2L
1P
CMC@ : XDP Component
CONN@ : Connector Component
KBBL@ : KB Backlight
3
R3_I7@
24
S IC FH8069004530104 SRK02 B1 2.8G A31 ! TPM@/NTPM@ : HW TPM/SW TPM
750_CTPM@ : 750 and china TPM
CTPM@/ST_CTPM@ : China TPM/ST China TPM
-L
FFS@ : Free Fall Sensor

TYPEC@/NTYPEC@ : Support TypeC/non-TypeC
TYPEC@EMI@/TYPEC@ESD@: EMI, ESD ,TypeC Component
LA
LBIST@/LBIST@RF@ : LBIST for LCD monitor

Layout Dell logo TP@/CMC@TP@ : Test Point/XDP Test Point
DISPCB@/UMAPCB@ : PCB MB
4 4
COPYRIGHT 2014
Security Classification
2018/04/01
Compal Secret Data
2019/04/01 Title
Compal Electronics, Inc.
ALL RIGHT RESERVED Issued Date Deciphered Date
REV: X01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
PWB: 9HTP8 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L241P
Date: Tuesday, April 13, 2021 Sheet 1 of 121
A B C D E
A B C D E
Block Diagram
DDR4
SODIMM A
DDR4 3200MHz Channel A
1 P23 1
DDR4
SODIMM B
DDR4 3200MHz Channel B
P24
USB2.0 x 1
Port 1 (USB3.0 Type-A)
USB3.0 x 1 Gen1
eDP connector eDP 1.2 Intel CPU P71
A
P38 TGL Lake-U 4+2
USB2.0 x 1
HDMI connector , 1.4b DDI x 4 Port 3 (USB3.0 Type-A)
P40 USB3.0 x 1 Gen1
P71
rn
15W USB2.0 x 1 Port 2 (USB2.0 Type-A)
P73
BGA 1526 balls
tu
50 x 25 mm
2 2
ck
USB2.0 x 1 Card reader SD 3.0 SD Card slot
RTS5144
P73
lo
USB2.0 x 1
BT with WLAN
PCIe x 1 / CNVi
P52
RJ45 Transformer LAN 1000 PCIe x 1
ar
Connector (10/100) USB2.0 x 1 Camera
DB DB P.73
P38
M.2 SSD (NVMe) PCIe x 4

PCIE only
W
P68 PCH-LP
USB2.0 x 1 Finger print

P73
3 3
2.5"
# FFS
1P
HDD/SSD
P67
SATA x 1
SMBus
RTC from Battery
P82
Reserve P67 Precision

I2C
24
Touchpad
Click Pad P63
SPI #dTPM
2CH SPEAKER
(2CH 2W/4ohm) NPCT750
Reserve P66
-L
HDA CODEC HDA

I2C
RING2/SLEEVE Realtek ALC3204-CG G3 Sharing SPI ROM PS/2
Topology 16 MB + 8MB
HP_R/L
P6~18
P56 P9
Universal Jack
DB
LA
eSPI
4
SMSC KBC 1515 4
MEC1515H
Battery RTC P58
Charger Daughter board
Keyboard PWM FAN Thermal sensor

NCT7718W
P63 P77 P66
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/04/01 Deciphered Date 2019/04/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP ALWAYS SUS RUN
USB 2.0 DESTINATION
CLOCKS
State
S3# S4# S5# PLANE PLANE PLANE
1 USB2.0 port1 Board ID & Model ID Table
S0 (Full ON) / M0 HIGH HIGH HIGH ON ON ON ON

2 USB2.0 Port2
3 USB2.0 port3, IO/B
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON OFF OFF
4 NC
D D
S4 (Suspend to DISK) / M3 LOW LOW HIGH ON OFF OFF OFF 5 Finger printer
S5 (SOFT OFF) / M3 LOW LOW LOW ON OFF OFF OFF

6 CCD
7 Card reader , IO/B
G3 OFF OFF OFF OFF OFF OFF OFF
8 NC
DS3 --- --- --- --- --- --- --- 9 Reserved
10 BT
Voltage Rails
Power Plane Description S0 S3 S4/S5 G3
+19V_ADPIN Adapter power supply N/A N/A N/A N/A
+17.4V_BATT++ Battery power supply N/A N/A N/A N/A
A
+19VB AC or battery power rail for System N/A N/A N/A N/A
+RTC_SOC RTC power ON ON ON ON
+3VALW_DSW +3VALW power for PCH DSW rails ON ON ON* OFF
+5VALW System +5V always on power rail ON ON ON* OFF
+3VALW System +3V always on power rail ON ON ON* OFF
+1.8V_PRIM System +1.8V always on power rail ON ON ON* OFF
rn
C C
+1.0V_PRIM System +1.0V always on power rail ON ON ON* OFF

+1.2V_DDR DDR4 +1.2V power rail ON ON OFF OFF
+2.5V_MEM DDR4 +2.5V power rail ON ON OFF OFF
+0.6V_DDR_VTT DDR +0.6VS power rail for DDR terminator ON OFF OFF OFF
USB3.0 PCIE SATA DESTINATION
+VCCIN_AUX CPU and PCH merged auxiliary power rail ON ON ON OFF
tu
+VCCST +1.05 VCCST power rail ON ON ON OFF USB3.0-1 PCIE-1 USB3.0 (MB)(Type-A)
+VCCSTG +1.05 VCCSTG power rail ON OFF OFF OFF
USB3.0-2 PCIE-2 USB3.0 (MB)(Type-A)
VCCPLL +1.05 VCCPLL power rail ON ON ON OFF
+VCC_IN Core voltage for CPU ON OFF OFF OFF USB3.0-3 PCIE-3 NC
+3VLP +19VB to +3VLP power rail for suspend power ON ON ON OFF
USB3.0-4 PCIE-4 NC
+3VALW_DSW +19VB to DSW power rail for suspend power ON ON ON OFF
+3VALW_PCH +3VALW power for PCH suspend rails ON ON ON* OFF PCIE-5 PCIE SSD
ck
+5VS System +5VS power rail ON OFF OFF OFF
PCIE-6 PCIE SSD
+3VS System +3VS power rail ON OFF OFF OFF
+1.35V_MEM_GFX +1.35V power rail for GPU ON OFF OFF OFF PCIE-7 PCIE SSD
+3VGS +3V power rail for GPU ON OFF OFF OFF
PCIE-8 PCIE SSD
+1.8VGS +1.8V power rail for GPU ON OFF OFF OFF
+0.95VSDGPU +0.95V power rail for GPU ON OFF OFF OFF PCIE-9 LOM
lo
B Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF B
PCIE-10 WLAN
PCIE-11 SATA-0 SATA HDD
PCIE-12 SATA-1 NC
ar
PCIE4 - 0 NC
PCIE4 - 1 NC
PCIE4 - 2 NC
W
PCIE4 - 3 NC
A
1P A
24
Note : VCCIN_AUX only down to 0V while SLP_S0# is asserted. On S3 mode, it only can down to 1.1V.
2018/04/01
Compal Secret Data
2019/04/01 Title
Issued Date Deciphered Date
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5 4 3 2 1
-L
LA
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5 4 3 2 1
FUSE 1.5A_24V FUSE 1A_65V

(F1) +DCBAT_LCD (F5) for USB TS +TS_VDD (1)
0ohm 0805
(RA1) +5V_PVDD
SY6288D20AAC USB_EN#
(UU1) +USB3_VCC
0ohm 0603
(RA3) +5V_AVDD
SY6288D20AAC
(UU2) USB_EN# +USB2_VCC 0ohm 1206
D (RS32) +5V_HDD D
PJP501 ALWON -->EN_5V PJP502

ENLDO_3V5V PJP503 SIO_SLP_S3#
SY8180CRAC EM5209VF FUSE 1.5A_6V
(PU501) +5VALWP +5VALW (UZ2) +5VS (FI1) +5V_HDMI
VBUS_P_CTRL# FUSE 0.5A_13.2V

PTP25814 (F3) +5V_KB_BL
(UT37) +CCG_VBUS
A
Adapter/Battery/19V
CPU PWR
GPU PWR
PJP301 JPC3
Peripheral Device PWR
SY8286BRAC BAS40C +3VS_SSD
rn
(PU301) +3VLP (D1) +RTC_CELL
FUSE 0.5A_13.2V
ALWON -->EN_3V (F7) +TP_VDD
ADAPTER ENLDO_3V5V
+RTC_VCC
tu
0 ohm 0402
(RA6) +3V_DVDD
+PWR_SRC
+19V_VIN (+19VB) LCD_VCC_TEST_EN
+3VALWP +RTC_CELL_VBAT G2895ALK21U or EDP_VDD_EN
to EC (U4)Hinge up PROC +LCDVDD (2)
C
CHARGER CHARGER C
ck
LCD_VCC_TEST_EN
ISL9538BHRTZ-T ISL95522HRZ-T SY6288C20AAC or EDP_VDD_EN
PJP302 (U1) +LCDVDD (1)
(PUB01) DSC (PUB01) UMA
SY6288C20AAC AUX_ON
(UL2) +LAN_VDD33 FUSE 1A_65V
(F4) +3VS_CAM (1)
+17.4V_BATT+
+3VALW VCCST_EN_R +VCCST_R
AOZ1334DI
lo
EM5209VF SIO_SLP_S3# FUSE 1A_65V (UZ12) +1.05V_VCCST
(UZ2) +3VS (F6) +TS_VDD (1) RZ23
I2C TS
BATTERY
D11
TPS22967DSGR
ar
VCCDSW_EN_GPIO
(UZ4) +3VALW_PCH +3.3V_SPI
CPU_C10_GATE# +VCCSTG_R
AOZ1334DI
Normal Protection Hinge up Protection
RW1
0 ohm 0603
+3.3V_WLAN
PCH +VCC1.05_OUT_FET (UZ8) RZ17 STG@
+VCCSTG_CPU
use Fuse Pop - U4
W
RC4164
RC4165 0 ohm 0603
0 ohm 0402 +VCCPRIM_1P8
0 ohm 0402 +3VALW_DSW
PRO@ ICPRO@ +3VALW_EC
(RE5) RC4068
0 ohm 0603
+VCCA_CLKLDO_1P8
PCH
PJP1801 PJP1802
+LCDVDD (1) +LCDVDD (2) RT8061AZQW PCH_PRIM_EN
(PU1801) +1.8VALWP +1.8V_PRIM RC4068
0 ohm 0603
+1.8VALW_EC
B
+TS_VDD (1)
+3VS_CAM (1)
+TS_VDD (2)
+3VS_CAM (2)
G2895ALK21U
1P SIO_SLP_S3#
+TS_VDD (2)
AO3416L
(QA1)
RA2
0 ohm 0402
RA5
+1.8V_AVDD
+VCCSTG_OUT_LGC
RC240
0 ohm 0402
B
0 ohm 0402
(U4) Hinge up PROC +3VS_CAM (2) +1.8V_CPVDD
24
+1.05V_VCCSTG
PJP2501 PJP2502
RT9059GSP SIO_SLP_S4#
(PU2501) +2.5VP +2.5V_MEM
-L
DZ1
+2.5V_PG
LA
PJPM01
RT8207PGQW +2.5V_PG PJPM02
(PUM01) +1.2VP +1.2V_DDR
0.6V_DDR_VTT_ON PJPM03
IMVP_VR_ON_EN +0.6VSP +0.6V_DDR_VTT
RT3612EBGQW +VCCIN
A
(PUZ1) A
1.8V_PRIM_PG
RT6543AGQW
(PUG1) +VCCIN_AUX

Power MAP
5 4 3 2 1
5 4 3 2 1
Power Up Sequence
G3 to S0
CHR Output B+
RTC battery or CHR Output +RTC_CELL

tPCH01
PCH Input RTCRST#/SRTCRST#
EC Input ACAV_IN
D D
EC Output EN_3V/EN_5V
VR Output +3VALW
VR Output +5VALW
VR Output POK
A
VCCDSW_EN_GPIO
tPCH05
PCH Input +3VALW_DSW tPCH04
PCH Input +3VALW_PCH(PRIM)

tPCH02
rn
PCH Input HW +3VALW PU PCH_DPWROK
tPCH32
PCH Output SIO_SLP_SUS# (PCH_PRIM_EN)
PCH Input VR Output +1.8V_PRIM tPCH06
tu
PCH Output +VCC1.05_OUT_PCH
PCH Output +VCC1.05_OUT_FET
VR Output 1.8V_PRIM_PG
PCH Input VR Output +VCCIN_AUX
ck
C C
VR Output PG_VCCIN_AUX (PRIM_PWRGD)

tPCH03
PCH Input EC Output PCH_RSMRST# tPCH07

tPCH18
PCH Output ESPI_RESET#
lo
PCH Output SUSCLK tPCH31
VR Output +VCCST_CPU
ar
PCH Input EC Output POWER_SW#_MB 16ms < T < 4s
PCH Output SIO_SLP_S5#
W
PCH Output CPU_C10_GATE#
B
VR Output
VR Output
VR Output
+2.5V_MEM
+2.5V_PG
+1.2V_DDR
1P B
24
VR Output 1.2V_VTT_PWRGD
VR Output +0.6V_DDR_VTT
+VCCSTG_CPU
+3VS
-L
+5VS
EC Input ALL_SYS_PWRGD (RUNPWROK) tCPU01 (DDR_VTT)

tCPU00 (VCCSTG)
PCH Input EC Output IMVP_VR_ON_P (VCCST_PWRGD)
LA
VR Output +VCCIN
VR Output IMVP_VR_PG
tCPU10
tCPU16
VR Output PCH_PWROK tPCH08
A CPU Output CPUPWRGD A
tPLT05
EC Output SYS_PWROK
tPCH33
PCH Output PCH_PLTRST#

Platform Power Sequence
5 4 3 2 1
5 4 3 2 1
D D
UC1A
AC2 REV 1.6 AY2
<38> EDP_TXP3 AC1 DDIA_TXP_3 TCP0_TXRX_P1 AY1
A
<38> EDP_TXN3 AD2 DDIA_TXN_3 TCP0_TXRX_N1 BB1
<38> EDP_TXP2 AD1 DDIA_TXP_2 TCP0_TXRX_P0 BB2
<38> EDP_TXN2 AF1 DDIA_TXN_2 TCP0_TXRX_N0 AM5
<38> EDP_TXP1 AF2 DDIA_TXP_1 TCP0_TX_P1 AM7
eDP <38>
<38>
EDP_TXN1
EDP_TXP0
AG2
AG1
DDIA_TXN_1
DDIA_TXP_0
TCP0_TX_N1
TCP0_TX_P0
AT7
AT5
+3VS <38> EDP_TXN0 DDIA_TXN_0 TCP0_TX_N0 AP7
AJ2 TCP0_AUX_P AP5
<38> EDP_AUXP DDIA_AUX_P TCP0_AUX_N
AJ1
<38> EDP_AUXN DDIA_AUX_N AT2
rn
RC4031 1 2 2.2K_0402_5% CPU_DP1_CTRL_CLK DN4 TCP1_TXRX_P1 AT1
DT6 GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 AU1
RC4032 2 1 2.2K_0402_5% CPU_DP1_CTRL_DATA GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 AU2
EDP_HPD DR5 TCP1_TXRX_N0 AD5
<38> EDP_HPD GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1 AD7
T12 TCP1_TX_N1 AH7
<40> CPU_DP1_P3 DDIB_TXP_3 TCP1_TX_P0
T11 AH5
<40> CPU_DP1_N3 DDIB_TXN_3 TCP1_TX_N0
Y11 AF7
<40> CPU_DP1_P2
tu
Y9 DDIB_TXP_2 TCP1_AUX_P AF5
+3VALW_PCH HDMI <40>
<40>
CPU_DP1_N2
CPU_DP1_P1
T9
P9
DDIB_TXN_2
DDIB_TXP_1
TCP1_AUX_N
BF1
<40> CPU_DP1_N1 DDIB_TXN_1 TCP2_TXRX_P1
V11 BF2
<40> CPU_DP1_P0 DDIB_TXP_0 TCP2_TXRX_N1
V9 BE2
KB_DET# <40> CPU_DP1_N0 DDIB_TXN_0 TCP2_TXRX_P0
RC1 1 2 100K_0201_5% BE1
AB9 TCP2_TXRX_N0 BD7
RC2 1 2 10K_0201_5% USB_OC1# AD9 DDIB_AUX_P TCP2_TX_P1 BD5
DDIB_AUX_N TCP2_TX_N1 AY5
RC3 1 2 10K_0201_5% USB_OC2# DM29 TCP2_TX_P0 AY7
C <40> CPU_DP1_CTRL_CLK GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0 C
DK27 BB5
ck
<40> CPU_DP1_CTRL_DATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P
OC2 for Type-C not use on UMA BB7
CPU_DP1_HPD DG43 TCP2_AUX_N
EDP_HPD <40> CPU_DP1_HPD GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD
RC5 1 2 100K_0201_5% BK1
DG47 TCP3_TXRX_P1 BK2
RC7 1 @ 2 100K_0201_5% USB_OC1# KB_DET# DJ47 GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1 BJ2
<63> KB_DET# GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0 BJ1
DU8 TCP3_TXRX_N0 BM7
TBT_0_LSX_RX Strap Pin DV8 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP3_TX_P1 BM5
RC338 1 @ 2 100K_0201_5% BKLT_IN_CPU GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP3_TX_N1 BH5
TCP3_TX_P0
lo
DF6 BH7
TBT_1_LSX_RX Strap Pin DD6 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0 BK5
Pull Low with eDP Side GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P BK7
DN23 TCP3_AUX_N
TBT_2_LSX_RX Strap Pin DM23 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# AN2 TCRCOMP_DP RC8 1 2 150_0201_1%
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P AN1 TCRCOMP_DN
DK23 TC_RCOMP_N
GPIO DEVICE CONTROL TBT_3_LSX_RX Strap Pin DN21 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO M8 DSI_DE_TE RC9 1 2 100K_0201_5%
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
ar
USB_OC0# USB Port (MB) TP@ TP190 1 PAD~D GPP_A17 DF43 AB1 DDI_RCOMP RC10 1 2 150_0201_1%
CPU_DP1_HPD RC4194 1 @ 2 0_0201_5% CPU_DP1_HPD_R DF45 GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
USB_OC1# USB Port (IO) DF47 GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK CE4 DISP_UTILS 1 TP1
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1 PAD~D
USB_OC2# TYPE-C USB_OC1# DH52 TP@
<73> USB_OC1# USB_OC2# GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
DK45
USB_OC3# NA GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
W
DM8
<38> EDP_VDD_EN BKLT_IN_CPU DN8 EDP_VDDEN
DEVSLP0 HDD <10> BKLT_IN_CPU DG10 EDP_BKLTEN
<38> EDP_BKLT_CTRL EDP_BKLTCTL
DEVSLP1 NA
DEVSLP2 M.2 SSD @ TGL-U_BGA1449
BKLT_IN_EDP 2 @ 1 BKLT_IN_CPU
<38> BKLT_IN_EDP RC339 0_0201_5%
B
R-short 0409 1P B
24
+3VALW_PCH +3VALW_PCH +3VALW_PCH +3VALW_PCH
1
1
RC11 RC270 RC12 RC272
@ 4.7K_0201_5% @ 4.7K_0201_5% @ 4.7K_0201_5% @ 4.7K_0201_5%
2
2
-L
TBT_0_LSX_RX TBT_1_LSX_RX TBT_2_LSX_RX TBT_3_LSX_RX

2
2
RC13 RC4037 RC14 RC4038
@ 20K_0201_5% @ 20K_0201_5% @ 20K_0201_5% @ 20K_0201_5%
LA
1
1
TBT LSX #0 PINS VCCIO CONFIGURATION TBT LSX #1 PINS VCCIO CONFIGURATION TBT LSX #2 PINS VCCIO CONFIGURATION TBT LSX #3 PINS VCCIO CONFIGURATION
HIGH 3.3V HIGH 3.3V HIGH 3.3V HIGH 3.3V
LOW 1.8V LOW 1.8V LOW 1.8V LOW 1.8V

A A
PLACE CLOSE TO THE SIGNAL TO AVOID STUB

P006 - TGL-U(1/13)TCSS,EDP
1.0
5 4 3 2 1
5 4 3 2 1
DIMM TYPE BOOT STRAP 3 BOOT STRAP 2 BOOT STRAP 1 Reserved Reserved
GPP_H2 (Weak internal PD 20K) GPP_H1 (Weak internal PD 20K) GPP_H0 (Weak internal PD 20K) GPP_F7 (Weak internal PD 20K) GPP_F10 (Weak internal PD 20K)
1 : Interleave
This is bit 3 of a total of 4-bit encoded pin straps for This is bit 2 of a total of 4-bit encoded pin straps for This is bit 1 of a total of 4-bit encoded pin straps for
0 : Non-Interleave boot configuration. boot configuration. boot configuration.
+3VALW_PCH +3VALW_PCH +3VALW_PCH +3VALW_PCH +3VALW_PCH +3VALW_PCH

The signal has a weak internal pull-down.
RC15 1 @ 2 4.7K_0201_5% RC16 1 @ 2 4.7K_0201_5% RC17 1 @ 2 4.7K_0201_5% RC317 1 @ 2 4.7K_0201_5% RC319 1 @ 2 4.7K_0201_5%
RC18 1 @ 2 10K_0201_5%
GPP_H2 RC19 1 @ 2 20K_0201_5% GPP_H1 RC20 1 @ 2 20K_0201_5% GPP_H0 RC21 1 @ 2 20K_0201_5% GPP_F7 RC316 1 @ 2 20K_0201_5% GPP_F10 RC318 1 @ 2 20K_0201_5%
MEM_INTERLEAVED RC22 1 @ 2 10K_0201_5%
D D
+1.05V_VCCSTG
A
+1.05V_VCCST
1
RC35
RC30 1 2 1K_0201_5% H_CATERR# 1K_0201_5%
UC1U
RC33 1 2 1K_0201_5% H_THERMTRIP# REV 1.6
2
H_CATERR# M7 K4 SOC_XDP_TRST#
PECI_EC_R CATERR# PROC_TRST# SOC_XDP_TMS SOC_XDP_TRST# <79>
BK9 B9
<58> PECI_EC_R H_PROCHOT#_R PECI PROC_TMS SOC_XDP_TDO SOC_XDP_TMS <79>
1 2 499_0201_1% E2 D12
rn
RC37
<16,58,82,85,98> H_PROCHOT# H_THERMTRIP# M5 PROCHOT# PROC_TDO A12 SOC_XDP_TDI SOC_XDP_TDO <79> PU on P.79
THRMTRIP# PROC_TDI SOC_XDP_TCK0 SOC_XDP_TDI <79>
B6
CPU_POPI_RCOMP PROC_TCK SOC_XDP_TCK0 <79>
@EMI@ RC38 2 1 49.9_0201_1% CT39
0.1U_0201_25V6K 2 1 CC730 H_THERMTRIP# RC39 2 1 49.9_0201_1% PCH_OPI_RCOMP CB9 PROC_POPIRCOMP D8 SOC_XDP_TCK0
RC40 2 @ 1 49.9_0201_1% A_PCH_OPIICCOBS CW12 PCH_OPIRCOMP PCH_JTAGX A9 SOC_XDP_TMS +VCCSTG_CPU
0.1U_0201_25V6K 2 1 CC731 H_PROCHOT#_R RC41 2 @ 1 49.9_0201_1% A_PCH_OPIICCCTL CM39 TP_1 PCH_TMS E12 SOC_XDP_TDO
TP_2 PCH_TDO B12 SOC_XDP_TDI
@EMI@ DBG_PMODE Strap Pin DF4 PCH_TDI A7 PCH_JTAG_TCK1
<79> DBG_PMODE PCH_JTAG_TCK1 <79>
tu
DBG_PMODE PCH_TCK
1
Strap setting in Page 79 H4 SOC_XDP_TRST#
EMI request,Place near CPU side. <38> TS_DET#
TS_DET#
TOUCH_PAD_INT#
DB42
DB41 GPP_B4/CPU_GP3
PCH_TRST#
C11 XDP_PREQ#
RC43
1K_0201_5%
TOUCH_SCREEN_PD# GPP_B3/CPU_GP2 PROC_PREQ# XDP_PREQ# <79>
RC279 1 @ 2 0_0201_5% TOUCH_SCREEN_PD#_R DF8 D11 XDP_PRDY#
<10,38> TOUCH_SCREEN_PD# MEM_INTERLEAVED GPP_E7/CPU_GP1 PROC_PRDY# XDP_PRDY# <79>
DU5
2
GPP_E3/CPU_GP0 G1 Strap Pin CPU_EAR
@EMI@ GPP_H2 Strap Pin DF31 EAR_N/EAR_N_TEST_NCTF
GPP_H2
1
33P_0201_50V8J 2 1 C43 TOUCH_SCREEN_PD# GPP_H1 Strap Pin DV32 DT15 Strap Pin GPP_F7 @
GPP_H0 Strap Pin DW32 GPP_H1 GPP_F7 DR15 RC44
GPP_H0 GPP_F9 DT14 Strap Pin GPP_F10 1K_0201_5%
C GPP_F10 C
DJ27
ck
GPP_H19/TIME_SYNC0
2
Stall reset sequence after PCU PLL
RC395 @ TGL-U_BGA1449
1 @ 2 TOUCH_PAD_INT# lock until de-asserted:
<58,63> TOUCHPAD_INTR# 1 = (Default) Normal Operation; No stall.
+3VS
0_0201_5%
R-short 0409 0 = Stall.
@ESD@
lo
RC36 1 @ 2 10K_0201_5% TOUCH_PAD_INT# H_THERMTRIP# CC70 1 2 0.1U_0201_10V6K
ESD@
H_PROCHOT# CC944 1 2 0.1U_0201_10V6K
ESD@
H_PROCHOT# CC945 1 2 0.1U_0201_10V6K
ar
+VCCIO_OUT
ESD Requesr:CC944 place near to RC37

RC370 1 2 10K_0201_5% BPM#0 CC945 place near to DC5
RC371 1 2 10K_0201_5% BPM#1
CC70 place near to M5
W
Place to CPU side
UC1T
+VCCIO_OUT Follow PDG REV 1.6
CFG15 T15 A51 RSVD_TP_7 PAD~D 1 TP@ TP2
CFG14 Strap Pin V17 CFG_15 RSVD_TP_7 B51 RSVD_TP_8 PAD~D 1 TP@ TP3
CFG13 U15 CFG_14 RSVD_TP_8
RC4147
RC4146
1
1
2
2
1K_0201_5%
1K_0201_5%
CFG11
CFG10
CFG12
CFG11
K11
K12
CFG_13
CFG_12
CFG_11
RSVD_TP_9
RSVD_TP_10
C1
D2
RSVD_TP_9
RSVD_TP_10
PAD~D 1
PAD~D 1
TP@
TP@
TP4
TP5
Non-I2CTCH --> RC295 pop
RC4145 1 2 1K_0201_5% CFG9 CFG10 K9 +3VALW_PCH
RC4143 1 2 1K_0201_5% CFG3 CFG9 T17 CFG_10 CP39 RSVD_TP_11 PAD~D 1 TP@ TP6
CFG_9 RSVD_TP_11
B
RC4142
RC4141
RC4177 1
RC4178 1
RC4180
RC4181
1
1
1
1
@
@
@
@
2
2
1K_0201_5%
1K_0201_5%
2 1K_0201_5%
2 1K_0201_5%
2
2
1K_0201_5%
1K_0201_5%
CFG2
CFG1
CFG0
CFG5
CFG8
CFG12
CFG8
CFG7
CFG6
CFG5
CFG4
CFG3
CFG2
CFG1
CFG0
1P
Strap Pin
K7
Strap Pin H7
K8
H9
E6
H5
E9
D9
E7
CFG_8
CFG_7
CFG_6
CFG_5
CFG_4
CFG_3
CFG_2
CFG_1
CFG_0
RSVD_TP_12
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_TP_13
CU40
AK9
AH9
DW6
DV6
DV4
DW3
RSVD_TP_12
RSVD_TP_13
RSVD_TP_14
PAD~D 1
PAD~D 1
PAD~D 1
TP@
TP@
TP@
TP7
TP8
TP9
TS_DET#
TS_DET#
100K_0201_5% 1
100K_0201_5% 1
@
2 RC295
2 RC294
B
RC4182 1 @ 2 1K_0201_5% CFG13 RC49 2 1 49.9_0402_1% CFG_RCOMP B5 RSVD_TP_14

I2CTCH --> RC294 pop
24
RC4183 1 @ 2 1K_0201_5% CFG15 CFG_RCOMP DU1 RSVD_TP_15 PAD~D 1 TP@ TP10
CMC@TP@ TP95 1 CFG17 U17 RSVD_TP_15 DT2 RSVD_TP_16 PAD~D 1 TP@ TP11
1 H11 CFG_17 RSVD_TP_16
Reserve CMC@TP@ TP94 CFG16
CFG_16 RSVD_TP_17 Pin Name TS_DET#
DW2 PAD~D 1 TP@ TP12
BPM#3 Y1 RSVD_TP_17 DV2 RSVD_TP_18 PAD~D 1 TP@ TP13
RC50 1 2 10K_0201_5% BPM#3 BPM#2 M4 BPM#_3 RSVD_TP_18 TOUCH HIGH
RC51 1 2 10K_0201_5% BPM#2 BPM#1 AB4 BPM#_2 E1 RSVD_TP_19 PAD~D 1 TP@ TP14
BPM#0 Y2 BPM#_1 RSVD_TP_19 F1 RSVD_TP_20 PAD~D 1 TP@ TP15
Non TOUCH LOW
BPM#_0 RSVD_TP_20
A3
RSVD_6 RSVD_16
AB2
Panel TOUCH DETECT#
-L
B3
X01_10 RSVD_7 DR1 RSVD_TP_21 PAD~D 1 TP@ TP16
TPC0_MBIAS_RCOMP AR2 RSVD_TP_21 DR2 RSVD_TP_22 PAD~D 1 TP@ TP18
TP19 TP@ 1 PAD~D RSVD_TP_2 AL10 TCP0_MBIAS_RCOMP RSVD_TP_22
RSVD_TP_2
1
+VCCIO_OUT TP20 TP@ 1 PAD~D RSVD_TP_3 AM12 DR53 RSVD_TP_23 PAD~D 1 TP@ TP21
RC768 TP22 TP@ 1 PAD~D RSVD_TP_4 AH12 RSVD_TP_3 RSVD_TP_23 DW5 RSVD_TP_24 PAD~D 1 TP@ TP23
2.2K_0201_1% TP24 TP@ 1 PAD~D RSVD_TP_5 AJ10 RSVD_TP_4 RSVD_TP_24
RC4179 1 @ 2 1K_0201_5% TP25 TP@ 1 PAD~D RSVD_TP_6 AR1 RSVD_TP_5 DV51
RSVD_TP_6 VSS_1 DW52 TP_3 PAD~D 1 TP@ TP26
2
RC4239 1 @ 2 1K_0201_5% CFG6 BN10 TP_3 DV53 TP_4 PAD~D 1 TP@ TP27
LA
BM12 RSVD_8 TP_4 W34

DD13 RSVD_9 RSVD_17 V35
DF13 RSVD_10 RSVD_18
RSVD_11 D52 SKTOCC# PAD~D 1 TP@ TP185
reserve pull down , refer by PDG 2.0 SKTOCC#
@ TGL-U_BGA1449
+VCCIO_OUT +VCCIO_OUT +VCCIO_OUT
RC4148 1 @ 2 1K_0201_5% RC4153 1 @ 2 1K_0201_5% RC4152 1 @ 2 1K_0201_5%
A RC4144 1 2 1K_0201_5% CFG4 RC4149 1 @ 2 1K_0201_5% CFG7 RC4151 1 @ 2 1K_0201_5% CFG14 A
eDP enable strap PEG Training PEG60 Lane Reversal

0 : enable 0 : PEG wait for BIOS training 0 : Reseved
Issued Date 2020/10/01 2018/10/01 Title
1 : disable 1 : PEG tranin immediately following 1 : Normal Deciphered Date
RESET# de-assertion 1 --> (default) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P007 - TGL-U(2/13)MISC,MIPI60
1 --> (default) 1.0
5 4 3 2 1
5 4 3 2 1
D D
UC1B UC1C
REV 1.6 REV 1.6
LP4-LP5(NIL)/DDR4 (NIL)/DDR4 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)

<23> DDR_M0_D[0..7] DDR_M0_D7 (IL) DDR4/LP4/LP5/LP5 CMD Flip DDR_M0_CLK1 <24> DDR_M1_D[0..7] DDR_M1_D7 DDR4/LP4/LP5/LP5 CMD Flip DDR_M1_CLK1
CP53 BT42 AL53 R41
DDR_M0_D6 DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7 DDR0_CLK_P1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P DDR_M0_CLK#1 DDR_M0_CLK1 <23> DDR_M1_D6 DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7 DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P DDR_M1_CLK#1 DDR_M1_CLK1 <24>
CP52 BT41 AL52 R42
DDR_M0_D5 DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6
DDR0_CLK_N1 / DDR3_CLK_N / DDR3_CLK_N / DDR3_CLK_N DDR_M0_CLK#1 <23> DDR_M1_D5 DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6
DDR1_CLK_N1 / DDR7_CLK_N / DDR7_CLK_N / DDR7_CLK_N DDR_M1_CLK#1 <24>
CP50 BP52 AL50 M52
DDR_M0_D4 CP49 DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P BP53 DDR_M1_D4 AL49 DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P M53
DDR_M0_D3 CU53 DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4 NC / DDR2_CLK_N / DDR2_CLK_N / DDR2_CLK_N CD42 DDR_M1_D3 AP53 DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4 NC / DDR6_CLK_N / DDR6_CLK_N / DDR6_CLK_N AC42
DDR_M0_D2 CU52 DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3 NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P CD41 DDR_M1_D2 AP52 DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P AC41
A
DDR_M0_D1 CU50 DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2 NC / DDR1_CLK_N / DDR1_CLK_N / DDR1_CLK_N CC52 DDR_M0_CLK0 DDR_M1_D1 AP50 DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2 NC / DDR5_CLK_N / DDR5_CLK_N / DDR5_CLK_N Y52 DDR_M1_CLK0
DDR_M0_D0 DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1 DDR0_CLK_P0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P DDR_M0_CLK#0 DDR_M0_CLK0 <23> DDR_M1_D0 DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1 DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P DDR_M1_CLK#0 DDR_M1_CLK0 <24>
CU49 CC53 DDR_M0_CLK#0 <23> AP49 Y53 DDR_M1_CLK#0 <24>
<23> DDR_M0_D[8..15] DDR_M0_D15 DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0
DDR0_CLK_N0 / DDR0_CLK_N / DDR0_CLK_N / DDR0_CLK_N <24> DDR_M1_D[8..15] DDR_M1_D15 DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0
DDR1_CLK_N0 / DDR4_CLK_N / DDR4_CLK_N / DDR4_CLK_N
CH53 AF53
DDR_M0_D14 CH52 DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7 DDR4/LP4/LP5/LP5 CMD BT45 DDR_M1_D14 AF52 DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7 DDR4/LP4/LP5/LP5 CMD Flip R47
DDR_M0_D13 DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6 Flip NC/DDR3_CKE0/DDR3_WCK_P/DDR3_WCK_P DDR_M1_D13 DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6 NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P
CH50 BT47 AF50 R45
DDR_M0_D12 CH49 DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5 NC / DDR3_CKE1 / DDR3_WCK_N / DDR3_WCK_N BN51 DDR_M1_D12 AF49 DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5 NC / DDR7_CKE1 / DDR7_WCK_N / DDR7_WCK_N K51
DDR_M0_D11 CL53 DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4 NC/DDR2_CKE0/DDR2_WCK_P/DDR2_WCK_P BN53 DDR_M1_D11 AH53 DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4 NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P K53
DDR_M0_D10 CL52 DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3 NC / DDR2_CKE1 / DDR2_WCK_N / DDR2_WCK_N CD45 DDR_M1_D10 AH52 DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3 NC / DDR6_CKE1 / DDR6_WCK_N / DDR6_WCK_N AC47
DDR_M0_D9 CL50 DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2 NC/DDR1_CKE0/DDR1_WCK_P/DDR1_WCK_P CD47 DDR_M1_D9 AH50 DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2 NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P AC45
DDR_M0_D8 CL49 DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1 NC / DDR1_CKE1 / DDR1_WCK_N / DDR1_WCK_N CA51 DDR_M1_D8 AH49 DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1 NC / DDR5_CKE1 / DDR5_WCK_N / DDR5_WCK_N W51
rn
<23> DDR_M0_D[16..23] DDR_M0_D23 DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0 NC/DDR0_CKE0/DDR0_WCK_P/DDR0_WCK_P <24> DDR_M1_D[16..23] DDR_M1_D23 DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0 NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P
CT47 CA53 AR41 W53
DDR_M0_D22 CV47 DDR1_DQ0_7/DDR0_DQ2_7/DDR1_DQ0_7 NC / DDR0_CKE1 / DDR0_WCK_N / DDR0_WCK_N DDR_M1_D22 AV42 DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7 NC / DDR4_CKE1 / DDR4_WCK_N / DDR4_WCK_N
DDR_M0_D21 CT45 DDR1_DQ0_6/DDR0_DQ2_6/DDR1_DQ0_6 DDR4/LP4/LP5/LP5 CMD Flip BU52 DDR_M0_CKE1 DDR_M1_D21 AR42 DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6 DDR4/LP4/LP5/LP5 CMD Flip P52 DDR_M1_CKE1
DDR_M0_D20 DDR1_DQ0_5/DDR0_DQ2_5/DDR1_DQ0_5 DDR0_CKE1/DDR2_CA4/DDR2_CA5/DDR2_CA1 DDR_M0_CKE0 DDR_M0_CKE1 <23> DDR_M1_D20 DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5 DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1 DDR_M1_CKE0 DDR_M1_CKE1 <24>
CV45 BL50 AV41 J50
DDR_M0_D19 DDR1_DQ0_4/DDR0_DQ2_4/DDR1_DQ0_4 DDR0_CKE0/DDR2_CA5/DDR2_CA6/DDR2_CA0 DDR_M0_CKE0 <23> DDR_M1_D19 DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4 DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0 DDR_M1_CKE0 <24>
CT42 AR45
DDR_M0_D18 CV42 DDR1_DQ0_3/DDR0_DQ2_3/DDR1_DQ0_3 DDR4/LP4/LP5/LP5 CMD Flip
CF42 DDR_M0_CS#1 DDR_M1_D18 AV45 DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3 DDR4/LP4/LP5/LP5 CMD Flip
AE42 DDR_M1_CS#1
DDR_M0_D17 DDR1_DQ0_2/DDR0_DQ2_2/DDR1_DQ0_2 DDR0_CS1/DDR1_CA1/DDR1_CA1/DDR1_CA5 DDR_M0_CS#0 DDR_M0_CS#1 <23> DDR_M1_D17 DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2 DDR1_CS1 / DDR5_CA1 / DDR5_CA1 / DDR5_CA5 DDR_M1_CS#0 DDR_M1_CS#1 <24>
CT41 CF47 DDR_M0_CS#0 <23> AR47 AE47 DDR_M1_CS#0 <24>
DDR_M0_D16 CV41 DDR1_DQ0_1/DDR0_DQ2_1/DDR1_DQ0_1 DDR0_CS0/NC/DDR1_CS1/DDR1_CA4 DDR_M1_D16 AV47 DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1 DDR1_CS0 / NC / DDR5_CS1 / DDR5_CA4
<23> DDR_M0_D[24..31] <24> DDR_M1_D[24..31]
tu
DDR_M0_D31 DDR1_DQ0_0/DDR0_DQ2_0/DDR1_DQ0_0 DDR4/LP4/LP5/LP5 CMD Flip DDR_M1_D31 DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0 DDR4/LP4/LP5/LP5 CMD Flip
CK47 CE53 AJ41 N42
DDR_M0_D30 CM47 DDR1_DQ1_7/DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_CA0/DDR0_CA0/DDR0_CA6 CE50 DDR_M1_D30 AJ42 DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7 NC/DDR7_CA5/DDR7_CA6/DDR7_CA0 N45
DDR_M0_D29 CK45 DDR1_DQ1_6/DDR0_DQ3_6/DDR1_DQ1_6 NC/DDR0_CA1/DDR0_CA1/DDR0_CA5 BL53 DDR_M1_D29 AL41 DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6 NC/DDR7_CA4/DDR7_CA5/DDR7_CA1 N44
DDR_M0_D28
DDR_M0_D27
CM45
CK42
DDR1_DQ1_5/DDR0_DQ3_5/DDR1_DQ1_5
NC/DDR2_CS0/DDR2_CA2/DDR2_CA2
NC/DDR3_CA5/DDR3_CA6/DDR3_CA0
BP47
BP42
Check symbol DDR_M1_D28
DDR_M1_D27
AL42
AJ45
NC/DDR7_CA3/DDR7_CA4/DDR7_CS1
NC/DDR7_CA2/DDR7_CA3/DDR7_CS0
N47
J53 Check symbol
DDR_M0_D26 CM42 DDR1_DQ1_3/DDR0_DQ3_3/DDR1_DQ1_3 NC/DDR3_CA4/DDR3_CA5/DDR3_CA1 BP45 DDR_M1_D26 AJ47 DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3 NC/DDR6_CS0/DDR6_CA2/DDR6_CA2 AC50
DDR_M0_D25 CM41 DDR1_DQ1_2/DDR0_DQ3_2/DDR1_DQ1_2 NC/DDR3_CA3/DDR3_CA4/DDR3_CS1 BP44 DDR_M1_D25 AL45 DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2 NC/DDR4_CA1/DDR4_CA1/DDR4_CA5 AC53
DDR_M0_D24 CK41 DDR1_DQ1_1/DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR3_CA2/DDR3_CA3/DDR3_CS0 DDR_M1_D24 AL47 DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1 NC/DDR4_CA0/DDR4_CA0/DDR4_CA6
<23> DDR_M0_D[32..39] DDR_M0_D39 DDR1_DQ1_0/DDR0_DQ3_0/DDR1_DQ1_0 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) DDR_M0_DQS7 <24> DDR_M1_D[32..39] DDR_M1_D39 DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) DDR_M1_DQS7
BF53 BB44 DDR_M0_DQS7 <23> A43 K36 DDR_M1_DQS7 <24>
DDR_M0_D38 BF52 DDR2_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7 DDR3_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_3 BD44 DDR_M0_DQS#7 DDR_M1_D38 B43 DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7 DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7 K38 DDR_M1_DQS#7
C DDR_M0_D37 DDR2_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6 DDR3_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_3 DDR_M0_DQS6 DDR_M0_DQS#7 <23> DDR_M1_D37 DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6 DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7 DDR_M1_DQS6 DDR_M1_DQS#7 <24> C
BF50 BK44 D43 G44
ck
DDR_M0_D36 DDR2_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5 DDR3_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_2 DDR_M0_DQS#6 DDR_M0_DQS6 <23> DDR_M1_D36 DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5 DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6 DDR_M1_DQS#6 DDR_M1_DQS6 <24>
BF49 BH44 E44 J44
DDR_M0_D35 DDR2_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4 DDR3_DQSN_0/DDR0_DQSN_6/DDR1_DQSN_2 DDR_M0_DQS5 DDR_M0_DQS#6 <23> DDR_M1_D35 DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4 DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6 DDR_M1_DQS5 DDR_M1_DQS#6 <24>
BH53 BA51 A46 D39
BH52 BA50 DDR_M0_DQS#5 <23> B46 C39 DDR_M1_DQS#5 <24>
DDR_M0_D33 BH50 DDR2_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2 DDR2_DQSN_1/DDR0_DQSN_5/DDR0_DQSN_3 BG51 DDR_M0_DQS4 DDR_M1_D33 D46 DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2 DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7 C45 DDR_M1_DQS4
BH49 BG50 DDR_M0_DQS#4 <23>
E47 D45 DDR_M1_DQS#4 <24>
<23> DDR_M0_D[40..47] DDR_M0_D47 DDR2_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0 DDR2_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2 DDR_M0_DQS3 <24> DDR_M1_D[40..47] DDR_M1_D47 DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0 DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6 DDR_M1_DQS3
AY53 CK44 DDR_M0_DQS3 <23>
E38 AJ44 DDR_M1_DQS3 <24>
DDR_M0_D46 AY52 DDR2_DQ1_7/DDR0_DQ5_7/DDR0_DQ3_7 DDR1_DQSP_1/DDR0_DQSP_3/DDR1_DQSP_1 CM44 DDR_M0_DQS#3 DDR_M1_D46 D38 DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7 DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5 AL44 DDR_M1_DQS#3
DDR_M0_D45 DDR2_DQ1_6/DDR0_DQ5_6/DDR0_DQ3_6 DDR1_DQSN_1/DDR0_DQSN_3/DDR1_DQSN_1 DDR_M0_DQS2 DDR_M0_DQS#3 <23> DDR_M1_D45 DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6 DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5 DDR_M1_DQS2 DDR_M1_DQS#3 <24>
AY50 CT44 DDR_M0_DQS2 <23> B38 AV44 DDR_M1_DQS2 <24>
DDR_M0_D44 AY49 DDR2_DQ1_5/DDR0_DQ5_5/DDR0_DQ3_5 DDR1_DQSP_0/DDR0_DQSP_2/DDR1_DQSP_0 CV44 DDR_M0_DQS#2 DDR_M1_D44 A38 DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5 DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4 AR44 DDR_M1_DQS#2
DDR2_DQ1_4/DDR0_DQ5_4/DDR0_DQ3_4 DDR1_DQSN_0/DDR0_DQSN_2/DDR1_DQSN_0 DDR_M0_DQS#2 <23> DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4 DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4 DDR_M1_DQS#2 <24>
lo
DDR_M0_D43 BC53 CK51 DDR_M0_DQS1 DDR_M1_D43 E41 AG51 DDR_M1_DQS1
BC52 CK50 DDR_M0_DQS#1 <23>
D40 AG50 DDR_M1_DQS#1 <24>
DDR_M0_D41 BC50 DDR2_DQ1_2/DDR0_DQ5_2/DDR0_DQ3_2 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 CR51 DDR_M0_DQS0 DDR_M1_D41 B40 DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2 DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5 AN51 DDR_M1_DQS0
BC49 CR50 DDR_M0_DQS#0 <23> A40 AN50 DDR_M1_DQS#0 <24>
<23> DDR_M0_D[48..55] DDR_M0_D55 DDR2_DQ1_0/DDR0_DQ5_0/DDR0_DQ3_0 DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 <24> DDR_M1_D[48..55] DDR_M1_D55 DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0 DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4
BK47 G42
DDR_M0_D54 BK45 DDR3_DQ0_7/DDR0_DQ6_7/DDR1_DQ2_7 DDR4/LP4/LP5/LP5 CMD Flip CF44 DDR_M0_ODT1 DDR_M1_D54 G41 DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7 DDR4/LP4/LP5/LP5 CMD Flip AE44 DDR_M1_ODT1
DDR_M0_D53 DDR3_DQ0_6/DDR0_DQ6_6/DDR1_DQ2_6 DDR0_ODT1/DDR1_CA0/DDR1_CA0/DDR1_CA6 DDR_M0_ODT0 DDR_M0_ODT1 <23> DDR_M1_D53 DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6 DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6 DDR_M1_ODT0 DDR_M1_ODT1 <24>
BH47 CF45 J41 AE45
DDR_M0_D52 DDR3_DQ0_5/DDR0_DQ6_5/DDR1_DQ2_5 DDR0_ODT0 / DDR1_CS0 / DDR1_CA2 / DDR1_CA2 DDR_M0_ODT0 <23> DDR_M1_D52 DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5 DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2 DDR_M1_ODT0 <24>
BH45 J42
DDR3_DQ0_4/DDR0_DQ6_4/DDR1_DQ2_4 DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4
ar
DDR_M0_D51 DDR4/LP4/LP5/LP5 CMD Flip DDR_M0_MA16_RAS# DDR_M1_D51 DDR4/LP4/LP5/LP5 CMD Flip DDR_M1_MA16_RAS#
BH42 CB47 DDR_M0_MA16_RAS# <23> G45 AA47 DDR_M1_MA16_RAS# <24>
DDR_M0_D50 BK42 DDR3_DQ0_3/DDR0_DQ6_3/DDR1_DQ2_3 DDR0_MA16/DDR1_CA4/DDR1_CA5/DDR1_CA1 CB44 DDR_M0_MA15_CAS# DDR_M1_D50 J45 DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3 DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1 AA44 DDR_M1_MA15_CAS#
DDR_M0_D49 DDR3_DQ0_2/DDR0_DQ6_2/DDR1_DQ2_2 DDR0_MA15/DDR1_CA3/DDR1_CA4/DDR1_CS1 DDR_M0_MA14_WE# DDR_M0_MA15_CAS# <23> DDR_M1_D49 DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2 DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1 DDR_M1_MA14_WE# DDR_M1_MA15_CAS# <24>
BK41 CB45 G47 AA45
DDR_M0_D48 DDR3_DQ0_1/DDR0_DQ6_1/DDR1_DQ2_1 DDR0_MA14/DDR1_CA2/DDR1_CA3/DDR1_CS0 DDR_M0_MA13 DDR_M0_MA14_WE# <23> DDR_M1_D48 DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1 DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0 DDR_M1_MA13 DDR_M1_MA14_WE# <24>
BH41 CF41 J47 AE41
<23> DDR_M0_D[56..63] DDR_M0_D63 DDR3_DQ0_0/DDR0_DQ6_0/DDR1_DQ2_0 DDR0_MA13/DDR1_CS1/DDR1_CS0/DDR1_CA3 DDR_M0_MA12 DDR_M0_MA13 <23> <24> DDR_M1_D[56..63] DDR_M1_D63 DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0 DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3 DDR_M1_MA12 DDR_M1_MA13 <24>
BD47 BU53 G38 P53
DDR_M0_D62 DDR3_DQ1_7/DDR0_DQ7_7/DDR1_DQ3_7 DDR0_MA12/DDR2_CA1/DDR2_CA1/DDR2_CA5 DDR_M0_MA11 DDR_M0_MA12 <23> DDR_M1_D62 DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7 DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5 DDR_M1_MA11 DDR_M1_MA12 <24>
BB47 BT51 DDR_M0_MA11 <23> G36 N51 DDR_M1_MA11 <24>
DDR_M0_D61 BD45 DDR3_DQ1_6/DDR0_DQ7_6/DDR1_DQ3_6 DDR0_MA11/NC/DDR2_CS1/DDR2_CA4 BV42 DDR_M0_MA10 DDR_M1_D61 H36 DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6 DDR1_MA11/NC/DDR6_CS1/DDR6_CA4 U42 DDR_M1_MA10
DDR_M0_D60 DDR3_DQ1_5/DDR0_DQ7_5/DDR1_DQ3_5 DDR0_MA10/DDR3_CA1/DDR3_CA1/DDR3_CA5 DDR_M0_MA9 DDR_M0_MA10 <23> DDR_M1_D60 DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5 DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5 DDR_M1_MA9 DDR_M1_MA10 <24>
BB45 BU50 H38 P50
DDR_M0_MA9 <23> DDR_M1_MA9 <24>
W
DDR_M0_D59 BB42 DDR3_DQ1_4/DDR0_DQ7_4/DDR1_DQ3_4 DDR0_MA9/DDR2_CA0/DDR2_CA0/DDR2_CA6 BY53 DDR_M0_MA8 DDR_M1_D59 N36 DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4 DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6 U53 DDR_M1_MA8
DDR_M0_D58 DDR3_DQ1_3/DDR0_DQ7_3/DDR1_DQ3_3 DDR0_MA8/DDR0_CA2/DDR0_CA3/DDR0_CS0 DDR_M0_MA7 DDR_M0_MA8 <23> DDR_M1_D58 DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3 DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0 DDR_M1_MA7 DDR_M1_MA8 <24>
BB41 CA50 DDR_M0_MA7 <23>
L36 W50 DDR_M1_MA7 <24>
DDR_M0_D57 BD42 DDR3_DQ1_2/DDR0_DQ7_2/DDR1_DQ3_2 DDR0_MA7/DDR0_CA4/DDR0_CA5/DDR0_CA1 BY52 DDR_M0_MA6 DDR_M1_D57 L38 DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2 DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1 U52 DDR_M1_MA6
DDR_M0_D56 DDR3_DQ1_1/DDR0_DQ7_1/DDR1_DQ3_1 DDR0_MA6/DDR0_CA3/DDR0_CA4/DDR0_CS1 DDR_M0_MA5 DDR_M0_MA6 <23> DDR_M1_D56 DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1 DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1 DDR_M1_MA5 DDR_M1_MA6 <24>
BD41 BY50 N38 U50
DDR3_DQ1_0/DDR0_DQ7_0/DDR1_DQ3_0 DDR0_MA5/DDR0_CA5/DDR0_CA6/DDR0_CA0 DDR_M0_MA4 DDR_M0_MA5 <23> DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0 DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0 DDR_M1_MA4 DDR_M1_MA5 <24>
CD51 AA51
DDR0_MA4/DDR0_CS0/DDR0_CA2/DDR0_CA2 DDR_M0_MA3 DDR_M0_MA4 <23> DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2 DDR_M1_MA3 DDR_M1_MA4 <24>
CD53 AA53
DDR0_MA3/DDR0_CS1/DDR0_CS0/DDR0_CA3 DDR_M0_MA2 DDR_M0_MA3 <23> DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3 DDR_M1_MA2 DDR_M1_MA3 <24>
BV47 U47
DDR0_MA2/DDR3_CS0/DDR3_CA2/DDR3_CA2 DDR_M0_MA1 DDR_M0_MA2 <23> DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2 DDR_M1_MA1 DDR_M1_MA2 <24>
CE52 DDR_M0_MA1 <23> AC52 DDR_M1_MA1 <24>
DDR0_MA1/NC/DDR0_CS1/DDR0_CA4 BV41 DDR_M0_MA0 DDR1_MA1/NC/DDR4_CS1/DDR4_CA4 U41 DDR_M1_MA0
DDR0_MA0/NC/DDR3_CS1/DDR3_CA4 DDR_M0_MA0 <23> DDR1_MA0/NC/DDR7_CS1/DDR7_CA4 DDR_M1_MA0 <24>
DDR4/LP4/LP5/LP5 CMD Flip DDR_M0_BG1 DDR4/LP4/LP5/LP5 CMD Flip DDR_M1_BG1
BN50 K50
DDR0_BG1/DDR2_CA2/DDR2_CA3/DDR2_CS0 DDR_M0_BG0 DDR_M0_BG1 <23> DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0 DDR_M1_BG0 DDR_M1_BG1 <24>
BL52 J52
DDR0_BG0/DDR2_CA3/DDR2_CA4/DDR2_CS1 DDR_M0_BG0 <23> DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1 DDR_M1_BG0 <24>
B
DDR4/LP4/LP5/LP5 CMD Flip
DDR0_BA1/DDR1_CA5/DDR1_CA6/DDR1_CA0
DDR0_ACT#/DDR2_CS1/DDR2_CS0/DDR2_CA3
DDR0_PAR/DDR3_CS1/DDR3_CS0/DDR3_CA3
DDR0_ALERT#
CB42
BV44
BT53
BV45
AU50
AU49
DDR_M0_BA1
DDR_M0_BA0
DDR_M0_ACT#
DDR_M0_PAR
DDR_M0_ALERT#
+V_DDR_REFA_R
1P DDR_M0_BA1
DDR_M0_BA0
DDR_M0_ACT#
DDR_M0_PAR
DDR_M0_ALERT#
<23>
<23>
<23>
<23>
<23>
DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3
DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3
DDR1_ALERT#
AA42
U44
N53
U45
AU53
AU52
DDR_M1_BA1
DDR_M1_BA0
DDR_M1_ACT#
DDR_M1_PAR
DDR_M1_ALERT#
+V_DDR_REFB_R
DDR_M1_BA1
DDR_M1_BA0
DDR_M1_ACT#
DDR_M1_PAR
DDR_M1_ALERT#
<24>
<24>
<24>
<24>
<24>
B
DDR0_VREF_CA +V_DDR_REFA_R DDR1_VREF_CA +V_DDR_REFB_R

24
E52 DDR_VTT_CNTL Trace width/Spacing >= 20mils Trace width/Spacing >= 20mils
DDR_VTT_CTL DV47 DDR_DRAMRST# @ TGL-U_BGA1449
DRAM_RESET# C49 DDR_RCOMP_0 RC55 1 2 100_0201_1%
DDR_RCOMP
@ TGL-U_BGA1449
-L
+VCC1.05_OUT_FET +VCCIN
1
RC4118 RC45
24.9_0201_1% 24.9_0201_1%
@ @
2
LA
DP_COMP
UC1D
+1.2V_DDR REV 1.6
Buffer with Open Drain Output For +1.2V_DDR +3VS 1 DV24

VTT power control T11 TP@ RSVD_2
1
DDR_RCOMP_2 DW47
0.1U_0201_10V6K 2 1 CC1 RD30 DDR_RCOMP_1 DW49 RSVD_3
RSVD_4
1
470_0201_5% DP_COMP A48

TD & RVP PU100K RSVD_5
1
UC4
1 5 RC4042 RC4119 RC4120
2
A NC VCC 100K_0201_5% 80.6_0201_1% 121_0201_1% @ TGL-U_BGA1449 A

DDR_VTT_CNTL 2 @ @
2
A 4 DDR_DRAMRST#_R 1 @ 2 DDR_DRAMRST#
0.6V_DDR_VTT_ON <89>
2
3 Y <23,24> DDR_DRAMRST#_R RD29 0_0201_5%
GND 1
@
74AUP1G07GW_TSSOP5 CC2
100P_0402_50V8J
2 R-short 0409

P008 - TGL-U(3/13)LPDDR4/x
1.0
5 4 3 2 1
5 4 3 2 1
BOOT HALT CONSENT STRAP A0 PERSONALITY STRAP TLS CONFIDENTIALITY CPUNSSC CLOCK FREQ ESPI OR EC LESS
SPI0_MOSI(NO INTERNAL PU/PD) SPI0_IO2(NO INTERNAL PU/PD) SPI0_IO3 GPP_C2 (Weak internal PD 20K) GPP_B23 (Weak internal PD 20K) GPP_C5 (Weak internal PD 20K)
0 = Enable 0 = Enable 0 = Enable 0 = TLS CONFIDENTIALITY DISABLE 0 = 38.4 MHz clock direct from crystal (default) 0 = Enable eSPI. (Default)
1 = Disable 1 = Disable 1 = Disable 1 = TLS CONFIDENTIALITY ENABLE 1 = 19.2 MHz clock from divider (Device from 38.4MHz crystal) 1 = Disable eSPI.
+3VALW_PCH +3VALW_PCH +3VALW_PCH
+3VALW_PCH +1.8V_PRIM +3VALW_PCH +1.8V_PRIM +3VALW_PCH +1.8V_PRIM
EDS recommend
100K(RVP(0.7) NC) GPP_C2 RC61 1 @ 2 4.7K_0201_5% GPP_B23 RC63 1 @ 2 4.7K_0201_5% GPP_C5 RC62 1 @ 2 4.7K_0201_5%
RC64 1 2 4.7K_0201_5% RC65 1 2 100K_0201_5% RC66 1 2 100K_0201_5%
RC67 1 2 4.7K_0201_5% RC69 1 @ 2 4.7K_0201_5% RC68 1 @ 2 4.7K_0201_5%
CPU_SPI_0_D0 RC70 1 @ 2 4.7K_0201_5% CPU_SPI_0_D2 RC71 1 @ 2 4.7K_0201_5% CPU_SPI_0_D3 RC72 1 @ 2 100K_0201_5%
RC73 1 @ 2 20K_0201_5% RC75 1 @ 2 20K_0201_5% RC74 1 @ 2 20K_0201_5%
D D
no need this security for CSMB This strap is used in conjunction with Boot Strap 1,2,3, (on GPP_H0, GPP_H1, GPP_H2
respectively).
(internal PD) 0000 = Master Attached Flash Configuration (BIOS / CSME on SPI). <--use this
Reserved 1000 = Slave Attached Flash Configuration (BIOS / CSME on eSPI attached device).
0100 = BIOS on eSPI Peripheral Channel; CSME on master attached SPI.
1100 = BIOS on eSPI peripheral Channel; CSME on slave attached SPI.
Others: Reserved.
GPP_E6 (External pull-up is required)
A
+3VALW_PCH +1.8V_PRIM
GPP_E6 RC97 1 @ 2 100K_0201_5%
RC98 1 2 100K_0201_5% +3VS
RC99 1 @ 2 4.7K_0201_5%
PCH_SMBDATA 2.2K_0201_5% 2 1 RC4052
PCH_SMBCLK 2.2K_0201_5% 2 1 RC4053
rn
UC1E
REV 1.6
RC87 1 2 100K_0201_5%
+3VALW_PCH
CPU_SPI_0_CLK DJ37 DK21 MEM_SMBCLK
CPU_SPI_0_D3 DG35 SPI0_CLK GPP_C0/SMBCLK DM19 MEM_SMBDATA
Strap Pin DDR4,XDP
CPU_SPI_0_D2 DJ39 SPI0_IO3 GPP_C1/SMBDATA DN19 Strap Pin (1.8V) GPP_C2
Strap Pin
tu
CPU_SPI_0_D1 DJ33 SPI0_IO2 GPP_C2/SMBALERT# MEM_SMBCLK RC4051 1 2 1K_0201_5%
CPU_SPI_0_D0 Strap Pin DJ35 SPI0_MISO DK19 SML0_SMBCLK RC4160 1 2 0_0201_5% MEM_SMBDATA RC4050 1 2 1K_0201_5%
CPU_SPI_0_CS#1 SPI0_MOSI GPP_C3/SML0CLK GPU_THM_SMBCLK <58,66>
DF35 DM17 SML0_SMBDATA RC46 1 2 0_0201_5% GPU,THM.EC
CPU_SPI_0_CS#0 DG37 SPI0_CS1# GPP_C4/SML0DATA DN17 Strap Pin GPP_C5 GPU_THM_SMBDAT <58,66>
+3VS CPU_SPI_0_CS#2 DF39 SPI0_CS0# GPP_C5/SML0ALERT# SML0_SMBDATA RC82 1 2 499_0201_1%
To TPM <66> CPU_SPI_0_CS#2 SPI0_CS2# DK17 SML1_SMBCLK SML0_SMBCLK RC84 1 2 499_0201_1%
DJ6 GPP_C6/SML1CLK DJ17 SML1_SMBDATA
DN5 GPP_E11 / THC0_SPI1_CLK GPP_C7/SML1DATA CY50 Strap Pin GPP_B23 Type-C , TBT
DR9 GPP_E2 / THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1# SML1_SMBCLK RC85 1 2 1K_0201_5%
RC4130 1 2 10K_0201_5% SATA_LED# DM6 GPP_E1 / THC0_SPI1_IO2 DN53 1.8V ESPI_CLK_R RC88 1 2 49.9_0201_1% SML1_SMBDATA RC86 1 2 1K_0201_5%
C GPP_E12 / THC0_SPI1_IO1 GPP_A5/ESPI_CLK ESPI_IO3_R ESPI_CLK <58> C
DK6 DJ53 1.8V RC89 1 2 15_0201_1%
ck
GPP_E13 / THC0_SPI1_IO0 GPP_A3/ESPI_IO3/SUSACK# ESPI_IO2_R ESPI_IO3 <58>
DK8 DH50 1.8V RC90 1 2 15_0201_1%
SATA_LED# GPP_E10 / THC0_SPI1_CS# GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK ESPI_IO1_R ESPI_IO2 <58>
DV11 DP50 1.8V RC92 1 2 15_0201_1% ESPI 1.8V
<63,68> SATA_LED# GPP_E8 / SATA_LED# GPP_A1/ESPI_IO1 ESPI_IO0_R ESPI_IO1 <58>
3.3V DW9 DP52 1.8V RC95 1 2 15_0201_1%
GPP_E6 GPP_E17/THC0_SPI1_INT# GPP_A0/ESPI_IO0 ESPI_CS# ESPI_IO0 <58>
Strap Pin (1.8V) DT8 DK52 1.8V
GPP_E6/THC0_SPI1_RST# GPP_A4/ESPI_CS# ESPI_RESET# ESPI_CS# <58>
DL50 1.8V
GPP_A6/ESPI_RESET# ESPI_RESET# <58>
3.3V DN15
1.8V DK13 GPP_F11/THC1_SPI2_CLK
1.8V DM13 GPP_F15/GSXSRESET#/THC1_SPI2_IO3
GPP_F14/GSXDIN/THC1_SPI2_IO2 Check!!
1.8V DN13 AEP pop RC91/RC93
1.8V DJ15 GPP_F13/GSXSLOAD/THC1_SPI2_IO1 +1.8V_PRIM
GPP_F12/GSXDOUT/THC1_SPI2_IO0 RVP unpop RC91/RC93
lo
DK15
DN10 GPP_F16/GSXCLK/THC1_SPI2_CS# RC91 1 @ 2 1K_0201_5%
DV14 GPP_F18/THC1_SPI2_INT#
GPP_F17/THC1_SPI2_RST# ESPI_CS# RC93 1 @ 2 75K_0201_1%
DH3
DH4 CL_CLK
Didn't support C-Link DF2 CL_DATA ESPI_RESET# RC96 1 2 75K_0201_1%
CL_RST#
ar
R1 R3 SPI1-64Mb @ TGL-U_BGA1449
PCH
R4 SPI2-128Mb
+3VS
EC R2 R5
W
CPU_SPI_0_D0 RC4199 1 CMC@ 2 1K_0201_5%
TPM CPU_SPI_0_D2
XDP_SPI_SI <79>
RC4200 1 CMC@ 2 1K_0201_5%
XDP_SPI_IO2 <79>
QC6A
2
L2N7002DW1T1G_SC88-6
SB00001CW00
MEM_SMBCLK 6 1
PCH_SMBCLK <23,24>
R1
5
QC6B DDR4
CPU_SPI_0_CLK RC76 1 2 0_0201_5% CPU_SPI_0_CLK_R NPI pop D11 MEM_SMBDATA 3 4
PCH_SMBDATA <23,24>
CPU_SPI_0_D3 CPU_SPI_0_D3_R
CPU_SPI_0_D2
RC77
RC78
1
1
2
2
0_0201_5%
0_0201_5% CPU_SPI_0_D2_R
MP pop RC56 SB00001CW00
PCH Side
B
<58>
<58>
SHD_CLK
SHD_IO3
CPU_SPI_0_D1
CPU_SPI_0_D0
SHD_CLK
SHD_IO3
SHD_IO2
RC79
RC80
RC23
RC24
RC25
1
1
1
2
2
0_0201_5%
0_0201_5%
CPU_SPI_0_D1_R
CPU_SPI_0_D0_R
R2 R2 should place near P.58 UE1 (EC side)

2
1 NTPM@ 2
1 NTPM@ 2
100_0201_1%
100_0201_1%
100_0201_1%
CPU_SPI_0_CLK_R
CPU_SPI_0_D3_R
CPU_SPI_0_D2_R
+3.3V_SPI
1P
RC300 1 2 0_0402_5%
+3VALW_PCH
2KV
B
From EC <58>
<58>
SHD_IO2
SHD_IO1
SHD_IO1
SHD_IO0
RC26 1 2 100_0201_1% CPU_SPI_0_D1_R
CPU_SPI_0_D0_R
+3VALW_PCH For EC Auto Load Code
RC27 1 2 100_0201_1%
24
<58> SHD_IO0
RC349 1 G3@ 2 4.7K_0201_5% CPU_SPI_0_CS#0 RC4173 1 G3@ 2 0_0201_5%
SHD_CS0# <58>
R3 RC350 1 G3@ 2 4.7K_0201_5% CPU_SPI_0_CS#1 RC4174 1 G3@ 2 0_0201_5%
SHD_CS1# <58>
CPU_SPI_0_CLK_R RC102 1 2 15_0201_1% SPI_CLK_ROM
CPU_SPI_0_D3_R RC103 1 2 15_0201_1% SPI_D3_ROM
CPU_SPI_0_D2_R RC104 1 2 15_0201_1% SPI_D2_ROM
CPU_SPI_0_D1_R
CPU_SPI_0_D0_R
RC105 1 2 15_0201_1% SPI_D1_ROM
SPI_D0_ROM
To SPI ROM 1
RC106 1 2 15_0201_1%
-L
+3.3V_SPI
R4 CC5
1 2
0.1U_0402_10V7K
CPU_SPI_0_CLK_R RC341 1 2 15_0201_1% SPI_CLK_ROM2 UC5
@
CPU_SPI_0_D3_R RC342 1 2 15_0201_1% SPI_D3_ROM2 CPU_SPI_0_CS#0 1 8
CPU_SPI_0_D2_R RC343 1 2 15_0201_1% SPI_D2_ROM2 SPI_D1_ROM 2 /CS VCC 7 SPI_D3_ROM
CPU_SPI_0_D1_R
CPU_SPI_0_D0_R
RC344 1 2 15_0201_1% SPI_D1_ROM2
SPI_D0_ROM2
To SPI ROM 2 SPI_D2_ROM 3 DO(IO1)
/WP(IO2)
/HOLD(IO3)
CLK
6 SPI_CLK_ROM
SPI_D0_ROM
RC345 1 2 15_0201_1% 4 5
LA
GND DI(IO0)
GD25B64CSIGR_SO8
SA000039A40 W25Q64JVSSIQ Use X76 control UC5 and UC6
R5 should place near P.66 UX1 (TPM side) 64Mb Flash ROM X7687131L84 - Winbond
R5 X7687131L85 - Gigadevice
CPU_SPI_0_CLK_R
CPU_SPI_0_D1_R
RC346
RC347
1 TPM@
1 TPM@
2
2
15_0201_1%
15_0201_1%
SPI_CLK_TPM
SPI_D1_TPM SPI_CLK_TPM <66> ROM_1 +3.3V_SPI X7687131L86 - XMC
CPU_SPI_0_D0_R RC348 1 TPM@ 2 15_0201_1% SPI_D0_TPM SPI_D1_TPM
SPI_D0_TPM
<66>
<66>
To TPM
1 2 RF@ @RF@
CC6 0.1U_0402_10V7K SML1_SMBCLK CC4 1 2 33P_0201_50V8J
RF Request
UC6
@
CPU_SPI_0_CS#1 1 8
SPI_D1_ROM2 2 CS# VCC 7 SPI_D3_ROM2 @EMI@ @EMI@
A For 2 Flash + 1 TPM SPI_D2_ROM2 3 DO(IO1) IO 6 SPI_CLK_ROM2
EMI@ SPI_CLK_ROM RC40542 1 CC7 2 1 A
4 IO2 CLK 5 SPI_D0_ROM2 33_0402_5%
GND DI(IO0) 33P_0402_50V8J
R2 R3 R4
W25Q128JVSIQ_SO8
SA00005VV20 W25Q128JVSIQ
place colse to UC5
128Mb Flash ROM
RC24 TPM@
49.9_0201_1%
SD00000TO00 FLASH ROM ROM_2
RC25 TPM@
49.9_0201_1%
SD00000TO00
P009 - TGL-U(4/13)SPI,SMB,ESPI
5 4 3 2 1
5 4 3 2 1
TOP SWAP OVERRIDE NO REBOOT

GPP_B14 / SPKR (Internal 20 K Pull Down)
GPP_B18/GSPI0_MOS (Internal 20 K Pull Down)
0 = Disable "Top Swap" mode. (Default)
0 = REBOOT ENABLED
1 = Enable "Top Swap" mode.
1 = NO REBOOT (This function is useful when running ITP/XDP).
+3VALW_PCH +3VS
SPKR RC115 1 @ 2 8.2K_0201_5% NRB_BIT RC1141 @ 2 4.7K_0201_5%
D D
UC1F
REV 1.6 +3VS
DC53 DR27 ISH_I2C_0_SCL RC328 1 @ 2 1K_0201_5%
A
NRB_BIT Strap Pin DA51 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD DW27
DC49 GPP_B18/GSPI0_MOSI GPP_D13/ISH_UART0_RXD DV25 KB_LED_BL_DET ISH_I2C_0_SDA RC329 1 @ 2 1K_0201_5%
DC50 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS# DT25 KB_LED_BL_DET <63>
X01_27 <56> SPKR Strap Pin
1 GPP_B15 DC52 GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1# GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5 ISH_I2C_1_SDA RC126 1 @ 2 1K_0201_5%
TP@ TP195 GPP_B15/GSPI0_CS0# DB45 ISH_I2C_0_SCL
TPM_SPI_IRQ# CY49 GPP_B6/ISH_I2C0_SCL DB44 ISH_I2C_0_SDA ISH_I2C_1_SCL RC128 1 @ 2 1K_0201_5%
<66> TPM_SPI_IRQ#
CY53 GPP_B20/GSPI1_CLK GPP_B5/ISH_I2C0_SDA Reserved for G/Gyro
TOUCH_SCREEN_PD# RC4195 1 @ 2 TOUCH_PANEL_PD# CY52 GPP_B22/GSPI1_MOSI CY39 ISH_I2C_1_SCL ISH_ACC1_INT# RC131 1 @ 2 10K_0201_5%
<7,38> TOUCH_SCREEN_PD# DA50 GPP_B21/GSPI1_MISO GPP_B8/ISH_I2C1_SCL DB47 ISH_I2C_1_SDA
0_0201_5% Reserve for FFS
GPP_B19/GSPI1_CS0# GPP_B7/ISH_I2C1_SDA ISH_ACC2_INT# RC779 1 @ 2 10K_0201_5%
DV21 DD47
rn
DT21 GPP_C9/UART0_TXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL DD44
DR21 GPP_C8/UART0_RXD GPP_B9/I2C5_SDA/ISH_I2C2_SDA TABLE_MODE#_EC RC323 1 TABLE@2 10K_0201_5%
BKLT_IN_CPU RC4186 1 @ 2 0_0201_5% ENBKL_TS DW21 GPP_C11/UART0_CTS# DJ8
<6> BKLT_IN_CPU GPP_C10/UART0_RTS# GPP_E16/ISH_GP7 DR7 1 2 10K_0201_5%
ISH_GP0 for Main Accelerometer (KB Board)INT# 0= Table Mode RC324 @
DV19 GPP_E15/ISH_GP6 DR24 ISH_GP1 for 2nd Accelerometer (Camera Board)INT# 1= Exit Table Mode
DT19 GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_D18/ISH_GP5 DU25 ISH_GP2 for TABLE_MODE#
DR18 GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_D17/ISH_GP4 DV31 ISH_GP3 for ALS_ALERT#
LCD_CBL_DET# DU19 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_D3/ISH_GP3/BK3/SBK3 DU31 TABLE_MODE#_EC ISH_GP4 for NB_MODE#(N/A)
<38> LCD_CBL_DET# GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_D2/ISH_GP2/BK2/SBK2 DT27 ISH_ACC2_INT# TABLE_MODE#_EC <58> ISH_GP5 for NB_LID#(N/A)
GPP_D1/ISH_GP1/BK1/SBK1 ISH_GP6 for TAB_LID#(N/A)
tu
RC4184 1 @ 2 0_0402_1% UART_2_CTXD_DRXD DJ21 DV27 ISH_ACC1_INT#
GPP_C21/UART2_TXD GPP_D0/ISH_GP0/BK0/SBK0 ISH_GP7 for Proximity sensor(Camera)INT#
RC4185 1 @ 2 0_0402_1% UART_2_CRXD_DTXD DG23
TOUCH_SCREEN_INT#_LCD RC292 1 2 0_0201_5% TOUCH_SCREEN_INT# DJ19 GPP_C20/UART2_RXD DR51 GPP_RCOMP RC137 1 2 200_0201_1%
<38> TOUCH_SCREEN_INT#_LCD DF21 GPP_C23/UART2_CTS# GPP_RCOMP
I2CTCH@ GPP_C22/UART2_RTS# DN33
I2C_0_LCD_SCL DV18 GPP_T3 DT35
<38> I2C_0_LCD_SCL I2C_0_LCD_SDA GPP_C17/I2C0_SCL GPP_T2
TS <38> I2C_0_LCD_SDA DW18
GPP_C16/I2C0_SDA DG17
I2C_1_SCL DJ23 GPP_U5 DG19
<63> I2C_1_SCL I2C_1_SDA DT18 GPP_C19/I2C1_SCL GPP_U4
TP <63> I2C_1_SDA GPP_C18/I2C1_SDA
C DJ29 C
ck
DJ31 GPP_H5/I2C2_SCL
+3VALW_PCH GPP_H4/I2C2_SDA
DBC_PANEL_EN DF29
<38> DBC_PANEL_EN GPP_H7/I2C3_SCL
DG29
GPP_H6/I2C3_SDA
GPP_H9 1.8V DF25
1 @ 2 GPP_H8 1.8V DF27 GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
RC145 0_0201_5% GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
RC781 2 @ 1 10K_0201_5% BT_RADIO_DIS#
@ TGL-U_BGA1449
lo
Place near JWLAN1
+3VS
ar
RC121 2 @ 1 49.9K_0201_1% UART_2_CRXD_DTXD
UART_2_CTXD_DRXD HDA_BIT_CLK
FLASH DESCRIPTOR SECURITY OVERRIDE
RC123 2 @ 1 49.9K_0201_1% RC151 1 2 33_0201_1%
HDA_SYNC HDA_BIT_CLK_R <56>
RC152 1 2 33_0201_1%
HDA_SDOUT HDA_SYNC_R <56>
RC156 1 2 33_0201_1% GPP_R2/HDA_SDO (Internal 20 K Pull Down)
HDA_SDIN0 HDA_SDOUT_R <56>
DBC_PANEL_EN HDA_SDIN0 <56>
RC4135 1 2 10K_0201_5% 1 1 1
0 = ENABLE (DEFAULT)
56P_0201_25V8J
CC946
2.2P_0201_50V8B
CC14 @RF@
2.2P_0201_50V8B
CC16 @RF@
W
2 2 2 1 = DISABLE (ME can update)
@RF@
HDA for Audio ME_FWP_PCH 1 HDA_SDOUT
Capacitor to only be used for HDA_SDO, HDA_RST#, and
<58> ME_FWP 1 @ 2 2
HDA_SDI for EMI purposes and should be a close as RC147 0_0201_5% RC148 2.2K_0201_5%
possible to the PCH.
R-short 0409
DW15
DW24
UC1G
GPP_F8/I2S_MCLK2_INOUT
GPP_D19/I2S_MCLK1
REV 1.6
1P GPP_R0/HDA_BCLK/I2S0_SCLK
GPP_R1/HDA_SYNC/I2S0_SFRM
DR38
DU37
DT37
HDA_BIT_CLK
HDA_SYNC
HDA_SDOUT
HDA_BIT_CLK RC149 1 @ 2 100K_0201_5%
B
DG41 GPP_R2/HDA_SDO/I2S0_TXD DV37 HDA_SDIN0

GPP_A23/I2S1_SCLK GPP_R3/HDA_SDI0/I2S0_RXD
24
N3V3_DET DT38
<73> N3V3_DET DPST_EN GPP_R7/I2S1_SFRM
DV38 DV41 @EMI@
<38> DPST_EN DW38 GPP_R6/I2S1_TXD GPP_R4/HDA_RST# DL53 DMIC_PCH_CLK_R 1 2 BLM15PX221SN1D_2P DMIC_PCH_CLK DMIC_PCH_CLK
3.3V LC2 1
GPP_R5/HDA_SDI1/I2S1_RXD GPP_A7/I2S2_SCLK/DMIC_CLK_A0 DG51 3.3V DMIC_PCH_DATA DMIC_PCH_CLK <38>
CODEC_DET 1.8V DN31 GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0 DG50 TOUCH_SCREEN_RST RC4214 1 2 0_0201_5% TOUCH_SCREEN_RST_LCD DMIC_PCH_DATA <38> CC15 @RF@
SKUID 1.8V DM31 GPP_S6/SNDW3_CLK/DMIC_CLK_A0 GPP_A10/I2S2_RXD/DMIC_DATA1 I2CTCH@ TOUCH_SCREEN_RST_LCD <38> 27P_0201_25V8
GPP_S7/SNDW3_DATA/DMIC_DATA0 DL49 2
1.8V DK33 GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1 DL52 GPP_A11 PAD~D 1
DK31 GPP_S4/SNDW2_CLK/DMIC_CLK_A1 GPP_A11/PMC_I2C_SDA/I2S3_SCLK TP189 TP@
GPP_S5/SNDW2_DATA/DMIC_DATA1 DH49 BT_RADIO_DIS#
GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0 BT_RADIO_DIS# <52>
DW35
DV35 GPP_S2/SNDW1_CLK/DMIC_CLK_B0 DF33 SNDW_RCOMP RC159 1 2 200_0201_1% EVT1_18
-L
GPP_S3/SNDW1_DATA/DMIC_CLK_B1 SNDW_RCOMP
1.8V DT32
1.8V DR35 GPP_S0/SNDW0_CLK
GPP_S1/SNDW0_DATA
@ TGL-U_BGA1449
LA
+1.8V_PRIM
REALTEK@
CODEC_DET 100K_0201_5% 1 2 RC3952
SKUID 100K_0201_5% 2 DIS@ 1 RC4062

CIRRUS@
CODEC_DET 100K_0201_5% 1 2 RC3959
SKUID 100K_0201_5% 1 UMA@ 2 RC4060
Pin Name CODEC_DET

A A
Main Realtek Codec HIGH REALTEK@
2nd Cirrus Codec LOW CIRRUS@
From eDP From DB to PCH
N3/V3 DPST_EN
+3VALW_PCH
N3V3_DET
+3VALW_PCH
100K_0201_5% 1 2 RC57 100K_0201_5% 1 2 RC58
UMA@ LOW Pin Name DPST_EN Pin Name N3V3_DET

SKUID Security Classification Compal Secret Data Compal Electronics, Inc.
HIGH 120 Hz Panel HIGH N3 non-LAN
DIS@ DSC Issued Date 2020/10/01 Deciphered Date 2018/10/01 Title
LOW 60 Hz Panel LOW V3 LAN P010 - TGL-U(5/13)HDA,I2C,ISH
1.0
5 4 3 2 1
5 4 3 2 1
+3VS
CLKREQ_PCIE#4 RC162 1 2 10K_0201_5% 33 ohm for EMI request

CLKREQ_PCIE#2 RC4064 1 2 10K_0201_5% EMI@
RC165 CC166
CLKREQ_PCIE#1 RC163 1 2 10K_0201_5% 33_0201_5% 10P_0201_50V8J
XTAL_PCH_38P4M_IN 1 2 XTAL_38P4M_IN 1 2
UC1K
1
REV 1.6
3
4
BW1 DU14 GPP_F19 PAD~D 1 RC167
BW2 CLKOUT_PCIE_P6
GPP_F19/SRCCLKREQ6# DF23 TP191 TP@ 200K _0201_1% YH1
CLKOUT_PCIE_N6
GPP_H11/SRCCLKREQ5# DG25 CLKREQ_PCIE#4 38.4MHZ_10PF_8Y38420005
CB2 GPP_H10/SRCCLKREQ4# DT24 CLKREQ_PCIE#4 <68> <--SSD
1
2
CB1 CLKOUT_PCIE_P5GPP_D8/SRCCLKREQ3# DT30 CLKREQ_PCIE#2 EMI@
CLKOUT_PCIE_N5GPP_D7/SRCCLKREQ2# DV30 CLKREQ_PCIE#1 CLKREQ_PCIE#2 <73> <--LAN RC168 CC169
D GPP_D6/SRCCLKREQ1# DW30
CLKREQ_PCIE#1 <52> <-- WLAN 33_0201_5% 10P_0201_50V8J D
BW4 GPP_D5/SRCCLKREQ0# <-- GPU XTAL_PCH_38P4M_OUT 1 2 XTAL_38P4M_OUT 1 2
SSD --> <68>
<68>
CLK_PCIE_P4
CLK_PCIE_N4
BW5 CLKOUT_PCIE_P4
CLKOUT_PCIE_N4 XTAL_OUT
DM1
DL1
XTAL_PCH_38P4M_OUT
XTAL_PCH_38P4M_IN
CL7 XTAL_IN
CL8 CLKOUT_PCIE_P3 DW41 SUSCLK RC4175 1 2 0_0402_5% RC170 CC171
CLKOUT_PCIE_N3 GPD8/SUSCLK SUSCLK_R <52,58> 0_0201_5% 15P_0201_50V8J
CB4 DT47 PCH_RTCX2 PCH_RTCX1 1 2 PCH_RTCX1_R 1 2
LAN --> <73>
<73>
CLK_PCIE_P2
CLK_PCIE_N2
CB5 CLKOUT_PCIE_P2
CLKOUT_PCIE_N2
RTCX2
RTCX1
DR47 PCH_RTCX1 SUSCLK
2
BY4 DN37 PCH_RTCRST#
1
WLAN --> <52>
<52>
CLK_PCIE_P1
CLK_PCIE_N1
BY3 CLKOUT_PCIE_P1
CLKOUT_PCIE_N1
RTCRST#
SRTCRST#
DK37 SRTCRST# @EMI@ YC1
1
CC140 32.768KHZ_12.5PF_9H03200042
CN7 0.1U_0201_10V6K RC172
A
GPU -->
1
CN8 CLKOUT_PCIE_P0 2 10M_0201_1% ESR MAX=50k ohm
CLKOUT_PCIE_N0
2
RC174 1 2 60.4_0201_1% XCLK_RCOMP DJ5
2
XCLK_BIASREF RC173
@ TGL-U_BGA1449 2 0_0201_5%
1
@ +RTC_SOC RC175 CC176
CLME1 CC17 0_0201_5% 15P_0201_50V8J
1
SHORT PADS 1U_0201_6.3V6M PCH_RTCX2 1 2 PCH_RTCX2_R 1 2
2
SRTCRST# 1 1 2
rn
RC177 20K_0201_5%
PCH_RTCRST# 1 2
1 RC178 20K_0201_5%
1
@
CLCMOS1 CC18
SHORT PADS 1U_0201_6.3V6M
2
2
tu
PDG_An RC delay circuit with a time delay in the
range of 18 - 25 ms should be provided. The circuit
should be connected to VCCRTC.
C C
ck
+3VALW_PCH
PCH_BATLOW# RC185 1 2 100K_0201_5% Follow Modena MLK and Intel check list
AC_PRESENT
change to 100K
RC186 1 2 100K_0201_5%
ESD@
VCCST_PWRGD CC20 1 2 100P_0201_50V8J
lo
ESD@ LAN_WAKE#_R RC188 1 2 1K_0201_5%
CPUPWRGD CC21 1 2 100P_0201_50V8J
PCIE_WAKE# RC757 1 2 1K_0201_5%
@ESD@
@ SYS_RESET# CC22 1 2 0.1U_0201_10V6K
AC_PRESENT 2 1 DV14 HW_ACAV_IN
ar
RB751S-40_SOD523-2 DV14 and RC130 co-lay ESD Request:place near CPU side
SCS00006300 CPU_C10_GATE# RC4222 1 2 100K_0201_5%
+3VALW_PCH
UC1L R-short 0409
SIO_SLP_SUS# DV49 REV 1.6 BM9 CPUPWRGD
<78> SIO_SLP_SUS# SLP_SUS# PROCPWRGD
1
DK41 SIO_PWRBTN#_R RC4065 1 @ 2 0_0201_5% SIO_PWRBTN#

SIO_SLP_S5# GPD3/PWRBTN# PCH_BATLOW# SIO_PWRBTN# <58>
RC198 DM43 DN41
<85> SIO_SLP_S5# SIO_SLP_S4# GPD10/SLP_S5# GPD0/BATLOW# AC_PRESENT HW_ACAV_IN
10K_0201_5% DJ41 DK43 RC4161 1 @ 2 0_0201_5%
<78,89> SIO_SLP_S4# HW_ACAV_IN <58,63,82,85,111>
W
SIO_SLP_S3# DJ43 GPD5/SLP_S4# GPD1/ACPRESENT
<38,78> SIO_SLP_S3# SIO_SLP_A# GPD4/SLP_S3#
DR41 CW40 Strap Pin PMCALERT# RC4231 1 2 10K_0201_5% +3VALW_PCH
2
SIO_SLP_WLAN# DT44 GPD6/SLP_A# GPP_B11/PMCALERT# DN27 CPU_C10_GATE#_R RC132 1 @ 2 0_0201_5%

SYS_RESET# GPD9/SPL_WLAN# GPP_H18/CPU_C10_GATE# CPU_C10_GATE# <78>
DG31 TPM_PRSNT#
SIO_SLP_S0# DD42 GPP_H3/SX_EXIT_HOLDOFF#
DN39 GPP_B12/SLP_S0# DK39 PCH_PCIE_WAKE# RC133 1 @ 2 0_0201_5% PCIE_WAKE# R-short 0409 +1.05V_VCCST
SLP_LAN# WAKE#
PCH_RSMRST#_AND DM35 DM41 LAN_WAKE#_R RC4138 1 @ 2 0_0201_5% PCIE_WAKE#
<63,78,79> PCH_RSMRST#_AND SYS_RESET# RSMRST# GPD2/LAN_WAKE# PCIE_WAKE# <52,58,68,73>
DD10 DT41
PCH_PLTRST# DD41 SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON 1.05V VCCST_PWRGD RC189 1 2 1K_0201_5%
GPP_B13/PLTRST# DN43 GPD7 1
PCH_DPWROK GPD7 TP@ T36
DK35
<78> PCH_DPWROK DSW_PWROK
B
PD in EC side <58> SYS_PWROK PCH_PWROK
INTRUDER#
DF10
DN35
DM37
SYS_PWROK
PCH_PWROK
INTRUDER#
VCCSTPWRGOOD_TCSS
VCCST_PWRGD
VCCST_OVERRIDE
CE5
BP8
BP9
VCCSTPWRGOOD_TCSS
VCCST_PWRGD_CPU
VCCST_OVERRIDE 1P
RC191 1 2 60.4_0201_1% VCCST_PWRGD
VCCST_PWRGD <78>
CPU Input, 1.05V VCCSTPWRGOOD_TCSS RC193 1 2 0_0201_5% VCCST_OVERRIDE_R
B
1
SPIVCCIOSEL Strap Pin DT49 DR12 PCH Output, 1.05V VCCST_OVERRIDE RC194 1 @ 2 0_0201_5%
SPIVCCIOSEL GPP_F20/EXT_PWR_GATE# DW12 RZ22
GPP_F21/EXT_PWR_GATE2# 100K_0201_5%
RC214 1 2 100K_0201_5% PCH_DPWROK R-short 0409
@ TGL-U_BGA1449
2
Follow Modena MLK and Intel check list
change to 100K
24
+3VALW_PCH
+RTC_SOC NTPM@
TPM_PRSNT# 100K_0201_5% 2 1 RC4226
RC196 1 2 1M_0201_5% INTRUDER#
RC761 1 @ 2 1M_0201_5% TPM_PRSNT# 100K_0201_5% 1 2 RC4227

TPM@
CC715 1 2 0.1U_0201_10V6K
-L
+3VALW_PCH
Pin Name TPM_PRSNT#
RC200 1 2 100K_0201_5% SIO_SLP_S0#
LOW TPM (HW)
RC207 1 @ 2 10K_0201_5% PCH_RSMRST#_AND
HIGH NTPM (SW)
LA
PCH GLITCH ISSUE MITIGATION(PDG p.306)

SIO_SLP_SUS#
TPM/NTPM +3VS CC26
PU 1.91K in power page88.
+3VS
RC204 1 2 100K_0201_5% 0.1U_0201_10V6K RC197 1 2 0_0201_5%
2
1 2
CC24 1 @ 2 0.33U_0201_6.3V6M RC199 +3VS
UC32 100K_0201_5% @
5
RC205 1 @ 2 100K_0201_5% SIO_SLP_S5# MC74VHC1G08EDFT2G_SC70 UC31 @
5
PCH_PLTRST# 1 MC74VHC1G08EDFT2G_SC70
STRAP FOR SPI 1.8V/3.3V SEL SA0000BIP00
1
CC25 1 @ 2 0.33U_0201_6.3V6M B 4 1
SA0000BIP00 PCH_PWROK
P
O PLTRST# <52,66,68,73> <98> VR_READY B
1
1 2 4
A O
1
RC206 1 2 100K_0201_5% SIO_SLP_S4# RC209 RUNPWROK 2
<58> RUNPWROK A
G
SPIVCCIOSEL CC3864 100K_0201_5% RC212
3
1
A CC27 1 @ 2 0.33U_0201_6.3V6M 0.1U_0201_10V6K 100K_0201_5% A
3
ESD@ 2 RC4212
2
RC208 1 2 100K_0201_5% SIO_SLP_S3# 0 = SPI voltage is 3.3V (4.7 k pull-down to GND) 100K_0201_5%
2
@
CC28 1 @ 2 0.33U_0201_6.3V6M
1 = SPI voltage is 1.8V (4.7K pull-up to DSW_PWROK)
2
RC210 1 @ 2 100K_0201_5% SIO_SLP_A#
+3VALW_PCH +3VALW_PCH same as +3VALW_DSW
2nd should pick CMOS And gate
CC29 1 @ 2 0.33U_0201_6.3V6M
RC217 1 @ 2 4.7K_0201_5% SPIVCCIOSEL
RC213 1 @ 2 100K_0201_5% SIO_SLP_WLAN#
RC218 1 2 4.7K_0201_5%
CC30 1 @ 2 0.33U_0201_6.3V6M
RC216 1 @ 2 100K_0201_5% SIO_SLP_S0#
P011 - TGL-U(6/13)CLK,GPIO
1.0
5 4 3 2 1
5 4 3 2 1
UC1I
BT7 REV 1.6 CV4
BT8
CE2
PCIE12_TXP/SATA1_TXP
PCIE12_TXN/SATA1_TXN
USB2P_10
USB2N_10
CY3 USB20_P10
USB20_N10
<52>
<52> BT
CE1 PCIE12_RXP/SATA1_RXP DD5
PCIE12_RXN/SATA1_RXN USB2P_9 DD4
BT9 USB2N_9
<67> SATA_CTX_DRX_P0 BV9 PCIE11_TXP/SATA0_TXP CW9
SATA HDD ---> <67> SATA_CTX_DRX_N0
<67> SATA_CRX_DTX_P0
CF4 PCIE11_TXN/SATA0_TXN USB2P_8 DA9 not support USB touch
CF3 PCIE11_RXP/SATA0_RXP USB2N_8
<67> SATA_CRX_DTX_N0 PCIE11_RXN/SATA0_RXN DD1
D
<52> PCIE_CTX_DRX_P10
BV7
BV8 PCIE10_TXP
USB2P_7
USB2N_7
DD2 USB20_P7
USB20_N7
<73>
<73> Card Reader (IO/B) D
WLAN ---> <52> PCIE_CTX_DRX_N10 CG2 PCIE10_TXN DA1

<52> PCIE_CRX_DTX_P10
<52> PCIE_CRX_DTX_N10
CG1 PCIE10_RXP
PCIE10_RXN
USB2P_6
USB2N_6
DA2 USB20_P6
USB20_N6
<38>
<38> CCD
BY7 DA12
LAN --->
<73> PCIE_CTX_DRX_P9
<73> PCIE_CTX_DRX_N9
BY8
CG5
PCIE9_TXP
PCIE9_TXN
USB2P_5
USB2N_5
DA11 USB20_P5
USB20_N5
<73>
<73> Finger Printer
<73> PCIE_CRX_DTX_P9 CG4 PCIE9_RXP DC8
<73> PCIE_CRX_DTX_N9 PCIE9_RXN USB2P_4 DC7
<68> PCIE_CTX_DRX_P8 CB8 USB2N_4 UMA not support Type-C
A
CB7 PCIE8_TXP DB4
<68> PCIE_CTX_DRX_N8
<68> PCIE_CRX_DTX_P8 CK5
CK4
PCIE8_TXN
PCIE8_RXP
USB2P_3
USB2N_3
DB3
USB20_P3
USB20_N3
<73>
<73> USB2.0 (IO/B)
<68> PCIE_CRX_DTX_N8 PCIE8_RXN DA5
<68> PCIE_CTX_DRX_P7 CD9
CD8 PCIE7_TXP
USB2P_2
USB2N_2
DA4
USB20_P2
USB20_N2
<71>
<71> USB2.0 (M/B)
<68> PCIE_CTX_DRX_N7 PCIE7_TXN
<68> PCIE_CRX_DTX_P7 CK1 DC11
<68> PCIE_CRX_DTX_N7 CK2 PCIE7_RXP
PCIE7_RXN
USB2P_1
USB2N_1
DC9 USB20_P1
USB20_N1
<71>
<71> USB2.0 (M/B)
rn
PCIE SSD ---> <68> PCIE_CTX_DRX_P6 CG8 DP4 HDD_DET#
CG7 PCIE6_TXP GPP_E0/SATAXPCIE0/SATAGP0 DF41 M2_SSD_PEDET HDD_DET# <67>
<68> PCIE_CTX_DRX_N6 PCIE6_TXN GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM M2_SSD_PEDET <68>
<68> PCIE_CRX_DTX_P6 CL4 +3VALW_PCH
CL3 PCIE6_RXP DD8 USB_OC0#
<68> PCIE_CRX_DTX_N6 PCIE6_RXN GPP_E9/USB_OC0# USB_OC0# <71>
DJ45 USB_OC3#
CJ8 GPP_A16/USB_OC3#/I2S4_SFRM USB_OC0# RC219 1 2 10K_0201_5%
<68> PCIE_CTX_DRX_P5 PCIE5_TXP
CJ7 DN6
tu
<68> PCIE_CTX_DRX_N5 PCIE5_TXN GPP_E5/DEVSLP1 SSD_DEVSLP <68>
CN2 DG8 USB_OC3# RC220 1 2 10K_0201_5%
<68> PCIE_CRX_DTX_P5 PCIE5_RXP GPP_E4/DEVSLP0 HDD_DEVSLP <67>
<68> PCIE_CRX_DTX_N5 CN1
PCIE5_RXN DN29
CR8 GPP_H15/M2_SKT2_CFG3 DK29 WLAN_RF_DIS#
PCIE4_TXP/USB31_4_TXP GPP_H14/M2_SKT2_CFG2 WLAN_RF_DIS# <52> WLAN_RF_DIS#
CR7 DT31 RC4230 1 @ 2 10K_0201_5%
CN5
CN4
PCIE4_TXN/USB31_4_TXN
PCIE4_RXP/USB31_4_RXP
GPP_H13/M2_SKT2_CFG1
GPP_H12/M2_SKT2_CFG0
DR32 Place near JWLAN1
PCIE4_RXN/USB31_4_RXN DV9 PCIE_RCOMPP RC221 1 2 100_0201_1%
C UMA not support Type-C PCIE_RCOMP_P PCIE_RCOMPN C
ck
CU8 DT9
CU7 PCIE3_TXP/USB31_3_TXP PCIE_RCOMP_N +3VS
CT2 PCIE3_TXN/USB31_3_TXN DC12 USB2_VBUSSENSE RC222 1 2 10K_0201_5%
CT1 PCIE3_RXP/USB31_3_RXP USB_VBUSSENSE DF1 USB2_ID RC223 1 2 10K_0201_5%
PCIE3_RXN/USB31_3_RXN USB_ID DE1 USB2_RCOMP RC224 1 2 113_0201_1% HDD_DET# RC4211 1 @ 2 10K_0201_5%
CW8 USB2_COMP
<71> USB3_CTX_DRX_P2 PCIE2_TXP/USB31_2_TXP
CW7 E3
USB3.0 (MB)(Type-A) ---> <71> USB3_CTX_DRX_N2
<71> USB3_CRX_DTX_P2 CU3 PCIE2_TXN/USB31_2_TXN RSVD_BSCAN
CT4 PCIE2_RXP/USB31_2_RXP
lo
<71> USB3_CRX_DTX_N2 PCIE2_RXN/USB31_2_RXN
<71> USB3_CTX_DRX_P1 DA8
DA7 PCIE1_TXP/USB31_1_TXP
USB3.0 (MB)(Type-A) ---> <71> USB3_CTX_DRX_N1
<71> USB3_CRX_DTX_P1 CV2 PCIE1_TXN/USB31_1_TXN
CV1 PCIE1_RXP/USB31_1_RXP
<71> USB3_CRX_DTX_N1 PCIE1_RXN/USB31_1_RXN
ar
@ TGL-U_BGA1449
W
B
P5
P7
UC1H
PCIE4_TX_P_3
REV 1.6
PCIE4_TX_P_1
V5
V7
1P B
N1 PCIE4_TX_N_3 PCIE4_TX_N_1 T1
PCIE4_RX_P_3 PCIE4_RX_P_1
24
N2 T2
PCIE4_RX_N_3 PCIE4_RX_N_1
T5 Y5
T7 PCIE4_TX_P_2 PCIE4_TX_P_0 Y7
R1 PCIE4_TX_N_2 PCIE4_TX_N_0 V1
R2 PCIE4_RX_P_2 PCIE4_RX_P_0 V2
PCIE4_RX_N_2 PCIE4_RX_N_0
Y12 PCIE4_RCOMP_P RC225 1 2 2.2K_0201_1%
PCIE4_RCOMP_P V12 PCIE4_RCOMP_N
-L
PCIE4_RCOMP_N
@ TGL-U_BGA1449
LA
A A

P012 - TGL-U(7/13)PCIE,USB
1.0
5 4 3 2 1
5 4 3 2 1
UC1J
REV 1.6
D22 DK47
B22 CSI_F_DP_1 CNVI_WT_D1P DM47 CNV_CTX_DRX_P1 <52>
E22 CSI_F_DN_1 CNVI_WT_D1N DN49 CNV_CTX_DRX_N1 <52>
D20 CSI_F_DP_0 CNVI_WT_D0P DR49 CNV_CTX_DRX_P0 <52>
A20 CSI_F_DN_0 CNVI_WT_D0N DN45 CNV_CTX_DRX_N0 <52>
B20 CSI_F_CLK_P CNVI_WT_CLKP DN47 CLK_CNV_CTX_DRX_P <52>
CSI_F_CLK_N CNVI_WT_CLKN CLK_CNV_CTX_DRX_N <52>
D
B18
A18 CSI_E_DP_1/CSI_F_DP_2 CNVI_WR_D1P
DU43
DV43
CNV_CRX_DTX_P1 <52> CNVi D
CSI_E_DN_1/CSI_F_DN_2 CNVI_WR_D1N CNV_CRX_DTX_N1 <52>
D18 DR44 CNV_CRX_DTX_P0 <52>
E18 CSI_E_DP_0/CSI_F_DP_3 CNVI_WR_D0P DT43
CSI_E_DN_0/CSI_F_DN_3 CNVI_WR_D0N CNV_CRX_DTX_N0 <52>
C16 DV44 CLK_CNV_CRX_DTX_P <52>
D16 CSI_E_CLK_P CNVI_WR_CLKP DW44 +1.8V_PRIM
CSI_E_CLK_N CNVI_WR_CLKN CLK_CNV_CRX_DTX_N <52>
D15 DN51 CNV_WT_RCOMP RC226 1 2 150_0201_1%
E15 CSI_C_DP_2 CNVI_WT_RCOMP
A15 CSI_C_DN_2 DJ13 1.8V CNV_RGI_CRX_DTX CNV_BRI_CRX_DTX RC227 1 @ 2 20K_0201_5%
CSI_C_DP_3 GPP_F3/CNV_RGI_RSP/UART0_CTS# CNV_RGI_CTX_DRX CNV_RGI_CRX_DTX <52> CNV_RGI_CRX_DTX
B15 DG13 Strap Pin(1.8V) RC229 1 @ 2 20K_0201_5%
CSI_C_DN_3 GPP_F2/CNV_RGI_DT/UART0_TXD CNV_BRI_CRX_DTX CNV_RGI_CTX_DRX <52>
DF15 1.8V
CNV_BRI_CRX_DTX <52>
L18 GPP_F1/CNV_BRI_RSP/UART0_RXD DF17 Strap Pin(1.8V) CNV_BRI_CTX_DRX
CSI_C_DP_1 GPP_F0/CNV_BRI_DT/UART0_RTS# CNV_BRI_CTX_DRX <52>
N18
L20 CSI_C_DN_1 DJ10 CLKREQ_CNV#
A
N20 CSI_C_DP_0 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ DV15 CLKREQ_CNV# <52>
G20 CSI_C_DN_0 GPP_F6/CNV_PA_BLANKING DK10 1.8V CNV_RF_RESET#
H20 CSI_C_CLK_P
CSI_C_CLK_N
GPP_F4/CNV_RF_RESET# CNV_RF_RESET# <52> M.2 CNVI MODES
H16
G16 CSI_B_DP_1
G18 CSI_B_DN_1
H18 CSI_B_DP_0 GPP_F2/CNV_RGI_DT
L16 CSI_B_DN_0
N16 CSI_B_CLK_P CNV_RF_RESET# RC4122 1 2 75K_0201_1% 0 = INTEGRATED CNVI ENABLE
rn
CSI_B_CLK_N
G14 CLKREQ_CNV# RC4132 1 @ 2 10K_0201_5%
H14 CSI_B_DP_2 1 = INTEGRATED CNVI DISABLE
L14 CSI_B_DN_2 +1.8V_PRIM
N14 CSI_B_DP_3
CSI_B_DN_3
RC231 2 1 150_0201_1% CSI_RCOMP K14
CSI_RCOMP RW29 1 CNV@ 2 100K_0201_1%
tu
DK25
DM25 GPP_H23/IMGCLKOUT4 CNV_RGI_CTX_DRX RW30 1 @ 2 4.7K_0201_5%
DN25 GPP_H22/IMGCLKOUT3
DJ25 GPP_H21/IMGCLKOUT2
TP186 TP@ 1 PAD~D GPP_D4 DR30 GPP_H20/IMGCLKOUT1
GPP_D4/IMGCLKOUT_0/BK4/SBK4
@ TGL-U_BGA1449
XTAL SEL
C C
ck
GPP_F0/CNV_BRI_DT (Internal 20 K Pull Down)
0 = 38.4/19.2MHZ (DEFAULT)
1 = 24MHZ (25 MHZ WHEN XTAL FREQ
DIVIDER NON ZERO) +1.8V_PRIM
lo
EVT1_3
RW32 1 @ 2 4.7K_0201_5%
CNV_BRI_CTX_DRX RW33 1 @ 2 20K_0201_5%
ar
W
B
1P B
24
-L
LA
A A

P013 - TGL-U(8/13)CSI,CNVi
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K032P
5 4 3 2 1
5 4 3 2 1
+VCCIN
+VCCIN
D D
UC1M 2 2 2 2 2 2
REV 1.6
RF@
CC948
RF@
CC951
RF@
CC949
RF@
CC953
RF@
CC950
RF@
CC952
A24 G32
A26 VCCIN_1 VCCIN_66 H24
A29 VCCIN_2 VCCIN_67 H26 1 1 1 1 1 1
A30 VCCIN_3 VCCIN_68 H30
VCCIN_4 VCCIN_69
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
A33 H32
A35 VCCIN_5 VCCIN_70 J1
A
AY39 VCCIN_6 VCCIN_71 J2 1.The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).
B24 VCCIN_7 VCCIN_72 K1
VCCIN_8 VCCIN_73
2.Route the Alert signal between the Clock and the Data signals.
B26 K2 CAD Note: Place the PU resistors close to CPU
B33 VCCIN_11 VCCIN_76 K30 +1.05V_VCCST
VCCIN_12 VCCIN_77
rn
B35 K32
BA10 VCCIN_13
VCCIN_14
VCCIN_78
VCCIN_79
L24 RF Request
BA40 L26
VCCIN_15 VCCIN_80
1
BB39 L30
BB9 VCCIN_16
VCCIN_17
VCCIN_81
VCCIN_82
L32 SVID DATA RC232
BC10 N24 100_0201_5%
VCCIN_18 VCCIN_83
tu
BC40 N26
BD39 VCCIN_19 VCCIN_84 N30
2
BD9 VCCIN_20 VCCIN_85 N32
BE10 VCCIN_21 VCCIN_86 P24
BE40 VCCIN_22 VCCIN_87 P26 SOC_SVID_DAT 1 @ 2
VCCIN_23 VCCIN_88 VR_SVID_DATA <98>
BF9 P28 RC4069 0_0201_5%
BG10 VCCIN_24 VCCIN_89 P30
VCCIN_25 VCCIN_90
ck
C BG40 P32 C
BH12 VCCIN_26 VCCIN_91 T21 R-short 0409
BH39 VCCIN_27 VCCIN_92 T23
BH9 VCCIN_28 VCCIN_93 T25 +1.05V_VCCST
BJ10 VCCIN_29 VCCIN_94 T27
BJ40 VCCIN_30 VCCIN_95 T31
BK39 VCCIN_31 VCCIN_96 U23
lo
VCCIN_32 VCCIN_97
1
BL10 U27
BL40 VCCIN_33
VCCIN_34
VCCIN_98
VCCIN_99
U29 SVID ALERT# RC234
BM39 U31 56_0201_5%
BN40 VCCIN_35 VCCIN_100 U33
BP12 VCCIN_36 VCCIN_101 V23
2
VCCIN_37 VCCIN_102
ar
BP39 V25
BR10 VCCIN_38 VCCIN_103 V27
BR40 VCCIN_39 VCCIN_104 V29 SOC_SVID_ALERT# 1 @ 2
VCCIN_40 VCCIN_105 VR_SVID_ALERT# <98>
BT12 V31 RC4071 0_0201_5%
BT39 VCCIN_41 VCCIN_106 V33
BU10 VCCIN_42 VCCIN_107 W22
R-short 0409
W
BU40 VCCIN_43 VCCIN_108 W24
BV12 VCCIN_44 VCCIN_109 W28
BY12 VCCIN_45 VCCIN_110 W32 +1.05V_VCCST
Trace Length Match<25 mils
CA10 VCCIN_46 VCCIN_111
VCCIN_47
Must be routed as differential pair to VR
CB12 R38
D24 VCCIN_48 VCCIN_SENSE R37 VCC_SENSE_VCCIN <98>
VCCIN_49 VSSIN_SENSE VSS_SENSE_VCCIN <98>
1
D26
D29 VCCIN_50
VCCIN_51 VIDSOUT
M12 SOC_SVID_DAT SVID CLK RC238
D30
D33
D35
VCCIN_52
VCCIN_53
VIDSCK
VIDALERT#
M11
P12 1P
SOC_SVID_CLK
SOC_SVID_ALERT#
@ 43_0201_5%
2
B E24 VCCIN_54 B
E26 VCCIN_55
E27 VCCIN_56 SOC_SVID_CLK 1 @ 2
VCCIN_57 VR_SVID_CLK <98>
E29 RC4070 0_0201_5%
E30 VCCIN_58
24
E32 VCCIN_59
E33 VCCIN_60 R-short 0409 1
G2 VCCIN_61 CC32 @RF@
G24 VCCIN_62 33P_0201_50V8J
G26 VCCIN_63 2
G30 VCCIN_64
VCCIN_65
-L
@ TGL-U_BGA1449
LA
A A

P014 - TGL-U(9/13)CPU PWR,SVID
5 4 3 2 1
5 4 3 2 1
D D
+VCCSTG_OUT_FUSE +VCCFPGM +VCCSTG_OUT_FUSE

R-short 0409
Primary side Cap 1 @ 2
10x 1uF 0402 RC308 0_0402_1% 1
@
16x 10uF 0402 +VCCSTG_FUSE CC960
A
+1.2V_DDR 1 1U_0201_6.3V6M
2
2x 47uF 0603 +1.2V_DDR RC309
1 @ 2
0_0402_1%
@
CC129
1
1U_0201_6.3V6M
CC130
1U_0201_6.3V6M
2
1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6K
CC33
1U_0201_6.3V6K
CC34
1U_0201_6.3V6K
CC35
1U_0201_6.3V6K
CC36
1U_0201_6.3V6K
CC37
1U_0201_6.3V6K
CC38
1U_0201_6.3V6K
CC39
1U_0201_6.3V6K
CC40
1U_0201_6.3V6K
CC41
1U_0201_6.3V6K
CC42
47U_0603_6.3V6M
CC61
47U_0603_6.3V6M
CC62
UC1O
REV 1.6 2 @
AF9
2 2 2 2 2 2 2 2 2 2 2 2 VCCSTG_OUT_1
rn
AA39 AF12
AB40 VDD2_1 VCCSTG_1 AD12
AC39 VDD2_2 VCCSTG_2
AD40 VDD2_3 AN10
AD51 VDD2_4 VCCSTG_OUT_2 AM9
+1.2V_DDR AD52 VDD2_5 VCCSTG_OUT_3 AG10 +VCCIO_OUT
AE39 VDD2_6 VCCSTG_OUT_4
AF40 VDD2_7 V15 +VCCSTG_OUT_LGC +1.05V_VCCSTG
tu
AG39 VDD2_8 VCCIO_OUT
AH40 VDD2_9 M9 1 @ 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD2_10 VCCSTG_OUT_LGC Output
10U_0402_6.3V6M
CC51
10U_0402_6.3V6M
CC52
10U_0402_6.3V6M
CC53
10U_0402_6.3V6M
CC54
10U_0402_6.3V6M
CC55
10U_0402_6.3V6M
CC56
10U_0402_6.3V6M
CC57
10U_0402_6.3V6M
CC58
10U_0402_6.3V6M
CC59
10U_0402_6.3V6M
CC60
10U_0402_6.3V6M
CC954
10U_0402_6.3V6M
CC955
10U_0402_6.3V6M
CC956
10U_0402_6.3V6M
CC957
10U_0402_6.3V6M
CC958
10U_0402_6.3V6M
CC959
AJ39 RC240 0_0402_1%
AK40 VDD2_11 BT2
AK51 VDD2_12 VCCST_1 BT1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 AK52 VDD2_13 VCCST_2 BT4 R-short 0409
AL39 VDD2_14 VCCST_3
AM40 VDD2_15 BP2 +1.05V_VCCST
C VDD2_16 VCCSTG_3 C
ck
AN39 BP1
AP40 VDD2_17 VCCSTG_4 BP4
VDD2_18 VCCSTG_5 Input
AR39
AT52 VDD2_19
VDD2_20 1 1
1U_0201_6.3V6M
CC49
1U_0201_6.3V6M
CC50
AU40 +VCCSTG_CPU
AW40 VDD2_21
AW51 VDD2_22
VDD2_23 Input 2 2
AW52 @
BD51 VDD2_24
lo
VDD2_25 1 1
1U_0201_6.3V6M
CC63
1U_0201_6.3V6M
CC64
BD52
BK51 VDD2_26
BK52 VDD2_27
+1.2V_DDR BV51 VDD2_28 2 @ 2
EMC CAPS - PLACE <4MM FROM SOC VDDQ, WITH EACH PAIR <12MM APART BV52 VDD2_29
CA40 VDD2_30
VDD2_31
ar
CC40
CC49 VDD2_32
1 1 1 1 1 1 1 1 VDD2_33
12P_0201_25V8J
CC86 RF@
2.2P_0201_25V8C
CC87 RF@
12P_0201_25V8J
CC88 RF@
2.2P_0201_25V8C
CC89 RF@
12P_0201_25V8J
CC90 RF@
2.2P_0201_25V8C
CC91 RF@
12P_0201_25V8J
CC92 RF@
2.2P_0201_25V8C
CC93 RF@
CC50
CE40 VDD2_34
CG40 VDD2_35
2 2 2 2 2 2 2 2 CH39 VDD2_36
CJ40 VDD2_37
W
CL40 VDD2_38
CN40 VDD2_39
CP47 VDD2_40
CR40 VDD2_41
D50 VDD2_42
E51 VDD2_43
F49 VDD2_44
T51 VDD2_45
T52 VDD2_46
VDD2_47
B
1P @ TGL-U_BGA1449
B
24
-L
LA
A A

P015 - TGL-U(10/13)CPU PWR
1.0
5 4 3 2 1
5 4 3 2 1
+VCCIN_AUX +VCCIN_AUX
1
+3VLP RC782 2 2 2 2 2 2
100_0402_1%
RF@
CC936
RF@
CC937
RF@
CC938
RF@
CC939
RF@
CC940
RF@
CC941
2
1
1 1 1 1 1 1
RC783
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
100K_0201_5%
6
2KV
QC5A
D D
2 +VCCPRIM_1P8 +1.8V_PRIM
SB00001CW00
3
+3VALW_PCH
1
RC4164 1 2 0_0603_5%
QC5B
@
SB00001CW00
<58,90,95> 1.8V_PRIM_PG
5 RF Request
R-short 0409
1 1 1
4
1
1U_0201_6.3V6M
CC135
0.1U_0201_10V6K
CC136
0.01U_0201_10V6K
CC137
1M_0201_1%
RC738
A
+VCCIN_AUX +VCCPRIM_1P8
2 2 2 @
EVT1_23 UC1N
2
REV 1.6 1
1U_0201_6.3V6M
CC134
1.8V/32A AB12 CY18 1.8V/1.3A
AC10 VCCIN_AUX_1 VCCPRIM_1P8_1 CY20
AE10 VCCIN_AUX_2 VCCPRIM_1P8_2 CY24
VCCIN_AUX_3 VCCPRIM_1P8_3 2 Place near DA35 , DC28 , DD30
rn
AK2 CY26
AR10 VCCIN_AUX_4 VCCPRIM_1P8_4 DA18 @
AT12 VCCIN_AUX_5 VCCPRIM_1P8_5 DA20 +VCCA_CLKLDO_1P8 +1.8V_PRIM
AU10 VCCIN_AUX_6 VCCPRIM_1P8_6 DA22 LC1 @
AW10 VCCIN_AUX_7 VCCPRIM_1P8_7 DA24 0.68UH_UHP252012NF-R68M_3A_20%
BV1 VCCIN_AUX_8 VCCPRIM_1P8_8 DA26 1 2
BV39 VCCIN_AUX_9 VCCPRIM_1P8_9 DC18 1 @ 2
BW40 VCCIN_AUX_10 VCCPRIM_1P8_10 DC20 RC4068 0_0603_5% +VCCRTCEXT +VCCLDOSTD_OUT_0P85
tu
VCCIN_AUX_11 VCCPRIM_1P8_11
1
BY39 DC22
CC1 VCCIN_AUX_12 VCCPRIM_1P8_12 DC24 RC243
CD12 VCCIN_AUX_13 VCCPRIM_1P8_13 DC26 +3VALW_PCH 0_0402_1%
R-short 0409
CF10 VCCIN_AUX_14 VCCPRIM_1P8_14 DD20
VCCIN_AUX_15 VCCPRIM_1P8_15 1 1
0.1U_0201_10V6K
CC138
2.2U_0402_6.3V6K
CC139
CG12 DD22
2
CH10 VCCIN_AUX_16 VCCPRIM_1P8_16 DV22
VCCIN_AUX_17 VCCPRIM_1P8_17 +VCCA_CLKLDO_1P8_C
CJ1 1
VCCIN_AUX_18 2 2
47U_0603_6.3V6M
CC97
CJ12 DA35 3.3V/0.202A
C VCCIN_AUX_19 VCCPRIM_3P3_1 C
ck
CK10 DC28
CL12 VCCIN_AUX_20 VCCPRIM_3P3_2 DC30
CM10 VCCIN_AUX_21 VCCPRIM_3P3_3 DD30 +VCCRTCEXT 2
CP1 VCCIN_AUX_22 VCCPRIM_3P3_4 +VCCLDOSTD_OUT_0P85
CP10 VCCIN_AUX_23 DV34
CR12 VCCIN_AUX_24 DCPRTC
VCCIN_AUX_25 Place near DV34 Place near DV46
+V1.05A_BYPASS +VNN_BYPASS CT10 DV46
CU12 VCCIN_AUX_26 VCCLDOSTD_0P85
CY1 VCCIN_AUX_27 DV16 +VCCDPHY_1P24
lo
AK1 VCCIN_AUX_28 VCCA_CLKLDO_1P8_1 DC15
X01_5 VCCIN_AUX_29 VCCA_CLKLDO_1P8_2
1
1
100K_0201_5%
RC257
100K_0201_5%
RC4077
+VCCDSW_1P05 +VCCDPHY_1P24 +VCCDSW_1P05

AV9 DV28
<95> VSS_SENSE_AUX AT9 VCCIN_AUX_VSSSENSE VCCDPHY_1P24
<95> VCC_SENSE_AUX VCCIN_AUX_VCCSENSE DD38
@ @ DD17 VCCDSW_1P05
1 1
2
VCC_VNNEXT_1P05_1
ar
+VCCPRTC_3P3 +RTC_SOC
4.7U_0402_6.3V6M
CC94
1U_0201_6.3V6M
CC95
DD18 BR3
VCC_VNNEXT_1P05_2 VCC1P05_OUT_FET BR4 +VCC1.05_OUT_FET
VCC1P05_OUT_FET Place near DC35
DA15 BT5 1 @ 2
DA17 VCC_V1P05EXT_1P05_1 VCC1P05_OUT_FET RC246 0_0402_1% 2 2
VCC_V1P05EXT_1P05_2 1 1
1
0.1U_0201_10V6K
CC98
1U_0201_6.3V6M
CC99
100K_0201_5%
R6227
DA31
VRALERT#_R VCCPRIM_1P05_1 +VCC1.05_OUT_PCH
RC247 1 2 0_0201_5% VRALERT# DB39 DC33
TP187 1 TP@ PAD~D VNN_CTRL DV12 GPP_B2/VRALERT# VCCPRIM_1P05_2 DC31 R-short 0409
W
TP188 1 TP@ PAD~D V1P05_CTRL DT12 GPP_F22/VNN_CTRL VCCPRIM_1P05_3 +3VALW_DSW 2 2 @
GPP_F23/V1P05_CTRL DC35
2
RC4073 1 @ 2 0_0201_5% AUX_VID0_R DB37 VCCRTC DD37
<95> AUX_VID0 GPP_B0/CORE_VID0 VCCDSW_3P3 Place near DV28 Place near DD38
RC249 1 @ 2 0_0201_5% AUX_VID1_R DB38 DA28
<95> AUX_VID1 GPP_B1/CORE_VID1 VCCPGPPR ?
CY31
?
R-short 0409 VCCPRIM_3P3_5 CY33 +3VALW_PCH
VCCPRIM_3P3_6 CV39
VCCPRIM_1P8_18 +VCCPRIM_1P8
+3VALW_PCH
AP12 PAD~D 1 +VCCPGPPR_3P3_1P8 RC251 +3VALW_PCH
RSVD_1
B
RC311
RC312
1
1
@
@
2 100K_0201_5%
2 100K_0201_5%
AUX_VID0_R
AUX_VID1_R
1P @ TGL-U_BGA1449
TP192 TP@
2
Audio Power
CC100
0.1U_0201_10V6K
0_0402_1%
1
@
RC252
0_0402_1%
1
2
2
+VCCPRIM_1P8
B
24
+3VALW_PCH for Audio
1
RC258
100K_0201_5%
-L
2
DC5
VRALERT#_R 1 2
H_PROCHOT# <7,58,82,85,98>
RB751S-40_SOD523-2
+3VALW_DSW +3VALW_PCH
LA
RC4165 1 2 0_0402_5%
1
@
CC141
0.1U_0201_10V6K
2
Place near DD37
A A

P016 - TGL-U(11/13)PCH Power
1.0
5 4 3 2 1
5 4 3 2 1
UC1P UC1Q UC1R

D REV 1.6 REV 1.6 REV 1.6 D
A27 B19 BY44 CY44 DP53 K34
A32 VSS_223 VSS_289 B2 BY45 VSS_109 VSS_169 CY45 DR11 VSS_2 VSS_46 K48
A45 VSS_224 VSS_290 B23 BY47 VSS_110 VSS_170 CY47 DR16 VSS_3 VSS_47 K5
A49 VSS_225 VSS_291 B27 BY49 VSS_111 VSS_171 CY5 DR22 VSS_4 VSS_48 L22
AA41 VSS_226 VSS_292 B32 BY9 VSS_112 VSS_172 D27 DR28 VSS_5 VSS_49 L28
AA48 VSS_227 VSS_293 B36 C13 VSS_113 VSS_173 D32 DR34 VSS_6 VSS_50 L34
AB5 VSS_228 VSS_294 B39 C19 VSS_114 VSS_174 D36 DR40 VSS_7 VSS_51 L39
AB7 VSS_229 VSS_295 B42 C23 VSS_115 VSS_175 D42 DR46 VSS_8 VSS_52 L41
AB8 VSS_230 VSS_296 B48 CA48 VSS_116 VSS_176 D49 DT4 VSS_9 VSS_53 L42
A
AC44 VSS_231 VSS_297 B52 CB41 VSS_117 VSS_177 D5 DT50 VSS_10 VSS_54 L44
AC49 VSS_232 VSS_298 B8 CC10 VSS_118 VSS_178 DA30 DU11 VSS_11 VSS_55 L45
AD4 VSS_233 VSS_299 BA48 CC3 VSS_119 VSS_179 DA33 DU16 VSS_12 VSS_56 L47
AD48 VSS_234 VSS_300 BA53 CC5 VSS_120 VSS_180 DA53 DU22 VSS_13 VSS_57 L49
AD8 VSS_235 VSS_301 BB4 CD44 VSS_121 VSS_181 DC17 DU28 VSS_14 VSS_58 M1
AF4 VSS_236 VSS_302 BB8 CD48 VSS_122 VSS_182 DD15 DU34 VSS_15 VSS_59 M2
VSS_237 VSS_303 VSS_123 VSS_183 VSS_16 VSS_60
rn
AF8 BC1 CD7 DD24 DU40 M50
AG41 VSS_238 VSS_304 BC2 CE49 VSS_124 VSS_184 DD26 DU46 VSS_17 VSS_61 N22
AG42 VSS_239 VSS_305 BD12 CG48 VSS_125 VSS_185 DD28 DV1 VSS_18 VSS_62 N28
AG47 VSS_242 VSS_308 BD8 CG9 VSS_128 VSS_188 DD35 DW51 VSS_21 VSS_65 N41
tu
AG48 BF39 CH41 DD39 E13 N48
AG53 VSS_244 VSS_310 BF4 CH42 VSS_130 VSS_190 DD45 E19 VSS_23 VSS_67 P11
AH4 VSS_245 VSS_311 BF41 CH44 VSS_131 VSS_191 DD51 E35 VSS_24 VSS_68 P14
AH8 VSS_246 VSS_312 BF42 CH45 VSS_132 VSS_192 DD52 E48 VSS_25 VSS_69 P16
AK12 VSS_247 VSS_313 BF44 CH47 VSS_133 VSS_193 DE3 G22 VSS_26 VSS_70 P18
AK4 VSS_248 VSS_314 BF45 CJ3 VSS_134 VSS_194 DE5 G28 VSS_27 VSS_71 P20
AK48 VSS_249 VSS_315 BF47 CJ5 VSS_135 VSS_195 DF19 G34 VSS_28 VSS_72 P22
ck
C AK5 BF5 CJ9 DF37 G39 P33 C
AK7 VSS_251 VSS_317 BF7 CK39 VSS_137 VSS_197 DG15 G48 VSS_30 VSS_74 P35
AK8 VSS_252 VSS_318 BF8 CK48 VSS_138 VSS_198 DG21 G51 VSS_31 VSS_75 P4
AM1 VSS_253 VSS_319 BG48 CK53 VSS_139 VSS_199 DG27 G52 VSS_32 VSS_76 P49
AM2 VSS_254 VSS_320 BG53 CL9 VSS_140 VSS_200 DG33 H12 VSS_33 VSS_77 P8
AM4 VSS_255 VSS_321 BH1 CN12 VSS_141 VSS_201 DG39 H22 VSS_34 VSS_78 R39
AM8 VSS_256 VSS_322 BH2 CN48 VSS_142 VSS_202 DG45 H28 VSS_35 VSS_79 R44
lo
AN41 VSS_257 VSS_323 BH4 CN51 VSS_143 VSS_203 DG5 H34 VSS_36 VSS_80 T19
AN42 VSS_258 VSS_324 BH8 CN52 VSS_144 VSS_204 DG53 H8 VSS_37 VSS_81 T29
AN44 VSS_259 VSS_325 BK12 CN9 VSS_145 VSS_205 DG6 J39 VSS_38 VSS_82 T33
AN45 VSS_260 VSS_326 BK4 CP3 VSS_146 VSS_206 DJ1 J49 VSS_39 VSS_83 T4
AN47 VSS_261 VSS_327 BK48 CP41 VSS_147 VSS_207 DJ2 K16 VSS_40 VSS_84 T48
ar
AN48 BK8 CP42 DJ4 K18 T8
AN53 VSS_263 VSS_329 BL49 CP44 VSS_149 VSS_209 DK51 K20 VSS_42 VSS_86 U19
AP4 VSS_264 VSS_330 BM1 CP45 VSS_150 VSS_210 DL3 K22 VSS_43 VSS_87 U25
AP8 VSS_265 VSS_331 BM4 CP5 VSS_151 VSS_211 DL5 K28 VSS_44 VSS_88 U39
AT4 VSS_266 VSS_332 BM41 CR48 VSS_152 VSS_212 DM10 VSS_45 VSS_89 U49
AT48 VSS_267 VSS_333 BM42 CR53 VSS_153 VSS_213 DM15 VSS_90 V19
W
AT51 VSS_268 VSS_334 BM44 CR9 VSS_154 VSS_214 DM21 VSS_91 V4
AT8 VSS_269 VSS_335 BM45 CT5 VSS_155 VSS_215 DM27 VSS_92 V8
AV12 VSS_270 VSS_336 BM47 CU4 VSS_156 VSS_216 DM33 VSS_93 W1
AV39 VSS_271 VSS_337 BM8 CU9 VSS_157 VSS_217 DM39 VSS_94 W16
AV4 VSS_272 VSS_338 BN48 CV10 VSS_158 VSS_218 DM4 VSS_95 W26
AV5 VSS_273 VSS_339 BP41 CV48 VSS_159 VSS_219 DM45 VSS_96 W30
AV7 VSS_274 VSS_340 BP49 CV5 VSS_160 VSS_220 DN1 VSS_97 W39
AV8 VSS_275 VSS_341 BP5 CV51 VSS_161 VSS_221 DN2 VSS_98 W41
VSS_276 VSS_342 VSS_162 VSS_222 VSS_99
B
AW1
AW2
AW48
AY4
AY41
AY42
AY44
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
BP50
BP7
BT44
BT48
BU49
BV3
BV48
1P CV52
CY17
CY22
CY35
CY41
CY42
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
W42
W44
W45
W47
W48
Y4
Y49
B
AY45 VSS_283 VSS_349 BV5 VSS_106 Y50

24
AY47 VSS_284 VSS_350 BW10 @ TGL-U_BGA1449 VSS_107 Y8
AY8 VSS_285 VSS_351 BY41 VSS_108
AY9 VSS_286 VSS_352 BY42
B13 VSS_287 VSS_353 @ TGL-U_BGA1449
VSS_288
@ TGL-U_BGA1449
-L
LA
A A

P017 - TGL-U(12/13)GND
5 4 3 2 1
5 4 3 2 1
UC1S
D REV 1.6 D
DF53 C53
RSVD_19 RSVD_23 T35
DF52 RSVD_24 E53
RSVD_20 RSVD_25 CF39
1 PCH_IST_TP_1 DT52 RSVD_26 U35
PAD~D TP@ TP30 1 PCH_IST_TP_0 DU53 PCH_IST_TP_1 RSVD_27 F53
PAD~D TP@ TP31 PCH_IST_TP_0 RSVD_28 B53
DF50 RSVD_29 AP9
DF49 RSVD_21 RSVD_30 A52
A
RSVD_22 RSVD_31
1 RSVD_TP_25 CY30 BF12 RSVD_TP_28 1
TP33TP@ PAD~D
PAD~D TP@ TP32 1 RSVD_TP_26 CY15 RSVD_TP_25 RSVD_TP_28 V21 RSVD_TP_29 1
+1.8V_PRIM_CY15 (ES1 solution) RSVD_TP_26 RSVD_TP_29 RSVD_TP_30 TP35TP@ PAD~D
PAD~DTP@TP194 W20 1
RSVD_TP_27 RSVD_TP_30 RSVD_TP_31 TP36TP@ PAD~D
1 D4 U37 1
PAD~D TP@ TP37 RSVD_TP_27 RSVD_TP_31 RSVD_TP_32 TP38TP@ PAD~D
CD39 1
RSVD_TP_32 TP39TP@ PAD~D
rn
1 IST_TP_1 A6 U21 RSVD_TP_33 1
TP41TP@ PAD~D
PAD~D TP@ TP40 1 IST_TP_0 A4 IST_TP_1 RSVD_TP_33 CB39
PAD~D TP@ TP42 IST_TP_0 RSVD_32 BB12 RSVD_TP_34 1
RSVD_TP_34 RSVD_TP_35 TP43TP@ PAD~D
W37 1
AY12 1
W38 1
RSVD_TP_37 TP46TP@ PAD~D
tu
U38 RSVD_TP_38 1
CY28 1
RSVD_TP_39 TP193 PAD~D
TP@
+1.8V_PRIM_CY28 (ES1 solution)
@ TGL-U_BGA1449
ck
C C
lo
ES1 Workaround Circuit
ar
Intel Document Number: 614056
W
B
1P B
24
-L
LA
A A

P018 - TGL-U(13/13)RSVD
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
Reserve
ck
C C
lo
ar
W
B
1P B
24
-L
LA
A A
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
Reserve
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
Reserve
C C
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
Reserve
tu
C C
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Func = DDR4(1/2)

REVERSE TYPE (5.2 mm)
CHANNEL-M0
JDIMM2A
DDR_M0_CLK0 137 RVS 8 DDR_M0_D63
<8> DDR_M0_CLK0 DDR_M0_CLK#0 CK0(T) DQ0 DDR_M0_D58
139 7
<8> DDR_M0_CLK#0 DDR_M0_CLK1 CK0#(C) DQ1 DDR_M0_D56
Non-Interleaved Memory
138 20
<8> DDR_M0_CLK1 DDR_M0_CLK#1 CK1(T) DQ2 DDR_M0_D59
<8> DDR_M0_CLK#1 140 21
CK1#(C) DQ3 4 DDR_M0_D60
DDR_M0_CKE0 109 DQ4 3 DDR_M0_D62
BOT: DIMM1(JDIMM2 CONN) Non-ECC DIMM <8> DDR_M0_D[0..15]
<8>
<8>
DDR_M0_CKE0
DDR_M0_CKE1
DDR_M0_CKE1 110 CKE0
CKE1
DQ5
DQ6
DQ7
16
17
DDR_M0_D61
DDR_M0_D57
DDR_M0_CS#0 149 13 DDR_M0_DQS7
<8> DDR_M0_CS#0 DDR_M0_CS#1 S0# DQS0(T) DDR_M0_DQS#7 DDR_M0_DQS7 <8>
157 11
+3VS +3VS +3VS <8> DDR_M0_D[16..31] <8> DDR_M0_CS#1 S1# DQS0#(C) DDR_M0_DQS#7 <8>
162
165 S2#/C0 28 DDR_M0_D51
<8> DDR_M0_D[32..47] S3#/C1 DQ8 DDR_M0_D53
29
DQ9
1
1
D DDR_M0_ODT0 155 41 DDR_M0_D49 D
<8> DDR_M0_D[48..63] <8> DDR_M0_ODT0 DDR_M0_ODT1 ODT0 DQ10 DDR_M0_D54
RD1 RD2 RD3 161 42
<8> DDR_M0_ODT1 ODT1 DQ11 DDR_M0_D48
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% 24
JDIMM2B DDR_M0_BG0 115 DQ12 25 DDR_M0_D52
<8> DDR_M0_BG0 DDR_M0_BG1 BG0 DQ13 DDR_M0_D55
RVS 113 38
<8> DDR_M0_BG1
2
2
SA0_CHA_DIM1 SA1_CHA_DIM1 SA2_CHA_DIM1 111 141 DDR_M0_BA0 150 BG1 DQ14 37 DDR_M0_D50
+1.2V_DDR 112 VDD1 VDD11 142
+1.2V_DDR <8> DDR_M0_BA0 DDR_M0_BA1 145 BA0 DQ15 34 DDR_M0_DQS6
VDD2 VDD12 <8> DDR_M0_BA1 BA1 DQS1(T) DDR_M0_DQS#6 DDR_M0_DQS6 <8>
117 147 32
VDD3 VDD13 DQS1#(C) DDR_M0_DQS#6 <8>
1
1
118 148 DDR_M0_MA0 144
VDD4 VDD14 <8> DDR_M0_MA0 DDR_M0_MA1 A0 DDR_M0_D45
RD4 RD5 RD6 123 153 133 50
VDD5 VDD15 <8> DDR_M0_MA1 DDR_M0_MA2 A1 DQ16 DDR_M0_D47
0_0402_5% 0_0402_5% 0_0402_5% 124 154 132 49
129 159 131 62
130 160 128 63
<8> DDR_M0_MA4
2
2
135 VDD8 VDD18 163 DDR_M0_MA5 126 A4 DQ19 46 DDR_M0_D44
A
+3VS VDD9 VDD19 <8> DDR_M0_MA5 DDR_M0_MA6 A5 DQ20 DDR_M0_D46
136 127 45
VDD10 <8> DDR_M0_MA6 DDR_M0_MA7 A6 DQ21 DDR_M0_D42
122 58
<8> DDR_M0_MA7 DDR_M0_MA8 A7 DQ22 DDR_M0_D43
255 258 125 59
VDDSPD VTT +0.6V_DDR_VTT <8> DDR_M0_MA8 DDR_M0_MA9 121 A8 DQ23 55 DDR_M0_DQS5
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM <8> DDR_M0_MA9 DDR_M0_MA10 A9 DQS2(T) DDR_M0_DQS#5 DDR_M0_DQS5 <8>
0.1U_0201_10V6K
2.2U_0201_6.3V6M
164 257 146 53
+0.6V_DDRA_VREFCA VREFCA VPP1 259
+2.5V_MEM <8> DDR_M0_MA10 DDR_M0_MA11 120 A10_AP DQS2#(C) DDR_M0_DQS#5 <8>
2 2 VPP2 <8> DDR_M0_MA11 A11
DDR_M0_MA12 119 70 DDR_M0_D36
CD2
CD1
1 99 158 71
VSS VSS <8> DDR_M0_MA13 DDR_M0_MA14_WE# A13 DQ25 DDR_M0_D33
2 102 151 83
SPD ADDRESS FOR CHANNEL A : 1 1 5 VSS VSS 103
<8> DDR_M0_MA14_WE# DDR_M0_MA15_CAS# 156 A14_WE# DQ26 84 DDR_M0_D35
rn
VSS VSS <8> DDR_M0_MA15_CAS# DDR_M0_MA16_RAS# A15_CAS# DQ27 DDR_M0_D39
6 106 152 66
VSS VSS <8> DDR_M0_MA16_RAS# A16_RAS# DQ28 DDR_M0_D37
9 107 67
10 VSS VSS 167 DDR_M0_ACT# 114 DQ29 79 DDR_M0_D34
SA0 = 0; SA1 = 0; SA2 = 0. PLACE NEAR TO PIN 14
15
VSS
VSS
VSS
VSS
168
171
+1.2V_DDR <8> DDR_M0_ACT#
DDR_M0_PAR 143
ACT# DQ30
DQ31
80
76
DDR_M0_D32
DDR_M0_DQS4
VSS VSS <8> DDR_M0_PAR DDR_M0_ALERT# PARITY DQS3(T) DDR_M0_DQS#4 DDR_M0_DQS4 <8>
18 172 116 74
VSS VSS <8> DDR_M0_ALERT# DIMM1_M0_EVENT# ALERT# DQS3#(C) DDR_M0_DQS#4 <8>
19 175 RD7 2 1 134
22 VSS VSS 176 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_M0_D11
<8,24> DDR_DRAMRST#_R
tu
23 VSS VSS 180 RESET# DQ32 173 DDR_M0_D10
26 VSS VSS 181 DQ33 187 DDR_M0_D14
27 VSS VSS 184 PCH_SMBDATA 254 DQ34 186 DDR_M0_D8
VSS VSS <9,24> PCH_SMBDATA PCH_SMBCLK SDA DQ35 DDR_M0_D12
30 185 253 170
VSS VSS <9,24> PCH_SMBCLK SCL DQ36 DDR_M0_D9
31 188 169
35 VSS VSS 189 SA2_CHA_DIM1 166 DQ37 183 DDR_M0_D15
36 VSS VSS 192
To SOC SA1_CHA_DIM1 260 SA2 DQ38 182 DDR_M0_D13
39 VSS VSS 193 SA0_CHA_DIM1 256 SA1 DQ39 179 DDR_M0_DQS1
VSS VSS SA0 DQS4(T) DDR_M0_DQS#1 DDR_M0_DQS1 <8>
40 196 177
VSS VSS DQS4#(C) DDR_M0_DQS#1 <8>
43 197
C VSS VSS DDR_M0_D5 C
44 201 92 195
ck
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_M0_D7
+1.2V_DDR 52 VSS VSS 209 88 CB3_NC DQ43 191 DDR_M0_D6
56 VSS VSS 210 +1.2V_DDR 87 CB4_NC DQ44 190 DDR_M0_D4
DIMM Side CPU Side 61
64
VSS
VSS
VSS
VSS
VSS
VSS
217
218
RD25 2
RD26 2
@
@
1 240_0402_1%
1 240_0402_1%
97
95
CB7_NC
DQS8(T)
DQS8#(C)
DQ47
DQS5(T)
DQS5#(C)
200
198
DDR_M0_DQS0
DDR_M0_DQS#0 DDR_M0_DQS0
DDR_M0_DQS#0
<8>
<8>
2
lo
65 222
RD9 +0.6V_DDRA_VREFCA +V_DDR_REFA_R 68 VSS VSS 223 216 DDR_M0_D31
69 VSS VSS 226 12 DQ48 215 DDR_M0_D24
1K_0402_1% +1.2V_DDR
72 VSS VSS 227 33 DM0#/DBI0# DQ49 228 DDR_M0_D26
1

1 RD10 2
VREF traces should be at least 20 mils 81 VSS VSS 235 199 DM4#/DBI4# DQ53 224 DDR_M0_D25
wide with 20 mils spacing to other VSS VSS DM5#/DBI5# DQ54
ar
2_0402_1% 82 238 DDR_DRAMRST#_R 220 225 DDR_M0_D28
85 VSS VSS 239 241 DM6#/DBI6# DQ55 221 DDR_M0_DQS3
1 signals 86 VSS VSS 243 96 DM7#/DBI7# DQS6(T) 219 DDR_M0_DQS#3 DDR_M0_DQS3 <8>
VSS VSS DM8#/DBI8# DQS6#(C) DDR_M0_DQS#3 <8>
2
CD5 89 244 2
RD11 0.022U_0201_25V6K 90 VSS VSS 247 CD3
2 93 VSS VSS 248 0.1U_0201_10V6K
1K_0402_1%
94 VSS VSS 251 @ESD@ 237 DDR_M0_D17
VSS VSS DQ56
2
98 252 1 236 DDR_M0_D23

1
W
RD12 VSS VSS DQ57 249 DDR_M0_D20
Follow 573129_ICL_U_DDR4_SODIMM_HW_SCH_Rev1P0 DQ58
24.9_0402_1% 262 261 250 DDR_M0_D18
GND GND DQ59 232 DDR_M0_D21
DQ60 233 DDR_M0_D19
1
DEREN_40-42271-26001RHF DQ61 245 DDR_M0_D22

CONN@ PLACE NEAR TO SODIMM DQ62
DQ63
246 DDR_M0_D16
242 DDR_M0_DQS2
SP07001CY0L DQS7(T) DDR_M0_DQS#2 DDR_M0_DQS2 <8>
240
DQS7#(C) DDR_M0_DQS#2 <8>
DEREN_40-42271-26001RHF
B
Decopling Cap._Channel A
1P +1.2V_DDR
Part Number:SP07001JH00
CONN@
SP07001CY0L
Part Value:S SOCKET LOTES ADDR0208-P001A 260P DDR4

B
@EMI@
@EMI@
@EMI@
@EMI@
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
Layout Note: Layout Note: Layout Note: 2 2 2 2
Place near JDIMM2.257,259 Place near JDIMM2.258 PLACE THE CAP near JDIMM2. 164
C107 place near JDIMM2
24
1 1 1 1
CD43
CD44
CD45
CD46
+0.6V_DDR_VTT
+2.5V_MEM +0.6V_DDR_VTT +0.6V_DDRA_VREFCA
2.2uF *1
10uF *1 10uF *1+1uF *2 0.1uF *1
1uF *1
10P_0201_25V8
C107
@RF@
1 Follow Intel RVP

2 2
10U_0402_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1
CD24 @ CD25
2
-L
CD47
CD48
CD49
CD51
CD52
0.1U_0201_10V6K 2.2U_0201_6.3V6M
1 1
2 2 2 2 2
EMC CAPS-PLACE
< 4mm from SO-DIMM VDDQ
with each pair < 12mm Apart
LA
12pF* 5 (EMI@)
2.2pF* 5 (EMI@)
Layout Note: +1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR

Place near JDIMM2
1 1 1 1 1 1 1 1 1 1
follow RVP 1p0
EMI@ CD3853
EMI@ CD3854
EMI@ CD3851
EMI@ CD3852
EMI@ CD3845
EMI@ CD3846
EMI@ CD3847
EMI@ CD3848
EMI@ CD3849
EMI@ CD3850
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
A
10uF*8 A
+1.2V_DDR 1uF*8 +1.2V_DDR 2 2 2 2 2 2 2 2 2 2
@330uF*1
POP
EMI@
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
UNPOP
CD57
CD58
CD59
CD60
CD61
CD62
CD63
CD64
CD65
CD66
CD67
CD68
CD69
CD70
CD71
CD72
delete CD3856
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @EMI@\@ESD@\@RF@\CONN@\@

DDR4_CHM0: DIMM0
1.0
5 4 3 2 1
5 4 3 2 1
Main Func = DDR4(2/2)
CHANNEL-M1 STD (5.2 mm)

BOT: DIMM2(JDIMM1 CONN) Non-ECC DIMM Non-Interleaved Memory <8> DDR_M1_CLK0
<8> DDR_M1_CLK#0
DDR_M1_CLK0
DDR_M1_CLK#0
DDR_M1_CLK1
137
139
138
JDIMM1A
CK0(T)
CK0#(C)
RVS
DQ0
DQ1
8
7
20
DDR_M1_D42
DDR_M1_D47
DDR_M1_D45
<8> DDR_M1_D[0..15] <8> DDR_M1_CLK1 DDR_M1_CLK#1 CK1(T) DQ2 DDR_M1_D43
140 21
+3VS +3VS +3VS <8> DDR_M1_CLK#1 CK1#(C) DQ3 DDR_M1_D41
4
<8> DDR_M1_D[16..31] DDR_M1_CKE0 DQ4 DDR_M1_D40
109 3
<8> DDR_M1_CKE0 DDR_M1_CKE1 CKE0 DQ5 DDR_M1_D46
110 16
<8> DDR_M1_D[32..47] <8> DDR_M1_CKE1
1
1
CKE1 DQ6 17 DDR_M1_D44
RD13 RD14 RD15 DDR_M1_CS#0 149 DQ7 13 DDR_M1_DQS5
<8> DDR_M1_D[48..63] <8> DDR_M1_CS#0 DDR_M1_CS#1 S0# DQS0(T) DDR_M1_DQS#5 DDR_M1_DQS5 <8>
@ 0_0201_5% 0_0201_5% @ 0_0201_5% 157 11
<8> DDR_M1_CS#1 S1# DQS0#(C) DDR_M1_DQS#5 <8>
JDIMM1B 162
D RVS 165 S2#/C0 28 DDR_M1_D34 D
2
2
SA0_CHB_DIM2 SA1_CHB_DIM2 SA2_CHB_DIM2 111 141 S3#/C1 DQ8 29 DDR_M1_D36
+1.2V_DDR 112 VDD1 VDD11 142
+1.2V_DDR DDR_M1_ODT0 155 DQ9 41 DDR_M1_D32
VDD2 VDD12 <8> DDR_M1_ODT0 DDR_M1_ODT1 ODT0 DQ10 DDR_M1_D37
117 147 161 42
VDD3 VDD13 <8> DDR_M1_ODT1 ODT1 DQ11
1
1
118 148 24 DDR_M1_D35
RD16 RD17 RD18 123 VDD4 VDD14 153 DDR_M1_BG0 115 DQ12 25 DDR_M1_D33
VDD5 VDD15 <8> DDR_M1_BG0 DDR_M1_BG1 BG0 DQ13 DDR_M1_D38
0_0201_5% @ 0_0201_5% 0_0201_5% 124 154 113 38
VDD6 VDD16 <8> DDR_M1_BG1 DDR_M1_BA0 BG1 DQ14 DDR_M1_D39
129 159 150 37
VDD7 VDD17 <8> DDR_M1_BA0 DDR_M1_BA1 BA0 DQ15 DDR_M1_DQS4
130 160 145 34
<8> DDR_M1_BA1 DDR_M1_DQS4 <8>
2
2
135 VDD8 VDD18 163 BA1 DQS1(T) 32 DDR_M1_DQS#4
+3VS VDD9 VDD19 DDR_M1_MA0 DQS1#(C) DDR_M1_DQS#4 <8>
136 144
VDD10 <8> DDR_M1_MA0 DDR_M1_MA1 A0 DDR_M1_D58
133 50
255 258 132 49
VDDSPD VTT +0.6V_DDR_VTT <8> DDR_M1_MA2 DDR_M1_MA3 131 A2 DQ17 62 DDR_M1_D60
A
0.1U_0201_10V6K
2.2U_0201_6.3V6M
164 257 128 63
+0.6V_DDRB_VREFCA VREFCA VPP1 259 +2.5V_MEM <8> DDR_M1_MA4 DDR_M1_MA5 126 A4 DQ19 46 DDR_M1_D59
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM 2 2 VPP2 <8> DDR_M1_MA5 DDR_M1_MA6 127 A5 DQ20 45 DDR_M1_D61
CD7
CD8
1 99 122 58
VSS VSS <8> DDR_M1_MA7 DDR_M1_MA8 A7 DQ22 DDR_M1_D56
2 102 125 59
1 1 VSS VSS <8> DDR_M1_MA8 DDR_M1_MA9 A8 DQ23 DDR_M1_DQS7
5 103 121 55
SPD ADDRESS FOR CHANNEL B : 6 VSS
VSS
VSS
VSS
106
<8>
<8>
DDR_M1_MA9
DDR_M1_MA10
DDR_M1_MA10
DDR_M1_MA11
146 A9
A10_AP
DQS2(T)
DQS2#(C)
53 DDR_M1_DQS#7 DDR_M1_DQS7
DDR_M1_DQS#7
<8>
<8>
9 107 120
VSS VSS <8> DDR_M1_MA11 DDR_M1_MA12 A11 DDR_M1_D54
10 167 119 70
<8> DDR_M1_MA12
PLACE NEAR TO PIN 14 VSS VSS 168 DDR_M1_MA13 158 A12 DQ24 71 DDR_M1_D49
rn
SA0 = 0; SA1 = 1; SA2 = 0. 15
18
VSS
VSS
VSS
VSS
171
172
<8>
<8>
DDR_M1_MA13
DDR_M1_MA14_WE#
DDR_M1_MA14_WE#
DDR_M1_MA15_CAS#
151
156
A13
A14_WE#
DQ25
DQ26
83
84
DDR_M1_D52
DDR_M1_D50
VSS VSS <8> DDR_M1_MA15_CAS# DDR_M1_MA16_RAS# A15_CAS# DQ27 DDR_M1_D55
19 175 152 66
VSS VSS <8> DDR_M1_MA16_RAS# A16_RAS# DQ28 DDR_M1_D51
22 176 67
23 VSS VSS 180 DDR_M1_ACT# 114 DQ29 79 DDR_M1_D53
VSS VSS +1.2V_DDR <8> DDR_M1_ACT# ACT# DQ30 DDR_M1_D48
26 181 80
27 VSS VSS 184 DDR_M1_PAR 143 DQ31 76 DDR_M1_DQS6
VSS VSS <8> DDR_M1_PAR DDR_M1_ALERT# PARITY DQS3(T) DDR_M1_DQS#6 DDR_M1_DQS6 <8>
30 185 116 74
<8> DDR_M1_ALERT# DDR_M1_DQS#6 <8>
tu
31 VSS VSS 188 RD19 2 1 DIMM2_M2_EVENT# 134 ALERT# DQS3#(C)
35 VSS VSS 189 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_M1_D8
VSS VSS <8,23> DDR_DRAMRST#_R RESET# DQ32 DDR_M1_D14
36 192 173
39 VSS VSS 193 DQ33 187 DDR_M1_D10
40 VSS VSS 196 PCH_SMBDATA 254 DQ34 186 DDR_M1_D12
VSS VSS <9,23> PCH_SMBDATA PCH_SMBCLK SDA DQ35 DDR_M1_D15
43 197 253 170
VSS VSS <9,23> PCH_SMBCLK SCL DQ36 DDR_M1_D13
44 201 169
47 VSS VSS 202 SA2_CHB_DIM2 166 DQ37 183 DDR_M1_D9
48 VSS VSS 205 To SOC SA1_CHB_DIM2 260 SA2 DQ38 182 DDR_M1_D11
+1.2V_DDR 51 VSS VSS 206 SA0_CHB_DIM2 256 SA1 DQ39 179 DDR_M1_DQS1
C VSS VSS SA0 DQS4(T) DDR_M1_DQS#1 DDR_M1_DQS1 <8> C
52 209 177
ck
VSS VSS DQS4#(C) DDR_M1_DQS#1 <8>
56 210
57 VSS VSS 213 92 195 DDR_M1_D7
68 VSS VSS 223 +1.2V_DDR 87 CB4_NC DQ44 190 DDR_M1_D5
DIMM Side CPU Side
2

VSS VSS CB7_NC DQ47
lo
RD21 73 230 RD27 2 @ 1 240_0402_1% 97 200 DDR_M1_DQS0
VSS VSS DQS8(T) DQS5(T) DDR_M1_DQS#0 DDR_M1_DQS0 <8>
1K_0402_1% 77 231 RD28 2 @ 1 240_0402_1% 95 198
+0.6V_DDRB_VREFCA +V_DDR_REFB_R VSS VSS DQS8#(C) DQS5#(C) DDR_M1_DQS#0 <8>
78 234
81 VSS VSS 235 216 DDR_M1_D30
1
82 VSS VSS 238 12 DQ48 215 DDR_M1_D26

85 VSS VSS 239
+1.2V_DDR 33 DM0#/DBI0# DQ49 228 DDR_M1_D29
1 RD22 2 86 VSS VSS 243 54 DM1#/DBI1# DQ50 229 DDR_M1_D25
2_0402_1% 89 VSS VSS 244 75 DM2#/DBI2# DQ51 211 DDR_M1_D27
VREF traces should be at least 20 mils VSS VSS DM3#/DBI3# DQ52
ar
90 247 178 212 DDR_M1_D31
wide with 20 mils spacing to other 93 VSS
VSS
VSS
VSS
248 DDR_DRAMRST#_R 199 DM4#/DBI4#
DM5#/DBI5#
DQ53
DQ54
224 DDR_M1_D28
2
94 251 220 225 DDR_M1_D24

RD23
1 signals 98 VSS VSS 252 241 DM6#/DBI6# DQ55 221 DDR_M1_DQS3
VSS VSS DM7#/DBI7# DQS6(T) DDR_M1_DQS#3 DDR_M1_DQS3 <8>
1K_0402_1% CD12 2 96 219
0.022U_0201_25V6K DM8#/DBI8# DQS6#(C) DDR_M1_DQS#3 <8>
262 261 CD9
2 GND GND 0.1U_0201_10V6K
1
@ESD@
W
2
DEREN_40-42271-26001RHF 1 237 DDR_M1_D21

RD24 DQ56 236 DDR_M1_D17
CONN@ Follow 573129_ICL_U_DDR4_SODIMM_HW_SCH_Rev1P0 DQ57
24.9_0402_1% 249 DDR_M1_D16
SP07001CY0L DQ58 250 DDR_M1_D20
DQ59 232 DDR_M1_D19
1
DQ60 233 DDR_M1_D23

DQ61 245 DDR_M1_D18
PLACE NEAR TO SODIMM DQ62 246 DDR_M1_D22
DQ63 242 DDR_M1_DQS2
DQS7(T) DDR_M1_DQS#2 DDR_M1_DQS2 <8>
240
DQS7#(C) DDR_M1_DQS#2 <8>
B Decopling Cap._Channel B
Layout Note:
1P Part Number:SP07001HY00
DEREN_40-42271-26001RHF
CONN@
SP07001CY0L
Part Value:S SOCKET LOTES ADDR0207-P001A 260P DDR4

B
Layout Note: Layout Note: PLACE THE CAP WITHIN 200 MILS
Place near JDIMM1.257,259 Place near JDIMM1.258 FROM THE JDIMM1
24
08/30
Update Table 4-26 for DDR4 SO-DIMM Decoupling Caps
572907_ICL_UY_PDG_Rev0p7 Page.99
+2.5V_MEM 10uF *1 +0.6V_DDR_VTT 10uF *1+1uF *2 +0.6V_DDRB_VREFCA

2.2uF *1
1uF *1 0.1uF *1
2 2
1U_0201_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1
-L
10U_0402_6.3V6M
CD55 @ CD56
CD14
CD16
CD18
CD20
CD21
0.1U_0201_10V6K 2.2U_0201_6.3V6M
1 1
2 2 2 2 2
LA
C108 place near JDIMM1

+0.6V_DDR_VTT
Layout Note:
10P_0201_25V8
C108
@RF@
Place near JDIMM1 1
2
follow RVP 1p0
A A
10uF*8
+1.2V_DDR 1uF*8 +1.2V_DDR
@330uF*1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD26
CD27
CD28
CD29
CD30
CD31
CD32
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD41
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

DDR4_CHM1: DIMM1
1.0
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
ck
Reserve
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
Reserve
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
1 2 3 4 5
Main Func = GPU
A A
A
rn
tu
B B
ck
lo
ar
W
C
1P C
24
-L
LA
D D

NV(1/5)-PCIE
1.0
1 2 3 4 5
1 2 3 4 5
Main Func = GPU
A A
A
rn
tu
B B
ck
lo
ar
W
C
1P C
24
-L
LA
D D

NV(2/5)-IFP_ABCDEF_DAC_XTAL
1.0
1 2 3 4 5
1 2 3 4 5
Main Func = GPU
A A
A
rn
tu
B B
ck
lo
ar
W
C
1P C
24
-L
LA
D D

NV(3/5)-POWER
1.0
1 2 3 4 5
1 2 3 4 5
Main Func = GPU
A A
A
rn
tu
B B
ck
lo
ar
W
C
1P C
24
-L
LA
D D

NV(4/5)-GPIO/Strap
1 2 3 4 5
1 2 3 4 5
Main Func = GPU
A A
A
rn
tu
B B
ck
lo
ar
W
C
1P C
24
-L
LA
D D

NV(5/5)-MEMORY FBA
1.0
1 2 3 4 5
5 4 3 2 1
D D
A
rn
tu
Reserve
ck
C C
lo
ar
W
B
1P B
24
-L
LA
A A

Reserve
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
Reserve
ck
C C
lo
ar
W
B
1P B
24
-L
LA
A A

SMbus Block Diagram
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
Reserve
ck
C C
lo
ar
W
B
1P B
24
-L
LA
A A

SMbus Block Diagram
5 4 3 2 1
5 4 3 2 1
Main Func = VRAM
D D
A
rn
tu
C C
ck
lo
ar
W
B
1P B
24
-L
LA
A A

N17S_GDDR5_A
1.0
5 4 3 2 1
5 4 3 2 1
Main Func = VRAM
D D
A
rn
tu
C C
ck
lo
ar
W
B
1P B
24
-L
LA
A A

N17S_GDDR5_B
1.0
5 4 3 2 1
5 4 3 2 1
Main Func = GPU DC
D D
A
rn
tu
C C
ck
lo
ar
W
B
1P B
24
-L
LA
A A

DGPU_DC/DC Interface
5 4 3 2 1
5 4 3 2 1
Main Func = LCD +3VS

Main Func = CAM&MIC, TS
Pin 5,6,9 Cable side NC
R90
1 @ 2 LCD_CBL_DET#
10K_0402_5% INVERTER POWER TCH@ -->Touch Screen
Pin 4 for 17" CAMERA
CONN@ JEDP1 +19VB +DCBAT_LCD
@RF@ --> RF
1
+DCBAT_LCD
60 mils DMIC_CLK_EDP
I2CTCH@ --> I2C Touch Screen Delete 3V Cam Fuse
1 2 +LCDVDD_LCD F1
2 3
3 4 60 mils 1 2 DMIC_DATA_EDP
USBTCH@ --> USB Touch Screen
4 5
10P_0201_25V8
C105
@RF@
RF@ 1.5A_24V_SMD1812P150TF-24 1 1
5 6
1
LCD_TST_C C5 C6
6 7 1 1
2
DBC_PANEL_EN_R
0.1U_0402_16V7K
1U 6.3V M X5R 0201
10P_0402_50V8J
@
+3VS_CAM
7 8 EDP_HPD
C7
C8
C9
0.1U_0402_50V7K
1000P_0402_50V7K
Delete USB touch Fuse
2
8 9 EDP_HPD <6> 2 2
C105 place near JEDP1
2
9 10 LCD_CBL_DET# 2 2
10 11 LCD_CBL_DET# <10> 1
EDP_AUXP_C @RF@
D 11 12 EDP_AUXN_C Delete I2C touch Fuse Delete +MIC_VCC PWR rail C102 D
12 13 ED4 10P_0201_25V8
1
13 14 EDP_TXN0_C CEST523NC5VB_SOT-523-3 2
14 15 EDP_TXP0_C +LCDVDD_LCD +LCDVDD @ESD@
15 16
16 17 EDP_TXN1_C @EMI@
17 18 EDP_TXP1_C 33P_0201_50V8J 2 1 C42 TOUCH_SCREEN_RST_LCD 1 2
18 19 R8 0_0603_5%
19 20 C102: colse to JEDP1
EDP_TXN2_C @EMI@
20 21 EDP_TXP2_C 33P_0201_50V8J 2 1 C40 DMIC_DATA_EDP Non-TCH -->R81, R82, F5 unpop
21 22 @EMI@ D3
22 23 EDP_TXN3_C DMIC_CLK_EDP
EE note: Never change R8 to short pad after MP
33P_0201_50V8J 2 1 C41
23 24 EDP_TXP3_C 1 2 RB551V-30_SOD323-2
A
24 25 BLON_OUT_C <58,66> LID_CL_SIO#
25 26 LCD_BRIGHTNESS DMIC_DATA_EDP R6243 1 2 0_0201_5% DMIC_DATA_CODEC to Codec
26 27 DMIC_CLK_EDP R6244 1 2 0_0201_5% DMIC_CLK_CODEC DMIC_DATA_CODEC <56> R14
27 28 TOUCH_SCREEN_INT#_LCD <10> DMIC_CLK_CODEC <56> TS_EN 1 2
28 29 TOUCH_SCREEN_RST_LCD
+3VS_CAM
<10>
R6245 1 @ 2 0_0201_5% DMIC_PCH_DATA TOUCH_SCREEN 1 33_0402_5%
TOUCH_SCREEN_PD# <7,10>
29 30 DMIC_CLK_EDP R6246 1 @ 2 0_0201_5% DMIC_PCH_CLK DMIC_PCH_DATA <10>
30 31 DMIC_DATA_EDP DMIC_PCH_CLK <10>
C18 @
31 32
32 33 USB20_N6_R 1 2 BKLT_CTRL to PCH 2
10P_0402_50V8J
rn
33 34 USB20_P6_R R75 1 2 100K_0402_5% BLON_OUT_D9
34 35 DPST_EN R76 100K_0402_5%
35 36 I2C_0_LCD_SDA DPST_EN <10> 1 2
@
36 37 I2C_0_LCD_SCL I2C_0_LCD_SDA <10>
R11 0_0201_5%
41
37 38
38 39
TS_DET#
TS_EN
I2C_0_LCD_SCL <10>
TS_DET# <7> D2
Brightness
Main Func = Hinge up protection
42 GND1 39 40 2
GND2 40 +TS_VDD EDP_BKLT_CTRL <6>
tu
TWVM_FPC0518-40RC-TAGHA LCD_BRIGHTNESS 1 2 BKLT_CTRL 1
SP01002NV00 R79 100_0402_5% +LCDVDD
3 LCD_TST
LCD_TST_C 1 2 LCD_TST LCD_TST <58>
+3VALW
R80 100_0402_5% +LCDVDD
BAT54CW_SOT323-3
JEDP1 need to update 1 @ 2
2
CABLE2_OCP#
CABLE2_OCP# <58>
1U_0201_6.3V6M
R790 0_0201_5% C350
C955
10U_0402_6.3V6M
R-short 0409 D9 1
U4 ICPRO@ ICPRO@ 1
Backlight
ck
C 2 1 10 C
1 2 DBC_PANEL_EN_R PANEL_BKEN_EC <58> IN1 OUT1
<10> DBC_PANEL_EN R13 @ 0_0201_5% ICPRO@ ICPRO@
BLON_OUT_C 1 2 BLON_OUT_D9 1 2 +3VALW LCDVDD_EN 2 9 CABLE1_OCP# R33 1 2 0_0201_5% CABLE2_OCP#
R78 100_0402_5% EN1 FLAG1
3 3 8
<6> EDP_TXN0 C12 1 2 0.1U_0201_16V6K EDP_TXN0_C BKLT_IN_EDP <6> VB GND to EC ICPRO@
C13 1 2 0.1U_0201_16V6K EDP_TXP0_C SIO_SLP_S3# 4 7 CABLE2_OCP#_R R34 1 2 0_0201_5% CABLE2_OCP#
<6> EDP_TXP0 BAT54CW_SOT323-3 <11,78> SIO_SLP_S3# EN2 FLAG2
1U_0201_6.3V6M
C956
1 5 6
lo
IN2 OUT2 +3VS_CAM
C14 1 2 0.1U_0201_16V6K EDP_TXN1_C +3VALW 11 ICPRO@
<6> EDP_TXN1 EDP_TXP1_C EPAD +3VS_CAM_TS 1
C15 1 2 0.1U_0201_16V6K ICPRO@ 2
<6> EDP_TXP1 2 R99 0_0402_5% +TS_VDD
1U_0201_6.3V6M
G2895BLK21U TDFN2X2
R105
C954
1 2
100K_0201_5%
1 SA0000E0700 R100 ICPRO@ 0_0402_5%
EDP_TXN2_C
ar
C109 1 2 0.1U_0201_16V6K D4
<6> EDP_TXN2 EDP_TXP2_C
10U_0402_6.3V6M
10U_0402_6.3V6M
<6> EDP_TXP2 C110 1 2 0.1U_0201_16V6K 2 @ ICPRO@ 1 1
1
<6> EDP_VDD_EN 2
LCDVDD_EN
C351
C352
1
C111 1 2 0.1U_0201_16V6K EDP_TXN3_C 3 2 2

<6> EDP_TXN3 <58> LCD_VCC_TEST_EN
High Active
1
C112 1 2 0.1U_0201_16V6K EDP_TXP3_C

<6> EDP_TXP3
BAT54CW_SOT323-3 R17
EC (BIST MODE)
W
100K_0402_5%
ICPRO@ ICPRO@
2
C17 1 2 0.1U_0201_16V6K EDP_AUXN_C

<6> EDP_AUXN EDP_AUXP_C
C19 1 2 0.1U_0201_16V6K
<6> EDP_AUXP
I2C Touch Screen (Reserved)
B
For BL_PWR_SRC & LCDVDD monitor
+19VB RF Request
LBIST@RF@
+19VB
1
LBIST@RF@
1
LBIST@RF@
1
1P B
1
CV75 CV76 CV77

47P_0201_25V8J
100P_0201_25V7K
0.1U_0201_25V6K
+DCBAT_LCD_DV13_R 2 2 2 2 +3VS
24
I2CTCH@
2
SB00000W600 1 2 I2C_0_LCD_SDA
R621 MMDT3906_SOT363-6 R86 4.7K_0402_5%
LBIST@ QV18A 1 I2CTCH@
2 I2C_0_LCD_SCL
+DCBAT_LCD 10K_0201_5% LBIST@ I2C_0_LCD_SDA R87 4.7K_0402_5%
I2CTCH@
6
1 2 TOUCH_SCREEN_RST_LCD
1
DV16 2 1 +DCBAT_LCD_DV13 I2C_0_LCD_SCL R88 10K_0402_5%

LBIST@
1
RB751S-40_SOD523-2 CV633 BL_PWR_MONITOR_R

-L
1
SCS00006300 LBIST@ place as close as QV18
2
2200P_0201_25V7K
R624 R627
2
200K_0201_5% LBIST@
LBIST@ 47K_0201_5%
2
QV19
2
LBIST@ C
BL_PWR_MONITOR 2
B ED5
Delete USB touch USB2.0 path
1
+3VS E CEST523NC5VB_SOT-523-3
3
LA
+LCDVDD_LCD @ESD@
LMBT3904WT1G_SC70-3
1
R658
4
LBIST@ USB20_P6_R
100K_0201_5%
USB20_N6_R
2
+LCDVDD_LCD_DV14_R 5
PANEL_MONITOR <58>
@
2
SB00000W600 1 2
R-short 0409
1
2
R622 MMDT3906_SOT363-6 R10 0_0201_5%
10K_0201_5% QV18B R677
+LCDVDD_LCD LBIST@ LBIST@ LBIST@
3
1M_0201_5% L3
1
DV15 2 1 +LCDVDD_LCD_DV14 USB20_P6_R 2 1 USB20_P6 <12>

2
A LBIST@ 2 1 A
1
RB751S-40_SOD523-2 CV651 LCDVDD_MONITOR_R ED3

1
1
SCS00006300 LBIST@ CEST523NC5VB_SOT-523-3 USB20_N6_R 3 4

3 4 USB20_N6 <12>
2200P_0201_16V7K
R623 R628 @ESD@

2
200K_0201_5% LBIST@ DLM0NSN900HY2D_4P

LBIST@ 47K_0201_5% @EMI@
2
QV21 @
2
LBIST@ C 1 2
LCDVDD_MONITOR 2 R12 0_0201_5%
R-short 0409
B
E
3
LMBT3904WT1G_SC70-3 Security Classification Compal Secret Data Compal Electronics, Inc.

LCD/Cam/MIC/T.Panel
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
Reserve
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Func = HDMI RI1 EMI@ RI2 EMI@

HDMI_CLKP 1 2 HDMI_L_CLKP HDMI_TX_N0 1 2 HDMI_L_TX_N0
5.6_0402_1% 5.6_0402_1%
CI1 1 2 0.1U_0201_10V6K HDMI_CLKN HCM1012GH900BP_4P HCM1012GH900BP_4P

<6> CPU_DP1_N3
1
CI2 1 2 0.1U_0201_10V6K HDMI_CLKP 2 1 3 4
<6> CPU_DP1_P3 RI3 EMI@
CI3 1 2 0.1U_0201_10V6K HDMI_TX_N0 150_0402_5% RI4 EMI@
<6> CPU_DP1_N2 CI4 1 2 0.1U_0201_10V6K HDMI_TX_P0 3 4 2 1 150_0402_5%
<6> CPU_DP1_P2
D D
2
LI1 @EMI@ LI2 @EMI@
CI5 1 2 0.1U_0201_10V6K HDMI_TX_N1

<6> CPU_DP1_N1 CI6 1 2 0.1U_0201_10V6K HDMI_TX_P1
<6> CPU_DP1_P1 RI5 EMI@ RI6 EMI@
CI7 1 2 0.1U_0201_10V6K HDMI_TX_N2 HDMI_CLKN 1 2 HDMI_L_CLKN HDMI_TX_P0 1 2 HDMI_L_TX_P0
<6> CPU_DP1_N0 CI8 1 2 0.1U_0201_10V6K HDMI_TX_P2
<6> CPU_DP1_P0 5.6_0402_1% 5.6_0402_1%
A
RI17
RI18
RI19
RI20
RI21
RI22
RI23
RI24
RI7 EMI@ RI8 EMI@
1
1
1
1
1
1
1
1
HDMI_TX_P2 1 2 HDMI_L_TX_P2 HDMI_TX_P1 1 2 HDMI_L_TX_P1
5.6_0402_1% 5.6_0402_1%
2
2
2
2
2
2
2
2
rn
HCM1012GH900BP_4P HCM1012GH900BP_4P
2
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
HDMI_PLL_GND 2 1 2 1
RI9 EMI@ RI10 EMI@
150_0402_5% 150_0402_5%
3 4 3 4
+5VS
1
1
tu
LI3 @EMI@ LI4 @EMI@
D QI1
2 2N7002K_SOT23-3
C G SB00000EN00 C
S
RI11 EMI@ RI12 EMI@
3
+5VS HDMI_TX_N2 1 2 HDMI_L_TX_N2 HDMI_TX_N1 1 2 HDMI_L_TX_N1
ck
5.6_0402_1% 5.6_0402_1%
2KV
1
ZZZ @
DI1
BAW56W_SOT323-3 +5VS +5V_HDMI RO0000002HM
lo
3
2
W=20mils
2
+3VS 2 2 1 ROYALTY HDMI W/LOGO

RI14 RI15
2.2K_0402_5% 2.2K_0402_5% FI1 1
ar
1.5A_6V_1206L150PR~D
2
CI9
1
0.1U_0402_10V7K
G
1 6 HDMI_CTRL_CLK 2
<6> CPU_DP1_CTRL_CLK
S
QI3B
5
W
SB00001CW00 JHDMI1 CONN@
G
4 3 HDMI_CTRL_DAT 19
<6> CPU_DP1_CTRL_DATA HP_DET
S
QI3A 18
L2N7002DW1T1G_SC88-6 17 +5V
SB00001CW00 HDMI_CTRL_DAT 16 DDC/CEC_GND
B SDA B
HDMI_CTRL_CLK 15
14 SCL 23
2KV 13 Utility
CEC
GND4
GND3
22
1P +3VS
HDMI_L_CLKN
HDMI_L_CLKP
HDMI_L_TX_N0
HDMI_L_TX_P0
12
11
10
9
8
7
CK-
CK+
D0-
D0_shield
D0+
GND2
CK_shield GND1
21
20
1
1M_0402_5%
HDMI_L_TX_N1 6
5 D1-
24
D1_shield
RI13
HDMI_L_TX_P1 4
HDMI_L_TX_N2 3 D1+
2
D2-
G
2
2
HDMI_L_TX_P2 1 D2_shield
D2+
3 1 HDMI_HPD LOTES_AHDM0053-P001A
<6> CPU_DP1_HPD
DC232006M00
D
S
-L
1
20K_0402_5%
QI2
2N7002KW_SOT323-3
RI16
SB000009Q80
2
2KV
LA
A A

HDMI L.Shifter/Conn
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
1 2 3 4 5
A A
A
rn
tu
B B
ck
lo
ar
W
C
1P C
24
-L
LA
D D

TBT_TYPE-C_Port0 (1/2)
1.0
1 2 3 4 5
1 2 3 4 5
Main Func =
A A
A
rn
tu
B B
ck
Reserve
lo
ar
W
C
1P C
24
-L
LA
D D

1.0
1 2 3 4 5
1 2 3 4 5
A A
A
rn
tu
B B
ck
Reserve
lo
ar
W
C
1P C
24
-L
LA
D D

1.0
1 2 3 4 5
1 2 3 4 5
A A
A
rn
tu
Reserve
ck
B B
lo
ar
W
C
1P C
24
-L
LA
D D

1 2 3 4 5
1 2 3 4 5
A A
A
rn
tu
ck
B B
lo
ar
W
C
1P C
24
-L
LA
D D

1 2 3 4 5
1 2 3 4 5
A A
A
rn
tu
B B
ck
lo
ar
W
C
1P C
24
-L
LA
D D

1.0
1 2 3 4 5
1 2 3 4 5
MB_USB3.1 TypeC Conn. (Port 3)
A A
A
rn
tu
ck
B B
Reserve
lo
ar
W
C
1P C
24
-L
LA
D D

1.0
1 2 3 4 5
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
ar
W
B
1P B
24
-L
LA
A A

Reserve for TBT_TYPE-C_Port3 (2/2)
5 4 3 2 1
1 2 3 4 5
A A
A
rn
tu
B B
ck
lo
ar
W
C
1P C
24
-L
LA
D D

TYPE-C_Power Path
1.0
1 2 3 4 5
5 4 3 2 1
Main Func = LAN
D D
A
rn
tu
C C
ck
lo
ar
B B
W
1P
24
-L
A A
LA
Security Classification Compal Secret Data

Title
Issued Date 2018/04/01 Deciphered Date 2019/04/01
LAN RTL8111/RTL8106
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
5 4 3 2 1
5 4 3 2 1
Main Func = WLAN E Key CONN
+3VALW_PCH
1A +3.3V_WLAN
RW1 1 @ 2 0_0603_5% +3.3V_WLAN
D D
R-short 0409
10U_0402_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
10P_0402_50V8J
1 1 1 1
CW1
CW2
CW3
CW4 RF@
2 2 2 2
A
rn
+3.3V_WLAN
JWLAN1
1 2
3 GND 3.3VAUX 4
C <12> USB20_P10 USB_D+ 3.3VAUX C
<12> USB20_N10 5 6
USB_D- LED1# TP51
tu
7 8
9 GND PCM_CLK 10
<13> CNV_CRX_DTX_N1 SIDO_CLK PCM_SYNC CNV_RF_RESET# <13>
11 12
<13> CNV_CRX_DTX_P1 13 SDIO_CMD
SDO_DAT0
PCM_IN
PCM_OUT
14
CLKREQ_CNV# <13>
1.8V
15 16
<13> CNV_CRX_DTX_N0 SDO_DAT1 LED2# TP52
17 18
<13> CNV_CRX_DTX_P0 19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_W AKE# 22 CNV_BRI_CRX_DTX_R RW3 1 CNV@ 2 49.9_0201_1%
ck
<13> CLK_CNV_CRX_DTX_N SDIO_W AKE# UART_RX CNV_BRI_CRX_DTX <13>
<13> CLK_CNV_CRX_DTX_P 23
SDIO_RESET#
RW4 1 @ 2 0_0201_5%
HOST_DEBUG_TX <58>
32 CNV_RGI_CTX_DRX_R RW5 1 CNV@ 2 0_0201_5%
UART_TX CNV_RGI_CRX_DTX_R CNV_RGI_CTX_DRX <13>
33 34 RW6 1 CNV@ 2 49.9_0201_1%
PCIE_CTX_C_DRX_P10 GND UART_CTS CNV_BRI_CTX_DRX_R CNV_RGI_CRX_DTX <13>
CW5 1 2 35 36 1 CNV@ 2
lo
<12> PCIE_CTX_DRX_P10 0.1U_0201_10V6K RW7 0_0201_5%
PCIE_CTX_C_DRX_N10 PETP0 UART_RTS CNV_BRI_CTX_DRX <13>
<12> PCIE_CTX_DRX_N10 0.1U_0201_10V6K CW6 1 2 37 38
39 PETN0 RESERVED 40
<12> PCIE_CRX_DTX_P10
41
43
GND
PERP0
RESERVED
RESERVED
42
44
RW5,RW7 close to CPU
<12> PCIE_CRX_DTX_N10 45 PERN0 COEX3 46
ar
47 GND COEX2 48
<11> CLK_PCIE_P1 REFCLKP0 COEX1
49 50 WLAN_SUSCLK RW24 1 2 0_0402_5% SUSCLK_R
<11> CLK_PCIE_N1 REFCLKN0 SUSCLK SUSCLK_R <11,58>
51 52
B
R-short 0409 1 @ 2 CLKREQ_PCIE#1_R 53 GND PERST0# 54 BT_RADIO_DIS#_R RC4123 1 @ 2 0_0201_5%
PLTRST# <11,66,68,73> B
<11> CLKREQ_PCIE#1 CLKEQ0# W _DISABLE2# BT_RADIO_DIS# <10>
RW8 1 @ 2 0_0201_5% PCIE_WAKE#_R 55 56 WLAN_RF_DIS#_R RC4124 1 @ 2 0_0201_5%
<11,58,68,73> PCIE_WAKE# PEW AKE0# W _DISABLE1# WLAN_RF_DIS# <12>
RW10 0_0201_5% 57 58
W
59 GND I2C_DATA 60
<13> CNV_CTX_DRX_N1 RSRVD/PETP1 I2C_CLK
<13> CNV_CTX_DRX_P1
61 62
63 RSRVD/PETN1 ALERT 64
GND RESERVED TP125
<13> CNV_CTX_DRX_N0 65 66
67 RSRVD/PERP1 RESERVED 68 +3.3V_WLAN
<13> CNV_CTX_DRX_P0 RSRVD/PERN1 RESERVED
69 70
71 GND RESERVED 72
<13> CLK_CNV_CTX_DRX_N RESERVED 3.3VAUX
<13> CLK_CNV_CTX_DRX_P 73 74
RESERVED 3.3VAUX
75
77
GND
MTG77
LOTES_APCI0128-P005A
1P MTG76
76
SP070011H00
24
CONN@
A A
-L

NGFF_WLAN CONN
LA-L241P
LA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
Main Function: WIGIG / WIDI
D D
A
rn
tu
C C
Reserve
ck
lo
ar
W
B B
1P
24
-L
LA
A A

WIGIG / WIDI(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
Reserve
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
Reserve
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Func = Audio

moat
moat
+1.8V_PRIM +1.8VS +1.8V_AVDD
+5VS 2A
+5V_PVDD +5V_AVDD +5VS QA1 SB00000FG10
AO3416L_SOT-23-3
RA1 1 @ 2 0_0805_5% 1 @ 2 1 3 1 @ 2
S
RA4 1 2 33_0402_5% DMIC_DATA
<38> DMIC_DATA_CODEC
CA4 1 CA5 CA6 1 CA7 RA3 RA2
R-short 0409 1 2
1
EMI@ CA1 CA2 0_0603_5% 0_0402_1%
G
2
.1U_0402_16V7K
.1U_0402_16V7K
DMIC_CLK
10U_0603_10V6M
10U_0603_10V6M
LA5 1 2 BLM15PX221SN1D_2P CA3
<38> DMIC_CLK_CODEC
Place close to Pin 20 R-short 0409 10U_0402_6.3V6M
2KV
2
10U_0603_10V6M
2 2 2 1
CA4,LA5 place colse to UA1.3
.1U_0402_16V7K
1 1 R-short 0409 +3VS Close pin33
CA8 CA9
10P_0402_50V8J 6.8P_0402_50V AUD_AGND
@RF@ @RF@
D 2 2 D
+1.8V_CPVDD
Layout Note: Layout Note: +DVDD_IO AUD_AGND

R-short 0409
Close pin39 Close pin34
1 @ 2
+3V_DVDD RA5
1 1 2 1 CA11
CA46 CA47 0_0402_1%
.1U_0402_16V7K
1 @ 2 +DVDD_IO .1U_0402_16V7K CA10
+3VS 25mA
+3V_DVDD +1.8VS RA33 0_0402_5%
10U_0402_6.3V6M
2 2
10U_0402_6.3V6M
1 2
1 2
1 @ 2 RA34 0_0402_5% Close pin29
RA6 0_0402_5%
A
R-short 0409 2
CA12
1
CA13
+3V_DVDD +5V_PVDD +5V_AVDD
10U_0402_6.3V6M
.1U_0402_16V7K
1 2
Close pin8
+1.8V_AVDD
1 1 +1.8V_CPVDD
CA14 CA15
10U_0402_6.3V6M .1U_0402_16V7K
34
39
20
33
29
1
8
2 2 UA1
rn
DVDD
CPVDD
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
+LINE1_VREFO_L
24 +MIC2-VREFO
HDA_BIT_CLK_R LINE1-VREFO-L
9 23
<10> HDA_SYNC_R 5 SYNC MIC2-VREFO 22 AUD_VREF 1 2
<10> HDA_BIT_CLK_R BIT-CLK VREF AUD_AGND
4 28 CBN CA16 2.2U_0402_6.3V6M
<10> HDA_SDOUT_R SDATA-OUT CBN
2
HDA_SDIN0_R +3VALW +RTC_CELL

33_0402_5%
1 2 7 30 CBP 1 2
<10> HDA_SDIN0 SDATA-IN CBP
tu
RA8
@EMI@
RA7 33_0402_5% CA17 1 21U_0201_6.3V6K

1 @ 2 10 16 CA44 1U_0201_6.3V6K RA9 1 moat
@ 2 0_0402_5%
RA10 0_0402_5% DMIC_DATA 2 DC_DET VD33STB V3D3_STB 1 @ 2
1 @ 2 DMIC_CLK 3 GPIO0/DMIC-DATA12 27 RA11 0_0402_1%
+3V_DVDD 10 mils 10 mils
1
RA12 100K_0402_5% 40 GPIO1/DMIC-CLK CPVEE CPVEE 1 2

<58> EC_MUTE# PDB R-short 0409
33P_0402_50V8J
1 2 CA18 1 21U_0201_6.3V6K Layout Note:

RA13 100K_0402_5% CA45 1U_0201_6.3V6K Width>40mil, to improve Headpohone Crosstalk noise
2
LDO1_CAP
CA20
@EMI@
AUD_AGND CA19 1 2 10U_0402_6.3V6M 21 Change it to sharp will be better.

CA21 1 2 10U_0402_6.3V6M LDO2_CAP 32 LDO1-CAP 13 RING2
LDO2-CAP MIC2-L/RING2
Add 2 vias (>0.5A) when trace layer change.
CA22 1 2 10U_0402_6.3V6M LDO3_CAP 6 14 SLEEVE
1
LDO3-CAP MIC2-R/SLEEVE 15 MIC_CAP 1 2

MIC2-CAP AUD_AGND
CA23 10U_0402_6.3V6M
AUD_SPK_L+ 35
ck
C C
AUD_SPK_L- 36 SPK-OUT-LP 18 LINE1_L
RA8,CA20: close to UA1.5 Layout Note: SPK-OUT-LN LINE1-L
AUD_SPK_R- 37 17 LINE1_R
Speaker trace width >40mil @ 2W4ohm speaker power AUD_SPK_R+ SPK-OUT-RN LINE1-R AUD_PC_BEEP
38 11
SPK-OUT-RP PCBEEP 25 AUD_HP1_JACK_L moat
1 2 AUD_SENSE_A 12 HP-OUT-L 26 AUD_HP1_JACK_R R-short 0409
<73> JACK_PLUG RA14 200K_0402_1% HP/LINE1_JD1 HP-OUT-R
RA15 2 1 100K_0402_5% AUD_SENSE_A Layout Note: Place close to Pin 12 19 RA16 1 @ 2 0_0402_1%
+3V_DVDD 1
330P_0402_50V7K
330P_0402_50V7K
AVSS1 31 RA17 1 @ 2 0_0402_1%
CA41
CA42
AVSS2 1
1 41 RA18 1 @ 2 0_0402_1%
THERMAL_PAD
@ CA24 2 CA25 1 2 0.1U_0402_10V7K
@EMI@
@EMI@
moat
lo
.1U_0402_16V7K ALC3204-CG_MQFN40_5X5 2
2 EMI@
SA0000B0B10
AUD_AGND CA43 1 2 0.1U_0402_10V7K
AUD_AGND AUD_AGND AUD_AGND @EMI@

CA41,CA42 place near UA1 AUD_AGND
Layout Note:
Tied at point only under
ar
Codec or near the Codec
Place on the moat between GND & GNDA.
W
DA3
Layout Note: <10> SPKR
2
Speaker trace width >40mil @ 2W4ohm speaker power Speaker
JSPK1 CONN@ 1 AUD_PC_BEEP_C 1 2 1 2 AUD_PC_BEEP
6 CONN Pin Net name RA23 1K_0402_5% CA32 0.1U_0402_16V7K
G2 5 3
AUD_SPK_R- AUD_SPK_R-_C G1 <58> BEEP
RA19 1 EMI@ 2 BLM15PX221SN1D_2P 4 Pin1 SPK_L+
3 4
1
AUD_SPK_R+ RA20 1 EMI@ 2 BLM15PX221SN1D_2P AUD_SPK_R+_C BAT54CW_SOT323-3
AUD_SPK_L- RA21 1 EMI@ 2 BLM15PX221SN1D_2P AUD_SPK_L-_C 2 3 Pin2 SPK_L-
AUD_SPK_L+ RA22 1 EMI@ 2 BLM15PX221SN1D_2P AUD_SPK_L+_C 1 2 RA24
1 10K_0402_5%
Pin3 SPK_R+
TWVM_WTB1220-04RD-TAGHD
2
SP02001RJ00 Pin4 SPK_R-
1P
3
2
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
1 1 1 1
EMI@ CA31
EMI@ CA28
EMI@ CA29
EMI@ CA30
B need to check pin define with Audio B

DA1
DA2
2 2 2 2
@ESD@
@ESD@
1
24
-L
Main Func = Audio Jack

Universal Jack
(Global Headset Jack + mic phone in + line in support)
LA
RA25 1 2 2.2K_0402_5%
+MIC2-VREFO
RA26 1 2 2.2K_0402_5%
RING2 LA1 1 ESD@ 2 BLM15PX330SN1D_2P RING2_R

AUD_HP1_JACK_L RA27 1 2 10_0402_1% AUD_HP1_JACK_L1 LA2 1 EMI@ 2 BLM15PX330SN1D_2P HPOUT_L RING2_R <73>
DA4 LINE1_L 1 2 LINE1-L_C RA28 1 2 1K_0402_5% HPOUT_L <73>
2 CA33 10U_0603_10V6M RA29 1 2 4.7K_0402_5%
1 AUD_HP1_JACK_R RA30 1 2 10_0402_1% AUD_HP1_JACK_R1 LA3 1 EMI@ 2 BLM15PX330SN1D_2P HPOUT_R

+LINE1_VREFO_L LINE1_R HPOUT_R <73>
1 2 LINE1-L_R RA31 1 2 1K_0402_5% LA4 1 ESD@ 2 BLM15PX330SN1D_2P SLEEVE_R
3 CA34 10U_0603_10V6M RA32 1 2 4.7K_0402_5% SLEEVE_R <73>
BAT54ATB_SOT-523-3 SLEEVE
A A
Layout Note:
Close to UA1

Issued Date 2018/04/01 2019/04/01 Title
Deciphered Date
Audio Codec ALC3204
1.0
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
ck
Reserve
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Func = EC RE3 DIS@ RE3 UMA@

Model ID
+3VALW_EC For RE1
Board ID Select
Board ID
+3VALW_EC
+3VALW +3VALW_EC
1
SD041100280 10K_0201_1% EVT 10K
RE5 1 @ 2 SD000026U00 17.8K_ 0201_1% RE3 DVT-1 17.8K RE1
+3VALW 0_0402_1% SD000015700 27K_ 0201_1% Ra @ Reserve 27K Ra @
SD000014200 37.4K_ 0201_1% 17.8K_ 0201_1% 10K_0201_1% 100K_0201_1% DVT-2 37.4K 100K_0201_1%
<63> KSI[0..7] 1 1 1 1 1 1 1 1 1 1
1
RE66 1 2 10K_0201_5% KSI0 CE1 CE2 CE5 CE6 CE7 CE8 CE9 CE506 CE507 CE100 CE101 SD000014400 49.9K_ 0201_1% Reserve 49.9K
R-short 0409
2
RE67 1 2 10K_0201_5% KSI1 RF@ RF@ SD000013K00 64.9K_ 0201_1% MODEL_ID Pilot 64.9K BOARD_ID
<63> KSO0[0..9] NA 82.5K_ 0201_1% SD000026U00 SD041100280 Reserve 82.5K
10U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
12P_0201_25V8J
100P_0201_25V8J
RE68 1 2 10K_0201_5% KSI2
SD00002AM80 107K_ 0201_1%
2
2 2 2 2 2 2 2 2 2 2
0.1U_0201_10V6K
RE69 1 2 10K_0201_5% KSI3 1 RE1 1
<63> KSO[10..16]
For CE10 RE4 CE11 RE2
RE70 1 2 10K_0201_5% KSI7 Model ID Select Rb Rb
0.1U_0201_10V6K
RE71 1 2 10K_0201_5% KSI6 100K_0201_1% 100K_0201_1%
RE72 1 2 10K_0201_5% KSI5 UMA 10K 2 2
1
RE73 1 2 10K_0201_5% KSI4 DIS 17.8K
64.9K_ 0201_1%
RE74 1 2 100K_0201_5% KSO00 A8 B5 B48 B39 A52 B26 B4 B9 SD000013K00
RE75 1 2 100K_0201_5% KSO01
RE76 1 2 100K_0201_5% KSO02 Every 0.1uF decoupling capacitor should close to designated UE1 power pin
RE77 1 2 100K_0201_5% KSO03
RE78 1 2 100K_0201_5% KSO04 +1.8VALW_EC +1.8V_PRIM

D
RE79 1 2 100K_0201_5% KSO05 R-short 0409 D
+RTC_CELL +3VALW_EC +3VALW_EC
RE80 1 2 100K_0201_5% KSO06 0.1U_0201_10V6K 2 1 CE13 1 @ 2 RE7
RE81 1 2 100K_0201_5% KSO07 0_0402_1%
RE6 1 @ 2 +RTC_CELL_VBAT
RE82 1 2 100K_0201_5% KSO10 0_0402_1% PBAT_CHG_SMBDAT RE8 1 2
RE83 1 2 100K_0201_5% KSO11 1 4.7K_0201_5%
A64
B48
B39
A52
B26
B19
RE84 1 2 100K_0201_5% KSO12 CE12 PBAT_CHG_SMBCLK RE9 1 2
A8
B5
B4
B9
RE85 1 2 100K_0201_5% KSO13 R-short 0409 UE1 4.7K_0201_5%
0.1U_0402_10V7K
VBAT
VTR1
VTR1
VTR1
VTR1
VTR1
VTR2
VTR3
VTR_PLL
VTR_REG
RE86 1 2 100K_0201_5% KSO08 2 CABLE2_OCP# RE555 1 2
RE87 1 2 100K_0201_5% KSO15 MISC. Interface & GPIO 100K_0201_5%
RE88 1 2 100K_0201_5% KSO14 B63 EC_PCH_SPI_EN TOUCHPAD_INTR# RE542 1 @ 2
GPIO062_nRESETO/I2C11_SCL NB_MUTE# EC_PCH_SPI_EN <59>
RE89 1 2 100K_0201_5% KSO16 A1 RE29 1 @ 2 0_0201_5% 100K_0201_5%
1 2 GPIO221/32KHz_OUT/nSYS_SHDN A2 EC_MUTE# <56> GPU_THM_SMBDAT 1 2
RE18 100K_0201_5% KSO09 RUNPWROK RE565 @
GPIO057/VCC_PWRGD B2 nRESET_IN R-short 0409 499_0201_1%
A
RE19 1 2 100K_0201_5% USB_PWR_EN# JTAG Interface nRESET_IN B3 RESET_OUT# RE550 1 @ 2 0_0201_5% GPU_THM_SMBCLK RE566 1 @ 2
BAT1_LED# JTAG_TMS GPIO106/PWROK LCD_VCC_TEST_EN SYS_PWROK <11>
RE21 1 2 100K_0201_5% A56 A3 499_0201_1%
BAT2_LED# JTAG_CLK GPIO150/I2C15_SCL/JTAG_TMS/UART2_DTR# GPIO226 SHD_IO1 LCD_VCC_TEST_EN <38>
RE23 1 2 100K_0201_5% B59 B22
1 2 VCCDSW_EN JTAG_TDO A55 GPIO147/I2C15_SDA/JTAG_CLK/UART2_DSR# GPIO224/GPTP_IN0/SHD_IO1 A21 SHD_IO3 SHD_IO1 <9> +RTC_CELL
RE58 100K_0201_5% PWRGD strap
1 2 EC_PCH_SPI_EN JTAG_TDI B58 GPIO146/I2C09_SCL/JTAG_TDO/UART2_TX GPIO016/GPTP-IN1/SHD_IO3/ICT3/DSW_PWROK B23 SHD_IO2 SHD_IO3 <9>
RE545 @ 100K_0201_5%
PTP_DIS# JTAG_RST# GPIO145/I2C09_SDA/JTAG_TDI/UART2_RX GPIO227/SHD_IO2/PWRGD_STRAP SHD_IO0 SHD_IO2 <9>
RE560 1 2 100K_0201_5% A40 A22 not support S5 LID
JTAG_nRST GPIO223/SHD_IO0 PS_ID SHD_IO0 <9>
B41
GPIO116 PS_ID <82> LID_POWER_ON#
A6 BEEP RE556 1 2 100K_0201_5%
GPIO035/PWM8/CTOUT1/ICT15 A30 BEEP <56>
KSO15
+3VS ESPI Host Interface GPIO151/ICT4/KSO15 A39 TABLE_MODE# RE501 1 @ 2 0_0201_5% TABLE_MODE#_EC
ESPI_IO0 A17 MEC1515 GPIO117 B32 KSI0
TABLE_MODE#_EC <10>
rn
RE163 1 @ 2 10K_0201_5% SSD_SCP# <9> ESPI_IO0 ESPI_IO1 A18 GPIO070/ESPI_IO0/I2C14_SDA GPIO017/KSI0/UART0_nDCD A31 KSO00 +3VS
<9> ESPI_IO1 ESPI_IO2 B20 GPIO071/ESPI_IO1/I2C14_SCL GPIO040/GPTP_OUT2/KSO00/UART1_nCTS B33 KSI7
<9> ESPI_IO2 ESPI_IO3 A19 GPIO072/ESPI_IO2/I2C01_SDA_ALT GPIO032/KSI7/GPTP-OUT0/UART0_nRI A32 KSI6 TACH_FAN1 RE16 1 2
+3VALW <9> ESPI_IO3 ESPI_CLK B18 GPIO073/ESPI_IO3/I2C01_SCL_ALT GPIO031/KSI6/GPTP_OUT1 B34 KSI3 10K_0201_5%
ESPI_CLK <9> ESPI_CLK ESPI_RESET# GPIO065/ESPI_CLK/I2C13_SCL GPIO026/KSI3/UART0_nDTR/I2C12_SDA PWM_FAN1
B16 B35 KSI4 RE17 1 2
<9> ESPI_RESET# ESPI_CS# GPIO061/ESPI_nRESET GPIO027/KSI4/UART0_nDSR/I2C12_SCL
B17 A33 KSI5 10K_0201_5%
<9> ESPI_CS# GPIO066/ESPI_nCS/I2C13_SDA GPIO030/KSI5/I2C10_SDA
1
A20 A34 KSO07

GPIO063/ESPI_nALERT/ICT8 GPIO120/KSO07
1
RE28 B37 KSO05

RE222 GPIO112/KSO05 A35 KSO06 43_0402_1% RESET_OUT# RE22 1 2
GPIO113/KSO06/ICT9
tu
100K_0201_5% 33_0402_5% I2C & GPIO A37 PECI_EC RE27 1 2 PECI_EC_R 100K_0201_5%
@EMI@ GPU_THM_SMBDAT A59 GPIO042/PECI_DAT/SB-TSI_DAT B40 PANEL_BKEN_EC PECI_EC_R <7> PCH_RSMRST#_R RE26 1 2
PANEL_BKEN_EC <38>
2
LID_CL_SIO# <9,66> GPU_THM_SMBDAT GPU_THM_SMBCLK B62 GPIO003/I2C00_SDA/UART2_nRI GPIO043/SB-TSI_CLK A38 PECI_VREF 100K_0201_5%
<9,66> GPU_THM_SMBCLK
2
PBAT_CHG_SMBCLK B27 GPIO004/I2C00_SCL/UART2_nDCD GPIO044/VREF_VTT B42 HOST_DEBUG_TX 1 2

1 <83,85> PBAT_CHG_SMBCLK GPIO131/I2C01_SCL GPIO170/JTAG_STRAP/UART1_TX/CEC_OUT +1.05V_VCCST
PBAT_CHG_SMBDAT A25 B43 MSCLK RE538 0_0201_5%
<83,85> PBAT_CHG_SMBDAT GPIO130/I2C01_SDA GPIO104/VTR2_STRAP/UART0_TX/TFDP_CLK
1
CE16 C6674 DAT_TP_SIO_I2C_CLK B51 A41 MSDATA 1 2

33P_0402_50V8J <63> DAT_TP_SIO_I2C_CLK CLK_TP_SIO_I2C_DAT GPIO155/I2C02_SCL/PS2_DAT1B GPIO105/UART0_RX/TFDP_DATA
@ A48 B44 KSO02 CE15 0.1U_0201_10V6K DVT 1.0
0.047U_0402_16V4Z 2 @EMI@ <63> CLK_TP_SIO_I2C_DAT FPR_SCAN# B50 GPIO154/I2C02_SDA/PS2_CLK1B GPIO046/KSO02/ICT11 A42 KSO03 Un-pop CE509.
<73> FPR_SCAN#
2
AUX_ON A47 GPIO010/I2C03_SCL/PS2_DAT0B GPIO047/KSO03/ICT13 B45 KSO08 @

<73> AUX_ON A58 GPIO007/I2C03_SDA/PS2_CLK0B GPIO121/PVT_IO0/KSO08 A43 PECI_EC 2 1
KSO09 @ESD@ CE509
B61 GPIO144/I2C04_SCL/UART0_nRTS GPIO122/PVT_IO1/KSO09 B46 KSO10 PCH_RSMRST# CE40 1 2 0.1U_0201_10V6K 100P_0201_25V8J
UMA not support Type-C A57 GPIO143/I2C04_SDA/UART0_nCTS GPIO123/PVT_IO2/KSO10 A44 KSO13
C Close to UE1 pin A37 C
ck
+3VALW_EC +3VALW PTP_DIS# B60 GPIO142/I2C05_SCL/UART2_nCTS GPIO126/PVT_IO3/KSO13 B30 PROCHOT
<63> PTP_DIS# CAP_LED# B53 GPIO141/I2C05_SDA/UART2_nRTS GPIO222/nPROCHOT_IN B47 KSO12
<63> CAP_LED# A49 GPIO140/I2C06_SCL/ICT5/KSO17 GPIO125/PVT_CLK/KSO12 B49 HW_ACAV_IN 2 1
BSS strap KSO16 CE32
GPIO132/I2C06_SDA/KSO16 GPIO156/LED0
1
A24 A50 BAT1_LED# 100P_0201_25V8J

RE516 VCCDSW_EN B25 GPIO013/I2C07_SCL GPIO157/LED1 B54 BAT2_LED# BAT1_LED# <63> Close to UE1 pin A61
<78> VCCDSW_EN GPIO012/I2C07_SDA GPIO153/LED2 PCH_RSMRST# BAT2_LED# <63>
@ 100K_0201_5% RE526 B38 RE537 1 @ 2 0_0201_5%
GPIO114/PS2_CLK0A/nEC_SCI A36 LID_CL_SIO# PCH_RSMRST#_R <59,78>
100K_0201_5%
FAN PWM & TACH GPIO115/PS2_DAT0A A46 RTCRST_ON LID_CL_SIO# <38,66>
RTCRST_ON <66>
2
SHD_CS0# JTAG_RST# GPIO127/A20M/UART1_nRTS A54 PCIE_WAKE# +3VALW_EC

KB_LED_PWM B29 GPIO165/32KHZ_IN/CTOUT0 B57 KSO01
PCIE_WAKE# <11,52,68,73> R-short 0409
<63> KB_LED_PWM GPIO053/PWM0 GPIO045/KSO01/ICT14[CR_STRAP] CR strap
1
A28 B36 KSO04 JTAG strap
lo
1 GPIO054/PWM1 GPIO107/nSMI/KSO04/I2C10_SCL
1
1
SHD_CS0#
SHORT PADS
CLEC1 @
1U_0201_6.3V6M
CE505
100_0201_1%
RE527
RE559 B24 B52

<9> SHD_CS0# SHD_CLK A23 GPIO055/PWM2/SHD_nCS0/BSS_STRAP GPIO060/KBRST/TST_CLK_OUT A16
@ 100K_0201_5% @ RE51
<9> SHD_CLK MASK_SATA_LED# B21 GPIO056/PWM3/SHD_CLK GPIO064/nPCI_RESET ME_FWP
A4 10K_0402_5%
<63> MASK_SATA_LED# ME_FWP <10>
2
2 SHD_CS1# B28 GPIO011/nSMI_ALT/PWM4/ICT7 GPIO255 A5 M_BIST RE513 1 @ 2 0_0201_5% @

<9> SHD_CS1# M_BIST_R <63>
2
PWM_FAN1 A27 GPIO002/PWM5/SHD_nCS1 GPIO246/CMP_VREF0 B56

<77> PWM_FAN1 UMA not support Type-C
2
TACH_FAN1 B55 GPIO014/PWM6/GPTP_IN2 GPIO171/UART1_RX/CEC_IN A53 HOST_DEBUG_TX
Boot Source Select Strap <77> TACH_FAN1 A51 GPIO050/ICT0_TACH0 GPIO241/CMP_VOUT0 B7 SIO_PWRBTN# <52> HOST_DEBUG_TX
1=Use the Shared SPI pins for Boot LCD_TST A26 GPIO051/ICT1_TACH1 GPIO254/CMP_VREF1 A63 LID_POWER_ON# SIO_PWRBTN# <11> R-short 0409
<38> LCD_TST GPIO052/ICT2_TACH2 nVCI_IN1/GPIO162
2
0=Use the eSPI Flash Channel for Boot RE532 2 @ 1 0_0201_5% IMVP_VR_ON B1 B67 POWER_SW_IN#
ar
<78> IMVP_VR_EN GPIO033/TACH3 nVCI_IN0/GPIO163 POWER_SW_IN# <63>
RE529
+RTC_CELL 4.7K_0402_5%
MISC. Interface & GPIO
R-short 0409
1
1
PBAT_PRES# A45 ADC Interface +3VALW_EC

<82,83,85> PBAT_PRES# AC_DIS GPIO175/CMP_VOUT1
RE20 A7
<85> AC_DIS PANEL_MONITOR B6 GPIO244/CMP_VIN1 B11
1 <38> PANEL_MONITOR GPIO242/CMP_VIN0 VREF_ADC
100K_0201_5% SYSPWR_PRES B68 A10
CE18 KSI1 A29 GPIO000/SYSPWR_PRES/nVCI_IN3/I2C11_SDA GPIO067/VREF2_ADC A15 I_ADP RE46 1 2
W
I_ADP_R <85>
2
POWER_SW_IN# RE25 1 2 KSI2 B31 GPIO020/KSI1 VTR1_ADC 300_0201_1%

POWER_SW#_MB <73> 0.1U_0201_10V6K GPIO021/KSI2 1 1 1
100_0201_5% 2 KSO14 A9 CE504 CE21 CE26
1 GPIO152/KSO14
CE14 KSO11 B10 A11 I_BATT
CABLE2_OCP# A60 GPIO124/PVT_CS#/KSO11/ICT12 GPIO200/ADC00 B12 I_ADP 0.1U_0201_10V6K 0.1U_0201_10V6K 2200P_0201_25V7K
<38> CABLE2_OCP# SSD_SCP# GPIO253/BGPO0 GPIO201/ADC01 MODEL_ID 2 2 2
2.2U_0201_6.3V6M B64 A12
2 <68> SSD_SCP# HW_ACAV_IN GPIO101/BGPO1 GPIO202/ADC02 TOUCHPAD_INTR#
A61 B13
<11,63,82,85,111> HW_ACAV_IN VCI_OVRD_IN/GPIO172 GPIO203/ADC03 BOARD_ID TOUCHPAD_INTR# <7,63> I_BATT
ALWON B65 A13 RE47 1 2
<87> ALWON VCI_OUT/GPIO250 GPIO204/ADC04 B14 I_BATT_R <85>
1 300_0201_1%
GPIO205/ADC05 A14 CE31
+3VALW_EC GPIO206/ADC06 PCH_DPWROK_EC_R USB_PWR_EN# <71,73>
B15
GPIO207/ADC07/CMP_STRAP 2200P_0201_25V7K
2
RE533 2 1 0_0201_5% PCH_SUSCLK A62
1 <11,52> SUSCLK_R SUSCLK_IN
CE508 B66
NC
1P VSS_EP
VR_CAP
+3VLP +RTC_CELL
2
G3@ OSC_CLK RE554 2 @ 1 0_0201_5% PCH_DPWROK_EC_R RE500 1 2 PCH_DPWROK_EC

PCH_DPWROK_EC <59,78>
0.1U_0201_6.3V6K RE511 0_0201_5% DVT 1.0
1
2 @ @ Un-pop RE546 100K_0201.
TP86
B 100K_0201_5% SA0000CEG00 MEC1515H-D0INB_DQFN132_11X11-V Pop RE32 100K_0201. RE30 RE546 B
C1
B8
5
UE5 1K_0201_5% 100K_0201_5%

1
PRIM_PWRGD 1 VCC +3VS @ @

B 4 nRESET_IN VR_CAP CE23 1 2
Y
2
EC_PCH_SPI_EN 2 1U_0402_16V6K SYSPWR_PRES
A
G
ESR <100m ohms 1
2
1
74LVC1G32GW_TSSOP5 G3@ CE22
3
RE544 SA0000CMN00 RE32

24
G3@ 0.1U_0201_10V6K 100K_0201_5%
100K_0201_5% 2 UE2
5
NL17SZ06EDFT2G_SOT-353
32.768KHz Oscillator +RTC_CELL
1
2
VCC
4 OUT Y 2 PROCHOT
+3V_OSC +3VLP <7,16,82,85,98> H_PROCHOT# INA
GND
2
XE1 @ NC
OSC_CLK 3 4 RE552 1 @ 2 0_0201_5% RE45
3
OUTPUT VCC
RE553 1 @ 2 0_0201_5% 100K_0201_5%
0.01U_0201_10V6K
1
2 1
-L
GND STAND-BY @ CE510

32.768KHZ_15PF_FRB5014A
SJ000009G00 2
+3VALW_EC
JESPI1 CONN@
LA
1
1 2
2 3 ESPI_IO0 R-short 0409
3 4 ESPI_IO1
4 5 ESPI_IO2 RUNPWROK 1 @ 2 ALL_SYS_PWRGD
5 6 ESPI_IO3 <11> RUNPWROK ALL_SYS_PWRGD <78,87>
RE508 0_0201_5%
6 7 ESPI_CS#
7 8 ESPI_RESET#
11 8 9
12 GND 9 10 ESPI_CLK
GND 10
JXT_FP241AH-010GAAM
+3VALW_EC
SP010021O00
+3VALW_PCH
1
A RE48 PU in PWR Page A

49.9_0402_1% RE473
@ 100K_0201_5%
2
JDEG1 CONN@
2
1 +EC_DEBUG_VCC +3VALW_EC
1 2 JTAG_TDI PRIM_PWRGD 1 @ 2 PRIM_PWRGD_R RE165 1 @ 2 0_0201_5%
2 3 JTAG_TMS JTAG_TDI 1.8V_PRIM_PG <16,90,95>
RE90 1 2 10K_0201_5% RE182 0_0201_5% RE507 1 2 0_0201_5%
3 4 JTAG_CLK JTAG_TMS 1 2 PG_VCCIN_AUX <95>
RE91 10K_0201_5%
4 5 JTAG_TDO JTAG_CLK RE92 1 2 10K_0201_5%
5 6 MSCLK JTAG_TDO RE93 1 2 10K_0201_5% R-short 0409
6 7 MSDATA 0_0201_5%
7 8 HOST_DEBUG_TX RE525 1 @ 2 DEBUG_TX RE524 1 @ 2 10K_0201_5%
11 8 9 DEBUG_TX MSCLK RE49 1 2 10K_0201_5%
12 GND 9 10 MSDATA RE50 1 @ 2 100K_0201_5%
GND 10 RE57 1 @ 2 10K_0201_5%
JXT_FP241AH-010GAAM R-short 0409 Security Classification Compal Secret Data Compal Electronics, Inc.
SP010021O00 Issued Date 2018/08/31 Deciphered Date 2019/08/06 Title
EC MEC1515
5 4 3 2 1
5 4 3 2 1
Main Function: WDT circuit
D D
+3VALW_EC
1
RE97
A
1
100K_0201_5%
RE99
2
1M_0402_1%
PCH_DPWROK_EC
PCH_DPWROK_EC <58,78>
U34
2
RE562 1 2 0_0201_5% DPWROK_OFF# 1 8
<58,78> PCH_RSMRST#_R A# VCC
RE563 1 @ 2 0_0201_5% 2 7 CEXT_U34
<58> EC_PCH_SPI_EN B R/CEXT
CLR#_U34 3 6
rn
CLR# CEXT
1
D Q19
4 5 PCH_DPWROK_OFF 2
GND Q G
2
0.22U_0402_16V7K
SN74LVC1G123DCUR_VSSOP8 1 2N7002KW_SOT323-3
CE36
RE98 S SB000009Q80
3
1M_0201_5%
2 2KV
tu
C C
ck
lo
ar
Main Function: S5 LID
W
B
1P B
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
Reserve
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Function:SMB/I2C Block Diagrams

@ 1k ohm
@ 1k ohm
+3VS
DB45 ISH_I2C_0_SCL
ISH_I2C_0_SCL
4.7k ohm @ 2.2k ohm Reserved
DB44 ISH_I2C_0_SDA
ISH_I2C_0_SDA
+3VS 4.7k ohm
+3VS @ 2.2k ohm
D D
USB20_P8_R 0 ohm I2C_0_LCD_SCL 0 ohm I2C_0_SCL DV18 1k ohm
I2C0_SCL
JeDP CONN DW18
I2C Address:0x10 For Touch Screen
USB20_N8_R 0 ohm I2C_0_LCD_SDA 0 ohm I2C_0_SDA
I2C0_SDA 1k ohm
+3VS
CY39 ISH_I2C_1_SCL
ISH_I2C_1_SCL SCL FreeFall Sensor FreeFall Sensor reserved
TGL-U
DB47 ISH_I2C_1_SDA LNG2DMTR LGA SMBus Address: 0101001b
ISH_I2C_1_SDA SDA
2.2k ohm @ 2.2k ohm
+TP_VDD (+3VS) 2.2k ohm

+3VS @ 2.2k ohm 1k ohm 2.2k ohm
I2C_1_SCL_R 0 ohm I2C_1_SCL DJ23 +3VALW_PCH +3VS

JTP CONN I2C1_SCL 1k ohm 2.2k ohm
I2C Address: 0x2C Touch PAD I2C_1_SDA_R 0 ohm I2C_1_SDA DT18 DK21 MEM_SMBCLK 253
0b0101 100 + R/W I2C I2C1_SDA SMBCLK PCH_SMBCLK PCH_SMBCLK SCL
DM19 MEM_SMBDATA 2N7002KDW 254 DIMMA
SMBDATA QC6 PCH_SMBDAT PCH_SMBDATA SDA DDR4
A
SMBus Address: 000
SCL 253
XDP CONN PCH_SMBCLK SCL
SDA 254 DIMMB
PCH_SMBDATA SDA DDR4
SMBus Address: 010
C C
499 ohm 2.2k ohm
rn
499 ohm
+3VALW_PCH 2.2k ohm
+3VS
DK19 SML0_SMBCLK 0 ohm GPU_THM_SMBCLK THM_SML1_CLK
SML0CLK 8
DM17 SML0_SMBDATA 2N7002KDW Thermal Sensor

SML0DATA 0 ohm GPU_THM_SMBDAT
Q11
THM_SML1_DATA
7 SMBus Address: 1001100xb (x is R/W bit)
NCT7718W
tu
1k ohm
1k ohm +3VALW_PCH
SML1CLK DK17 SML1_SMBCLK
I2C_1_SCL_R 0 ohm SML1DATA DJ17 SML1_SMBDATA Reserved for Type-C , TBT
ck
I2C_1_SDA_R 0 ohm
4.7k ohm
B B
+TP_VDD (+3VS) 4.7k ohm
lo
DAT_TP_SIO_R 0 ohm DAT_TP_SIO_I2C_CLK GPU_THM_SMBCLK
JTP CONN GPIO155 GPIO004
Touch PAD CLK_TP_SIO_R 0 ohm CLK_TP_SIO_I2C_DAT GPU_THM_SMBDAT
GPIO154 GPIO003
PS2
ar
KBC 4.7K ohm
+3VALW_EC
MEC 1515 GPIO131
PBAT_CHG_SMBCLK
4.7K ohm
100 ohm
CLK_SMB 7 SCL
BATT CONN 7-bit Address:0x0B
PBAT_CHG_SMBDAT 100 ohm
W
GPIO130 DAT_SMB 6 SDA 0001011x x is R/W
0 ohm
21 SDA Charger
0 ohm
SMBus Address:0b00010011(resd)
ISL95522
22 SCL
PUB01 0b00010010 (write)
A A
1P Security Classification
Issued Date 2018/04/01
Compal Secret Data
Deciphered Date 2019/04/01
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Title
Size
SMB/I2C Block Diagrams
Document Number Rev
1.0
24
5 4 3 2 1
-L
LA
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
Reserve
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Func = KB Main Func = TPAD

<58> KSI[0..7]
Keyboard Backlight (N3 only) +TP_VDD
KB Backlight Power Consumption: 285mA max. +3VS +TP_VDD

<58> KSO0[0..9]
+5VS F3 KBBL@ +5V_KB_BL
<58> KSO[10..16]
1
2 1
JKB1 CONN@ 1 R45 R43 R106 1 @ 2 0_0603_5%
30 32 0.5A_13.2V_MF-NSMF050-2 KBBL@ 2.2K_0201_5% 2.2K_0201_5%
<6> KB_DET# KSI7 29 30GND32 31 C22
KSI6 28 29GND31 .1U_0402_16V7K R-short 0222
PCH/I2C
2
KSI4 27 28 2
KSI2 26 27 I2C_1_SCL RC4220 2 @ 1 0_0201_5% I2C_1_SCL_R
26 <10> I2C_1_SCL
KSI5 25
KSI1 24 25 KBBL@ JKBBL1 I2C_1_SDA RC4221 2 @ 1 0_0201_5% I2C_1_SDA_R
24 <10> I2C_1_SDA
KSI3 23 R38 1
KSI0 22 23 1 2 KB_LED_DET_C 1
2
D KSO05 21 22 <10> KB_LED_BL_DET 51K_0402_5% 2
3 5 R-short 0409 D
1
KSO04 20 21 KB_BL_CTRL# 3 G1 6
4
KSO07 19 20 4 G2 +TP_VDD
KSO06 18 19 R40 TWVM_FPC1018-04RC-TAGHA
KSO08 17 18 100K_0201_5% I2CPAD@
17 CONN@
1
KSO03 16 CLK_TP_SIO_I2C_DAT RC4171 2 1 0_0201_5%
EC/I2C
2
KSO01 15 16 SP01002NM00 DAT_TP_SIO_I2C_CLK RC4172 2 1 0_0201_5% R42
KSO02 14 15 I2CPAD@ 100K_0201_5%
KSO00 13 14
13
1
KSO12 12
2
KSO16 11 12 D Q31 KBBL@
KSO15 10 11 2 AO3416L_SOT-23-3 RC4225 2 @ 1 0_0201_5% INT_TP#
KSO13 9 10 <58> KB_LED_PWM SB00000FG10 <7,58> TOUCHPAD_INTR#
G
KSO14 8 9
A
S
KSO09 7 8 +TP_VDD
R-short 0831
3
KSO11 6 7
KSO10 5 6
CAP_LED 4 5 2KV
3 4
3
Co-lay EC to PAD I2C/PS2
2
1 2
it's used for TP I2C(EC will do PS2 virturlization)
1
1
I/F to control it in ePSA mode or BIOS menu
TWVM_FPC0812-30RC-TAGHA R6239 R6420
rn
SP01002NU00 4.7K_0201_5% 4.7K_0201_5%
PS2PAD@
2
DAT_TP_SIO_I2C_CLK RC731 2 1 0_0201_5% DAT_TP_SIO_R
<58> DAT_TP_SIO_I2C_CLK CLK_TP_SIO_I2C_DAT CLK_TP_SIO_R
RC732 2 1 0_0201_5%
<58> CLK_TP_SIO_I2C_DAT
PS2PAD@
EC/PS2
tu
+TP_VDD
10P_0201_50V8J
@ESD@ C24
10P_0201_50V8J
@ESD@ C25
CONN@
1 1 SP01002JM00
2 1
0.1U_0402_16V7K C26 TWVM_FPC1020-08RC-MA0HA
+3VS +TP_VDD
2 2 8 10
R46 1 2 100K_0201_5% I2C_1_SDA_R 7 8 GND2 9
I2C_1_SCL_R 6 7 GND1
5 6
5
1
C D5 INT_TP# 4 C
ck
R47 +5VS 1 2 TP_LOCK# 3 4
<58> PTP_DIS# DAT_TP_SIO_R 3
100K_0402_5% 2
RB551V-30_SOD323-2 CLK_TP_SIO_R 1 2
ESD depop location 1
CAP LED Control
2
Q9 JTP1
LOW actived from KBC GPIO
2
G
R2
3 1 CAP_LED_R# 2 Q12
<58> CAP_LED#
lo
DDTA144VCA-7-F_SOT23-3
S
R1
AO3416L_SOT-23-3
SB00000FG10
1
2KV R48
CAP_LED_Q 1 2 CAP_LED
ar
1K_0402_5%
W
Main Func = Battery LED BJT
+3VALW
R1: 47 K
Low actived from KBC GPIO R2: 10 K
1
R89
100K_0402_5% +5VALW
1P
2
LED1
1 2 1 2 WHITE_LED_BAT 2 1 2 1
B
+1.8V_PRIM B
R26 @ 10K_0402_5% RC158 10K_0402_5% R27 1K_0402_5% W
3
AMBER_LED_BAT 2 1 4 3
2
R28 1K_0402_5% Y
R2
<58> MASK_SATA_LED# CHG_AMBER_LED_R#
1 6 2 Q2 LTW-295DSKS-5A_YEL-WHITE~D
<58> BAT1_LED#
DDTA144VCA-7-F_SOT23-3
24
R1
Q15A
2
G
SB00001CW00
SATA_LED#_R 3 1 BATT_WHITE_LED_R#
1
S
3
5
AMBER_LED_BAT WHITE_LED_BAT 1 2
Q3 2KV R2
C21 1U_0402_10V6K
AO3416L_SOT-23-3 4 3 BATT_WHITE_LED_R# 2 Q4
<58> BAT2_LED#
SB00000FG10 DDTA144VCA-7-F_SOT23-3
-L
R1
Q15B
SB00001CW00
1
SATA_LED# 1 @ 2 SATA_LED#_R
R791 0_0201_5% 2KV
WHITE_LED_BAT
M_BIST feature BAT1_LED#

+3VS @
LA
HW_ACAV_IN DZ12 1 2
<11,58,82,85,111> HW_ACAV_IN
1
3
RB751S-40_SOD523-2
R30 SCS00006300
100K_0402_5% M_BIST_R R2
QZ3
+3VS <58> M_BIST_R BAT1_LED#_Q 2 LMUN5111T1G_SC70-3
+3VALW SB000010P00
2
R1
1
SATA_LED#_R RZ36 1 2
R31 1M_0201_5%
1
100K_0402_5% C
1
3
PCH_RSMRST#_AND RZ1413 2 @ 1 2 QZ21

<11,78,79> PCH_RSMRST#_AND
Q16B 330K_0201_1% 1 B LMBT3904WT1G_SC70-3
2
L2N7002DW1T1G_SC88-6 E
1
5 SB00001CW00 CZ218
A 2.2U_0201_6.3V6M RZ35 A
2
4
6
150_0402_5%
Q16A
2KV
2
SATA_LED# 2 SB00001CW00 POWER_SW_IN#
<9,68> SATA_LED# <58> POWER_SW_IN#
1
2018/04/01
Compal Secret Data
2019/04/01 Title
Keyboard/Touch Pad/Thermal/FAN
1.0
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
Reserve
tu
C C
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
Reserve
C C
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Func = Hall Sensor 750_CTPM@

RX19 1 2 0_0402_5% +3VS
Follow FAE suggestion
+3V_LID change power rail to S0 state
+3VALW +3V_LID
Main Func = TPM 0_0402_5% 1 @ 2 RX18 +3VALW
0.1U_0201_10V6K
CX1 750_CTPM@
10U_0402_6.3V6M
CX2 750_CTPM@
1 1
1
1 @ 2
RS3 0_0402_1% RS4 +3VS CX1, CX2: close to Pin1
10K_0402_5% 2 2
D R-short 0222 1 TPM@ 2 TPM_SPI_IRQ#
D
2
RX1 10K_0201_5%
LID_CLOSE#
<73> LID_CLOSE# 1 @ 2 CPU_SPI_0_CS#2
RX23 10K_0201_5% UX1 @ +3VS
1
29 VSB
SDA/GPIO0
2
@EMI@ 1 1 1 30 8 RX12 1 2 750_CTPM@ 0_0402_5%
CS23 CS20 US1 CS21 GPIO1/SCL VHIO 22 RX15 1 2 0_0402_5% +3VS
VOUT
VCC
VHIO
0.1U_0201_10V6K
CX3 750_CTPM@
10U_0402_6.3V6M
CX4 750_CTPM@
TCS40DLR_SOT23F3 0.1U_0402_16V7K 6 750_CTPM@ 1 1
TP80 GPIO3
33P_0201_50V8J
0.1U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
CX7 ST_CTPM@
2 1 1
2 2 2 SPI_D1_TPM NC
CX6
24 3 1 2
GND
<9> SPI_D1_TPM SPI_D0_TPM MISO NC +3VALW_PCH
RX11
<9> SPI_D0_TPM 21 5 RX16 ST_CTPM@
MOSI/GPIO7 NC
2
TPM_SPI_IRQ# 18 7 0_0402_5% 2 2
<10> TPM_SPI_IRQ# SPI_IRQ#/GPIO2 NC TP81 2 2
ST_CTPM@
TPM@
9
1
NC
0_0201_5%
10
SPI_CLK_TPM NC
RX21 0_0201_5%
<9> SPI_CLK_TPM
19 11 CX5, CX6, CX7: colse to Pin22
SCLK NC
2
CTPM@
<9> CPU_SPI_0_CS#2 20 12
1
17 SCS#/GPIO5 NC 14 1 @ 2
<11,52,68,73> PLTRST# RESET# NC +3VALW_PCH
27 15 RX17 0_0402_5%
13 NC NC 26 1 CTPM@ 2
GPIO4/SINT# NC +3VS CX3, CX4: colse to Pin8
25 RX20 0_0402_5%
1
NC 28
RS5 1 2 100_0402_5% LID_CLOSE# 4 NC 31
A
<38,58> LID_CL_SIO# PP/GPIO6 NC 32 RX22 2 CTPM@ 1 0_0201_5% UX1
NC
C 16 RX13 1 2 750_CTPM@ 0_0201_5% SA0000AQ2C0 C
GND 23 RX14 1 2 750_CTPM@ 0_0201_5%
GND 33 750_CTPM@
For EMI Reserved PGND
@ESD@ S IC NPCT750JABYX QFN 32P TPM FW 7.2.1.0 S IC NPCT750JADYX QFN 32P TPM FW 7.2.2.0
LID_CLOSE# CS22 1 2 0.1U_0402_10V7K
SA0000AQ270
UX1
HW TPM:TPM@
rn
SW TPM:fTPM@ UX1 place colse to UC3 SA0000CYO30
China TPM:CTPM ST_CTPM@
S IC ST33HTPH2X32AHD8 VQFN 32P TPM
Main Func = Thermal

+3VS
Main Func = RTC
tu
+3VS RTC power gating circuit
+3VS
1
R54 1 2 7.5K_0402_1% ALERT# +RTC_SOC +RTC_CELL
R49 Q17 SB000006R00
R55 1 2 7.5K_0402_1% T_CRIT# 2.2K_0201_5%
T_CRIT# <87>
AO3419L_SOT23-3
2
1 3
S
B B
2
+3VS Q11B
G
THM_SML1_DATA
ck
6 1
<9,58> GPU_THM_SMBDAT
1
10K_0402_5%
D
S
R63
1U_0201_6.3V6M
SB00001CW00 1
1 R50 2KV
C3
G
2.2K_0201_5%
5
C28 Q11A
2
2
G
0.1U_0402_16V7K
2
2 3 4 THM_SML1_CLK D8
<9,58> GPU_THM_SMBCLK
S
L2N7002DW1T1G_SC88-6 RB751S-40_SOD523-2
SB00001CW00 2 1
lo
2KV
1
NCT7718_DXP D
SB000009Q80
2N7002KW_SOT323-3
R64
Q13 U3 2 RTCRST_ON_R 1 2 RTCRST_ON
RTCRST_ON <58>
1 8 THM_SML1_CLK G
1 1 VDD SCL 1M_0402_5%
1
Q18
LMBT3904LT1G_SOT23-3
C @
THM_SML1_DATA
100K_0402_5%
0.1U_0402_10V7K
2 C29 C30 2 7 S
3
D+ SDA
2
22P_0402_50V8J
@
B 470P_0603_50V8J 2200P_0402_25V7K 1
2 2
R65
E 3 6 ALERT#
3
NCT7718_DXN D- ALERT#
C2
C33
ar
T_CRIT# 4 5 2KV
2
T_CRIT# GND 2
DIMM CPU Core
1
NCT7718W_MSOP8
Layout Note:
A
Layout Note: C30 close U3
A
W
DXN and DXP routing width and spacing is 10 mil / 10
mil.
2018/04/01
Compal Secret Data
2019/04/01 Title
TPM/RTC/Screw hole
5 4 3 2 1
1P
24
-L
LA
Main Func = HDD&FFS
+5VS +5V_HDD JHDD1
1
CS15 1 2 0.01U_0201_10V6K SATA_CTX_C_DRX_P0 2 1
<12> SATA_CTX_DRX_P0
CS16 1 2 0.01U_0201_10V6K SATA_CTX_C_DRX_N0 3 2 CONN FFC
80 mils 1 2 80 mils <12> SATA_CTX_DRX_N0
4 3
RS32 0_1206_5% CS17 1 2 0.01U_0201_10V6K SATA_CRX_C_DTX_N0 5 4
<12> SATA_CRX_DTX_N0 5 GND S1 1
1000P_0402_50V7K
0.1U_0402_10V7K
10U_0603_10V6M
CS18 1 2 0.01U_0201_10V6K SATA_CRX_C_DTX_P0 6
<12> SATA_CRX_DTX_P0 6
10P_0201_25V8
C104
@RF@
7
R-short 0409 1 1 1 1
RS28 1 @ 2 0_0201_5% HDD_DEVSLP_R 8 7
<12> HDD_DEVSLP 8 A+ S2 2
CS29
CS30
CS31
9
RS33 1 @ 2 0_0201_5% 10 9
2 2 2 2 <12> HDD_DET# +5V_HDD 10
11 13
12 11 GND1 14 A- S3 3
12 GND2
R-short 0409 TWVM_FPC0518-12RC-TAGHA
C104 place near JHDD1 CONN@
GND S4 4
SP01002NP00
B- S5 5
A
B+ S6 6
GND S7 7
DEVSLP P3 8
rn
5V P7 10
5V P8 11
tu
5V P9 12
GND P10
ck
Device
Activity P11 9
lo
ar
Main Func = ODD
W
1P
24
Cancel ODD
-L
LA

HDD/FFS/ODD
5 4 3 2 1
Main Func = SSD M Key CONN
+3VS_SSD +3VS
JUMP@ JPC3
80 mils 1 2
D 1 2 D
10U_0603_10V6M
0.1U_0402_10V7K
1000P_0402_50V7K
22U_0603_6.3V6M
JUMP_43X79
@ 1 1 1 1
10P_0201_25V8
C103
@RF@
CS1
CS3
CS4
CS5
2
2 2 2 2
NGFF Key M
A
+3VS_SSD
JSSD1
1 2
3 GND1 3P3VAUX2 4
rn
5 GND3 3P3VAUX4 6
<12> PCIE_CRX_DTX_N8 7 PERn3 NC_6 8 1 @ 2
<12> PCIE_CRX_DTX_P8 PERp3 NC_8 SSD_SCP# <58>
9 10 RS2 1 @ 2 0_0201_5%
CS13 1 2 0.22U_0201_10V6K PCIE_CTX_C_DRX_N8 11 GND9 DAS/DSS# 12 RS34 0_0201_5% SATA_LED# <9,63>
<12> PCIE_CTX_DRX_N8 PCIE_CTX_C_DRX_P8 PETn3 3P3VAUX12
CS14 1 2 0.22U_0201_10V6K 13 14
<12> PCIE_CTX_DRX_P8 PETp3 3P3VAUX14
tu
15 16
17 GND15 3P3VAUX16 18 R-short 0409
<12> PCIE_CRX_DTX_N7 19 PERn2 3P3VAUX18 20
C <12> PCIE_CRX_DTX_P7 PERp2 NC_20 C
21 22
CS11 1 2 0.22U_0201_10V6K PCIE_CTX_C_DRX_N7 23 GND21 NC_22 24
<12> PCIE_CTX_DRX_N7 1 2 PCIE_CTX_C_DRX_P7 25 PETn2 NC_24 26
CS12 0.22U_0201_10V6K
<12> PCIE_CTX_DRX_P7 27 PETp2 NC_26 28
ck
29 GND27 NC_28 30
<12> PCIE_CRX_DTX_N6 31 PERn1 NC_30 32
<12> PCIE_CRX_DTX_P6 33 PERp1 NC_32 34
<12> PCIE_CTX_DRX_N6 1 2 PCIE_CTX_C_DRX_P6 37 PETn1 NC_36 38
CS10 0.22U_0201_10V6K
<12> PCIE_CTX_DRX_P6 PETp1 DEVSLP SSD_DEVSLP <12>
39 40
lo
41 GND39 NC_40 42
<12> PCIE_CRX_DTX_N5 43 PERn0/SATA-B+ NC_42 44
<12> PCIE_CRX_DTX_P5 45 PERp0/SATA-B- NC_44 46
<12> PCIE_CTX_DRX_N5 PCIE_CTX_C_DRX_P5 PETn0/SATA-A- NC_48
CS8 1 2 0.22U_0201_10V6K 49 50
ar
<12> PCIE_CTX_DRX_P5 51 PETp0/SATA-A+ PERST# 52 PLTRST# <11,52,66,73>
53 GND51 CLKREQ# 54 CLKREQ_PCIE#4 <11>
<11> CLK_PCIE_N4 55 REFCLKN PEWake# 56 PCIE_WAKE# <11,52,58,73>
<11> CLK_PCIE_P4 57 REFCLKP NC_56 58
1 RS1 @ 2 GND57 NC_58
+3VS_SSD
W
10K_0402_5%
B 67 68 SSD_SUSCLK PAD~D 1 TP@ TP196 B

69 NC_67 SUSCLK(32kHz) 70
<12> M2_SSD_PEDET 71 PEDET(NC-PCIE/GND-SATA) 3P3VAUX70 72
73 GND71 3P3VAUX72 74
75 GND73 3P3VAUX74
PEDET Module Type

1P 77
79
GND75
GND77
NPTH_79
LOTES_APCI0079-P005A
CONN@
GND76
NPTH_78
76
78
SP07001EZ00
24
0 SATA
1 PCIE
-L
LA
A A

NVME SSD
5 4 3 2 1
A B C D E F G H
Main Func = eMMC
1 1
A
rn
tu
2 2
ck
lo
ar
W
3
1P 3
24
-L
LA
4 4

eMMC (RSVD)
1.0
A B C D E F G H
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
Reserve
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Func = USB3.0 Port1
EU1
W=80mils USB3.0 Port1
USB3_CRX_L_DTX_N1 1 1 10 9 USB3_CRX_L_DTX_N1 +USB3_VCC
USB3_CRX_L_DTX_P1 2 2 9 8 USB3_CRX_L_DTX_P1 JUSB1

1 @EMI@ 2 USB3_CTX_L_DRX_P1 9
RU1 0_0201_5% USB3_CTX_L_DRX_N1 4 4 7 USB3_CTX_L_DRX_N1 1 STDA_SSTX+
7
USB3_CTX_L_DRX_N1 VBUS +USB3_VCC
Layout Note: Close JUSB1
8
USB3_CTX_L_DRX_P1 5 5 6 USB3_CTX_L_DRX_P1 USB20_P1_R 3 STDA_SSTX-
6
DLM0NSN900HY2D_4P 4 D+
<12> USB20_N1
3 4 USB20_N1_R 3 3 USB20_N1_R 2 GND_1 100 mils
3 4 USB3_CRX_L_DTX_P1 6 D-
STDA_SSRX+ 1
8 7 1 1 1 1
D USB20_P1_R USB3_CRX_L_DTX_N1 GND_2 D
4.7U_0402_6.3V
22U_0603_6.3V6M
22U_0603_6.3V6M
100U_A_6.3VM_R70M
2 1 5 + @RF@
<12> USB20_P1 2 1 STDA_SSRX-
CU4
CU5
CU6
CU7
SE00000O000
S DIO(BR) AZ1045-04F.R7G DFN2510P10E ESD C100
LU1 EMI@ ESD@ ESD@ 10 10P_0201_25V8
2
EU2 11 GND1 2 2 2 2 2
AZC199-02SPR7G_SOT23-3 12 GND2
GND3
1
1 @EMI@ 2 13
RU2 0_0201_5% GND4
1
SANTA_375145-2
CONN@
DC23300TV00
A
1 2 USB3_CTX_C_DRX_P1 2 EMI@ 1 USB3_CTX_L_DRX_P1 2 EMI@ 1 USB3_CRX_L_DTX_P1
<12> USB3_CTX_DRX_P1 <12> USB3_CRX_DTX_P1
CU1 0.1U_0201_16V6K RU3 0_0402_5% RU4 0_0402_5%
3 4 3 4
rn
2 1 2 1
LU2 @EMI@ LU3 @EMI@
1 2 USB3_CTX_C_DRX_N1 2 EMI@ 1 USB3_CTX_L_DRX_N1 2 EMI@ 1 USB3_CRX_L_DTX_N1

<12> USB3_CTX_DRX_N1 <12> USB3_CRX_DTX_N1
CU2 0.1U_0201_16V6K RU5 0_0402_5% RU6 0_0402_5%
tu
C C
ck
Maximum Output
Current 2A
lo
+5VALW +USB3_VCC
UU1
1
5 OUT
IN
ar
2
4 GND
<58,73> USB_PWR_EN# EN 3
1 OCB USB_OC0# <12>
CU13
1U_0201_6V3M SY6288D20AAC_SOT23-5
2
W
Main Func = USB3.0 Port2
B
1P +USB3_VCC
USB3.0 Port2
JUSB2
B
1 @EMI@ 2 USB3_CTX_L_DRX_P2 9
EU3 1 STDA_SSTX+
24
RU7 0_0201_5% Layout Note: Close JUSB2
USB3_CRX_L_DTX_N2 1 1 9 USB3_CRX_L_DTX_N2 USB3_CTX_L_DRX_N2 8 VBUS +USB3_VCC
10
USB20_P2_R 3 STDA_SSTX-
DLM0NSN900HY2D_4P USB3_CRX_L_DTX_P2 2 2 8 USB3_CRX_L_DTX_P2 4 D+
<12> USB20_P2
3 4 USB20_P2_R
9
USB20_N2_R 2 GND_1 100 mils
3 4 USB3_CTX_L_DRX_N2 4 4 7 USB3_CTX_L_DRX_N2 USB3_CRX_L_DTX_P2 6 D-
7
STDA_SSRX+ 1
7 1 1 1 @ 1
USB20_N2_R USB3_CTX_L_DRX_P2 USB3_CTX_L_DRX_P2 USB3_CRX_L_DTX_N2 GND_2
4.7U_0402_6.3V
22U_0603_6.3V6M
22U_0603_6.3V6M
100U_A_6.3VM_R70M
2 1 5 5 6 6 5 + @RF@
<12> USB20_N2 2 1 STDA_SSRX-
CU9
CU10
CU11
CU12
C101
2
3
LU4 EMI@ 3 3 10 10P_0201_25V8
GND1
-L
2 11 2 2 2 2 2
3
ESD@ GND2
8 12
1 @EMI@ 2 AZC199-02SPR7G_SOT23-3 13 GND3
GND4
1
RU8 0_0201_5% S DIO(BR) AZ1045-04F.R7G DFN2510P10E ESD EU4

ESD@ SANTA_375145-2
1
CONN@
DC23300TV00
LA
1 2 USB3_CTX_C_DRX_P2 2 EMI@ 1 USB3_CTX_L_DRX_P2 2 EMI@ 1 USB3_CRX_L_DTX_P2

<12> USB3_CTX_DRX_P2 <12> USB3_CRX_DTX_P2
CU14 0.1U_0402_10V7K RU9 0_0402_5% RU10 0_0402_5%
3 4 3 4
2 1 2 1
A A
LU5 @EMI@ LU6 @EMI@
1 2 USB3_CTX_C_DRX_N2 2 EMI@ 1 USB3_CTX_L_DRX_N2 2 EMI@ 1 USB3_CRX_L_DTX_N2

<12> USB3_CTX_DRX_N2 <12> USB3_CRX_DTX_N2
CU15 0.1U_0402_10V7K RU11 0_0402_5% RU12 0_0402_5%

USB3.0
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
Reserve
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
Main Func = USB2.0 Port3 + Card Reader on IO/B Main Func = FPR
+5VALW +USB2_VCC 1 @EMI@ 2

RU13 0_0201_5%
UU2
1 DLM0NSN900HY2D_4P
5 OUT 3 4 USB20_P7_R
IN <12> USB20_P7 3 4
2
4 GND
<58,71> USB_PWR_EN# EN 3 2 1 USB20_N7_R
OCB USB_OC1# <6> <12> USB20_N7 2 1
1
CU16 SY6288D20AAC_SOT23-5 LU7 EMI@
D D
1U_0201_6V3M
2 +USB2_VCC 1 @EMI@ 2
RU14 0_0201_5% +3VALW
1 1 @EMI@ 2 R6242 2 @ 1 10K_0201_5%

CU17 RU15 0_0201_5%
22U_0603_6.3V6M
@ +3VS
2 LU8 EMI@
3 4 USB20_P3_R FPR_SCAN# R6 2 1 10K_0201_5%
<12> USB20_P3 3 4
A
2 1 USB20_N3_R
<12> USB20_N3 2 1
DLM0NSN900HY2D_4P
1 @EMI@ 2
RU16 0_0201_5%
rn
Main Func = PWR Button
tu
POWER_SW#_MB
<58> POWER_SW#_MB
TST71-N-220-T170-S017_2P
ck
C C
SW1
@
2
lo
JIOB1 and JIOB2 CONN co-lay
ar
JIOB1 CONN@
<12> PCIE_CRX_DTX_P9 1
1
W
2
<12> PCIE_CRX_DTX_N9 2
3
for co-lay add net , Pin1/2 in 34 pin should be NC JIOB2 CONN@ CL8 1 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_P9 4 3
PCIE_WAKE# 1 <12> PCIE_CTX_DRX_P9 PCIE_CTX_C_DRX_N9 4
CL9 1 2 0.1U_0201_10V6K 5
AUX_ON 1 <12> PCIE_CTX_DRX_N9 5
2 6
3 2 7 6
+USB2_VCC 3 <11> CLK_PCIE_P2 7
4 8
80 mils 5 4 <11> CLK_PCIE_N2 9 8
6 5 <11,52,66,68> PLTRST# 10 9
6 <11> CLKREQ_PCIE#2 10
7 <11,52,58,68> PCIE_WAKE# 11
8 7 12 11
+3VALW
+3VS N3V3_DET
1P
9
10
11
8
9
10
11
<58> AUX_ON
High Active
+USB2_VCC
80 mils
13
14
15
12
13
14
15
2
USB20_P7_R 12 16
B USB20_N7_R 13 12 RL11 17 16 B
14 13 100K_0402_5% 18 17
USB20_P3_R 14 +3VALW 18
15 +3VS 19
USB20_N3_R 16 15 N3V3_DET 20 19
1
17 16 <10> N3V3_DET 21 20
USB20_P5 18 17 USB20_P7_R 22 21
24
USB20_N5 19 18 USB20_N7_R 23 22
20 19 24 23
POWER_SW#_MB 21 20 USB20_P3_R 25 24
LID_CLOSE# 22 21 USB20_N3_R 26 25
FPR_SCAN# 23 22 27 26
AUD_AGND 24 23 USB20_P5 28 27
HPOUT_L 24 <12> USB20_P5 USB20_N5 28
25 <12> USB20_N5 29
SLEEVE_R 26 25 30 29
27 26 POWER_SW#_MB 31 30
-L
28 27 LID_CLOSE# 32 31
RING2_R 29 28 <66> LID_CLOSE# FPR_SCAN# 33 32
30 29 <58> FPR_SCAN# AUD_AGND 34 33
31 30 HPOUT_L 35 34
HPOUT_R 32 31 <56> HPOUT_L SLEEVE_R 36 35
JACK_PLUG 33 32 35 <56> SLEEVE_R 37 36
34 33 GND1 36 38 37
34 GND2 RING2_R 39 38
<56> RING2_R 39
LA
HEFEN_AFC69-S34FIA-1H 40
41 40
AUD_AGND HPOUT_R 42 41
<56> HPOUT_R JACK_PLUG 43 42 45
<56> JACK_PLUG 44 43 GND1 46
44 GND2
HEFEN_AFC69-S44FIA-1H
AUD_AGND
A A

Finger Print & I/O CONN
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
C C
ck
Reserve
lo
ar
W
B B
1P
24
-L
LA
A A

DOCK(RSVD)
5 4 3 2 1
5 4 3 2 1
(6) +3VALW
(6) +3VALW
10k-ohm VIN
(3) B+
VOUT (3) B+
(2) +SDC_IN +3VALW_PCH
VIN CHARGER
(4) ACAV_IN1 (6) VCCDSW_EN_GPIO (7) +3VALW_PCH (7) +3VALW_PCH 0-ohm (7) +3VALW_DSW
EN VOUT
ACOK VIN (6) POK
PG
D D
(5) ALWON
+3VALW
(6) +3VALW
EN VOUT
(3) B+ 0-ohm
(10) SIO_SLP_SUS# (10) PCH_PRIM_EN
(6) +3VALW
VIN
PG (6) POK
(1) +RTC_VCC (3) B+
A
(5) ALWON
+5VALW
(6) +5VALW 100k -ohm
EN VOUT
VIN
PG (12) 1.8V_PRIM_PG
(3) +3VLP
+1.8V_PRIM (6) +3VALW
(7) +3VALW_PCH (10) PCH_PRIM_EN (11) +1.8V_PRIM
EN VOUT
(7) +3VALW_DSW
rn
(3) B+
(5) ALWON 100k -ohm
100K-ohm (6) +3VALW
VBAT GPIO_172 GPIO250
10K-ohm VCI_OVRD_IN VCI_OUT VIN (15) PG_VCCIN_AUX
PG
+VCCIN_AUX
tu
(6) POK 100K-ohm (12) 1.8V_PRIM_PG (14) +VCCIN_AUX
ACPRESENT EN VOUT
(9) PCH_DPWROK
DSW_PWROK (8) PCH_DPWROK_EC
(7) +3VALW_DSW VCC_DSW3P3 GPIO_207 for TGL 0-ohm
(6)VCCDSW_EN
GPIO_012
(6) VCCDSW_EN_GPIO
(10) SIO_SLP_SUS#
SLP_SUS# open 1.8V_Prim (6) +3VALW (3) B+ (3) B+
(7) +3VALW_PCH
C VCC_PRIM3P3 C
ck
(16) PCH_RSMRST# (15) PRIM_PWRGD 0-ohm
RSMRST# VIN
VOUT (24) +2.5V_MEM VIN
(17) PCH_RSMRST#_AND nRESET_IN
RSMRST#
(6) POK EC_RESET# +2.5V_MEM +1.2V_DDR
GPIO_227 (23) SIO_SLP_S4# (24) +2.5V_PG (25) +1.2V_DDR
EN PG EN VOUT
(18) ESPI_RESET#
ESPI_RESET# GPIO_061
ESPI_RESET# PG (25) 1.2V_VTT_PWRGD
lo
(19) ESPI_IO
ROM SPI ESPI_IO ESPI_IO +0.6V_DDR_VTT
high with 1.2V_DDR
(25) DDR_VTT_CNTL (26) DDR_VTT_CNTL (27) +0.6V_DDR_VTT
Buffer EN VOUT
(20) POWER_SW_IN#
(11) +1.8V_PRIM GPIO_163/VCI_IN0# Power Button
VCCPRIM_1P8
ar
(12) +VCC1.05_OUT_PCH (21) SIO_PWRBTN# (12) +VCC1.05_OUT_FET
VCCPRIM_1P05 PWRBTN# GPIO_254
(12) +VCC1.05_OUT_FET
VCC1P05
SLP_S5#
(22) SIO_SLP_S5#
GPI0_040
EC 1515 (13) CORE_VID0
(13) CORE_VID1
(14)VCCIN_AUX_CORE_VID
VIN
+VCCST_CPU
W
(23) SIO_SLP_S4#
SLP_S4# GPIO_026
(15) VCCST_EN (16) +VCCST_CPU
(24) SIO_SLP_S0# EN VOUT
SLP_S0#
SLP_S3# (24) SIO_SLP_S3# VCCST_OVERRIDE_R
GPIO_032
(6) +3VALW (24) CPU_C10_GATE#
CPU_C10_GATE# SLP_VCCST_OVRD (12) +VCC1.05_OUT_FET
(24) SIO_SLP_S3#
100k-ohm (13) CORE_VID0 (13) CORE_VID0

CORE_VID0
TGL U PCH (28) VCCST_PWRGD
(MIPI60 debug use only)
VIN
Level
VCCST_PWRGD +VCCSTG_CPU
B
100k-ohm (13) CORE_VID1 (13) CORE_VID1
VCCST_OVERRIDE_R
CORE_VID1
VCCST_OVERRIDE
Shifter
UZ3
(28) IMVP_VR_ON_P
open VCCIN
1P
(27) IMVP_VR_EN
GPIO_033 (24) CPU_C10_GATE#
EN
VOUT
(32) +VCCSTG_CPU
(6) +3VALW
B
(32) CPUPWRGD
24
0-ohm VIN
+3VS
10ms 10ms
delay delay (24) SIO_SLP_S3# (25) +3VS
(30) IMVP_VR_PG EN VOUT
(31) PCH_PWROK (34) PCH_PLTRST# (35) PCH_PLTRST#_EC

PCH_PWROK PLTRST#
+5VS
-L
(26) RUNPWROK (33) SYS_PWROK

SYS_PWROK
(ALL_SYS_PWRGD) (24) SIO_SLP_S3# (25) +5VS
EN VOUT
Reserve AND gate (25) +3VS
VIN
(6) +5VALW
(33) SYS_PWROK
LA
GPIO_106/PWROK 10K-ohm delay

All_SYS_PWRGD power down use S3 off
(26) RUNPWROK
(ALL_SYS_PWRGD) (24) SIO_SLP_S3#
GPIO_057/VCC_PWRGD Buffer
UZ1
(25) 1.2V_VTT_PWRGD
A
(3) B+ A
VIN
PG (30) IMVP_VR_PG
+VCCIN
(28) IMVP_VR_ON_P (29) +VCCIN
EN VOUT
2018/04/01
Compal Secret Data
2019/04/01 Title
(RSVD)
1.0
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
A
rn
tu
Reserve
C C
ck
lo
ar
W
B B
1P
24
-L
LA
A A

(RSVD)
5 4 3 2 1
5 4 3 2 1
EMI reserve bridge
+5VALW
@EMI@
D D
C44 1 2 33P_0201_50V8J
@EMI@
C45 1 2 33P_0201_50V8J
A
rn
tu
PCB PN
ck
C C
Screw hole/FD FAN +5VS

HCPU1 HCPU2 HCPU3 HCPU4
HOLEA HOLEA HOLEA HOLEA
H1 H2 H3 H4 H5 H6
PCB R1
lo
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA 1
22U_0603_6.3V6M
1
C27
ZZZ
1
H_3P6-G-V H_3P6-G-V H_3P6-G-V H_3P6-G-V 2 DA6002E0000
ar
H_2P5X3P0 H_6P0X8P0 H_2P5X4P9-G-V H_3P7-G-V H_6P0 H_2P5-G-V UMAPCBN3@
CPU
PCB 3LE LA-L241P REV0 M/B 1 S S
H7 H8 H9 H12 JFAN1
HOLEA HOLEA HOLEA HOLEA 1 ZZZ
FD1 FD2 FD3 FD4 2 1
W
<58> PWM_FAN1 2
3 DA6002E0100
<58> TACH_FAN1 3
4
1
4 5 UMAPCBV3@
PU 10k on EC side
1
G1 6
H_7P0-G-V H_2P5 H_2P8-G-V H_3P2-G-V G2 PCB 3LE LA-L241P REV0 M/B 1 L S
TWVM_WTB1220-04RD-TAGHD
CONN@
SP02001RJ00
B
1P need to check pin define with Thermal
ZZZ
PCB DAZ R1
ZZZ
PCB DAZ R3
B
24
DAZ3LE00100 DAZ3LE00101
DAZN3R1@ DAZN3R3@
PCB 3LE LA-L241P REV0 M/B 1 S S PCB 3LE LA-L241P REV0 M/B 1 S S
ZZZ ZZZ
-L
DAZ3LK00100 DAZ3LK00101
DAZV3R1@ DAZV3R3@
PCB 3LE LA-L241P REV0 M/B 1 L S PCB 3LE LA-L241P REV0 M/B 1 L S
LA
A A
1029 ME update
PWRBTN/PCB PN//SCREW/FAN
Date: Wednesday, April 14, 2021 Sheet 77 of 121
5 4 3 2 1
5 4 3 2 1
Main Func = DC/DC

Sequence Logic
+5VS / +3VS for System +5VALW +5VS
<11,89> SIO_SLP_S4#
1
DZ1
2
+2.5V_PG <89>
UZ2 RB751S-40_SOD523-2
CZ3 2 1 1 14 1 2 SCS00006300
2 VIN1 VOUT1 13 CZ2 0.1U_0402_10V7K
1U_0201_6V3M VIN1 VOUT1 1 @ 2
3 12 1 2 RZ1 0_0201_5%
ON1 CT1 CZ4 470P_0402_50V7K R-short 0409
4 11
VBIAS GND RZ4
5 10 1 2 0_0402_1%
<11,38> SIO_SLP_S3# ON2 CT2 PCH_PRIM_EN_R 1
CZ7 470P_0402_50V7K <11> SIO_SLP_SUS# RZ3 1 2 0_0201_5% @ 2
PCH_PRIM_EN <90>
0.1U_0201_6.3V6K
1 6 9
+3VALW VIN2 VOUT2 +3VS
@ESD@
7 8
VIN2 VOUT2
1
VCCDSW_EN_GPIO
CZ8
1M_0201_5%
1
15
@ RZ5
@ CZ9
1 1
0.1U_0402_25V6
D 07/4 ESD require 2 GPAD DZ3 D
CZ10
1U_0201_6.3V6M EM5209VF_DFN14_3X2 CZ11 RZ7 1 @ 2 0_0201_5% 2 1 VCCDSW_EN_Q RZ29 1 @ 2 0_0201_5%
<58> VCCDSW_EN
2
0.1U_0402_10V7K
2
2 2 RB751S-40_SOD523-2
R-short 0409 SCS00006300
DZ4
1 2
<78,82,87> POK
RB751S-40_SOD523-2
SCS00006300
+3VALW TO +3VALW_PCH
A
JP8
CZ15 2 1
Always Short +3VALW_PCH
UZ4 +3VALW_PCH
DVT1
1U_0201_6.3V6M JP1 JUMP@
+3VALW 1
2 VIN VOUT
7
8
+3VALW_PCH_OUT 1
1 2
2
+3VALW +3VALW_PCH
VIN VOUT
1
JUMP_43X79 CZ38
VCCDSW_EN_GPIO RZ8 1 2 0_0402_5% 3 6 RZ32 1 2 0.1U_0402_16V7K
ON CT 1
1
CZ16
1 1 0.1U_0402_10V7K 100K_0402_5% RZ33
4 @ 100K_0402_5%
rn
+5VALW
2
VBIAS
5
CZ18 5 CZ19 2
1 GND
0.22U_0402_16V7K CZ20 9 1000P_0402_50V7K PCH_DPWROK_EC 1
P
<58,59> PCH_DPWROK_EC
2
2 1U_0201_6V3M GND 2 B 4 PCH_DPWROK
O PCH_DPWROK <11>
1 POK 2 1
IMVP_VR_ON&VCCST_PWRGD
A
G
2 TPS22967DSGR_SON8_2X2
CZ40 UZ14 CZ39
3
0.22U_0402_16V7K MC74VHC1G08EDFT2G_SC70 @ 100P_0402_50V8J
2 2
SA0000BIP00
+3VS
tu
2nd should pick CMOS And gate
1
RZ9
R-short 0409 10K_0402_5%
2
RZ10 1 @ 2 0_0201_5% ALL_SYS_PWRGD
<89> 1.2V_VTT_PWRGD ALL_SYS_PWRGD <58,87>
Buffer with Open Drain Output For ALL_SYS_PWRGD

RSMRST circuit
0.1U_0201_16V6K
C C
2
+3VALW
@ESD@
CZ21
ck
+3VALW 07/4 ESD require DZ2 CZ1
@ CZ17 1 2 0.1U_0402_16V7K 2 1
1 2 1
RB751S-40_SOD523-2 UZ1
0.1U_0201_16V6K SCS00006300 1 5
NC VCC
5
SIO_SLP_S3# 1 RZ2 2 2
1 10K_0402_1% A 4 ALL_SYS_PWRGD
1
P
<58,59> PCH_RSMRST#_R B PCH_RSMRST#_AND Y

4 3 1
O PCH_RSMRST#_AND <11,63,79> GND
POK 2 CZ5
<78,82,87> POK A
G
1U_0402_10V6K 74AUP1G07GW_TSSOP5 CZ6
lo
1
UZ5 2 @ 100P_0402_50V8J
3
MC74VHC1G08EDFT2G_SC70 RZ37 +3VALW CC113 2

0.1U_0201_10V6K
SA0000BIP00 100K_0201_5%
1 2
2
2nd should pick CMOS And gate Buffer with Open Drain Output For H_VCCST_PWRGD
UC34
5
MC74VHC1G08EDFT2G_SC70 +3VALW +1.05V_VCCST
SIO_SLP_S3# 1
SA0000BIP00
P
B 4 IMVP_VR_ON_P 0.1U_0402_16V7K 2 1 CZ12
ar
O
1
2
<58> IMVP_VR_EN A
G
UZ3 RZ6 @
3.3Valw 1 5 100K_0201_5%
R-short 0409
3
NC VCC
IMVP_VR_ON_P 2
Change to pop 1.05V
2
A
1
RC282 1 @ 2 0_0201_5% 4 1
IMVP_VR_ON_EN <98> Y VCCST_PWRGD <11>
1 2 RC284 3
GND
0.1U_0402_10V7K
@ RC283 0_0201_5% 100K_0201_5% 2 CZ13 @
@ESD@
CZ14
Change to pop 74AUP1G07GW_TSSOP5 100P_0201_25V8J
W
VCCSTG 2
2
DVT2_0618 1
+VCC1.05_OUT_FET
1 07/4 ESD require

STG@
CZ24
1U_0201_6.3V6M
2
DVT1_17
VCCST
B
<11> CPU_C10_GATE#
RZ1414 2 @
+VCC1.05_OUT_FET
1 0_0402_1% VCCSTG_EN
+5VALW
1
2
4
UZ8
VIN1
VIN2
VIN thermal
VBIAS
ON
VOUT
GND
6
5
+VCCSTG_R 1
0_0603_5%
@
+VCCSTG_CPU
R-short 0409
+VCCSTG_CPU
2
RZ17
1P B
AOZ1334DI-01_DFN8-7_3X3
R-short 0409
24
STG@ 1
STG@
CZ25
0.1U_0201_10V6K +VCCSTG_CPU
2
1 @ 2
RZ31 0_0603_5%
+VCC1.05_OUT_FET
+1.2V_VDDQ TO +1.2V_VCCPLL_OC 1
UZ12
+1.05V_VCCST
-L
2 VIN1
VIN2
+5VALW 7 6 +VCCST_R 1 2
VIN thermal VOUT RZ23 0_0603_5%
R-short 0409 3
VBIAS
SIO_SLP_S3# RZ24 1 @ 2 0_0402_1% VCCST_EN 4 5 +1.05V_VCCST
ON GND
AOZ1334DI-01_DFN8-7_3X3 1
CZ31
LA
0.1U_0201_10V6K
2
+VCC1.05_OUT_FET
1
CZ33
1U_0201_6.3V6M
2
DVT1_17
SN74AUP1G97DRLR truth table
A A

2018/04/01 2019/04/01 Title
DC/DC
1.0
Date: Friday, April 16, 2021 Sheet 78 of 121
5 4 3 2 1
5 4 3 2 1
Main Func = Debug connector

SOC_XDP_TDO 1
<7> SOC_XDP_TDO TP140
+1.05V_VCCSTG
Place to CPU side CMC@TP@
SOC_XDP_TDI 1
<7> SOC_XDP_TDI TP141
CMC@TP@
RC360 2 CMC@ 1 51_0201_5% SOC_XDP_TMS SOC_XDP_TMS 1
<7> SOC_XDP_TMS TP142
CMC@TP@
RC361 2 CMC@ 1 51_0201_5% SOC_XDP_TDI SOC_XDP_TCK0 1
<7> SOC_XDP_TCK0 TP143
CMC@TP@
RC362 2 CMC@ 1 100_0201_5% SOC_XDP_TDO near D12 SOC_XDP_TRST# 1
<7> SOC_XDP_TRST# TP144
CMC@TP@
RC363 2 CMC@ 1 100_0201_5% SOC_XDP_TDO near E12 PCH_JTAG_TCK1 1
<7> PCH_JTAG_TCK1 TP145
CMC@TP@
RC364 2 @ 1 51_0201_5% XDP_PREQ# XDP_SPI_IO2 1
XDP_PREQ# <7> <9> XDP_SPI_IO2 TP148
CMC@TP@
XDP_SPI_SI 1
D +VCC1.05_OUT_FET <9> XDP_SPI_SI DBG_PMODE TP149 D
1 CMC@TP@
<7> DBG_PMODE PCH_RSMRST#_AND TP150
1 CMC@TP@
<11,63,78> PCH_RSMRST#_AND TP151
CMC@TP@
RC365 1 2 1K_0201_5% DBG_PMODE XDP_ITP_PMODE
DFX TEST MODE
RC366 1 @ 2 1K_0201_5% INTERNAL PD 20K
HIGH: DFX TEST MODE DISABLED(DEFAULT)
LOW: DFX TES TMODE ENABLED
RC367 2 CMC@ 1 51_0201_5% SOC_XDP_TCK0
RC368 2 @ 1 51_0201_5% PCH_JTAG_TCK1
A
RC369 2 @ 1 51_0201_5% SOC_XDP_TRST#
Place to CPU side
rn
XDP_PRDY# 1
<7> XDP_PRDY# TP147
CMC@TP@
tu
ck
C C
lo
ar
W
B
1P B
24
-L
LA
A A

Debug connector
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
C C
ck
lo
ar
W
B B
1P
24
-L
LA
A A

XDP
B 1.0
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
A B C D
Main Func = DCIN CONN 1

@ PJP1
1 2
2 HBM (2000~<4000)
CDM (>=2000) PSID@ PQ1
JUMP_43X79
+19V_VIN FDV301N-G_SOT23-3
PSID@ PR1
@ PJPDC1 EMI@ PL1 1 3 33_0402_5%
S
D
5A Z150 20M 1210_2P PSID-2 PSID-3 1 2 PS_ID <58>
8 +19V_ADPIN 1 2
GND 7
GND
1000P_0402_50V7K
1
6 PSID@ PR4
2200P_0402_50V7K
1000P_0402_50V7K
2200P_0402_50V7K
2
10P_0402_25V8J
100P_0201_50V8J
6
100K_0402_1%
1
TVNST52302AB0_SOT523-3
5 10K_0402_1% PR5 PSID@
100P_0201_50V8J
5
@ESD@ PC6
PSID@ PR3
4 2 1 2.2K_0402_5%
4
+5VALW
3
EMI@ PC1
EMI@ PC2
@ESD@ PC5
EMI@ PC3
EMI@ PC4
3
@RF@ PC15
3 2
2
2
@ESD@ PD1
1 1 2
LMBT3904WT1G NPN SC70-3 -D

2
1
+3VALW
1
1 @EMI@ PL2 C 1
PQ2
5A Z150 20M 1210_2P PSID-1 2
ACES_50458-00601-001 B
1
@PJP2 E @ PR7
3
+5VALW
1
PR6 PSID@
1 2 3
PSID@
100_0402_5%
HBM (4000~<8000)
15K_0402_1%
1 2 1 2 1
JUMP_43X79 EMI@ PL3 CDM (1000~<1500) 2
BLM15AG102SN1D_2P
PSID 1 2 @ PD2
2
BAV99W_SC70-3
1
A
@ PD3
BAV99W_SC70-3
3
rn
+5VALW
tu
Battery Bot Side
PIN1 GND
PIN2 GND
PIN3 GND
ck
2 2
PIN4 SYS_PRES
PIN5 BATT_PRS
PIN6 DAT_SMB
PIN7 CLK_SMB
PIN8 Batt+
lo
PIN9 Batt+
PIN10 Batt+
SP021412220
ar
ACES_50458-01001-P01_10P-T
W
3
1P 3
24
Adapter protection: Battery protection: +19V_VIN
-L
if battery removed, adaptor only, asserts H_PROCHOT# when adaptor is Erp lot6 Circuit
then trigger the H_PROCHOT#, unplugged, keep low for 10ms HBM (1000)
keep @ in BOM since battery can not till SW PROCHOT# is issued by EC CDM (1000~<1500) @ PR31
1
be removed by end user <11,58,63,85,111> HW_ACAV_IN 0_0402_5%
3.3K_1206_5%
1
1 2
H_PROCHOT#
@ PR32
+19V_VIN +3VALW
10K_0402_1%
<7,16,58,85,98> H_PROCHOT# @ PR34
LA
1
1M_0402_1%
3 2
PR33
@ PR35
2
3
PC13 0_0402_5%
NX7002BKS 2N SOT363-6 -D
.1U_0402_16V7K 1 2
2N7002KDW_SOT363-6
1
PQ12B
@ PQ13B
2
PR36 1 2 5 POK <78,87> 5
6
@ PC14 1M_0402_1%
1
.1U_0402_16V7K
2N7002KDW_SOT363-6
NX7002BKS 2N SOT363-6 -D
4
1
1
D
@ PQ13A
2
<58,83,85> PBAT_PRES#
PQ12A
1 2 2 @ PQ11 PR40 2 @ PR38
G 2N7002KW_SOT323-3 2 100K_0402_1% 1M_0402_1%
1
100K_0402_1%
S
3
2
1
2
@ PR45
2
PR43
PR44 1M_0402_1%
4 1M_0402_1% 4
@
2
2
1
PWR_DCIN CONN
A B C D
A B C D
Main Func = BATT CONN
1 1
A
rn
+17.4V_BATT+
1
@ PJP3
2
+17.4V_BATT++
1 2
JUMP_43X79
EMI@ PL4
tu
5A Z150 20M 1210_2P
1 2
10P_0402_25V8J
Battery Bot Side
1
1000P_0201_50V7K
0.01UF_0402_25V7K
1
1
@RF@ PC16
EMI@ PC11
EMI@ PC12
@ESD@ PD5 @ESD@ PD6
L03ESDL5V0CG3-2_SOT-523-3-X L03ESDL5V0CG3-2_SOT-523-3-X
PIN1 GND
2
PIN2 GND
PIN3 GND
ck
2 2
PIN4 SYS_PRES
PIN5 BATT_PRS
@ PBATT1
PIN6 DAT_SMB 1
1
PIN7 CLK_SMB 2
2
3
PR37
100_0402_5%
PIN8 Batt+ 3 4 CLK_SMB 1 2 +3.3V_BAT_LDO
lo
4 5 DAT_SMB 1 2 PR39
PIN9 Batt+ 5 6 PBAT_PRES#_R 1 2
PIN10 Batt+ 6
7
7 SYS_PRES PR42
8 100_0402_5%
SP021412220 8 9 0_0402_5%
9 10
10 11
ar
ACES_50458-01001-P01_10P-T GND 12 PBAT_CHG_SMBCLK <58,85>
GND
ACES_50458-01001-P01
PBAT_CHG_SMBDAT <58,85>
99.9
W
3
1P 3
24
COIN RTC Battery
+3VALW_EC
+3VLP +3.3V_BAT_LDO
1
PR18
-L
100K_0402_1%
+3.3V_BAT_LDO
1
PR16
2
PR19 1K_0201_5%
PBAT_PRES# <58,82,85> 0_0201_5%
2
1
D
2
LA
PQ5
2
G 2N7002KW_SOT323-3 PD4
BAS40CW SOT-323
S
3
HBM (2500)
1
PR12
+RTC_CELL
1
1M_0402_1% CDM (1500)
1
2
PC20
1U_0402_25VAK
2
4 4
PWR_BATT CONN
A B C D
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
A B C D
Main Func = CHARGER
1M_0402_1%
HBM (2500)
2
PRB04
CDM (1500) PQB12 Effective
PQB11
PE600BA_PDFN8-5 PRB02
+19VB Lgate LDO output
1 0.01_1206_1%
2N7002KW_SOT323-3
EMB04N03H_EDFN5X6-8-5 2 capacitance Capacitance
1
1 3 5 1 4 EMI@ PLB02 (post-
1
2 D 5A_Z80_0805_2P
+19V_VIN +CHARGER_SRC derating)
PQB30
5 3 2 2 3 1 2
2200P_0402_50V7K
G
0.1U_0402_25V_X5R
1000P_0402_50V8J
1000P_0402_50V8J
4
@ PJPB01
15U_B2_25VM_R100M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
S
3
1 PRB03 2
1 2
3M_0402_5%
HBM (700)
10P_0402_25V8J
1 1nF 0.4uF
4
1 2
CDM (2000)
1
+
PCB70
PCB20
PCB21
EMI@ PCB22
EMI@ PCB23
EMI@ PCB24
EMI@ PCB25
EMI@ PCB26
EMI@ PCB27
@RF@ PCB72
JUMP_43X118
1 2nF 0.4uF 1
2
@ 2
HBM (500~<999)
CDM (1000)
5nF 0.4uF
6.5nF 0.4uF
0.022U_0402_25V7K
1
PCB01
A
1
1
HBM (500~<999) 10nF 0.4uF
3
PRB11 PRB12
1_0402_1% 2_0402_5% @ESD@ PDB13 CDM (1000)
AZ4024-02S_SOT23
5
CSIP_CHG
CSIN_CHG
PQB13
15nF 0.8uF
PE600BA_PDFN8-5 PD14
1
PCB03
rn
0.1U_0402_25V7K 3
1 2 BGATE_CHG 4 1
20nF 0.8uF
1
1
PRB07 PRB08
4.02K_0402_1% 4.02K_0402_1% +19V_VIN PCB04 PCB05 AZ4024-02S_SOT23 25nF 1uF
0.47U_0402_25V6K
3
2
1
1
0.22U_0402_25V5K 1U_0402_25VAK @ESD@
2
tu
PCB28
ASGATE_CHG
CMSRC_CHG
@
0.1U_0402_25V7K
30nF 1uF
2
1
@
2
PCB06
PRB09
374K_0402_1%
BAS40CW SOT-323
2 1
PDB01
2
@
BA_PWR 3
100K_0402_5%
PRB14
HBM (500~<999)
1
<111> ACIN_CHG
ck
2
1 0_0603_5% 2
2 CDM (1000)
PRB13
@ PDB14
0.01UF_0402_25V7K
+19V_VIN
PCB02
PRB10
2N7002KW_SOT323-3
RB751V-40_SOD323-2
1
1
5
D 48.7K_0402_1%
PQB31
2 PQB26
<58> AC_DIS
2
BOOT1_CHG
G PE600BA_PDFN8-5
2
S HBM (2500)
3
2
1
PRB45
ACIN_CHG
NTC_CHG
UG1_CHG
LX1_CHG
LG1_CHG
CDM (1500)
1
100K_0402_1% PRB39 UG1_CHG 4
lo
4.7_0402_5%
PRB15 1 2 VDD_CHG
10_1206_5% +17.4V_BATT+_R
2
PCB07 PUB01
16
15
14
13
12
11
10
33
2
3
2
1
9
4.7U_0603_25V6K ISL95522AHRZ-TS2778_TQFN32_4X4
2 1 DCIN_CHG ACIN
CSIN
NTC
GND
BOOT
CSIP
UGATE
PHASE
LGATE
ar
PCB19
PRB16 75K_0402_1% Vmax=5.8V
2 1 17 8 VDDP_CHG 1 2 PRB01
PCB08 DCIN VDDP PLB01
0.01_1206_1%
1 2 VDD_CHG 18 7 ASGATE_CHG 4.7UH_5.5A_20%_7X7X3_M
PRB17 150K_0402_1% VDD ASGATE 2.2U_0402_16V6K LX1_CHG 1 2 1 4
1
1 2 PROG_CHG 19 6 QPCN_CHG
2.2U_0402_16V6K PROG QPCN
PRB18 200K_0402_1% 2 3 +17.4V_BATT+
5
PRB25 2 1 ACLIN_CHG 20 5 CMSRC_CHG PCB18
ACLIM CMSRC
1
499K_0402_1% @ PRB19 0.47U_0402_25V6K PQB25
4.7_1206_5%
1 2 0_0402_5% 21 4 QPCP_CHG 1 2
@EMI@ PRB40
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
PE600BA_PDFN8-5
2
<58,83> PBAT_CHG_SMBDAT @ PRB20 SDA QPCP

<11,58,63,82,111> HW_ACAV_IN 1 2 22 3 FSET_CHG 1 2
0_0402_5%
SCL FSET
1
<58,83> PBAT_CHG_SMBCLK LG1_CHG 4
PCB30
PCB31
PCB32
PCB33
PCB34
1SNUB1_CHG 2
1
1@ PRB21 2 0_0402_5% 23 2 CSOP_CHG

768K_0402_1%
PRB38
<7,16,58,82,98> H_PROCHOT# PROCHOT# CSOP
PRB26
22.6K_0402_1%
2
24 1 CSON_CHG
BATGONE
PROH
ACOK CSON
680P_0402_50V7K
BGATE
3
2
1
CCLIM
@
BMON
AMON
COMP
1 ACOK_CHG
1P
PSYS
2
VBAT
HBM (500~<999)
2
@ PRB22 0_0402_5%
CDM (1000)
@EMI@ PCB29
PRB23 PCB09
25
26
27
28
29
30
31
32
3 100K_0402_1% 10P_0402_50V8J 3
2
@ PRB24 1 2 1 2
100K_0402_1%
BGATE_CHG
COMP_CHG
VBAT_CHG
2 1 BATGONE_CHG
<58,82,83> PBAT_PRES#
PRB31
PRB27 200K_0402_1%
24 1
VDD_CHG 1 2 PQB28
3
@ LMUN5113T1G_SOT323-3
0_0603_5%
@ PRB28 100K_0402_1%
1 2
PRB41
0_0402_5%
2
2
@ PRB29 PCB17
1 2 0_0402_5% 1U_0402_25VAK @
<58> I_BATT_R
2
1 2
PQB29
2200P_0402_50V7K
-L
1
499_0402_1%
@ LTC015EUBFS8TL_UMT3F
1
1
PRB36 2_0402_5%
10.5K_0402_1%
1
1 2
PCB10
PRB30
0_0402_5%
0.1U_0402_25V7K
0.1U_0402_25V7K
560P_0402_50V7K
1
PRB33
1
1
PRB34
2
PCB13
PCB15
I_ADP_R
2
BA_PWR
PCB12
PRB37
2
@ <11> SIO_SLP_S5#
2
@ 1 2 0_0402_5%
0.22U_0402_16V7K
2
LA 1
3
PCB11
Delay adaptor OC H_PROCHOT# @ PCB16

2
2ms while hybrid power 1 2 Effective Renesas

transition 0.22U_0402_25V6K
CPN Value capacitance recommend
+3VALW 2 1 +17.4V_BATT+
VDD_CHG <58> I_ADP_R <98> I_SYS
PRB35
DCIN SE000013880 4.7uF_0603_25V 0.4uF 0.4uF
H_PROCHOT# 100_0402_5%
1
PRB42
VDD SE000013780 2.2uF_0402_16V 0.55uF 0.4uF
1
10K_0402_5% PRB43
160K_0402_1%
1
4 PRB44 D 4
2
10K_0402_5% 1 2 2 PQB32
G Close to EC ADP_I pin
VDDP SE000013780 2.2uF_0402_16V 0.55uF 0.4uF
0.047U_0402_25V7K
RUM002N02GT2L_VMT3
2
1
RUM002N02GT2L_VMT3
1
PCB14
PCB36
D S
3
PQB33
PROH 2 0.1U_0402_25V7K
HBM (2000) CBOOT SE00000WA00 0.47uF_0402_25V 0.22uF 0.2uF
2
G
@
2
CDM (1000)
S
3
LA-F611PR01_0531B.DSN
I_SYS change to TSENSE_PSYS(P.72 PUZ01.24) PWR_CHARGER
0.1
A B C D
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
A B C D E
Main Func = 3.3VALWP/5VALWP

@EMI@ PL311
5A_Z120_25M_0805_2P PR302
1 2 499K_0402_1%
ENLDO_3V5V 1 2 +19VB
@ PC307
PR301
@ PJP301 0.1U_0402_10V7K
1
150K_0402_1%
1 2 +19VB_3V BST_3V 1 2 BST_3V_R 1 2
+19VB
1
PR303
JUMP_43X39 PC317
PU301 0_0603_5%
1
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
1000P_0402_25V8J
1000P_0402_50V8J
1
0.1U_0402_25V6
1
1U_0402_25V6K
2
10P_0402_25V8J
SY8386BRHC_QFN16_2P5X2P5
IN3
IN2
IN1
BS
2
LX_3V
1
1
@RF@ PC318
@EMI@ PC301
EMI@ PC302
PC303
PC304
EMI@ PC305
EMI@ PC306
5 17 PL301
LX EP 1.5UH_9A_20%_7X7X3_M
2
@ LX_3V 1 2
LX2
16 +3VALWP
@EMI@ PR305
6
GND
4.7_1206_5%
A
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
15
LX1
1
PC310
PC311
PC312
PC313
@ PC314
@ PC316
7
PG 14
2
GND1
+3VLP
1 SN_3V 2
PR304 8 13 @
EN2 LDO
680P_0603_50V7K
4.7U_0402_6.3V6M
10K_0402_1%
rn
@EMI@ PC309
1 2
TEST
OUT
+3VALWP
EN1
1
ENLDO_3V5V
PC308
FF
9
10
11
12
2
<78,82> POK
tu
3 3VALWP
2
@ESD@ 3
TDC 6 A
2
PD301 PC315 PR306
L03ESDL5V0CG3-2_SOT-523-3-X 1000P_0402_50V8J 1K_0402_5% Peak Current 8.5 A
EN_3V FB_3V1 2 FB_3V_R 1 2
OCP Current 10 A
ck
2 2
1
1
@ PJP302
lo
1 2
+3VALWP 1 2 +3VALW
JUMP_43X118
@EMI@ PL511
ar
5A Z150 20M 1210_2P
1 2
@ PJP502
@ 1 2
@ PJP501
PR501
PC507 +5VALWP 1 2 +5VALW
1 2 +19VB_5V BST_5V 1 2 BST_5V_R
1 2 JUMP_43X79
W
+19VB 1 2
JUMP_43X79 0.1U_0402_10V7K @ PJP503
0_0603_5%
2200P_0402_50V7K
1000P_0402_25V8J
1000P_0402_50V8J
1 2
PU501 1 2
10U_0603_25V6M
10U_0603_25V6M
10P_0402_25V8J
0.1U_0402_25V6
1
SY8288CRAC_QFN20_3X3 JUMP_43X79
1
1
@RF@ PC522
@EMI@ PC501
EMI@ PC502
PC503
PC504
EMI@ PC505
EMI@ PC506
BS
IN
IN
IN
IN
LX_5V 6 20 PL501
2
@ LX LX 1.5UH_9A_20%_7X7X3_M
7
GND 1P LX
19 LX_5V 1 2
+5VALWP
4.7_1206_5%
8 18
GND GND
1
3 3
@EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR505
9 17 1 2
PG VCC
1
PC510
PC511
PC514
PC512
PC519
@ PC513
@ PC520
@ PC521
10 16 PC508
@ NC NC 4.7U_0402_6.3V6M
OUT
LDO
PR502
1 SN_5V 2
2
EN2
EN1
24
0_0402_5% 21
FF
EN_3V 1 2 GND
680P_0402_50V7K
11
12
13
14
15
@ @ PR504
PR503 VL
@EMI@ PC509
10K_0402_1%
EN_5V 1 2 +3VALWP 1 2
ENLDO_3V5V
4.7U_0402_6.3V6M
2
1
4.7U_0402_6.3V6M
-L
0_0402_5%
1
EN_5V
@ PC2506
PC515
POK
PR506
2
2.2K_0402_5%
5VALWP
2
1 2
<58> ALWON
TDC=6 A
@ 2N7002KW_SOT323-3
PR507
PQ501 Peak Current 8 A
OCP current 10 A
LA
1 2 3 1
S
<66> T_CRIT#
4.7U_0402_6.3V6M
0_0402_5%
1
G
2
PC516
PR508 PC517 PR509

1M_0402_5% 1000P_0402_50V8J 1K_0402_5%
FB_5V 1 2 FB_5V_R 1 2
2
<58,78> ALL_SYS_PWRGD
2
HBM (2500)
4 CDM (1500) 4

PWR_3.3VALWP/5VALWP
Size
A B C D E
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
A B C D
Main Func = +1.2V_DDR/+0.6V_DDR_VTT/ +2.5VP

PRM02
2.2_0603_5%
BST_1.2V_R 2 1 BST_1.2V
+19VB_1.2V 0.6Volt +/- 5%
1
@EMI@ PLM11 TDC 1.2A
HCB2012KF-121T50_2P PCM12 +1.2VP Peak Current 1.5A
1 2 0.1U_0402_10V7K
2
1 1
+19VB @ PJPM01
+19VB_1.2V UG_1.2V
1 2
+0.6VSP
JUMP_43X39
10U_0603_25V6M
10U_0603_25V6M
10P_0402_25V8J
1000P_0402_50V7K
1000P_0201_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
22U_0603_6.3V6M
1
1
LX_1.2V
@EMI@ PCM22
EMI@ PCM23
EMI@ PCM01
EMI@ PCM02
PCM03
PCM04
@RF@ PCM24
PCM20
A
16
17
18
19
20
2
2
@ PUM01
2
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PAD
LG_1.2V 15 1
LGATE VTTGND
rn
PRM03
PQM01 9.76K_0402_1% 14 2
PGND VTTSNS
1
PE642DT_PDFN8-10 2 1
D1
D1
D1
G1
CS_1.2V 13 3
PCM13 CS RT8207PGQW _W QFN20_3X3 GND
tu
10 9 2.2U_0402_6.3V6M
D1 D2/S1 2 1 VDDP_1.2V 12 4 VTTREF_1.2V
PRM04 VDDP VTTREF
HBM (750) 5.1_0603_5%
G2
S2
S2
S2
CDM (1000) 1 2 VDD_1.2V 11
VDD VDDQ
5
+1.2VP
1
PGOOD
5
8
2 1 PCM19
TON
+5VALW
ck
2 0.033U_0402_16V7K 2
FB
S5
S3
2
1
1
@ PDM01 PRM05
10
6
PCM14 RB751V-40_SOD323-2 2.2_0603_5%
2.2U_0402_6.3V6M
2
@ PCM17
EN_0.6VSP
EN_1.2V
FB_1.2V
2
TON_1.2V
220P_0402_25V8J
lo
1 2
+5VALW
PLM01
1UH_11A_20%_7X7X3_M <78> 1.2V_VTT_PWRGD PRM10
1 2 6.04K_0402_1%
+1.2VP
ar
@ PRM06 PRM07 1 2
10K_0402_1% +19VB_1.2V 1 2 +1.2VP
1 2
+3VALW 453K_0402_1% +1.2V_DDR
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
@ PRM11
@ PCM18 TDC 5.5 A
W
PRM08 .1U_0402_16V7K Peak Current 7.8 A
1
1
@ PCM05
PCM06
PCM07
PCM08
PCM09
PCM10
@EMI@ PRM01 10K_0402_1%
2
1 2
4.7_1206_5%
<78> +2.5V_PG OCP Current 9.4 A
2
2
1
0_0402_5% @ PCM15
0.1U_0402_10V7K
SN_1.2V
2
@ PRM09
1P
1
1 2
<8> 0.6V_DDR_VTT_ON
@EMI@ PCM11
1
3 680P_0402_50V7K @ PCM16 3
2
0_0402_5% 0.1U_0402_10V7K
@ PJPM02
2
1 2 +5VALW _VDD 1 2
+5VALW +1.2VP 1 2 +1.2V_DDR
24
PR2504 JUMP_43X118
1
2.2_0402_1% PC2504
2.2U_0402_6.3V6M
2
4 5
GND
@ PJP2501 VDD NC @ PJPM03

-L
+3VALW
1 2 +3VALW _2.5V 3
VIN VOUT
6 +2.5VP 1 2
ADJ_2.5V
+0.6VSP +0.6V_DDR_VTT
JUMP_43X39 2 7 JUMP_43X39
22U_0603_6.3V6M
22U_0603_6.3V6M
EN ADJ
1
1
1
1 8
PC2501
PC2502
PGOOD GND PR2502 @ PC2505
LA
21.5K_0402_1% 0.01U_0402_25V7K
2
PU2501
2
RT9059GSP_SO8 @ PJP2502
1 2
+2.5VP +2.5V_MEM +2.5V
PR2501 +2.5V_PG
Vref=0.8V JUMP_43X39 TDC 0.32 A
1
2 1 EN_2.5V
<11,78> SIO_SLP_S4# Peak Current 0.45 A
2
22K_0402_1% PR2505 PR2503

10K_0402_1% 10K_0402_1%
0.1U_0402_10V6K
1
PC2503
4 4
1
2
+3VALW
Title
PWR_+1.2V_MEN/+0.6V/+2.5VP
A B C D
A B C D
Main Func = +1.8VALWP / +1.05VALWP
@ PJP1802
JUMP_43X79
1 2
1
+1.8VALWP 1 2 +1.8V_PRIM 1
@
PR1801
EN_1.8V 1 2
PCH_PRIM_EN <78>
0_0402_5%
1
1
@ PC1805 @ PR1802
+3VALW 0.1U_0402_10V7K 1M_0402_5% +1.8V_PRIM
A
TDC 1.6 A
2
Peak Current 2.3 A
2
2
PR1803
OCP Current 2.8A
100K_0402_5%
rn
@ PL1811
<16,58,95> 1.8V_PRIM_PG
HCB2012KF-121T50_2P PU1801
1 2 9
1 PGND 8
FB SGND
2 7 PL1801
@ PJP1801 PG EN 1UH_6.6A_20%_5X5X3_M
+3VALW 1 2 +3VALW_1.8V 3 6 LX_1.8V 1 2
+1.8VALWP
tu
IN LX
JUMP_43X39 4 5
PGND NC
22U_0603_6.3V6M
1
1
G5719CRC1U TDFN 8P
PC1801
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PR1807 PC1807
@EMI@ PR1804 20K_0402_1% 68P_0402_50V8J
PC1802
PC1803
@ PC1804
2
4.7_1206_5%
2
2
ck
2 2
FB=0.6V FB_1.8V
Note:Iload(max)=3A
1
1
@EMI@ PC1806 PR1805
lo
680P_0402_50V7K 10K_0402_1%
ar
W
3
1P 3
24
-L
LA
4 4

Title
PWR_+1.8VALWP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
A B C D
5 4 3 2 1
D D
A
rn
tu
ck
C C
Reserve
lo
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
Reserve
lo
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
Main Func = VCCIN_AUX
D D
A
EMI@ PLG3
5A Z150 20M 1210_2P
2 1
BST_AUX_R +19VB_AUX +19VB_AUX

PJG2
+19VB
rn
ICCMAX=26A
1
PRG1 1 2
2.2_0603_5% PCG2 PRG2 1 2
0.1U_0402_25V7K 0_0805_5% TDC=10A
2200P_0402_50V7K
2
JUMP_43X118
EMI@ PCG58
EMI@ PCG61
DC LL=TBD
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
1000P_0402_50V7K
2
1
PCG62
PCG59
OCP is Lowside MOSFET Rdson sense
1
HBM (1000~<1999)
@EMI@ PCG63
@EMI@ PCG64
AC LL=TBD
1000P_0402_50V7K
BST_AUX
2
tu
CDM (2000)
0.1U_0402_25V7K
2
1
5
226K x1.2 PQG4
PCG1
255K x1.4 PK616BA_PDFN8-5
2
PUG1
10
RT6543AGQW_WQFN20_3X3 PRG38 0_0603_5%
PRG4 UG_AUX 1 2 UG_AUX_R 4 +VCCIN_AUX
BOOT
187K_0402_1%
1 2 CS_DSI_RT6543 1 20 VSYS_RT6543 Rdc=1.19mohm
CS_DIS VSYS
ck
C C
+5VALW PLG2
3
2
1
0.24UH_22A_+-20%_ 7X7X3_M
PRG6 0_0603_5%
1 2 PVCC_RT6543 15 11 UG_AUX LX_AUX 1 4
PVCC UGATE
2 1 ISENSEP_AUX 2 3 ISENSEN_AUX
PCG5 1U_0402_6.3V6K PQG3
1
PRG7 5.1_0603_5% PK632BA_PDFN8-5 @
@EMI@ PRG32
4.7_1206_5%
lo
1 2 VCC_RT6543 16 12 LX_AUX PRG33
VCC PH
0_0603_5%
2 1
PCG6 1U_0402_6.3V6K PRG8
1 AUX_SNUB
2
2
100K_0402_1% LG_AUX 4
High > 1V +3VALW 1 2 PG_VCCIN_AUX 4
PGOOD LGATE
13 LG_AUX
1ISENSEP_AUX_R
Low <0.4V
ar
<58> PG_VCCIN_AUX
1
@ @
HBM (2000)
@EMI@ PCG57
PRG11
3
2
1
680P_0402_50V7K
PRG37
<16,58,90> 1.8V_PRIM_PG
1 2 EN_RT6543 19
EN PGND
14 CDM (1000) 0_0402_5%
2
1
10.7K_0603_1%
2
0_0402_5% PCG9 @
PRG12
W
0.1U_0402_25V7K
PRG35
2
AUX_VID1 17 2 ISENSEP_RT6543 1 2 ISENSEP_RT6543_R

@ <16> AUX_VID1 VID1 ISENSEP
2
PRG36
@ PRG39 PRG34
2
0_0402_5% @ 0_0402_5% 1 2 1 2
PRG14
ISENSEN_RT6543_R
+3VALW <16> AUX_VID0
AUX_VID0 18 3 ISENSEN_RT6543 1 2 ISENSEN_RT6543_R 1.15K_0402_1% 1.5K_0402_1%
1
VID0 ISENSEN
PCG11 +VCCIN_AUX PHG2
1 2 0_0402_5%
@ PRG16 @ ISENSEN_AUX_NTC 1 2
PRG17 PRG18
100K_0402_1% 0.1U_0402_25V7K
+5VALW 1 2 FSWSEL_RT6543 9
FSWSEL
1P VOUT
8 VOUT_RT6543 1 2 2 1 10K_0402_1%_B25/50 3370K
ISENSEP_RT6543_R
1
0_0402_5% 100_0402_1% B=3435(B25/85)

@ PRG21 PCG12
B 100K_0402_1% B
2000P_0402_50V7K PRG23 10K_0402_1% @ PCG13 390P_0402_50V7K @ PRG24 1.6K_0402_1%
1
5 COMP_RT6543 1 2 1 2 1 2 1 2 1 2
COMP
2
PRG25 PRG22 PCG60

10K_0402_1% 10K_0402_1% PCG14 0.1U_0402_25V7K
27P_0402_50V8J PRG26 6.2K_0402_5%
24
2
AUX_VID0 FB_RT6543
6 1 2 1 2
AUX_VID1
5V: 800KHz FB
1
Float: 600KHz PRG27
GND: 400KHz 0_0402_5%
1
7 RGND_RT6543 1 2
RGND VSS_SENSE_AUX <16>
AGND
@ PRG28
2
@ PRG29 PRG30 0_0402_5%
10K_0402_1% 10K_0402_1%
1
-L
VCC_SENSE_AUX <16>
PRG31
2
21
1
100_0402_1%
PCG16
@ PCG17 0.1U_0402_25V7K
2
2
1 2
0.082U_0402_16V7K
330P_0402_50V7K
@ PCG18
1
LA
2
VCCIN_AUX VID Follow Intel PDG Rev0.71 @PCG29
1 2
VID1 VID0 +VCCIN_AUX 0.01UF_0402_25V7K

Voltage
0 0 0
0 1 1.1
1 0 1.65
A A
1 1 1.8

PWR VCCIN_AUX
Date: Wednesday, April 14, 2021 Sheet 95 of 121
5 4 3 2 1
4
3
2
1
PCZ107
330U_D2_2.5VY_R9M
2
1
+
PCZ97
330U_D2_2.5VY_R9M
2
1
+
+VCCIN
+VCCIN
A
A
2 1 2 1
@
PCZ77
PCZ89 @ PCZ100 330U_D3_2.5VY_R6M
22U_0603_6.3V6M 22U_0603_6.3V6M 2
1
+
2 1 2 1
PCZ101 PCZ98
22U_0603_6.3V6M 22U_0603_6.3V6M
+VCCIN
2 1 2 1
2 1
PCZ88 PCZ81
@
PCZ76 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ85 PCZ79
@
PCZ92 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
330U_R9
@ PCZ96 PCZ102
@
PCZ75 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ99 PCZ90
*2
@
PCZ91 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603 *14
1U_0201_6.3V6M 2 1 2 1
Primary side :
2 1
Main Func = VCCIN/ VCCIN_AUX
PCZ93 @ PCZ80
@
PCZ94 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
@ PCZ95 @ PCZ84
@
PCZ78 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
@ PCZ83 PCZ87
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PCZ82 PCZ86
B
B
22U_0603_6.3V6M 22U_0603_6.3V6M
LA
-L
24
2
1
+
2 1 2 1 PCG45
1P
330U_D2_2.5VY_R9M
+VCCIN_AUX
+VCCIN_AUX
PCG81 PCG20
C
C
2
1
+
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 PCG46
330U_D2_2.5VY_R9M
PCG83 PCG25
22U_0603_6.3V6M 22U_0603_6.3V6M
W 2 1 2 1 2 1
+VCCIN_AUX
PCG72 PCG76 PCG51

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Issued Date
2 1 2 1 2 1
PCG73 PCG75 PCG50
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
@
PCG84 PCG21 PCG56

47U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
ar
PCG66 PCG22 PCG67
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
330U_R9
2 1 2 1 2 1
22U_0603
2019/05/10
PCG74
lo PCG23 PCG70
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
*1
*26
PCG65 PCG26 PCG68

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PCG24 PCG27 PCG69

ck
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
@
PCG71 PCG28 PCG19

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Compal Secret Data
D
D
Deciphered Date
tu
2024/05/10 rn
A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Date:
Title
Document Number
Tuesday, April 13, 2021

E
E
Sheet
96
PWR_VCCIN/ VCCIN_AUX
of
121
Rev
0.1
4
3
2
1
5 4 3 2 1
Baseline Baseline
UP3_4+2 15W (U42) UP3_4+2 28W (U42)
Frequency 750KHz ICCMAX=47A ICCMAX=55A
D
TDC=30A TDC=36A D
EMI@ PLZ11
5A Z150 20M 1210_2P
1 2
+19VB_VCCIN
@
<98> UG_VCCIN1 PJZ01 +19VB
1 2
1 2
HBM (1000~<1999)
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
100U_D3L_25VM_R50M
100U_D3L_25VM_R50M
JUMP_43X118
A
EMI@ PCZ22
EMI@ PCZ25
PCZ26
PCZ27
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_25V6
1 1
CDM (2000)
1
+ +
@EMI@ PCZ28
@EMI@ PCZ29
PCZ23
PCZ24
PQZ1
PRZ29 PK616BA_PDFN8-5
2
0_0603_5% 2 2@
1 2 BST_VCCIN1_R
<98> BST_VCCIN1 4
1 PCZ30
rn
0.22U_0402_25V6K
+VCCIN
2
3
2
1
Rdc=0.9mohm PLZ01
1 4
<98> LX_VCCIN1
2 3
@EMI@ PRZ31
4.7_1206_5%
5
1
ISUMP 1 2
HBM (2000)
tu
<98> ISUMP 0.15UH_NA__35A_20%
1
CDM (1000) PRZ34
3.65K_0603_1%
PRZ32
1 SNUB_VCCIN1 2
4 100K_0402_1%
<98> LG_VCCIN1
2
PK632BA_PDFN8-5 ISEN1
PQZ2 <98> ISEN1
3
2
1
V2N 1 2
C C
ck
PRZ35
@EMI@ PCZ31
100K_0402_1%
680P_0402_50V7K
2
ISUMN 1 2 V1N
<98> ISUMN
PRZ33
10_0402_1%
lo
ar
W
+19VB_VCCIN
<98> UG_VCCIN2
HBM (1000~<1999)
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
CDM (2000)
EMI@ PCZ32
EMI@ PCZ33
PCZ34
PCZ35
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_25V6
5
1
@EMI@ PCZ36
@EMI@ PCZ37
PRZ37
PQZ3
PK616BA_PDFN8-5
1P
2
2
0_0603_5%
B 1 2 BST_VCCIN2_R B
<98> BST_VCCIN2 4
1
PCZ38
0.22U_0402_25V6K
2
3
2
1
+VCCIN
Rdc=0.9mohm PLZ02
24
1 4
<98> LX_VCCIN2
2 3
4.7_1206_5%
@EMI@ PRZ38
5
ISUMP 1 2
0.15UH_NA__35A_20%
1
PRZ41
3.65K_0603_1% PRZ39
100K_0402_1%
1SNUB_VCCIN2 2
4
<98> LG_VCCIN2
-L
2
PK632BA_PDFN8-5 ISEN2
PQZ4 <98> ISEN2
HBM (2000)
3
2
1
CDM (1000) V1N 1 2

@EMI@ PCZ39
PRZ42
680P_0402_50V7K
100K_0402_1%
2
LA
ISUMN 1 2 V2N
PRZ40
10_0402_1%
A A

PWR_VCCIN
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCST
0.1U_0402_25V7K
1
1
45.3_0402_1%
75_0402_1%
100_0402_1%
PCZ01
PRZ04
PRZ02
PRZ03
2
@ PRZ01
2
D 0_0603_5% D
1 2 VR_SCLK VDD_VCCIN 1 2
<14> VR_SVID_CLK
PRZ06 0_0402_5% +5VALW
<14> VR_SVID_ALERT# @ 1 2 VR_ALERT# PRZ05
PRZ07 0_0402_5% 0_0603_5%
0.22U_0402_25V6K
@ 1 2 VR_SDA VIN_VCCIN 1 2
<14> VR_SVID_DATA +19VB_VCCIN
1U_0402_25V6K
PRZ08 0_0402_5%
<7,16,58,82,85> H_PROCHOT# PRZ09 @
1
100_0402_1%
PCZ02
PCZ03
1 2 1 2
A
2
2
@ PCZ04 47P_0402_50V8J 1.91K_0402_1% PRZ11
1 2
+3VS
<11> VR_READY
PRZ13
@
<78> IMVP_VR_ON_EN 1 2
rn
@ PRZ14 PRZ15 0_0402_5%
PRZ48
82K_0402_1% 7.5K_0402_1% PUZ01
1 2 1 2 1 2 ISL95869HRTZ-T_TQFN32_4X4 PRZ10
PCZ05 PCZ06 78.7K_0402_1%
32
31
30
29
28
27
26
25
330P_0402_50V8J 4700P_0402_25V7K PROG1_VCCIN 1 2
0_0402_5% 1 2 1 2
VR_ENABLE
VR_READY
SCK
SDA
VDD
VIN
VR_HOT#
ALERT#
tu
PROG2_VCCIN 1 2
@
PRZ17
0_0402_5% PRZ12
PHZ01 near PQZ01 MOS Side PRZ18 <85> I_SYS 1 2 1 24 9.31K_0402_1%
220K_0402_5%_B25/50 4700K PHZ01 12K_0402_1% 2 PSYS PROG1 23
1 2 1 2 3 IMON PROG2 22
NTC BOOT1 BST_VCCIN1 <97>
4 21 UG_VCCIN1 <97>
1 2 5 COMP UGATE1 20
FB PHASE1 LX_VCCIN1 <97>
@ PRZ19 6 19 PRZ16
ck
C RTN LGATE1 LG_VCCIN1 <97> C
27.4K_0402_1% 7 18 0_0603_5%
8 ISUMN PWM3 17 VDDP_VCCIN 1 2
PCZ07
PRZ20
ISUMP VDDP +5VALW
UGATE2
1U_0402_25V6K
PHASE2
8200P_0402_25V7K
LGATE2
1K_0402_5%
BOOT2
1
ISEN1
ISEN2
ISEN3
FCCM
1 2 1 2 33 GND_PAD
PCZ08
PCZ09
2
68P_0402_50V8J
lo
9
10
11
12
13
14
15
16
1 2
PCZ10 PRZ21
PRZ46 100_0402_5% 270P_0402_50V7K 2K_0402_1% LG_VCCIN2 <97>
+VCCIN 1 2 1 2 2 1 LX_VCCIN2 <97>
UG_VCCIN2 <97>
<14> VCC_SENSE_VCCIN BST_VCCIN2 <97>
ar
@ PCZ12 PRZ22
PRZ43 PRZ45
PCZ11 820PF_0402_50V7K 499_0402_1% @ 0_0402_5%
1 2 1 2 1 2 1 2 1 2
+5VALW
0.082U_0402_16V7K
@ ISEN2 <97>
PRZ49
330P_0402_50V7K ISEN1 <97> @ PRZ24
0_0402_5%
1
PCZ13
1 2 1 2 20M_0402_5%
W
1 2
PCZ15 0.022U_0402_25V7K
PCZ16 0.022U_0402_25V7K
@ PRZ23
PRZ44
2
PCZ14 @ 0_0402_5% 2.61K_0402_1%

1 2 1 2 ISUMP <97>
1
4.3K_0402_1%
0.01U_0402_25V7K
0.015U_0402_25V7K
0.1U_0402_25V7K
330P_0402_50V7K
0_0402_5%
<14> VSS_SENSE_VCCIN
PRZ25
11K_0402_1%
PRZ47 100_0402_5%
1
1 2
2
1
1
1P
PCZ40
PCZ18
PCZ19
PRZ26
PRZ27
PHZ02 near PLZ01 Choke Side
1
475_0402_1%
2
1 2 PHZ02
Local sense put on HW site
2
B 10K_0402_5%_B25/50 4250K B
PCZ20 PRZ28
2200P_0402_50V7K 3.48K_0402_1%
2
1 2 1 2 ISUMN <97>
24
1 2
PCZ21
0.01U_0402_16V7K
-L
LA
A A
2014/11/05 2014/12/15 Title
Issued Date Deciphered Date PWR_VCCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00(0.1)
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
@ PC902
0.01UF_0402_25V7K
1 2
D +3VLP D
AZV3002
@ PR902 Icc=12uA_max
A
200K_0402_1%
1 2 Vout=3.15V@Vcc=3.3V and Io=3mA
Vth 1.80V-1.86V-1.93V @ PR903 @ PR901
300K_0402_1% 0_0402_5%
1 2 @ PU900 1 2
rn
ACIN_CHG <85>
AZV3002RL-7_U-FLGA8_1P65X1P65
8
@ PC901 @ PD901
82P_0201_50V8J RB520SM-30T2R_EMD2-2-X
VCC
3
1 2
tu
@ PQ900B
2
+VCCIN @ PR904 IN-1 - 1 NO_SMOKE_OVP 5
OUT1
1U_0201_6.3V6M 1U_0201_6.3V6M
1U_0201_6.3V6M 1U_0201_6.3V6M
200K_0402_1% 3
C IN+1 + C
1
@ PC908
@ PC909
1 2
4
@ PR905 6
-
2
IN-2
6
100K_0402_1% 7
ck
1 2 5 OUT2
IN+2 +
@ PQ900A
@PR906 @ PC903 NO_SMOKE_UVP 2
VEE
0_0402_5% 82P_0201_50V8J
1
@ PC910
@ PC911
1 2 1 2
1
lo
4
+19VB
2
3 @ PR907
2
237K_0402_1%
1 1 2
ar
@ PD902
+3VLP 2 @ PR908 RB520SM-30T2R_EMD2-2-X
43.2K_0402_1%
1
@ PD900 1 2 RB520SM
BAT54CW_SOT323-3
Vf =0.29V@1mA
W
@ PC904
82P_0201_50V8J @ PR909 Ir =1uA @Vr=10V
1 2 14.7K_0402_1%
B 1 2 B
HW_ACAV_IN <11,58,63,82,85>
Vth 4.9V-5V-5.1V @ PR911 3.3V+-2%

4.32K_0402_1%
1P 1
@ PC905
1 2
2
0.22U_0402_10V6K
24
-L
LA
A A

NO SMOKE
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
A
rn
tu
ck
C C
lo
Reserve
ar
W
B
1P B
24
-L
LA
A A

Reserve for PWR
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request Issue Solution
Item Page# Title Date Owner Description Description Rev.
D D
0.2(X01)
1 P83 BATT 20190423 COMPAL RF request for RF test
CONN Reserve PC16
A
2 P84 PWR 20190423 COMPAL 0.2(X01)
"Based on Loki G issue, change to follow
rn
CHARGER 1. PCB07 change to 0603
Renesas recommendation
" 2. Remove PCB71
3. PRB15 change to 1206
tu
3 P96 NO 20190423 COMPAL 0.2(X01)
ck
C C
SMOKE customer request

Add page 96: reserve NO SMOKE schematic
lo
4 P88 PWR 20190507 COMPAL 0.2(X01)
ar
VCCIN Change RC value for Intel EA test "Change RC value for Intel test:
PCZ77=330UF
PCZ79/80/81/82/84/85/86/87/90/96/98/99/100/102=22uF
W
VCCAUX 
Output caps 1+9
PCG46=330UF

PCG19/24/28/50/51/65/71/75/76=22uF
B
1P PRZ14/25=2.21Kohm
PRZ13/24=2.05kohm
PRZ17/26=3.01Kohm
PRZ48=37.4Kohm
B
PRZ66=200ohm
24
PRZ49=12.1Kohm
PRZ53=14.7kohm
PCZ10=82pF
PCZ11=220pF
-L
"
LA
A A

Changed-List PWR History
Size
5 4 3 2 1

La-L241pr10 Warlock TGL Uma 041

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La-L241pr10 Warlock TGL Uma 041

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La-L241pr10 Warlock TGL Uma 041

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A B C D E

FFS@ : Free Fall Sensor

LBIST@/LBIST@RF@ : LBIST for LCD monitor

BGA 1526 balls

RJ45 Transformer LAN 1000 PCIe x 1

M.2 SSD (NVMe) PCIe x 4

USB2.0 x 1 Finger print

Reserve P67 Precision

HDA CODEC HDA

Charger Daughter board

Keyboard PWM FAN Thermal sensor

S0 (Full ON) / M0 HIGH HIGH HIGH ON ON ON ON

S5 (SOFT OFF) / M3 LOW LOW LOW ON OFF OFF OFF

+1.0V_PRIM System +1.0V always on power rail ON ON ON* OFF

FUSE 1.5A_24V FUSE 1A_65V

PJP501 ALWON -->EN_5V PJP502

VBUS_P_CTRL# FUSE 0.5A_13.2V

use Fuse Pop - U4

Security Classification Compal Secret Data Compal Electronics, Inc.

RTC battery or CHR Output +RTC_CELL

PCH Input RTCRST#/SRTCRST#

PCH Input +3VALW_PCH(PRIM)

PCH Input VR Output +1.8V_PRIM tPCH06

PCH Output +VCC1.05_OUT_FET

PCH Input VR Output +VCCIN_AUX

VR Output PG_VCCIN_AUX (PRIM_PWRGD)

PCH Input EC Output PCH_RSMRST# tPCH07

PCH Output ESPI_RESET#

PCH Output SIO_SLP_S5#

PCH Output SIO_SLP_S3#

PCH Output SIO_SLP_S0#

PCH Output CPU_C10_GATE#

EC Input ALL_SYS_PWRGD (RUNPWROK) tCPU01 (DDR_VTT)

A CPU Output CPUPWRGD A

Security Classification Compal Secret Data Compal Electronics, Inc.

TBT_0_LSX_RX TBT_1_LSX_RX TBT_2_LSX_RX TBT_3_LSX_RX

HIGH 3.3V HIGH 3.3V HIGH 3.3V HIGH 3.3V

LOW 1.8V LOW 1.8V LOW 1.8V LOW 1.8V

PLACE CLOSE TO THE SIGNAL TO AVOID STUB

Security Classification Compal Secret Data Compal Electronics, Inc.

+3VALW_PCH +3VALW_PCH +3VALW_PCH +3VALW_PCH +3VALW_PCH +3VALW_PCH

ESD Requesr:CC944 place near to RC37

RC4182 1 @ 2 1K_0201_5% CFG13 RC49 2 1 49.9_0402_1% CFG_RCOMP B5 RSVD_TP_14

BM12 RSVD_8 TP_4 W34

+VCCIO_OUT +VCCIO_OUT +VCCIO_OUT

RC4148 1 @ 2 1K_0201_5% RC4153 1 @ 2 1K_0201_5% RC4152 1 @ 2 1K_0201_5%

A RC4144 1 2 1K_0201_5% CFG4 RC4149 1 @ 2 1K_0201_5% CFG7 RC4151 1 @ 2 1K_0201_5% CFG14 A

eDP enable strap PEG Training PEG60 Lane Reversal

LP4-LP5(NIL)/DDR4 (NIL)/DDR4 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)

DDR0_VREF_CA +V_DDR_REFA_R DDR1_VREF_CA +V_DDR_REFB_R

Buffer with Open Drain Output For +1.2V_DDR +3VS 1 DV24

470_0201_5% DP_COMP A48

A NC VCC 100K_0201_5% 80.6_0201_1% 121_0201_1% @ TGL-U_BGA1449 A

Security Classification Compal Secret Data Compal Electronics, Inc.

GPP_E6 RC97 1 @ 2 100K_0201_5%

RC98 1 2 100K_0201_5% +3VS

R2 R2 should place near P.58 UE1 (EC side)

TOP SWAP OVERRIDE NO REBOOT

SPKR RC115 1 @ 2 8.2K_0201_5% NRB_BIT RC1141 @ 2 4.7K_0201_5%

+2.5V_MEM 10uF 1 +0.6V_DDR_VTT 10uF 1+1uF *2 +0.6V_DDRB_VREFCA