21 - EEE - EDC Notes

ELECTRONIC DEVICES AND CIRCUITS (15A04301)
CONTENTS
1 Unit-I : 1-37
1.1 Introduction 1
1.2 Unit-I notes 8
1.3 Solved Problems 29
1.4 Part A Questions 31
1.5 Part B Questions 36
2 Unit-II : (Topic) 38-63
2.1 Introduction 38
2.2 Unit-II notes 39
3 Unit-III : (Topic) 64-91
3.1 Introduction 64
3.2 Unit-III notes 65
4 Unit-IV : (Topic) 92-119
4.1 Introduction 92
4.2 Unit-IV notes 93
5 Unit-V : (Topic) 120-140
5.1 Introduction 120
5.2 Unit-V notes 121
6 Appendix :Important Formula (For all units )
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

II B.Tech I-Sem (E.E.E) T Tu C
3 1 3
(15A04301) ELECTRONIC DEVICES AND CIRCUITS
Course Objectives:
To give understanding on semiconductor physics of the intrinsic, p and n materials,
characteristics of the p-n junction diode, diode’s application in electronic circuits,
Characteristics of BJT,FET,MOSFET, characteristics of special purpose electronic devices.
To familiarize students with dc biasing circuits of BJT, FET and analyzing basic transistor
amplifier circuits.
Course Outcomes:
Upon completion of the course, students will:
 Analyze the operating principles of major electronic devices, its characteristics and
applications.
 Design and analyze the DC bias circuitry of BJT and FET.
 Design and analyze basic transistor amplifier circuits using BJT and FET.
UNIT- I:- Junction Diode Characteristics : Open circuited p-n junction, Biased p-n
junction, p-n junction diode, current components in PN junction Diode, diode equation, V-I
Characteristics, temperature dependence on V-I characteristics, Diode resistance, Diode
capacitance, energy band diagram of PN junction Diode. Special Semiconductor Diodes:
Zener Diode, Breakdown mechanisms, Zener diode applications, LED, LCD, Photo diode,
Varactor diode, Tunnel Diode, DIAC, TRIAC, SCR, UJT. Construction, operation and
characteristics of all the diodes is required to be considered.
UNIT- II:- Rectifiers and Filters: Basic Rectifier setup, half wave rectifier, full wave
rectifier, bridge rectifier, derivations of characteristics of rectifiers, rectifier circuits-
operation, input and output waveforms,Filters, Inductor filter, Capacitor filter, L- section
filter, - section filter, Multiple L- section and Multiple  section filter ,comparison of
various filter circuits in terms of ripple factors.
UNIT- III:- Transistor Characteristics: BJT: Junction transistor, transistor current

components, transistor equation, transistor configurations, transistor as an amplifier,
characteristics of transistor in Common Base, Common Emitter and Common Collector
configurations, Ebers-Moll model of a transistor, punch through/ reach through, Photo
transistor, typical transistor junction voltage values.
FET: FET types, construction, operation, characteristics, parameters, MOSFET-types,
construction, operation, characteristics, comparison between JFET and MOSFET.
UNIT- IV:-Transistor Biasing and Thermal Stabilization : Need for biasing, operating
point, load line analysis, BJT biasing- methods, basic stability, fixed bias, collector to base
bias, self bias, Stabilization against variations in VBE, Ic, and β, Stability factors, (S, S ', S'’),
Bias compensation, Thermal runaway, Thermal stability. FET Biasing- methods and
stabilization.
UNIT- V:- Small Signal Low Frequency Transistor Amplifier Models: BJT: Two port
network, Transistor hybrid model, determination of h-parameters, conversion of h-
parameters, generalized analysis of transistor amplifier model using h-parameters, Analysis
of CB, CE and CC amplifiers using exact and approximate analysis, Comparison of transistor
amplifiers. FET: Generalized analysis of small signal model, Analysis of CG, CS and CD
amplifiers, comparison of FET amplifiers.
TEXT BOOKS:
1. J. Millman, C. Halkias, “Electronic Devices and Circuits”, Tata Mc-Graw Hill, 4th Edition,2010.
2. David A.Bell, “Electronic Devices and Circuits”, Fifth Edition, Oxford University Press, 2009.
3. Salivahanan, Kumar, Vallavaraj, “Electronic Devices and Circuits”, Tata Mc-Graw Hill,
Second Edition
REFERENCES:
1. Jacob Millman, C. Halkies, C.D.Parikh, “Integrated Electronics”, Tata Mc-Graw Hill, 2009.
2. R.L. Boylestad and Louis Nashelsky, “Electronic Devices and Circuits”, Pearson Publications,
9th Edition, 2006.
3. BV Rao, KBR Murty, K Raja Rajeswari, PCR Pantulu, “Electronic Devices and Circuits”,
Pearson, 2nd edition.
UNIT- I: - JUNCTION DIODE CHARACTERISTICS

1.0 INTRODUCTON
Based on the electrical conductivity all the materials in nature are classified as
insulators, semiconductors, and conductors.
Insulator: An insulator is a material that offers a very low level (or negligible) of
conductivity when voltage is applied. Eg: Paper, Mica, glass, quartz. Typical resistivity level
of an insulator is of the order of 1010 to 1012 Ω-cm. The energy band structure of an insulator
is shown in the fig.1.1. Band structure of a material defines the band of energy levels that an
electron can occupy. Valance band is the range of electron energy where the electron remain
bended too the atom and do not contribute to the electric current. Conduction bend is the
range of electron energies higher than valance band where electrons are free to accelerate
under the influence of external voltage source resulting in the flow of charge.
The energy band between the valance band and conduction band is called as
forbidden band gap. It is the energy required by an electron to move from balance band to
conduction band i.e. the energy required for a valance electron to become a free electron.
1 eV = 1.6 x 10-19 J
For an insulator, as shown in the fig.1.1 there is a large forbidden band gap of greater
than 5Ev. Because of this large gap there a very few electrons in the CB and hence the
conductivity of insulator is poor. Even an increase in temperature or applied electric field is
insufficient to transfer electrons from VB to CB.
Conductors: A conductor is a material which supports a generous flow of charge

when a voltage is applied across its terminals i.e. it has very high conductivity. E.g.: Copper,
Aluminium, Silver, and Gold. The resistivity of a conductor is in the order of 10 -4 and 10-6 Ω-
cm. The Valance and conduction bands overlap (fig1.1) and there is no energy gap for the
electrons to move from valance band to conduction band. This implies that there are free
electrons in CB even at absolute zero temperature (0K).
C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 1

Therefore at room temperature when electric field is applied large current flows through the
conductor.
Semiconductor: A semiconductor is a material that has its conductivity somewhere
between the insulator and conductor. The resistivity level is in the range of 10 and 104 Ω-cm.
Two of the most commonly used are Silicon (Si=14 atomic no.) and germanium (Ge=32
atomic no.). Both have 4 valance electrons. The forbidden band gap is in the order of 1eV.
For e.g., the band gap energy for Si, Ge and GaAs is 1.21, 0.785 and 1.42 eV, respectively at
absolute zero temperature (0K). At 0K and at low temperatures, the valance band electrons do
not have sufficient energy to move from V to CB. Thus semiconductors act as insulators at
0K, as the temperature increases, a large number of valance electrons acquire sufficient
energy to leave the VB, cross the forbidden band gap and reach CB. These are now free
electrons as they can move freely under the influence of electric field. At room temperature
there are sufficient electrons in the CB and hence the semiconductor is capable of conducting
some current at room temperature. Inversely related to the conductivity of a material is its
resistance to the flow of charge or current. Typical resistivity values for various materials‘ are
given as follows.
1.0.1 Semiconductor Types
A pure form of semiconductors is called as intrinsic semiconductor. Conduction in

intrinsic sc is either due to thermal excitation or crystal defects. Si and Ge are the two most
important semiconductors used. Other examples include Gallium arsenide GaAs, Indium
Antimonide (InSb) etc.
Let us consider the structure of Si. A Si atomic no. is 14 and it has 4 valance
electrons. These 4 electrons are shared by four neighbouring atoms in the crystal structure by
means of covalent bond. Fig. 1.2a shows the crystal structure of Si at absolute zero
temperature (0K). Hence a pure SC acts has poor conductivity (due to lack of free electrons)
at low or absolute zero temperature.
At room temperature some of the covalent bonds break up to thermal energy as shown
in fig 1.2b. The valance electrons that jump into conduction band are called as free electrons
that are available for conduction.

The absence of electrons in covalent bond is represented by a small circle usually

referred to as hole which is of positive charge. Even a hole serves as carrier of electricity in a
manner similar to that of free electron.
The mechanism by which a hole contributes to conductivity is explained as follows:
When a bond is in complete so that a hole exists, it is relatively easy for a valance
electron in the neighbouring atom to leave its covalent bond to fill this hole. An electron
moving from a bond to fill a hole moves in a direction opposite to that of the electron. This
hole, in its new position may now be filled by an electron from another covalent bond and the
hole will correspondingly move one more step in the direction opposite to the motion of
electron. Here we have a mechanism for conduction of electricity which does not involve free
electrons. This phenomenon is illustrated in fig1.3

Fig 1.3a show that there is a hole at ion 6.Imagine that an electron from ion 5 moves
into the hole at ion 6 so that the configuration of 1.3b results. If we compare both fig1.3a
&fig 1.3b, it appears as if the hole has moved towards the left from ion6 to ion 5. Further if
we compare fig 1.3b and fig 1.3c, the hole moves from ion5 to ion 4. This discussion
indicates the motion of hole is in a direction opposite to that of motion of electron. Hence we
consider holes as physical entities whose movement constitutes flow of current.
In a pure semiconductor, the number of holes is equal to the number of free electrons.
1.0.2 EXTRINSIC SEMICONDUCTOR

Intrinsic semiconductor has very limited applications as they conduct very small
amounts of current at room temperature. The current conduction capability of intrinsic
semiconductor can be increased significantly by adding a small amounts impurity to the
intrinsic semiconductor. By adding impurities it becomes impure or extrinsic semiconductor.
This process of adding impurities is called as doping. The amount of impurity added is 1 part
in 106 atoms.
N type semiconductor: If the added impurity is a pentavalent atom then the resultant
semiconductor is called N-type semiconductor. Examples of pentavalent impurities are
Phosphorus, Arsenic, Bismuth, Antimony etc.
A pentavalent impurity has five valance electrons. Fig 1.4a shows the crystal structure
of N-type semiconductor material where four out of five valance electrons of the impurity

atom(antimony) forms covalent bond with the four intrinsic semiconductor atoms. The fifth
electron is loosely bound to the impurity atom. This loosely bound electron can be easily
Excited from the valance band to the conduction band by the application of electric
field or increasing the thermal energy. The energy required to detach the fifth electron form
the impurity atom is very small of the order of 0.01ev for Ge and 0.05 eV for Si.
The effect of doping creates a discrete energy level called donor energy level in the
forbidden band gap with energy level Ed slightly less than the conduction band (fig 1.4b).
The difference between the energy levels of the conducting band and the donor energy level
is the energy required to free the fifth valance electron (0.01 eV for Ge and 0.05 eV for Si).
At room temperature almost all the fifth electrons from the donor impurity atom are raised to
conduction band and hence the number of electrons in the conduction band increases
significantly. Thus every antimony atom contributes to one conduction electron without
creating a hole.
In the N-type sc the no. of electrons increases and the no. of holes decreases
compared to those available in an intrinsic sc. The reason for decrease in the no. of holes is
that the larger no. of electrons present increases the recombination of electrons with holes.
Thus current in N type sc is dominated by electrons which are referred to as majority carriers.
Holes are the minority carriers in N type sc
P type semiconductor: If the added impurity is a trivalent atom then the resultant
semiconductor is called P-type semiconductor. Examples of trivalent impurities are Boron,
Gallium, indium etc. The crystal structure of p type sc is shown in the fig1.5a. The three
valance electrons of the impurity (boon) forms three covalent bonds with the neighbouring
atoms and a vacancy exists in the fourth bond giving rise to the holes. The hole is ready to
accept an electron from the neighbouring atoms. Each trivalent atom contributes to one hole
generation and thus introduces a large no. of holes in the valance band. At the same time the
no. electrons are decreased compared to those available in intrinsic sc because of increased
recombination due to creation of additional holes.
Thus in P type sc, holes are majority carriers and electrons are minority carriers. Since
each trivalent impurity atoms are capable accepting an electron, these are called as acceptor
atoms. The following fig 1.5b shows the pictorial representation of P type sc

• The conductivity of N type sc is greater than that of P type sc as the mobility of

electron is greater than that of hole.
• For the same level of doping in N type sc and P type sc, the conductivity of an N type
sc is around twice that of a P type sc
1.0.3 CONDUCTIVITY OF SEMICONDUCTOR

In a pure sc, the no. of holes is equal to the no. of electrons. Thermal agitation
continue to produce new electron- hole pairs and the electron hole pairs disappear because of
recombination. With each electron hole pair created, two charge carrying particles are
formed. One negative which is a free electron with mobility μn. The other is a positive i.e.,
hole with mobility μp. The electrons and hole move in opposite direction in an electric field
E, but since they are of opposite sign, the current due to each is in the same direction. Hence
the total current density J within the intrinsic sc is given by
J = Jn + Jp
=q n μn E + q p μp E
= (n μn + p μp) qE
=σ E

Where n=no. of electrons / unit volume i.e., concentration of free electrons

P= no. of holes / unit volume i.e., concentration of holes
E=applied electric field strength, V/m
q= charge of electron or hole I n Coulombs
Hence, σ is the conductivity of sc which is equal to (n μn + p μp) q. The resistivity of
sc is reciprocal of conductivity.
ρ= 1/ σ
It is evident from the above equation that current density with in a sc is directly
proportional to applied electric field E.
For pure sc, n=p= ni where ni = intrinsic concentration. The value of ni is given by
Therefore, J= ni (μn + μp) q E

Hence conductivity in intrinsic sc is σi= ni (μn + μp) q
Intrinsic conductivity increases at the rate of 5% per o C for Ge and 7% per o C for Si.
Conductivity in extrinsic sc (N Type and P Type):
The conductivity of intrinsic sc is given by σi= ni (μn + μp) q = (n μn + p μp) q
For N type, n>>p; Therefore σ= q n μn
For P type, p>>n; Therefore σ= q p μp
1.0.4 CHARGE DENSITIES IN P TYPE AND N TYPE SEMICONDUCTOR:

Mass Action Law:
Under thermal equilibrium for any semiconductor, the product of the no. of holes and
the concentration of electrons is constant and is independent of amount of donor and acceptor
impurity doping.
n.p= ni2
Where n= electron concentration
p = hole concentration
ni2= intrinsic concentration
Hence in N-type sc, as the no. of electrons increases the no. of holes decreases.
Similarly in P-type as the no. of holes increases the no. of electrons decreases. Thus the
product is constant and is equal to ni2 in case of intrinsic as well as extrinsic sc.
The law of mass action has given the relationship between free electrons
concentration and hole concentration. These concentrations are further related by the law of
electrical neutrality as explained below.
Law of electrical neutrality:
Sc materials are electrically neutral. According to the law of electrical neutrality, in an
electrically neutral material, the magnitude of positive charge concentration is equal to that of
negative charge concentration. Let us consider a sc that has ND donor atoms per cubic
centimetre and NA acceptor atoms per cubic centimetre i.e., the concentration of donor and
acceptor atoms are ND and NA respectively. Therefore ND positively charged ions per cubic
centimetre are contributed by donor atoms and NA negatively charged ions per cubic
centimetre are contributed by the acceptor atoms. Let n, p is concentration of free electrons
and holes respectively. Then according to the law of neutrality
ND + p =NA + n eq. 1.1
For N type sc, NA =0 and n>>p. Therefore ND ≈ n eq. 1.2
Hence for N type sc the free electron concentration is approximately equal to the
concentration of donor atoms. In later applications since some confusion may arise as to
which type of sc is under consideration a given moment, the subscript n or p is added for N-
type or P-type respectively.

Hence eq1.2 becomes ND ≈ nn

Therefore current density in N type sc is J = ND μn q E and conductivity σ= ND μn q
For P type sc, ND = 0 and p>>n. Therefore NA ≈ p or NA ≈ pp
Hence for P type sc the hole concentration is approximately equal to the concentration
of acceptor atoms.
Therefore current density in N type sc is J = NA μp q E and conductivity σ= NA μp q
Mass action law for N type, nn pn= ni 2
pn= ni2/ ND since (nn≈ ND)
Mass action law for P type, np pp= ni 2
np= ni2/ NA since (pp≈ NA)
1.1 QUANTITATIVE THEORY OF PN JUNCTION DIODE

1.1.1 PN JUNCTION WITH NO APPLIED VOLTAGE OR OPEN CIRCUIT
CONDITION:
In a piece of sc, if one half is doped by P-type impurity and the other half is doped by
N-type impurity, a PN junction is formed. The plane dividing the two halves or zones is
called PN junction. As shown in the fig the N-type material has high concentration of free
electrons, while P-type material has high concentration of holes. Therefore at the junction
there is a tendency of free electrons to diffuse over to the P side and the holes to the N side.
This process is called diffusion. As the free electrons move across the junction from N-type
to P-type, the donor atoms become positively charged. Hence a positive charge is built on the
N-side of the junction. The free electrons that cross the junction uncover the negative
acceptor ions by filing the holes. Therefore a negative charge is developed on the P side of
the junction. This net negative charge on the P side prevents further diffusion of electrons
into the P side. Similarly the net positive charge on the N side repels the hole crossing from P
side to N side. Thus a barrier sis set up near the junction which prevents the further
movement of charge carriers i.e. electrons and holes. As a consequence of induced electric
field across the depletion layer, an electrostatic potential difference is established between P
and N regions, which are called the potential barrier, junction barrier, diffusion potential or
contact potential, Vo. The magnitude of the contact potential Vo varies with doping levels and
temperature Vo is 0.3V for Ge and 0.72 V for Si.
Fig 1.6: Symbol of PN Junction Diode

The electrostatic field across the junction caused by the positively charged N-Type
region tends to drive the holes away from the junction and negatively charged P-type regions
tend to drive the electrons away from the junction. The majority holes diffusing out of the P
region leave behind negatively charged acceptor atoms bound to the lattice, thus exposing a
negatives pace charge in a previously neutral region. Similarly electrons diffusing from the N
region expose positively ionized donor atoms and a double space charge builds up at the
junction as shown in the fig. 1.7a
It is noticed that the space charge layers are of opposite sign to the majority carriers
diffusing into them, which tends to reduce the diffusion rate. Thus the double space of the
layer causes an electric field to be set up across the junction directed from N to P regions,
which is in such a direction to inhibit the diffusion of majority electrons and holes as

illustrated in fig 1.7b. The shape of the charge density, ρ, depends upon how diode id doped.
Thus the junction region is depleted of mobile charge carriers. Hence it is called depletion
layer, space region, and transition region. The depletion region is of the order of 0.5μm thick.
There are no mobile carriers in this narrow depletion region. Hence no current flows across
the junction and the system is in equilibrium. To the left of this depletion layer, the carrier
concentration is p= NA and to its right it is n= ND.

1.1.2 FORWARD BIASED JUNCTION DIODE

When a diode is connected in a Forward Bias condition, a negative voltage is applied
to the N-type material and a positive voltage is applied to the P-type material. If this external
voltage becomes greater than the value of the potential barrier, approx. 0.7 volts for silicon
and 0.3 volts for germanium, the potential barriers opposition will be overcome and current
will start to flow. This is because the negative voltage pushes or repels electrons towards the
junction giving them the energy to cross over and combine with the holes being pushed in the
opposite direction towards the junction by the positive voltage. This results in a
characteristics curve of zero current flowing up to this voltage point, called the "knee" on the
static curves and then a high current flow through the diode with little increase in the external
voltage as shown below.
Forward Characteristics Curve for a Junction Diode
The application of a forward biasing voltage on the junction diode results in the
depletion layer becoming very thin and narrow which represents a low impedance path
through the junction thereby allowing high currents to flow. The point at which this sudden
increase in current takes place is represented on the static I-V characteristics curve above as
the "knee" point.
Forward Biased Junction Diode showing a Reduction in the Depletion Layer

This condition represents the low resistance path through the PN junction allowing
very large currents to flow through the diode with only a small increase in bias voltage. The
actual potential difference across the junction or diode is kept constant by the action of the
depletion layer at approximately 0.3v for germanium and approximately 0.7v for silicon
junction diodes. Since the diode can conduct "infinite" current above this knee point as it
effectively becomes a short circuit, therefore resistors are used in series with the diode to
limit its current flow. Exceeding its maximum forward current specification causes the device
to dissipate more power in the form of heat than it was designed for resulting in a very quick
failure of the device.
1.1.2 PN JUNCTION UNDER REVERSE BIAS CONDITION:

Reverse Biased Junction Diode
This condition represents a high resistance value to the PN junction and practically
zero current flows through the junction diode with an increase in bias voltage. However, a
very small leakage current does flow through the junction which can be measured in
microamperes, (μA). One final point, if the reverse bias voltage Vr applied to the diode is
increased to a sufficiently high enough value, it will cause the PN junction to overheat and
fail due to the avalanche effect around the junction. This may cause the diode to become
shorted and will result in the flow of maximum circuit current, and this shown as a step
downward slope in the reverse static characteristics curve below.
Reverse Characteristics Curve for a Junction Diode

Sometimes this avalanche effect has practical applications in voltage stabilizing

circuits where a series limiting resistor is used with the diode to limit this reverse breakdown
current to a preset maximum value thereby producing a fixed voltage output across the diode.
These types of diodes are commonly known as Zener Diodes.
1.2 VI CHARACTERISTICS AND THEIR TEMPERATURE DEPENDENCE

Diode terminal characteristics equation for diode junction current:
( )
Where VT = KT/q;
VD - diode terminal voltage, Volts
Io - temperature-dependent saturation current, μA
T - Absolute temperature of p-n junction, K
K - Boltzmann‘s constant 1.38x 10 -23J/K)
q - Electron charge 1.6x10-19 C
n - Empirical constant, 1 for Ge and 2 for Si
Temperature Effects on Diode

Temperature can have a marked effect on the characteristics of a silicon
semiconductor diode as shown in Fig 1.11 It has been found experimentally that the reverse
saturation current Io will just about double in magnitude for every 10°C increase in
temperature.
Fig 1.11 Variation in Diode Characteristics with temperature change

It is not uncommon for a germanium diode with an Io in the order of 1 or 2 A at 25°C
to have a leakage current of 100 A - 0.1 mA at a temperature of 100°C. Typical values of Io
for silicon are much lower than that of germanium for similar power and current levels. The
result is that even at high temperatures the levels of Io for silicon diodes do not reach the
same high levels obtained. For germanium—a very important reason that silicon devices
enjoy a significantly higher level of development and utilization in design. Fundamentally,
the open-circuit equivalent in the reverse bias region is better realized at any temperature with

silicon than with germanium. The increasing levels of Io with temperature account for the
lower levels of threshold voltage, as shown in Fig. 1.11. Simply increase the level of Io in and
not rise in diode current. Of course, the level of TK also will be increase, but the increasing
level of Io will overpower the smaller percent change in TK. As the temperature increases the
forward characteristics are actually becoming more ―ideal‖.
1.3 IDEAL VERSUS PRACTICAL RESISTANCE LEVELS

DC or Static Resistance
The application of a dc voltage to a circuit containing a semiconductor diode will
result in an operating point on the characteristic curve that will not change with time. The
resistance of the diode at the operating point can be found simply by finding the
corresponding levels of VD and ID as shown in Fig. 1.12 and applying the following Equation:
Rd=VD/ID
The dc resistance levels at the knee and below will be greater than the resistance
levels obtained for the vertical rise section of the characteristics. The resistance levels in the
reverse-bias region will naturally be quite high. Since ohmmeters typically employ a
relatively constant-current source, the resistance determined will be at a preset current level
(typically, a few mill amperes).
Fig 1.12 Determining the dc resistance of a diode at a particular operating point.

AC or Dynamic Resistance
It is obvious from Eq. 1.3 that the dc resistance of a diode is independent of the shape
of the characteristic in the region surrounding the point of interest. If a sinusoidal rather than
dc input is applied, the situation will change completely. The varying input will move the
instantaneous operating point up and down a region of the characteristics and thus defines a
specific change in current and voltage as shown in Fig. 1.13. With no applied varying signal,
the point of operation would be the Q point appearing on Fig. 1.13 determined by the applied
dc levels. The designation Q-point is derived from the word quiescent, which means ―still or
unvarying.‖ A straight-line drawn tangent to the curve through the Q-point as shown in Fig.
1.13 will define a particular change in voltage and current that can be used to determine the
ac or dynamic resistance for this region of the diode characteristics. In equation form,
rd=ΔVD/ΔID
Where Δ signifies a finite change in the quantity
Fig 1.13: Determining the ac resistance of a diode at a particular operating point.

1.4 DIODE EQUIVALENT CIRCUITS

An equivalent circuit is a combination of elements properly chosen to best represent
the actual terminal characteristics of a device, system, or such in a particular operating
region. In other words, once the equivalent circuit is defined, the device symbol can be
removed from a schematic and the equivalent circuit inserted in its place without severely
affecting the actual behaviour of the system. The result is often a network that can be solved
using traditional circuit analysis techniques.
Piecewise-Linear Equivalent Circuit
One technique for obtaining an equivalent circuit for a diode is to approximate the
characteristics of the device by straight-line segments, as shown in Fig. 1.31. The resulting
equivalent circuit is naturally called the piecewise-linear equivalent circuit. It should be
obvious from Fig. 1.31 that the straight-line segments do not result in an exact duplication of
the actual characteristics, especially in the knee region. However, the resulting segments are
sufficiently close to the actual curve to establish an equivalent circuit that will provide an
excellent first approximation to the actual behaviour of the device. The ideal diode is
included to establish that there is only one direction of conduction through the device, and a
reverse-bias condition will result in the open- circuit state for the device. Since a silicon
semiconductor, diode does not reach the conduction state until VD reaches 0.7 V with a
forward bias (as shown in Fig. 1.14a), a battery VT opposing the conduction direction must
appear in the equivalent circuit as shown in Fig. 1.14b. The battery simply specifies that the
voltage across the device must be greater than the threshold battery voltage before conduction
through the device in the direction dictated by the ideal diode can be established. When
conduction is established, the resistance of the diode will be the specified value of rav.
Fig: 1.14aDiode piecewise-linear model characteristics
Fig: 1.14b Diode piecewise-linear model equivalent circuit

The approximate level of rav can usually be determined from a specified operating
point on the specification sheet. For instance, for a silicon semiconductor diode, if IF =10 mA
(a forward conduction current for the diode) at VD=0.8 V, we know for silicon that a shift of
0.7 V is required before the characteristics rise.
Fig 1.15 Ideal Diode and its characteristics

Diode capacitances: The diode exhibits two types of capacitances transition capacitance and
diffusion capacitance.
• Transition capacitance: The capacitance which appears between positive ion layer in
n-region and negative ion layer in p-region.
• Diffusion capacitance: This capacitance originates due to diffusion of charge carriers
in the opposite regions.
The transition capacitance is very small as compared to the diffusion capacitance.
where CT - transition capacitance

A - diode cross sectional area
W - depletion region width
In forward bias, the diffusion capacitance is the dominant and is given by:
where CD - diffusion capacitance

dQ - change in charge stored in depletion region
dV - change in applied voltage- time interval for change in
voltage
g - Diode conductance
r - diode resistance
The diffusion capacitance at low frequencies is given by the formula:
The diffusion capacitance at high frequencies is inversely proportional to the

frequency and is given by the formula:
1.6 BREAK DOWN MECHANISMS

When an ordinary P-N junction diode is reverse biased, normally only very small
reverse saturation current flows. This current is due to movement of minority carriers. It is
almost independent of the voltage applied. However, if the reverse bias is increased, a point is
reached when the junction breaks down and the reverse current increases abruptly. This
current could be large enough to destroy the junction. If the reverse current is limited by
means of a suitable series resistor, the power dissipation at the junction will not be excessive,
and the device may be operated continuously in its breakdown region to its normal (reverse
saturation) level. It is found that for a suitably designed diode, the breakdown voltage is very
stable over a wide range of reverse currents. This quality gives the breakdown diode many
useful applications as a voltage reference source.
The critical value of the voltage, at which the breakdown of a P-N junction diode
occurs, is called the breakdown voltage. The breakdown voltage depends on the width of the
depletion region, which, in turn, depends on the doping level. The junction offers almost zero
resistance at the breakdown point. There are two mechanisms by which breakdown can occur
at a reverse biased P-N junction:
1. Avalanche breakdown and
2. Zener breakdown.

Avalanche breakdown: The minority carriers, under reverse biased conditions, flowing
through the junction acquire a kinetic energy which increases with the increase in reverse
voltage. At a sufficiently high reverse voltage (say 5 V or more), the kinetic energy of
minority carriers becomes so large that they knock out electrons from the covalent bonds of
the semiconductor material. As a result of collision, the liberated electrons in turn liberate
more electrons and the current becomes very large leading to the breakdown of the crystal
structure itself. This phenomenon is called the avalanche breakdown. The breakdown region
is the knee of the characteristic curve. Now the current is not controlled by the junction
voltage but rather by the external circuit.
Zener breakdown: Under a very high reverse voltage, the depletion region expands and the
potential barrier increases leading to a very high electric field across the junction. The electric
field will break some of the covalent bonds of the semiconductor atoms leading to a large
number of free minority carriers, which suddenly increase the reverse current. This is called
the Zener effect. The breakdown occurs at a particular and constant value of reverse voltage
called the breakdown voltage; it is found that Zener breakdown occurs at electric field
intensity of about 3 x 107 V/m.
Fig 1.18: Diode characteristics with breakdown
Either of the two (Zener breakdown or avalanche breakdown) may occur

independently, or both of these may occur simultaneously. Diode junctions that breakdown
below 5 V are caused by Zener effect. Junctions that experience breakdown above 5 V are
caused by avalanche effect. Junctions that breakdown around 5 V are usually caused by
combination of two effects. The Zener breakdown occurs in heavily doped junctions (P-type
semiconductor moderately doped and N-type heavily doped), which produce narrow
depletion layers. The avalanche breakdown occurs in lightly doped junctions, which produce
wide depletion layers. With the increase in junction temperature Zener breakdown voltage is
reduced while the avalanche breakdown voltage increases. The Zener diodes have a negative
temperature coefficient while avalanche diodes have a positive temperature coefficient.
Diodes that have breakdown voltages around 5 V have temperature coefficient zero. The
breakdown phenomenon is reversible and harmless so long as the safe operating temperature
is maintained.
1.7 ZENER DIODES

The Zener diode is like a general-purpose signal diode consisting of a silicon PN
junction. When biased in the forward direction it behaves just like a normal signal diode
passing the rated current, but as soon as a reverse voltage applied across the Zener diode
exceeds the rated voltage of the device, the diodes breakdown voltage VB is reached at which

point a process called Avalanche Breakdown occurs in the semiconductor depletion layer and
a current starts to flow through the diode to limit this increase in voltage.
The current now flowing through the zener diode increases dramatically to the
maximum circuit value (which is usually limited by a series resistor) and once achieved this
reverse saturation current remains fairly constant over a wide range of applied voltages. This
breakdown voltage point, VB is called the "zener voltage" for zener diodes and can range
from less than one volt to hundreds of volts.
The point at which the zener voltage triggers the current to flow through the diode can
be very accurately controlled (to less than 1% tolerance) in the doping stage of the diodes
semiconductor construction giving the diode a specific zener breakdown voltage, (Vz) for
example, 4.3V or 7.5V. This zener breakdown voltage on the I-V curve is almost a vertical
straight line.
Zener Diode I-V Characteristics
Fig 1.19 Zener diode characteristics

The Zener Diode is used in its "reverse bias" or reverse breakdown mode, i.e. the
diodes anode connects to the negative supply. From the I-V characteristics curve above, we
can see that the Zener diode has a region in its reverse bias characteristics of almost a
constant negative voltage regardless of the value of the current flowing through the diode and
remains nearly constant even with large changes in current as long as the Zener diodes
current remains between the breakdown current IZ(min) and the maximum current rating
IZ(max).
This ability to control itself can be used to great effect to regulate or stabilize a
voltage source against supply or load variations. The fact that the voltage across the diode in
the breakdown region is almost constant turns out to be an important application of the Zener
diode as a voltage regulator. The function of a regulator is to provide a constant output
voltage to a load connected in parallel with it in spite of the ripples in the supply voltage or
the variation in the load current and the Zener diode will continue to regulate the voltage until
the diodes current falls below the minimum IZ(min) value in the reverse breakdown region.
SPECIAL PURPOSE ELECTRONIC DEVICES

1.8 PRINCIPLE OF OPERATION AND CHARACTERISTICS OF TUNNEL DIODE
A tunnel diode or Esaki diode is a type of semiconductor diode which is capable of
very fast operation, well into the microwave frequency region, by using quantum mechanical
effects.

It was invented in August 1957 by Leo Esaki when he was with Tokyo Tsushin
Kogyo, now known as Sony. In 1973 he received the Nobel Prize in Physics, jointly with
Brian Josephson, for discovering the electron tunnelling effect used in these diodes. Robert
Noyce independently came up with the idea of a tunnel diode while working for William
Shockley, but was discouraged from pursuing it.
Fig 1.19: Tunnel diode schematic symbol

These diodes have a heavily doped p–n junction only some 10 nm (100 Å) wide. The
heavy doping results in a broken band gap, where conduction band electron states on the n-
side are more or less aligned with valence band hole states on the P-side. Tunnel diodes were
manufactured by Sony for the first time in 1957 followed by General Electric and other
companies from about 1960, and are still made in low volume today. Tunnel diodes are
usually made from germanium, but can also be made in gallium arsenide and silicon
materials. They can be used as oscillators, amplifiers, frequency converters and detectors.
Tunnelling Phenomenon: In a conventional semiconductor diode, conduction takes place
while the p–n junction is forward biased and blocks current flow when the junction is reverse
biased. This occurs up to a point known as the ―reverse breakdown voltage‖ when conduction
begins (often accompanied by destruction of the device). In the tunnel diode, the dopant
concentration in the p and n layers are increased to the point where the reverse breakdown
voltage becomes zero and the diode conducts in the reverse direction. However, when
forward-biased, an odd effect occurs called ―quantum mechanical tunnelling‖ which gives
rise to a region where an increase in forward voltage is accompanied by a decrease in
forward current. This negative resistance region can be exploited in a solid state version of
the dynatron oscillator which normally uses a tetrode thermionic valve (or tube).
Forward bias operation: Under normal forward bias operation, as voltage begins to
increase, electrons at first tunnel through the very narrow p–n junction barrier because filled
electron states in the conduction band on the N-side become aligned with empty valence band
hole states on the p-side of the p-n junction. As voltage increases further these states become
more misaligned and the current drops – this is called negative resistance because current
decreases with increasing voltage. As voltage increases yet further, the diode begins to
operate as a normal diode, where electrons travel by conduction across the p–n junction, and
no longer by tunnelling through the p–n junction barrier. Thus the most important operating
region for a tunnel diode is the negative resistance region.
Reverse bias operation: When used in the reverse direction they are called back diodes and
can act as fast rectifiers with zero offset voltage and extreme linearity for power signals (they
have an accurate square law characteristic in the reverse direction).
Fig 1.20a: current-voltage characteristic of tunnel diode

Under reverse bias filled states on the p-side become increasingly aligned with empty
states on the N-side and electrons now tunnel through the p-n junction barrier in reverse
direction – this is the Zener effect that also occurs in Zener diodes.
Energy band structure of tunnel diode:
Fig 1.20b Energy band structure of tunnel diode

For the degenerated semiconductors, the energy band diagram at thermal equilibrium
is presented in Figure 1.20b.
In Figure 1.20c the tunneling processes in different points of the current voltage
characteristic for the tunnel diode are presented.
Advantages of tunnel diodes:

• Environmental immunity i.e. peak point is not a function of temperature.
• Low cost.
• Low noise.
• Low power consumption.
• High speed i.e. tunnelling takes place very fast at the speed of light in the order of
nanoseconds
• Simplicity i.e. a tunnel diode can be used along with a d.c supply and a few passive
elements to obtain various application circuits.
Applications for tunnel diodes:
• local oscillators for UHF television tuners
• Trigger circuits in oscilloscopes
• High speed counter circuits and very fast-rise time pulse generator circuits
• The tunnel diode can also be used as low-noise microwave amplifier.

1.9 VARACTOR DIODE

Varactor diode is a special type of diode which uses transition capacitance property i.e
voltage variable capacitance .These are also called as varicap,VVC(voltage variable
capacitance) or tuning diodes. The varactor diode symbol is shown below with a diagram
representation.
Fig 1.21a: symbol of varactor diode

When a reverse voltage is applied to a PN junction, the holes in the p-region are
attracted to the anode terminal and electrons in the n-region are attracted to the cathode
terminal creating a region where there is little current. This region, the depletion region, is
essentially devoid of carriers and behaves as the dielectric of a capacitor.
The depletion region increases as reverse voltage across it increases; and since
capacitance varies inversely as dielectric thickness, the junction capacitance will decrease as
the voltage across the PN junction increases. So by varying the reverse voltage across a PN
junction the junction capacitance can be varied .This is shown in the typical varactor voltage-
capacitance curve below.
Fig 1.21b: voltage- capacitance curve

Notice the nonlinear increase in capacitance as the reverse voltage is decreased. This
nonlinearity allows the varactor to be used also as a harmonic generator.
Major varactor considerations are:
• Capacitance value
• Voltage
• Variation in capacitance with voltage.
• Maximum working voltage
• Leakage current
Applications:
• Tuned circuits.
• FM modulators
• Automatic frequency control devices
• Adjustable bandpass filters
• Parametric amplifiers
• Television receivers.
1.10 PRINCIPLE OF OPERATION OF SCR

A silicon-controlled rectifier (or semiconductor-controlled rectifier) is a four-layer
solid state device that controls current. The name "silicon controlled rectifier" or SCR is
General Electric's trade name for a type of thyristor. The SCR was developed by a team of

power engineers led by Gordon Hall and commercialized by Frank W. "Bill" Gutzwiller in
1957.symbol of SCR is given below:
Fig 1.22: symbol of SCR

Construction of SCR
An SCR consists of four layers of alternating P and N type semiconductor materials.
Silicon is used as the intrinsic semiconductor, to which the proper dopants are added. The
junctions are either diffused or alloyed. The planar construction is used for low power SCRs
(and all the junctions are diffused). The mesa type construction is used for high power SCRs.
In this case, junction J2 is obtained by the diffusion method and then the outer two layers are
alloyed to it, since the PNPN pellet is required to handle large currents. It is properly braced
with tungsten or molybdenum plates to provide greater mechanical strength. One of these
plates is hard soldered to a copper stud, which is threaded for attachment of heat sink. The
doping of PNPN will depend on the application of SCR, since its characteristics are similar to
those of the thyratron. Today, the term thyristor applies to the larger family of multilayer
devices that exhibit bistable state-change behaviour, i.e. switching either ON or OFF. The
operation of a SCR and other thyristors can be understood in terms of a pair of tightly
coupled bipolar junction transistors, arranged to cause the self-latching action. The following
figures are construction of SCR, its two transistor model and symbol respectively.
Fig 1.23: Construction, Two transistor model of SCR and symbol of SCR
SCR Working Principle
Fig 1.24: Current flow and voltage bias in an SCR

The SCR is a four-layer, three-junction and a three-terminal device and is shown in
fig.1.24. The end P-region is the anode, the end N-region is the cathode and the inner P-
region is the gate. The anode to cathode is connected in series with the load circuit.
Essentially the device is a switch. Ideally it remains off (voltage blocking state), or appears to
have an infinite impedance until both the anode and gate terminals have suitable positive
voltages with respect to the cathode terminal. The thyristor then switches on and current
flows and continues to conduct without further gate signals. Ideally the thyristor has zero
impedance in conduction state. For switching off or reverting to the blocking state, there must

be no gate signal and the anode current must be reduced to zero. Current can flow only in one
direction.
In absence of external bias voltages, the majority carrier in each layer diffuses until
there is a built-in voltage that retards further diffusion. Some majority carriers have enough
energy to cross the barrier caused by the retarding electric field at each junction. These
carriers then become minority carriers and can recombine with majority carriers. Minority
carriers in each layer can be accelerated across each junction by the fixed field, but because
of absence of external circuit in this case the sum of majority and minority carrier currents
must be zero.
A voltage bias, as shown in figure 1.24 and an external circuit to carry current allow
internal currents which include the following terms:
• The current Ix is due to
• Majority carriers (holes) crossing junction J1
• Minority carriers crossing junction J1
• Holes injected at junction J2 diffusing through the N-region and crossing junction J1
and
• Minority carriers from junction J2 diffusing through the N-region and crossing
junction J1.
V I characteristics of SCR:
Fig 1.25: V-I characteristics of SCR

As already mentioned, the SCR is a four-layer device with three terminals, namely,
the anode, the cathode and the gate. When the anode is made positive with respect to the
cathode, junctions J1 and J3 are forward biased and junction J2 is reverse-biased and only the
leakage current will flow through the device. The SCR is then said to be in the forward
blocking state or in the forward mode or off state. But when the cathode is made positive with
respect to the anode, junctions J1 and J3 are reverse-biased, a small reverse leakage current
will flow through the SCR and the SGR is said to be in the reverse blocking state or in
reverse mode.
When the anode is positive with respect to cathode i.e. when the SCR is in forward
mode, the SCR does not conduct unless the forward voltage exceeds certain value, called the
forward breakover voltage, VFB0. In non-conducting state, the current through the SCR is the
leakage current which is very small and is negligible. If a positive gate current is supplied, the
SCR can become conducting at a voltage much lesser than forward break-over voltage. The
larger the gate current, lower the break-over voltage. With sufficiently large gate current, the
SCR behaves identical to PN rectifier. Once the SCR is switched on, the forward voltage

drop across it is suddenly reduced to very small value, say about 1 volt. In the conducting or
on-state, the current through the SCR is limited by the external impedance.
When the anode is negative with respect to cathode that is when the SCR is in reverse
mode or in blocking state no current flows through the SCR except very small leakage
current of the order of few micro-amperes. But if the reverse voltage is increased beyond a
certain value, called the reverse breakover voltage, VRB0 avalanche break down takes place.
Forward break-over voltage VFB0 is usually higher than reverse breakover voltage, VRBO.
From the foregoing discussion, it can be seen that the SCR has two stable and
reversible operating states. The change over from off-state to on-state, called turn-on, can be
achieved by increasing the forward voltage beyond VFB0. A more convenient and useful
method of turn-on the device employs the gate drive. If the forward voltage is less than the
forward break-over voltage, VFB0, it can be turned-on by applying a positive voltage
between the gate and the cathode. This method is called the gate control. Another very
important feature of the gate is that once the SCR is triggered to on-state the gate loses its
control.
The switching action of gate takes place only when
• SCR is forward biased i.e. anode is positive with respect to cathode, and
• Suitable positive voltage is applied between the gate and the cathode.
Once the SCR has been switched on, it has no control on the amount of current flowing
through it. The current through the SCR is entirely controlled by the external impedance
connected in the circuit and the applied voltage. There is, however, a very small, about 1 V,
potential drop across the SCR. The forward current through the SCR can be reduced by
reducing the applied voltage or by increasing the circuit impedance. There is, however, a
minimum forward current that must be maintained to keep the SCR in conducting state. This
is called the holding current rating of SCR. If the current through the SCR is reduced below
the level of holding current, the device returns to off-state or blocking state.
The SCR can be switched off by reducing the forward current below the level of holding
current which may be done either by reducing the applied voltage or by increasing the circuit
impedance.
Note: The gate can only trigger or switch-on the SCR, it cannot switch off. Alternatively the
SCR can be switched off by applying negative voltage to the anode (reverse mode); the SCR
naturally will be switched off.
Here one point is worth mentioning, the SCR takes certain time to switch off. The
time, called the turnoff time, must be allowed before forward voltage may be applied again
otherwise the device will switch-on with forward voltage without any gate pulse. The turn-off
time is about 15 micro-seconds, which is immaterial when dealing with power frequency, but
this becomes important in the inverter circuits, which are to operate at high frequency.
Merits of SCR
• Very small amount of gate drive is required.
• SCRs with high voltage and current ratings are available.
• On state losses of SCR is less.
Demerits of SCR
• Gate has no control, once SCR is turned on.
• External circuits are required for turning it off.
• Operating frequencies are low.
• Additional protection circuits are required.
Application of SCRs
SCRs are mainly used in devices where the control of high power, possibly coupled with high
voltage, is demanded. Their operation makes them suitable for use in medium to high-voltage

AC power control applications, such as lamp dimming, regulators and motor control. SCRs
and similar devices are used for rectification of high power AC in high-voltage direct current
power transmission
1.11 PHOTO DIODE

The photo diode is a semiconductor p-n junction device whose region of operation is
limited to the reverse biased region. The figure below shows the symbol of photodiode
Fig 1.26: Symbol of photodiode.

Principle of operation:
A photodiode is a type of photo detector capable of converting light into either current
or voltage, depending upon the mode of operation. The common, traditional solar cell used to
generate electric solar power is a large area photodiode. A photodiode is designed to operate
in reverse bias. The deletion region width is large. Under normal conditions it carries small
reverse current due to minority charge carriers. When light is incident through glass window
on the p-n junction, photons in the light bombard the p-n junction and some energy s
imparted to the valence electrons. So valence electrons break covalent bonds and become free
electrons. Thus more electron-hole pairs are generated. Thus total number of minority charge
carriers increases and hence reverse current increases. This is the basic principle of operation
of photo diode.
Fig 1.27: Basic Biasing Arrangement and construction of photodiode and symbols
Characteristics of photodiode:
When the P-N junction is reverse-biased, a reverse saturation current flows due to
thermally generated holes and electrons being swept across the junction as the minority
carriers. With the increase in temperature of the junction more and more hole-electron pairs
are created and so the reverse saturation current I0 increases. The same effect can be had by
illuminating the junction. When light energy bombards a P-N junction, it dislodges valence
electrons. The more light striking the junction larger reverse current in a diode. It is due to
generation of more and more charge carriers with the increase in level of illumination. This is
clearly shown in figure for different intensity levels. The dark current is the current that exists
when no light is incident. It is to be noted here that current becomes zero only with a positive
applied bias equals to VQ. The almost equal spacing between the curves for the same
increment in luminous flux reveals that the reverse saturation current I0 increases linearly
with the luminous flux as shown in figure. Increase in reverse voltage does not increase the
reverse current significantly, because all available charge carriers are already being swept
across the junction. For reducing the reverse saturation current I0 to zero, it is necessary to
forward bias the junction by an amount equal to barrier potential. Thus the photodiode can be
used as a photoconductive device.
C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page

Page 24
24
Fig 1.28: characteristics of photodiode
On removal of reverse bias applied across the photodiode, minority charge carriers
continue to be swept across the junction while the diode is illuminated. This has the effect of
increasing the concentration of holes in the P-side and that of electrons in the N-side but the
barrier potential is negative on the P-side and positive on the N-side, and was created by
holes flowing from P to N-side and electrons from N to P-side during fabrication of junction.
Thus the flow of minority carriers tends to reduce the barrier potential.
When an external circuit is connected across the diode terminals, the minority carrier;
return to the original side via the external circuit. The electrons which crossed the junction
from P to N-side now flow out through the N-terminal and into the P-terminal This means
that the device is behaving as a voltage cell with the N-side being the negative terminal and
the P-side the positive terminal. Thus, the photodiode is & photovoltaic device as well as
photoconductive device.
Advantages:
• It can be used as variable resistance device.
• Highly sensitive to the light.
• The speed of operation is very high.
Disadvantages:
• Temperature dependent dark current.
• Poor temperature stability.
• Current needs amplification for driving other circuits.
Applications:
• Alarm system.
• Counting system.
1.12 DIAC
The DIAC is basically a two-terminal parallel-inverse combination of semiconductor

layers that permits triggering in either direction. The characteristics of the device, presented
in Figure, clearly demonstrate that there is a break over voltage in either direction. This
possibility of an on condition in either direction can be used to its fullest advantage in ac
applications.
When anode 1 is positive with respect to anode 2, the semiconductor layers of

particular interest are p1n2p2 and n3. For anode 2 positive with respect to anode 1, the
applicable layers are p2n2p1 and n1.

Page 25
25
Fig (a) DIAC characteristics Fig (b) Symbols and basic constructions
1.13 TRIAC
The TRIAC is fundamentally a DIAC with a gate terminal for controlling the turn-on
conditions of the bilateral device in either direction. In other words, for either direction the
gate current can control the action of the device in a manner very similar to that demonstrated
for an SCR. The characteristics, however, of the TRIAC in the first and third quadrants are
somewhat different from those of the DIAC. For each possible direction of conduction, there
is a combination of semiconductor layers whose state will be controlled by the signal applied
to the gate terminal.
The action of this circuit during the positive portion of the input signal is very similar
to that encountered for the Shockley diode. The advantage of this configuration is that during
the negative portion of the input signal, the same type of response will result since both the
DIAC and TRIAC can fire in the reverse direction. The resulting waveform for the current
through the load is provided in Fig.
1.14 UNIJUNCTION TRANSISTOR

The UJT is a three-terminal device having the basic construction of Fig. A slab of
lightly doped (increased resistance characteristic) n-type silicon material has two base
contacts attached to both ends of one surface and an aluminium rod alloyed to the opposite
surface. The p-n junction of the device is formed at the boundary of the aluminium rod and
the n-type silicon slab. The single p-n junction accounts for the terminology unijunction. It

was originally called a duo (double) base diode due to the presence of two base contacts.
Note in Figure that the aluminium rod is alloyed to the silicon slab at a point closer to the
base 2 contact than the base 1 contact and that the base 2 terminal is made positive with
respect to the base 1 terminal by VBB volts. The effect of each will become evident in the
paragraphs to follow.
Note that the emitter leg is drawn at an angle to the vertical line representing the slab
of n-type material. The arrowhead is pointing in the direction of conventional current (hole)
flow when the device is in the forward-biased, active, or conducting state.
The inter base resistance RBB is the resistance of the device between terminals B1 and
B2when IE =0. In equation form
RBB = (RB1 +RB2) IE=0
|
The Greek letter (eta) is called the intrinsic stand-off ratio of the device. For
applied emitter potentials (VE) greater than VRB1 (VBB) by the forward voltage drop of the
diode VD (0.35->0.70 V), the diode will fire. Assume the short-circuit representation (on an
ideal basis), and IE will begin to flow through RB1. In equation form, the emitter firing
potential is given by

Note that for emitter potentials to the left of the peak point, the magnitude of IE is
never greater than IEO (measured in microamperes). The current IEO corresponds very closely
with the reverse leakage current ICO of the conventional bipolar transistor. This region, as
indicated in the figure, is called the cut-off region. Once conduction is established at VE =VP,
the emitter potential VE will drop with increase in IE. This corresponds exactly with the
decreasing resistance RB1 for increasing current IE, as discussed earlier. This device,
therefore, has a negative resistance region that is stable enough to be used with a great deal of
reliability in the areas of application listed earlier. Eventually, the valley point will be
reached, and any further increase in IE will place the device in the saturation region. In this
region, the characteristics approach that of the semiconductor diode in the equivalent circuit.
The decrease in resistance in the active region is due to the holes injected into the n-
type slab from the aluminium p-type rod when conduction is established. The increased hole
content in the n-type material will result in an increase in the number of free electrons in the
slab, producing an increase in conductivity (G) and a corresponding drop in resistance
1.15 LIGHT-EMITTING DIODES

The increasing use of digital displays in calculators, watches, and all forms of
instrumentation has contributed to the current extensive interest in structures that will
emit light when properly biased. The two types in common use today to perform this function
are the light-emitting diode (LED) and the liquid-crystal display (LCD).
As the name implies, the light-emitting diode (LED) is a diode that will give off
visible light when it is energized. In any forward-biased p-n junction there is, within the
structure and primarily close to the junction, a recombination of holes and electrons. This
recombination requires that the energy possessed by the unbound free electron be transferred
to another state. In all semiconductor p-n junctions some of this energy will be given off as
heat and some in the form of photons. In silicon and germanium the greater percentage is
given up in the form of heat and the emitted light is insignificant. In other materials, such as
gallium arsenide phosphide (GaAsP) or gallium phosphide (GaP), the number of photons of
light energy emitted is sufficient to create a very visible light source.
The conducting surface connected to the p-material is much smaller, to permit the
emergence of the maximum number of photons of light energy. Note in the figure that the
recombination of the injected carriers due to the forward-biased junction results in emitted
light at the site of recombination. There may, of course, be some absorption of the packages
of photon energy in the structure itself, but a very large percentage are able to leave, as
shown in the figure.
Figure shows the process of electroluminescence in the LED.

UNIT -1
Solved Problems:
1. A silicon diode has a saturation current of 7.5 μA at room temperature 300 K. Calculate
the saturation current at 400 K. 4M (Nov/Dec-2016)
Solution:
Given data:-
Reverse saturation current IO1 = 7.5 μA, at room temperature T1 = 3000K, silicon diode η=2, and
forward bias voltage of Si=0.7V, at room temperature T2=4000K, reverse saturation current IO2=?
T = T2-T1 = 4000K-3000K = 1000K.
IO2=IO1 X 2(T2-T1)/10
=7.5 μA X 2(400K-300K)/10
= 7.5 μA X 2(100)/10
=7.5 μA X1024
IO2=7.68mA
2. For a Ge diode, the I0 = 2𝜇𝐴 and the voltage of 0.26 V is applied. Calculate the forward
and reverse dynamic resistance values at room temperature. 4M (Nov/Dec-2018)
Solution:
Given data:- IO=2 𝜇𝐴, V=0.26V, Ge Diode η=1, at room temperature T= 3000K, Forward
resistance rf=?, reverse resistance rr=?
Case 1: WhenV= 0.26V
ηVT T 300
Dynamic resistance rf = , Where VT = 11600 = 11600 =0.025V
𝐼
For calculation of diode current I = I0(eV/ήVT-1)

= 2 (e0.26/1X0.025-1)
= 2 (32859.62-1)
I= 65m𝐴
ηVT 0.025
Reverse dynamic resistance rf = = 𝟔𝟓𝐦𝐀
𝐼
rf =0.384Ω
Case 2: WhenV= -0.26V

ηVT T 300
Dynamic resistance rf = 𝐼 , Where VT = 11600 = 11600 =0.025V
For calculation of diode current I = I0(e-V/ήVT-1)
= 2 (e-0.26/1X0.025-1)
= 2 (30X10-6-1)
I=2 𝜇𝐴
ηVT 0.025
Reverse dynamic resistance rf = =
𝐼 2𝛍𝐀
rf =12500Ω or 12.5KΩ
1 29
3. The voltage across a silicon diode at room temperature is 0.7 volts when 2 mA current flows
through it. If the voltage increases to 0.75 volts, calculate the diode current.
Solution:
Given data:- V1=0.7V, I1=2mA,Silicon diode η=2, at room temperature T=3000K, VT=26mV,
V2=0.75V, I2=?
Case 1:-
I1 = I0 (eV1/ήVT-1)
2mA = I0 (e0.7V/2X26mV-1)
2mA = I0 (e0.7V/52mV-1) = 2mA = I0 (e9.42-1) is approximately equal to I0 (e9.42)
2mA
Finally I0= e9.42 --------- e.q (1)
Case 1:-
I2 = I0 (eV2/ήVT-1)
2mA
I2 = e9.42 (e0.75V/2X26mV-1)
2mA
I2 = e9.42 (e0.75V/52mV-1)
2mA
I2 = e9.42 (e10.81)
I2 = 2mA (e10.81-9.42)
I2 = 2mA (3.76)
I2 =7.41mA
4. Calculate the factor by which the current will increase in silicon diode operating at a forward voltage of
0.4 volts, when the temperature is raised from 250C to 1500C.
Solution:
Given data:- Silicon diode Vf=0.4V, Si η=1, T1=250C,T2=1500
In Kelvin the temperature T1=(25+273)=2980K, T2=(150+273)=4230K
T = T2-T1 = 4230K-2980K = 1250K.
IO2(150) = IO1(25) X 2(T2-T1)/10
= IO1(25) X 2(423K-298K)/10
= IO1(25) X 2(125)/10
= IO1(25) X 5792
VT at 4230K =T/11600 = 4230K/11600 = 36mV.
VT at 2980K =T/11600 = 2980K/11600 = 26mV.
I(25) = I01(25) (eV/ήVT-1) ___________ e.q (1)
I(150) = I02(150) (eV/ήVT-1) ___________ e.q (2)
Divide the equation (1) w.r.t. equation (2)
I(25) I(25) (eV/ήVT−1)
= I(150) (eV/ήVT−1)
I(150)
I(25) (e0.4/1X26mV−1)
= IO1(25) X 5792 (e0.4/1X36mV−1)
𝐈(𝟐𝟓) 𝟐𝟑𝟗𝟕
= (𝟓𝟕𝟗𝟐)(𝟐𝟑𝟗) = 1.73X10-3 times factor the current increases
𝐈(𝟏𝟓𝟎)
2
30
UNIT-1 PART-A QUESTIONS WITH ANSWERS (2 Marks)
1. What are the classifications of semiconductors?

The semiconductors are classified as intrinsic and extrinsic semiconductors. A pure
semiconductor is called intrinsic semiconductor. A doped semiconductor is called as an extrinsic
semiconductor.
2. What is meant by doping?
The process of adding impurities to a semiconductor is known as doping.
3. How the extrinsic Semiconductors are classified?
N-type semiconductor and P-type semiconductor
4. How the n-type semiconductor can be obtained?
The n-type semiconductor can be obtained by adding pentavalent impurities to intrinsic
semiconductor. Examples for pentavalent atoms are Arsenic, phosphorous, bismuth and
antimony
5. How the p-type semiconductor can be obtained?
The p-type semiconductor can be obtained by adding trivalent impurities to intrinsic
semiconductor. Examples for trivalent atoms are boron, indium and gallium.
6. Define Fermi level? And what is Fermi Dirac distribution function?
Fermi level is the energy at which the probability of occupation by an electron is exactly
0.5
1
F(E) =
1 + e(E–EF)/KT
7. For Intrinsic semiconductor where the Fermi level lies?
The Fermi level lies in the centre of the forbidden energy band for an intrinsic
semiconductor.
8. What is energy band gap of silicon and germanium at 3000k?
For germanium 0.66 eV; for silicon 1.12eV
9. What is mass action law?
Under equilibrium the product of number of holes and the number of electron is constant
and is independent of the amount of donor and acceptor atoms. This relation is known as mass
action law and is given by np=ni2
10. Write an expression for the conductivity of a semiconductor?
The conductivity of a semiconductor is given by o = (nµn + pµp)q
11. What is depletion region in PN junction?
The region around the junction from which the mobile charge carriers (electrons and
holes) are depleted is called as depletion region. Since this region has immobile ions, which are
electrically charged, the depletion region is also known as space charge region.
12. Give the other names of depletion region?
i. Space charge region ii. Transition region
13. What is barrier potential?
The oppositely charged ions present on both sides of PN junction an electric potential is
established across the junction even without any external voltage source which is termed as
barrier potential.
14. What is meant by biasing a PN junction?
3
31
Connecting a PN junction to an external voltage source is biasing a PN junction.

15. What is forward bias and reverse bias in a PN junction?
When positive terminal of the external supply is connected to P region and negative
terminal to N region, the PN junction is said to be forward biased. Under forward biased
condition the PN region offers a very low resistance and a large amount of current flows through
it.
16. What is Reverse saturation current?
The current due to the minority carriers in reverse bias is said to be reverse saturation
current. This current is independent of the value of the reverse bias voltage.
17. Why contact differences of potential exist in PN junction?
When a PN junction is formed by placing a p-type and n-type material in intimate
contact, the Fermi level throughout the newly formed specimen is not constant at equilibrium.
There will be transfer of electron and energy until Fermi levels in the two sides did line up. But
the valence and conduction band in p side cannot be at the same level as in n side .this shift in
energy level results in contact difference of potential.
18. What is the static resistance of a diode?
Static resistance R of a diode can be defined as the ratio of voltage V across the diode to
the current flowing through the diode.
R = V/ I
Where, R - Static resistance of a diode, V -
Voltage across the diode
I - current across the diode
19. Define dynamic resistance.
Dynamic resistance of a diode can be defined as the ratio of change in voltage across
the diode to the change in current through the diode.
r=V/I
Where r - Dynamic resistance of a diode,
V - Change in voltage across the diode I -
change in current through the diode
20. What is an ideal diode?
An ideal diode is one which offers zero resistance when forward biased and infinite
resistance when reverse
21. Define knee/cut-in/threshold voltage of a PN diode.
It is the forward voltage applied across the PN diode below which practically no
current flows Biased.
22. What is the effect of junction temperature on cut-in voltage of a PN diode?
Cut-in voltage of a PN diode decreases as junction temperature increases.
23. What is the effect of junction temperature on forward current and reverse current of
a PN diode?
For the same forward voltage, the forward current of a PN diode increases and reverse
saturation current increases with increase in junction temperature.
24. Define transition capacitance of a diode.
Transition Capacitance (CT) or Space-charge Capacitance: When a PN-Junction is
reverse biased, the depletion region acts like an insulator or as a dielectric. The P- and N-
4 32
regions on either side have low resistance and act as the plates. Hence it is similar to a parallel-
plate capacitor. This junction capacitance is called transition or space-charge capacitance
25. Differentiate avalanche and Zener breakdowns.

Zener break down Avalanche breakdown
Breakdown occurs due to heavil Breakdown occurs due to avalanche
doped junction and applie y multiplication thermally
electric field d stron betwee
n generated ions
g
Doping level is high Doping level is low
Breakdown occurs at lower voltage Break down occurs at higher voltage
compared to avalanche breakdown
26. Differentiate Drift and Diffusion currents
Drift current Diffusion current
It is developed due to potential It is developed due to charge
Gradient concentration gradient
This phenomenon is found both in This is found only in semiconductors
metals and semiconductors
27. Define diffusion capacitance of a diode.
Diffusion or Storage Capacitance (CD): This capacitive effect is present when the
junction is forward-biased. It is called diffusion capacitance due to the time delay in minority
charges across the junction by diffusion process. Due to this fact, this capacitance cannot be
identified in terms of a dielectric and plates. It varies directly with forward current. When a
forward-biased PN-junction is suddenly reversed biased, a reverse current flow which is large
initially, but gradually decreases to the level of saturation current, I0.
28. State the principle of operation of an LED.
When a free electron from the higher energy level gets recombined with the hole, it
gives out the light output. Here, in case of LEDs, the supply of higher level electrons is
provided by the battery connection.
29. State any four advantages of LED.
They are small in size.
i. Light in weight.
ii. Mechanically rugged.
iii. Low operating temperature.
iv. Switch on time is very small.
v. Available in different colours.
vi. They have longer life compared to lamps.
vii. Linearity is better.
viii. Compatible with ICs
ix. Low cost
30. State some disadvantages of LED.
i. Output power gets affected by the temperature radiation.
ii. Quantum efficiency is low.
iii. Gets damaged due to over –voltage and over-current.
31. List the applications of LED.
5 33
i. They are used in various types of displays.

ii. They are used as source in opto-couplers.
iii. Used in infrared remote controls.
iv. Used as indicator lamps.
v. Used as indicators in measuring devices.
32. Describe tunnelling phenomenon?
When the doping level is increased the depletion region reduces, Due to thin depletion
region, even for very small forward bias many carriers penetrates through the junction and
appear at the other side. This phenomenon of penetration of carriers through the depletion region
is known as tunnelling.
33. What are the applications of tunnel diode?
Relaxation oscillator, storage device, pulse generator, high spedd switching networks
34. Define cut in voltage?
This is the voltage at which the forward bias curve abruptly increases from the smaller
value. The cut in voltage of Ge is 0.3V & for Si is 0.6V.
35. What are the advantages of SCR and TRIAC?
SCR performs rectification, inversion and regulation of power flow
TRIAC is a bidirectional switch and hence it can conduct in both the direction.
36. What are the advantages of SCR?
Switching speed is high No moving parts. So it gives noiseless operation at high
frequency It controls large current in the load by means of small gate current Occupies less
space.
37. What are the merits and demerits of SCR?
Merits of SCR
i. Very small amount of gate drive is required.
ii. SCRs with high voltage and current ratings are available.
iii. On state losses of SCR is less.
Demerits of SCR
i. Gate has no control, once SCR is turned on.
ii. External circuits are required for turning it off.
iii. Operating frequencies are low.
iv. Additional protection circuits are required.
38. What is photo diode?
The photo diode is a semiconductor p-n junction device whose region of operation is
limited to the reverse biased region. The figure below shows the symbol of photodiode
39. List out the advantages, disadvantages and applications of photo diode?
Advantages:
i. It can be used as variable resistance device.
ii. Highly sensitive to the light.
iii. The speed of operation is very high.
Disadvantages:
6 34
i. Temperature dependent dark current.

ii. Poor temperature stability.
iii. Current needs amplification for driving other circuits.
Applications:
i. Alarm system.
ii. Counting system.
40. Draw the V-I characteristics of the tunnel diode?
41. What are the advantages and Applications of the tunnel diode?
Advantages of tunnel diodes:
i. Environmental immunity i.e. peak point is not a function of temperature.
ii. Low cost.
iii. Low noise.
iv. Low power consumption.
v. High speed i.e. tunneling takes place very fast at the speed of light in the order of
nanoseconds
vi. Simplicity i.e. a tunnel diode can be used along with a d.c supply and a few passive
elements to obtain various application circuits.
Applications for tunnel diodes:
i. local oscillators for UHF television tuners
ii. Trigger circuits in oscilloscopes
iii. High speed counter circuits and very fast-rise time pulse generator circuits
iv. The tunnel diode can also be used as low-noise microwave amplifier.
42. Define varactor Diode? And list out the applications?
Varactor diode is a special type of diode which uses transition capacitance property i.e
voltage variable capacitance .These are also called as varicap, VVC (voltage variable
capacitance) or tuning diodes.
Applications:
i. Tuned circuits.
ii. FM modulators
iii. Automatic frequency control devices
iv. Adjustable band pass filters
v. Parametric amplifiers
vi. Television receivers.
7 35
UNIT-1 PART-B Questions (10 Marks):

1. (a) Derive diode current equation. 6M
(b) A silicon diode has a saturation current of 7.5 μA at room temperature 300 K. Calculate the
saturation current at 400 K. 4M (Nov/Dec-2016)
2. Explain construction and operation of UJT & SCR with necessary diagrams. 10M (Nov/Dec-2016)
3. (a) With neat diagrams, explain the operation of p-n junction diode considering different biasing
conditions. 6M
(b) Illustrate V-I characteristics of p-n junction diode. 4M (Nov/Dec-2017)
4. Discuss the operation and characteristics of the following: (Nov/Dec-2017)
(a) SCR 5M
(b) UJT 5M
5. (a) Give diode current equation. Mention any two applications of a diode. 5M
(b) Explain the operation of LCD. Mention its applications. 5M (June-2017)
6. (a) Discuss about V-I characteristics of tunnel diode with help of Fermi level diagram. 6M
(b) Discuss diode capacitances with the help of equations? 4M (June-2017)
7. (a) Compare the characteristics of PN junction diode, Zener diode and Tunnel diode. 6M
(b) For a Ge diode, the I0 = 2𝜇𝐴 and the voltage of 0.26 V is applied. Calculate the forward and
reverse dynamic resistance values at room temperature. 4M (Nov/Dec-2018)
8. Explain semi-conductors, insulators and metals classification using energy band diagrams. 10M
(Nov/Dec-2018)
9. With a neat diagram, explain the energy band diagram of PN junction diode. 10M (June-2018)
10. Explain the construction, operation and characteristics of Tunnel diode. 10M (June-2015&2018)
11. What is Fermi level? By indicating the position of Fermi level in intrinsic, N-type and P-type
semiconductor, explain its significance in semiconductors? 10M (Dec-2015)
12. Draw the basic structure and equivalent circuit of UJT, explain how the UJT can be used as
negative-resistance device with the aid of static characteristics. 10M (Dec-2015)
13. Describe the following briefly:
(a) Principle of operation of a Photodiode 5M
(b) Energy band structure and V-I characteristics of a Tunnel diode. 5M (Dec-2015)
13. Draw and explain the energy band diagrams for extrinsic semiconductor. 10M (June-2015)
14. Sketch and curve of photodiode current as a function of the position of a narrow light source form
the junction. Explain the shape of the curve. 10M (June-2015)
15. Sketch and explain the volt-ampere characteristics of a tunnel diode. Indicate the negative resistance
portion. 10M (Dec-2014)
16. (a) Explain the construction and working of photo diode. 5M
(b) Explain Schottky diode with necessary sketches. 5M (Dec-2014)
17. (a)Discuss PN diode VI characteristics & temperature dependence of PN diode VI characteristics
with neat sketch. 6M
(b) With the help of necessary equations, explain the terms Drift Current and Diffusion Current. 4M
8 36
18. (a) Discuss about zener diode and explain its characteristics & operation as voltage regulator. 6M
(b) The voltage across a silicon diode at room temperature is 0.7 volts when 2 mA current flows
through it. If the voltage increases to 0.75 volts, calculate the diode current. 4M
19. (a) Calculate the factor by which the current will increase in silicon diode operating at a forward
voltage of 0.4 volts, when the temperature is raised from 250C to 1500C. 5M
(b) A PN junction silicon diode has a reverse saturation current of 30 µA at a room
Temperature of 1250 C. At the same temperature find the dynamic resistance for
0.2V bias in forward and reverse direction. 5M
9 37
UNIT- II: - RECTIFIERS AND FILTERS
Block Diagram of D.C Power Supply

The block diagram of d.c power supply is shown in
It consists of a transformer, rectifier, filter and regulator circuits.

Transformer
The transformer step-up or step-down the input voltage into required voltage, and it
also isolates the rectifier unit from power line and reduces the electrical shock.
Rectifier
A rectifier is a device which converts a.c voltage into pulsating d.c voltage using one or
more PN-junction diodes.
*Note: The rectifier is the heart of d.c power supply.
Filter
The output of rectifier is not pure d.c. It contains both d.c components and a.c
components (a part of a.c).
A filter is a circuit, which removes the ripples (or unwanted a.c components) present in
the rectifier output.
Regulator
It is a circuit, which maintains output voltage constant even if the input voltage or load
current varies.
Types of Rectifiers
1. Rectifier circuits are basically of two types depending on the alternating voltage they
take as input. They are:
a) Single phase rectifiers
b) Poly phase rectifiers
2. Rectifiers may be classified into two categories depending upon the period of
conduction. They are:
a) Half waver rectifier
b) Full wave rectifier
3. Full wave rectifier may further be classified into two categories depending upon nature
of the circuit connection. They are:
c) Centre tap full wave rectifier
d) Bridge type full wave rectifier
C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page3829

PN-Junction Half Wave Rectifier

Circuit Details
A single phase half wave rectifier circuit is shown in fig. It consists of a transformer, a
diode and a load resistor RL.
The step down transformer reduces the available a.c voltage into required level of
smaller a.c voltage. The diode D and the load resistor RL are in series with secondary of the
transformer.
The primary of the transformer is connected to the single phase a.c supply. An a.c
voltage is induced in the secondary of transformer by mutual induction. The voltage across
the secondary is given by vin  Vm sin ωt. Figure shows how this voltage varies with time. It
has alternate positive and negative half cycles. Voltage Vm is the peak value of this
alternating voltage.
Working
Case - I
During positive half cycle of a.c input voltage, terminal A is positive with respect to
terminal B. The diode D is forward biased and it acts as closed circuit. Sinusoidal current i L
flows through the load resistor RL in clock wise direction as shown in fig.
Case - II
During negative half cycle of the input voltage, terminal B is positive with respect to
terminal A. The diode D is revere biased and it acts as open circuit. No current flows
through load resistor RL.
Thus we get a unidirectional current through RL which flows in the form of half
sinusoidal pulses. The load voltage being the product of load current and load resistance will
also be in the form of half sinusoidal pulses. The input and output waveforms are shown in
fig

39
Mathematical Analysis
Let the input voltage applied to the PN-junction diode is given by,
vin  Vm sin ωt  Vm sin θ θ  ωt
The instantaneous load current iL through RL is given by,
Vm
i L  sin θ  I m sin θ for 0θπ
Rf  R L
iL  0 for π  θ  2π
Where Im = Peak value of load current = Vm

Rf  RL
Rf = Forward resistance of diode
and RL = Load resistance
D.C or Average value of Output Current
The average d.c current over one complete cycle is given by,
2π
1
Idc 
2π i
0
L
dθ
π 2π 

 1  i L  i L dθ
2π  0 

π
π 
 2π1  I sin θdθ 
 0
m 
 m  cosθ 
I π
2π 0

Im
 cosπ  cos0
2π

Im
 1 1
2π
 Idc  Iavg  Im
π
Similarly the d.c or average value of output voltage across the load is given by,
Im
Vdc  Vavg  Idc R L  R
L
π
V R
 V m L
π Rf  R L
dc
V 1
 πm  R 
1  
f
 R L 
 R 
 V V V  f 1
dc avg  m  
π  RL 

40

R.M.S value or Effective value of Output Current
By the definition, the r.m.s value of load current is given by,
 1 2π 2
Irms  iL dθ
2π 0
1 π 2 2π

 i L dθ   iL dθ
2

2π 0
 π 
 π
1

2π 0 I m sin θ  dθ
2


Im2 π 2
 sin θdθ
 2π 0
 2 π
I  1  cos 2θ 
dθ
 m 
 2π 0  2 

Im 2 π
π


4π  
1dθ  cos 2θ dθ 
 
 0 0 

 π 

2
 I m θ π  cos 2θdθ  0 
 

0
4π  0 

 Irms  Im
2

Rectifier Efficiency
The rectifier efficiency is defined as the ratio of d.c output power to the a.c input power.
D.C output power Pdc
 η P
A.C input power ac
2
2 I R
The d.c output power, Pdc  Idc R L  m L
π2 2
2 R  R   m R  R 
I
The a.c input power, Pac  Irms
f L f L
4
The rectifier efficiency is given by,
 I 2R 
 m L 
 π 2 
P
η  Pdc   2 

I m R  R 
ac
L 
 4
f

4 RL
 2
π R f  RL
0.406
η   R 
1

f 

 R L 

41

The percentage rectifier efficiency is given by,
40.6 %
%η   R 
1 f 
  R L 
*Note: 
1. If R f  RL the rectifier efficiency is maximum.
Rf
2. The theoretical maximum rectifier efficiency is obtained when  0 and is equal to
RL
40.6%.
Ripple factor
The output of rectifier is not pure d.c. It contains both d.c components and a.c
components (a part of a.c). A measure of such a.c components (ripples) present in the
rectifier output is given by ripple factor γ .
*Note: Smaller the ripple factor closer is the output to a pure d.c.
a) Definition
Mathematically ripple factor is defined as the ratio of r.m.s value of the a.c component
to the average or d.c component of the output.
R.M.Svalue of a.ccomponent of output
 Ripple factor  Average or d.ccomponent of output
Vr rms I r rms
or γ 
Vdc Idc
b) Expression for Ripple factor

Let Ir rms = R.M.S value of a.c component present in the output
Idc = D.C component present in the output
Irms = R.M.S value of total output
It can be noted that the output current is composed of a.c component as well as d.c
component.
 Irms  Idc  I r rms
2 2 2
I r rms  Irms  Idc

2 2 2
or
Dividing by Idc 2 on both sides, we get,
I
I 2   rms 2 1
 r rms   
 
 I    Idc 
dc
 2
 I 
 Ripple factor, γ   rms  1
  Idc 
*Note: This is the general expression for ripple factor and can be used for any rectifier
circuit.
c) Ripple factor for Half Wave Rectifier
For a half wave rectifier, we have,
Irms  Im and Idc  Im
2 π

 I 2
γ   rms  1
  
 I dc  

 2
  Im  
  2
 π 
 γ  2  1     1  1.467
 Im   2 
 
 π 
 γ  1.21
This indicates that the ripple contents in the output are 1.21 times the d.c component i.e.
121% of d.c component.
Peak Inverse Voltage (PIV)
It is defined as the maximum voltage across the diode in the reverse direction.
or
It is the reverse voltage that a diode can withstand without destroying the junction,
during the non conducting period.
In a half wave rectifier, the reverse voltage across the diode during non-conducting
period equals the maximum value of transformer secondary voltage Vm.
 PIV of diode = Vm = Maximum value of transformer secondary voltage.
*Note: The diode must be selected based on PIV rating and circuit specifications.
Advantages of Half Wave Rectifier
1. It is simple and low cost circuit.
2. It requires only one diode.
Disadvantages of Half Wave Rectifier
1. Low rectification efficiency.
2. The ripple factor of half wave rectifier is 1.21, which is quite high. The output contains
lot of a.c components. Therefore an elaborate filtering is required to produce steady
direct current.
3. D.C saturation of transformer core, which results when the current in the secondary
side of transformer flows in the same direction, leads to hysteresis losses and
harmonics in the output.
4. The a.c supply delivers power only half the time. Therefore the output is low.
Centre tap Full Wave Rectifier
Circuit Details
The centre tap full wave rectifier circuit is shown in fig. In order to rectify both the half
cycles of a.c input, two diodes are used in this circuit. A centre tapped secondary winding
AB is used with two diodes such that, diode D1 utilises the a.c voltage appearing across the
upper half of secondary winding 0A for rectification while diode D2 uses the lower half
winding 0B.
*Note:
1. The full wave rectifier conducts during both positive and negative half cycles of input
supply.
2. Each diode uses one half cycle of input a.c voltage.
3. In this circuit the centre of the transformer secondary is taken as reference point
(earth).

Working
Case - I
During positive half cycle of a.c input voltage, terminal A is positive with respect to the
earth and terminal B is negative. This makes the diode D1 forwarded biased and diode D2
reverse biased. Therefore diode D1 conducts and diode D2 non-conducting. Current takes the
path A  D1  RL  0  A. In other words the conventional current flows through diode D1,
load resistor RL and upper half of secondary winding 0A as shown by the dotted arrows.
Case - II
During negative half cycle of a.c input voltage terminal A is negative with respect to
earth and terminal B is positive. The diode D2 conducts and D1 does not. The current takes
the path B D2 RL  0 B. In other words the conventional current flows through diode
D2, load resistor RL and lower half of secondary winding 0B as shown by the solid arrows.
Thus the current in the load resistor RL is in the same direction for both half cycles of
input a.c voltage. Therefore d.c is obtained across the load resistor RL.
Let the input voltage vin is given by,
vin  Vmsin ωt  Vmsin θ
The instantaneous current iL1 through diode D1 and load resistor RL is given by,
iL1  Imsin θ for 0  θ  π

35
iL1  0 for π  θ  2π
Similarly the instantaneous current iL2 through diode D2 and load resistor RL is given by,
iL2  0 for 0  θ  π
iL2  Imsin θ for π  θ  2π
The total current flowing through RL is the sum of two currents iL1 and iL2 i.e.
iL  iL1  iL2
D.C or Average value of Output Current
The average d.c current over one half cycle is given by,
π
1
Idc  π i Ldθ
0

1 
π
  I m sin θ dθ
π  0 


Im
 cos θπ
π 0

Im
 cos π  cos 0
π

Im
 1 1
π
 Idc  Iavg  2Im
π
Similarly the d.c or average value of output voltage across the load is given by,
Vdc  Vavg  IdcR L  2Im R
L
2V R π
 Vdc  m L
π Rf  RL
2V 1
 πm  R 
1

f 

 R 
 R 
L
 V V 2V  f 1
dc avg  m  
π  RL 
R.M.S value or Effective value of Output Current
By the definition, the r.m.s value of load current is given by,
1π 2
Irms  i L dθ
π0
π
 1 I m sin θ 2 dθ
π 0
Im2 π 2
  sin θdθ
π 0
2 π
I 1 cos 2θ dθ
  
π 0 
m
2 

36


I
2
π
π

 m
2π  
1dθ  cos 2θ dθ 
 
 0 0 
I m θ π
2
 0
2π
Im
 Irms 
2
Rectifier Efficiency
The d.c output power,
R  
2Im 2
P I
2
R 4Im 2
L
 RL
dc dc L
 π 
2
π
The a.c input power, 
 I 2
P I
2
R f  R L    m  R f  R L   Im R f  R L 
2
ac rms  
 2  2
Therefore the rectifier efficiency is given by,
 4I 2 
 m R L 
 2 
η P  π
Pac   2 
dc
8 RL
  π2 R  R L
I m R  R  f
 2 L 
 f

 η  0.8106
 R f 
1 
 R L 
The percentage rectifier efficiency is given by,
 %η  81.6 %
 R f 
1 
 R L 
*Note: The theoretical maximum efficiency is obtained when (Rf/RL) = 0 and is equal to
81.06%
Ripple factor for Full Wave Rectifier
For full wave rectifier,
I
2Im
Irms 
m
and I 
2 dc
π
2
 Im  2
 I 
 γ   rms  1   2  1

 Idc   2Im 
  π 
 

2
 π 
 1  π 1  0.233
2
 
 2 2  8
 γ  0.48
Peak Inverse Voltage (PIV)

Peak inverse voltage is the maximum possible voltage across a diode when it is reverse
biased. Consider that diode D1 is in forward biased i.e. conducting and diode D2 is reverse
46 37
biased i.e. non-conducting. In this case a voltage Vm is developed across the load resistor RL.
Now the voltage across the diode D2 is the sum of the voltage across load resistor RL and
voltage across the lower half of transformer secondary Vm. hence PIV of diode D2 = Vm + Vm
= 2 Vm. Similarly PIV of diode D1 is 2Vm.
Advantages of Centre tap Full Wave Rectifier
1. The d.c load current in case of full wave rectifier is twice to that in half wave rectifier.
2. Rectification efficiency of a full wave rectifier is twice to that of half wave rectifier.
3. Lower ripple factor.
4. Easy filtering due to high ripple frequency (2f).
5. The d.c saturation of the core is avoided as current flows through the two halves of the
centre tapped secondary of the power transformer in opposite directions.
Disadvantages Centre tap Full Wave Rectifier
1. For the same d.c output voltage, the transformer secondary voltage required in full
wave rectifier is twice that of required for half wave rectifier.
2. The diodes used must have high peak inverse voltage.
3. It is difficult to locate the centre tap on the secondary winding.
Bridge type Full Wave Rectifier
Circuit Details
A bridge type full wave rectifier circuit is shown in fig. It is so named because four
diodes are connected in Wheatstone bridge form. To one diagonal of the bridge, the a.c
voltage is applied through a transformer and the rectified d.c voltage is taken across the other
diagonal of the bridge. The main advantage of this is that it does not require a centre tap on
the secondary winding of the transformer.
*Note:
1. To overcome few drawbacks of centre tap full wave rectifier, a bridge type full wave
rectifier is used.
2. The most commonly used rectifier for electronic d.c power supply is bridge type full
wave rectifier.
Working
Case - I
During positive half cycle of a.c input voltage, terminal A is positive with respect to B.
The diodes D1 and D3 are forward biased and D2 and D4 are reverse biased. This makes the
diodes D1 and D3 are conducting and the diodes D2 and D4 are non conducting. The current
flows through the secondary winding, diode D1, load resistor RL and diode D3 as shown in
fig. 1.9(a).
Case - II
During negative half cycle of a.c input voltage, terminal B is positive with respect to A.
The diodes D2 and D4 are forward biased and D1 and D3 are reverse biased. This makes the
diodes D2 and D4 are conducting and the diodes D1 and D3 are non conducting. The current

flows through the secondary winding, diode D2, load resistor RL and diode D4 as shown in
fig. 1.9(a).
Thus the current in the load resistor RL is in the same direction for both half cycles of
input a.c voltage. Therefore d.c is obtained across the load resistor RL.
Fig. 1.9(b)
*Note: The output wave forms are exactly the same as that obtained for the centre tap full
wave rectifier circuit as shown in fig. 1.9(b).
The derivations for bridge type full wave rectifier is same as that of centre tap full wave
rectifier circuit, except
Vm
Im 
2Rf  RL
So the only modification is that instead of Rf, which is forward resistance of each diode,
the term 2Rf appears in the denominator.
The remaining expressions are identical to those derived for centre tap full wave
rectifier and reproduced for the convenience of the reader.
Table: 1
Sl.No. Parameters Expressions
1. D.C or average value of 2Im

I 
output current dc
π
2. R.M.S or effective value of Im
I rms 
output current 2

48
3. A.C input power 4I m2

Pac  RL
π 2
2
4. D.C output power
Pac 
I
m 2R  RL

f
2
5. Rectifier efficiency 0.8106

η   2R 
1 R 
f
 L 
6. Ripple factor γ  0.48
7. PIV of each diode Vm
Advantages of Bridge type Full Wave Rectifier

1. Transformer with centre tap in secondary is not required. This leads to reduction in
cost and weight.
2. PIV rating is one half of the centre tap diode, so smaller and cheaper diodes can be
used.
Disadvantage of Bridge type Full Wave Rectifier
1. The only disadvantage of bridge rectifier is it requires four diodes as compared to
centre tap full wave rectifier.
Bridge type Full Wave Rectifier
Sl.No. Parameters Half wave Centre tap Bridge type full

rectifier full wave wave rectifier
rectifier
1. Idc Im 2Im 2Im
π π π
2. Vdc Vm 2Vm 2Vm

π π π
3. Irms Im Im Im
2 2 2
4. %Efficiency 40.6% 81.06% 81.06%
5. Ripple Factor 1.21 0.482 0.482
6. Ripple f 2f 2f
frequency
7. Peak inverse Vm 2Vm Vm

Voltage
8. Voltage Rf Rf 2Rf
regulation RL RL RL

40
9. Number of 1 2 4
diodes
10. Necessity of No Yes No
transformer
11. Cost Low Costly Less costly
12. Use Simple Used in high

Used in low
circuits voltage, low
voltage, high
current d.c
current d.c
power supply
power
circuits.
supply
circuits.
Need for a Filter Circuit in power supply

The output of a rectifier consists of a d.c component and an a.c component (also known
as ripple). The a.c component is undesirable and must be kept away from the load. To do so
a filter circuit is used which removes the a.c component and allows only the d.c component to
reach the load.
A filter circuit is a device which removes the a.c component of rectifier output but
allows the d.c component to reach the load.
Obviously, a filter circuit should be connected between the rectifier and the load as
shown in fig. A filter circuit is generally a combination of inductors (L) and capacitors(C).
The filtering action of L and C depends upon the basic electrical properties.
*Note:
1. The main function of filter is to minimize the ripple content in the rectifier output.
2. The ideal inductor acts as short circuit for d.c, therefore it cannot be placed in shunt
across the load; otherwise the d.c will be shorted. Hence, in a filter circuit the inductor
is always connected in series with the load.
3. Similarly, the ideal capacitor acts as open circuit for d.c, i.e. it blocks d.c, and
therefore it cannot be connected in series with the load. It is always connected in
parallel with the load.
4. The inductor used in filter circuits is also called choke.
5. The filter circuit is also known as smoothing circuit.

41
Shunt Capacitor Filter

Types of Filter Circuits
The commonly used filter circuits in the power supply circuits are listed below.
1. Shunt capacitor filter
2. Series inductor filter
3. L-section (LC) or inductor input filter
4. π -section (CLC) or capacitor input filter
5. CRC filter
Circuit Details
Fig. shows a typical capacitor filter circuit. Fig. shows a full wave rectifier with a
capacitor filter. The filter uses a single capacitor connected in parallel with the load resistor
RL. In order to minimize the ripple in the output, the capacitor C used in the filter circuit is
quite large of the order of tens of microfarads (F).
*Note: Electrolyte capacitor which is polarized is generally used in filter circuits.
Working
Immediately when power is turned on, the capacitor C gets charged through forward
biased diode D1 to Vm, during first quarter cycle of the rectified output voltage.
π
In the next quarter cycle from to π , the input voltage falls below the capacitor voltage
2
(Vm). As a result the diode D1 becomes reverse biased and stops conducting. So the
capacitor starts discharging through RL and supplies the load current. It discharges to point B
as shown in fig.
3π
At point B, lying in the quarter cycle π to of the rectified output voltage, the input
2
voltage exceeds capacitor voltage, making D2 forward biased. This charges capacitor back to
Vm at point C.
The time required by capacitor C to charge to Vm is quite small and only for this period,
diode D2 is conducting. Again at point C, diode D2 stops conducting and capacitor starts
discharging through RL and supplies the load current. It discharges to point D shown in fig.
At this point the diode D1 conducts to charge capacitor back to Vm.

51 42
This process is repeated again and again and the output waveform becomes ABCD. Fig
shows the load voltage variation with a.c voltage. It is obvious from the fig. that nearly
constant d.c voltage appears across RL at all times.
*Note:
1. The discharging time constant (CRL) is large usually 100 times more than charging
time, hence the condenser does not have sufficient time to discharge appreciable. Due
to this fact the voltage of condenser C decreases slightly.
2. The diodes are not conducting for the entire half cycle. The diode currents are shown in
fig.
3. When the capacitor is discharging through the load resistor RL, both the diodes are
non-conducting. The capacitor supplies the load current.
Series Inductor Filter
Circuit Details
Fig. shows a typical series inductor filter circuit. Fig. shows a full wave rectifier with a
series inductor filter. The filter uses single inductor connected in series with the load. An
inductor has the fundamental property of opposing any change in current flowing through it.
This property is used in the series inductor filter.

Working
Whenever an a.c flows through an inductor, self induced e.m.f or back e.m.f is induced
in the inductor which prevents the very cause of its production i.e., alternating current to flow
through it according to Lenz‘s law. As a result the inductor permits d.c to flow through it and
prevents a.c.
The working of series inductor filter can be understood in another way also as
follows:
1. For d.c and low frequency ripple components, XL is low, thus it permits d.c and
low frequency components.
2. For high frequency ripple components, XL is very high, thus it completely blocks
it.
Therefore the output of inductor contains d.c and low frequency components.
Fig shows the output waveform obtained by using series inductor filter or choke filter
with full wave rectifier.
*Note:
1. This filter can only be used with a full wave rectifier since it requires current to flow at
all times.
2. The operation of a series inductor filter depends upon the current through it. Higher
the current flowing through it, the better is its filtering action.
3. The inductor filter is suitable for heavy loads (RL=low).
L-S ection (LC) or Choke Input Filter
Circuit Details
We have seen that series inductor filter and shunt capacitor filter are not much efficient
to provide low ripple at all loads. The shunt capacitor filter has low ripple at small loads
while series inductor filter has low ripple at heavy loads. A combination of these two filters
may be selected to make the ripple independent of load resistor R L. The resulting filter is
called L-section or choke input filter. This name is due to the fact that the inductor and
capacitor are connected as an inverted L.
Fig shows a typical choke input filter circuit. It consists of a choke L connected in
series with the rectifier output and a filter capacitor C across the load. A full wave rectifier
with choke input filter is shown in fig. 1.13(b). Only a single filter section is shown, but
several identical sections are often used to reduce the pulsations effectively as possible.
*Note: The a.c reactance of the capacitor is made sufficiently small compared with R L so that
essentially all of the alternating current passes through the capacitor and none through RL.
The ripple factor is thus reduced very much.

5344
Working
The pulsating output of the rectifier is applied across terminals 1 and 2 of the filter
circuit. As discussed before, the pulsating output of rectifier contains a.c and d.c
components. The choke offers high opposition to the passage of a.c component but negligible
opposition to the d.c component. The result is that most of the a.c component appears across
the choke while whole of d.c component passes through the choke on its way to load. This
results in the reduced pulsations at terminal 3.
At terminal 3, the rectifier output contains d.c component and remaining part of a.c
component. Since the capacitor C is connected across the load, it bypasses the a.c component
but prevents the d.c component to flow through it. Therefore, only d.c component reaches the
load. In this way, the filter circuit has filtered out the a.c component from the rectifier
output, allowing d.c component to reach the load.
Bleeder Resister
A bleeder resistor is a resistor placed in parallel with a high voltage supply for the
purpose of discharging the energy stored in the filter capacitors or other components that
store electrical energy when the equipment is turned OFF.
A bleeder resistor is essential for the power supply circuits that include the choke filters
for smoothening action. Since the inductor operations depends on the current there should be
always a flow of minimum current through the inductor for better functioning of filtering
action.

54
Otherwise a large back e.m.f is developed across the choke, which may be in excess of
PIV rating of diodes and/or maximum voltage rating of the capacitor C. Thus this back e.m.f
is harmful to the diodes and capacitor. To eliminate the back e.m.f developed across the
choke, the current through it must be continuous. This is achieved by connecting a bleeder
resistor across the output terminals.
Advantages of Bleeder Resistor
1. It improves the filtering action by maintaining a minimum current through the choke.
2. It improves the voltage regulation of the supply by acting as preload on the supply.
3. It provides the safety to the persons handling the equipments, (when the supply is
switched OFF, the capacitor retains its charge for some time, this voltage may be
dangerous for people working with equipment) by acting as discharging path for
capacitors.
-section (CLC) or Capacitor Input Filter
Circuit Details
Fig shows a typical capacitor input filter or π  filter . It consists of a filter capacitor C1
connected across the rectifier output, a choke L in series and another filter capacitor C 2
connected across the load. Only one filter section is shown but several identical sections are
often used to improve the smoothing action.
Working
The pulsating output from the rectifier is applied across the input terminals (i.e.
terminal 1 and 2) of the filter. The filtering action of the three components viz C1, L and C2
of this filter is described below:
a. The filter capacitor C1 offers low reactance to a.c component of rectifier output while it
offers infinite reactance to the d.c component. Therefore, capacitor C1 bypasses an
appreciable amount of a.c component while the d.c component continues its journey to
the choke L.
b. The choke L offers high reactance to the a.c component but it offers almost zero
reactance to the d.c component. Therefore, it allows the d.c component to flow through
it, and blocks the a.c component which could not be by-passed by the capacitor C1.
c. The filter capacitor C2 bypasses the a.c component which could not be by-passed by
inductor L. Therefore, only d.c component appears across the load.

55
CRC Filter
The disadvantages of -section filter are the cost, weight, size and external field
produced by the series inductor. These disadvantages can be overcome by replacing the
series inductor with a series resistor of 100 to 200  . It is then called capacitor-input RC
filter or CRC filter.
Fig.shows a CRC filter connected between the output of rectifier and the load resistor.
By deliberate design, R is much greater than XC at the ripple frequency. Therefore the ripple
is dropped across the series resistance instead of across the load resistor. Typically, R is at
least 10 times greater than XC. This means that each section attenuates the ripple by a factor
of at least 10. The function of capacitor is same as in CLC filter.
Advantages
• Low cost
• Small size
• Less weight
• No external field due to series inductor
Disadvantages
• The main disadvantage of the CRC filter is the loss of d.c voltage across the R.
This means that the RC is suitable only for light loads.
• The voltage regulation becomes poorer.
• This circuit requires adequate ventilation to conduct away the heat produced in
the resistor.

56
UNIT-II
Solved Problems:
1. A diode whose internal resistance is 20Ω is to supply power to a 100Ω load from
110V(rms) source pf supply. Calculate (a) peak load current (b) the dc load current
(c) the ac load current (d) the percentage regulation from no load to fullload.
Solution:
Given a half-wave rectifiercircuit

Rf=20Ω,RL=100Ω
Given an ac source with rms voltage of 110V, therefore the maximum amplitude of
sinusoidal input is given by
Vm=√2 Vrms= √2 x 110=155.56V
(a) Peakloadcurrent : Im= Vm/Rf+RL
155.56= 1.29A
Im
Im 120
(b)The dc loadcurrent: I =0.41A
dc
(c) The ac load current : Irms = Im/2=1.29/2 =0.645A.
(d) Vno-load = Vm/π = 155.56/π = 49.51V
Vm
(e) Vfull-load = I R
dc f
= 155.56/π – 0.41X20Ω = 41.26 V
V V
no load fullload
%Regulation = 100 =19.97%
V full load
2. A diode has an internal resistance of 20Ω and 1000Ω load from 110V(rms) source
pf supply. Calculate (a) the efficiency of rectification (b) the percentage regulation
from no load to fullload.
Solution:
Given a half-wave rectifier circuit
Rf=20Ω, RL=1000Ω
Given an ac source with rms voltage of 110V, therefore the maximum amplitude
1 57
of sinusoidal input is given by

Vm= 2 Vrms= 2 x 110 = 155.56V.
(a) %Efficiency( )=
3 . A 230V, 60 Hz voltage is applied to the primary of 5:1 step down center tapped
transformer used in a FWR having a load of 900 . If the diode resistance and secondary
coil resistance together has a resistance of 100 , determine:
a) DC voltage across theload
b) DC current flowing through theload
c) DC power delivered to theload
d) PIV across eachdiode
e) Ripple voltage andfrequency.
Given:
AC input – 230V,60Hz RL=900 RS + Rf =100
(a)
DC voltage across load = ?
Voltage secondary of transformer = 230/5 = 46 V.
Each of half = 23 volts,(rms); Vrms=23V; Vm = ? Vrms = Vmax (0.707)
(b) DC current IDC = Imax(0.636)

= 32.53 (0.636) = 20.69 mA.
VRL = IDC.RL = 20.69 x 10-3 x 900 = 18.62 volts
(c) DC power Pdc = Vdc. Idc = 18.62 x 20.69 x 10-3 = 3.85m.w.
(d) PIV across each diode = Vmax x 2 = 32.53 x 2 = 65.06volts
(e) Ripple voltage =?
Ripple factor =Ripple Voltage/Load Voltage
V = .VRL = 0.483 x 18.62 = 8.99volts
Ripple frequency = 2 x Input source frequency
=2 x 60=120 Hz
2 58
4. Determine the peak and rms voltages on the secondary of a transformer connected across
a bridge rectifier to provide a no load dc voltage of 9 V. If the secondary winding resistance
is 3 Ω and dynamic resistance of each diode is 1 Ω, determine the dc output across a load
resistance of 100 Ω and 1 K. Also determine the regulation.
Solution:
5. A 220 V, 60 Hz voltage is applied to a centre tapped step-down transformer of 22: 1 with a

load of 1 K connected across the output of two-diode full-wave rectifier. Assume diodes to be
ideal. If the resistance of half-secondary winding is 0.5 Ω, determine the (a) peak, rms and
dc voltages, (b) peak, rms and dc currents, (c) dc power delivered to the load, (d) VA rating
of the transformer secondary, (e) ac input to transformer assuming it to be 80% efficient, (f)
ac ripple voltage across the load and its frequency, (g) How much is the PIVof each diode if
the circuit is changed to a bridge rectifier using the full secondary winding of the same
transformer? (h) How much are the peak, rms, dc voltages?
Solution:
(a) Vm (between full secondary) = 10√2 = 14.14 V
vrms (full secondary) = 10 V, Vm (half secondary) = 7.07 V
(c)DC power delivered the load = I2DCRL = (4.495 mA)21 K = 20.2 mW

(d) VA rating of the transformer can be found out using TUF.
3 59
(f)As the ripple voltage under consideration would be the second harmonics because the magnitude
of higher harmonics will become much less than it. Hence, the ac ripple voltage is expressed as
UNIT-II PART-A (2 MARKS QUESTIONS WITH ANSWERS):

1. What are the advantages of bridge rectifier over center tapped counterpart?
• The ripple factor and efficiency are same as full wave rectifier.
• The bulky centre tapped transformer is not required.
2. Define and explain peak inverse voltage (PIV)?

Peak inverse voltage is the maximum reverse voltage that can be applied to the PN
junction without damage to the junction. If the reverse voltage across the junction exceeds to
its peak inverse voltage, the junction may be destroyed due to excessive heat.
3. Define ripple factor?
Ripple factor can be defined as the variation of the amplitude of DC (Direct
current) due to improper filtering of AC power supply.
4. Define TUF of a rectifier.
Most of the rectifier circuits make use of transformer whose secondary feeds the AC
power. The transformer rating is necessary to design a power supply. Transformer utilization
factor (TF) is defined as the ratio of DC power delivered to the load to the AC power rating of
transformer secondary.
5. Give the advantages and disadvantages of HWR.
Half Wave Rectifier (HWR)
Advantages
• Simple circuit.
4 60
• Low cost.
Disadvantages.
• Rectification efficiency is low (40.6%).
• Very high amount of ripple (γ = 1.21)
• Low TUF (0.287)
• Saturation of transformer core occurs
6. What is the need for a filter in rectifier?
The output of a rectifier is pulsating and contains a steady DC component with

undesirable ripples. If such pulsating DC is given to the electronic circuits, it produces
disturbances and other interferences. Hence ripples have to be kept far from the load. This is
achieved by use of a filter circuit.
7. What is a rectifier-filter? List the different types of filters.
A filter circuit is a device which removes the AC component but allows the DC
components of the rectifier to reach the load.
Ripples can be removed by one of the following filtering methods.
i. A capacitor, in parallel to the load, provides a easier bypass for the ripples due
to low impedance to AC at ripple frequency and leave the DC appear across the
load.
ii. An inductor, in series with the load, prevents the passage of ripples due to high
impedance at ripple frequency, while allowing the DC due to low resistance to
DC.
iii. Various combinations of capacitor and inductor, such has L-section filter, π-
section filter, etc., which make use of both the properties depicted above.
Types of filter circuits: Depending upon the components used in the filter circuits and the
way they are connected, the filter circuits are classified as:
i. Shunt capacitor filter
ii. Series inductor filter
iii. Choke-input (LC) filter
iv. Capacitor-input (π) filter.
8. List some advantages and disadvantages of CLC filters.
• It can be used with both HWRs and FWRs.
• More output voltage is obtained.
• Output is almost pure DC.
9. What is a Rectifier?
A rectifier is a wave shaping circuit that converts ac voltage to dc voltage.
10. What is a dc power supply? What are its basic elements?
The dc power supply converts the ac voltage. It consists of the following
elements: The transformer, rectifier, filter and voltage regulator.
11. Define Voltage regulation?
The degree to which the dc output voltage changes under load condition is measured
by voltage regulation. It is defined as the variation of the dc output voltage as a function of
the dc current.
% Regulation= (Vno-load-Vfull-load)/Vfull-load
12. Define efficiency of a rectifier?
The efficiency of a rectifier is defined by the ratio of dc power supplied to the load
5
61
to total input ac power.

13. What are the advantages and disadvantages of FWR?
• Ripple factor = 0.482 (against 1.21 for HWR)
• Rectification efficiency is 0.812 (against 0.405 for HWR)
• Better TUF (secondary) is 0.574 (0.287 for HWR)
• No core saturation problem
Disadvantages:
• Requires centre tapped transformer.
14. Comparisons of filters
• A capacitor filter provides Vm volts at less load current. But regulation is poor.
• An Inductor filter gives high ripple voltage for low load currents. It is used for high load
currents
• L – Section filter gives a ripple factor independent of load current. Voltage
Regulation can be improved by use of bleeder resistance
• Multiple L – Section filter or π filters give much less ripple than the single L –Section
Filter.
15. What are the advantages and disadvantages of C filter?
Advantages
• Output voltage is large
• At small load currents smoothing is good i.e. low ripple
Disadvantages
• Ripple increases with increase of load current
• Poor regulation
• The current through diode flows in pulses of high value
16. Compare HWR, FWR and Bridge rectifier.

HWR FWR Bridge Rectifer
Number of diodes 1 2 4
No load dc output Vm/n 2Vm/n 2Vm/n
PIV Vm 2Vm Vm
Ripple factor 1.21 0.482 0.482
TUF 0.287 0.693 0.812
Ratio of rectification 0.406 0.812 0.812
Ripple frequency F 2f 2f
UNIT –II PART-B (10 Marks Questions):

1. Explain construction and operation of a bridge rectifier and derive its expressions. 10M (Nov/Dec-
2016)
2. (a) Discuss full wave rectifier with L-section filter. 5M
(b)Design a filter for full wave rectifier circuit with LC filter to provide an output voltage of 10 V with
a load of 200 mA and the ripple is limited to 2%. 5M (Nov/Dec-2016)
3. (a) With the help of a neat circuit diagram, input and output waveforms, describe the operation of Half-
wave rectifier. 6M
(b) Derive the expressions for ripple factor and maximum efficiency of HWR. 4M (Nov/Dec-2017)
4. (a) Design a Full-wave center-tap rectifier with capacitor filter and then explain its operation. 6M
6
62
(b) Derive the expression for ripple factor of a Full-wave center-tap rectifier with capacitor filter and
then comment on the result. 4M (Nov/Dec-2017)
5. (a) A 50 Ω load resistance is connected across a half wave rectifier. The input supply voltage is 230 V
(rms) at 50 Hz Determine the DC output (average) voltage, peak-to-peak ripple in the output voltage
(Vp-p), and output ripple frequency (fr). 4M
(b) Explain full wave rectifier with capacitor filter and derive expression for capacitor. 6M (June-2017)
6. (a) In the full-wave rectifier circuit, the transformer has a turns ratio of 1:2. The transformer primary
winding is connected across an AC source of 230 V (rms), 50 Hz. The load resistor is 50 Ω. For this
circuit, determine the DC output voltage, peak-to-peak ripple in the output voltage, and output ripple
frequency. 4M
(b) Explain the working principle of Bridge rectifier with derivations. Differentiate with Full Wave
Rectifier. 6M (June-2017)
7. (a) Derive the expression for ripple factor for full wave rectifier with L-section filter. 6M
(b) Compare FWR and Bridge rectifier. 4M (Nov/Dec-2018)
8. (a) With the help of a neat diagram, explain about the half wave and full wave rectifiers. Also derive
the ripple factor and rectification efficiency. 7M
(b) Determine the rating of a transformer to deliver 125 watts of dc power to a load for the following:
(i) Half wave rectifier. (ii) Full wave rectifier. (iii) Bridge rectifier. 3M (Nov/Dec-2018)
9. With neat circuit diagram and waveforms, explain the working of full wave bridge rectifier with
capacitor filter. 10M (June-2018)
10. A 230 V, 50 Hz ac signal is given as input to a centre tapped full wave rectifier through a 5:1 step
down transformer. The load resistance is found to be 100 Ω. Determine the dc output voltage, peak
inverse voltage and rectification efficiency. 10M (June-2018)
11. (a) Compare the performance of inductive, L-section and π-section filters used with rectifiers? 5M
(b) In a FWR using an LC filter, L=10H, C=100µF, and RL=500Ω. Calculate Idc, Vdc, and ripple
factor for an input of Vi=30 Sin (100πt) V. 5M (Dec-2015)
12. Derive the ripple factor and efficiency for full wave rectifier with input capacitance. 10M (Dec-
2014)
13. Explain the working of bridge rectifier. Give the expressions for RMS current, PIV, ripple factor
and efficiency. 10M (June-2015)
14. (a) With circuit and necessary waveforms explain the operation of Bridge Rectifier. 5M
(b) In a Bridge rectifier, the transformer is connected to 220 volts, 60 Hz mains and turns Ratio
of the step down transformer is 11:1. Assuming the diodes to be ideal, find i) voltage across the
load ii) D.C current iii) PIV. 5M
7 63
UNIT- III: - TRANSISTOR CHARACTERISTICS: BJT & FET
3.1 INTRODUCTION
A bipolar junction transistor (BJT) is a three terminal device in which operation
depends on the interaction of both majority and minority carriers and hence the name bipolar.
The BJT is analogues to vacuum triode and is comparatively smaller in size. It is used as
amplifier and oscillator circuits, and as a switch in digital circuits. It has wide applications in
computers, satellites and other modern communication systems.
3.2 CONSTRUCTION OF BJT AND ITS SYMBOLS
The Bipolar Transistor basic construction consists of two PN-junctions producing
three connecting terminals with each terminal being given a name to identify it from the other
two. These three terminals are known and labelled as the Emitter ( E ), the Base ( B ) and the
Collector ( C ) respectively. There are two basic types of bipolar transistor construction, PNP
and NPN, which basically describes the physical arrangement of the P-type and N-type
semiconductor materials from which they are made.
Transistors are three terminal active devices made from different semiconductor
materials that can act as either an insulator or a conductor by the application of a small signal
voltage. The transistor's ability to change between these two states enables it to have two
basic functions: "switching" (digital electronics) or "amplification" (analogue electronics).
Then bipolar transistors have the ability to operate within three different regions:
1. Active Region - the transistor operates as an amplifier and Ic = β.Ib
2. Saturation - the transistor is "fully-ON" operating as a switch and Ic = I(saturation)
3. Cut-off - the transistor is "fully-OFF" operating as a switch and Ic = 0
Bipolar Transistors are current regulating devices that control the amount of current
flowing through them in proportion to the amount of biasing voltage applied to their base
terminal acting like a current-controlled switch. The principle of operation of the two
transistor types PNP and NPN, is exactly the same the only difference being in their biasing
and the polarity of the power supply for each type (fig 1).
Fig 3.1 Bipolar Junction Transistor Symbol

The construction and circuit symbols for both the PNP and NPN bipolar transistor are
given above with the arrow in the circuit symbol always showing the direction of

64
"conventional current flow" between the base terminal and its emitter terminal. The direction
of the arrow always points from the positive P-type region to the negative N-type region for
both transistor types, exactly the same as for the standard diode symbol.
3.3 TRANSISTOR CURRENT COMPONENTS:
Fig 3.2 Bipolar Junction Transistor Current Components

The above fig 3.2 shows the various current components, which flow across the
forward biased emitter junction and reverse- biased collector junction. The emitter current IE
consists of hole current (holes crossing from emitter into base) and electron current
(electrons crossing from base into emitter).The ratio of hole to electron currents, / ,
crossing the emitter junction is proportional to the ratio of the conductivity of the p material
to that of the n material. In a transistor, the doping of that of the emitter is made much larger
than the doping of the base. This feature ensures (in p-n-p transistor) that the emitter current
consists an almost entirely of holes. Such a situation is desired since the current which results
from electrons crossing the emitter junction from base to emitter do not contribute carriers,
which can reach the collector.
Not all the holes crossing the emitter junction JE reach the collector junction JC
because some of them combine with the electrons in n-type base. If is hole current at
junction JC there must be a bulk recombination current ( - ) leaving the base.
Actually, electrons enter the base region through the base lead to supply those
charges, which have been lost by recombination with the holes injected in to the base across
JE. If the emitter were open circuited so that IE=0 then would be zero. Under these
circumstances, the base and collector current IC would equal the reverse saturation current
ICO. If IE≠0 then IC= ICO- .
For a p-n-p transistor, ICO consists of holes moving across JC from left to right (base to
collector) and electrons crossing JC in opposite direction. Assumed referenced direction for
ICO i.e. from right to left, then for a p-n-p transistor, ICO is negative. For an n-p-n transistor,
ICO is positive. The basic operation will be described using the p-n-p transistor. The operation
of the p-n-p transistor is exactly the same if the roles played by the electron and hole are
interchanged.
One p-n junction of a transistor is reverse-biased, whereas the other is forward-biased.
3.3a Forward-biased junction of a pnp transistor

49
3.3b Reverse-biased junction of a pnp transistor
3.3 c Both biasing potentials have been applied to a pnp transistor and resulting majority and
minority carrier flows indicated.
Majority carriers (+) will diffuse across the forward-biased p-n junction into the n-
type material. A very small number of carriers (+) will through n-type material to the base
terminal. Resulting IB is typically in order of microamperes. The large number of majority
carriers will diffuse across the reverse-biased junction into the p-type material connected to
the collector terminal
Applying KCL to the transistor :
IE=IB+IC
The comprises of two components – the majority and minority carriers
IC = ICmajority + ICOminority
ICO – IC current with emitter terminal open and is called leakage current
3.4 Bipolar Transistor Configurations
As the Bipolar Transistor is a three terminal device, there are basically three
possible ways to connect it within an electronic circuit with one terminal being common to
both the input and output. Each method of connection responding differently to its input
signal within a circuit as the static characteristics of the transistor varies with each circuit
arrangement.
1. Common Base Configuration - has Voltage Gain but no Current Gain.
2. Common Emitter Configuration - has both Current and Voltage Gain.
3. Common Collector Configuration - has Current Gain but no Voltage Gain.
3.5 COMMON-BASE CONFIGURATION
Common-base terminology is derived from the fact that the: base is common to both
input and output of the configuration. Base is usually the terminal closest to or at ground
potential. Majority carriers can cross the reverse-biased junction because the injected

50
majority carriers will appear as minority carriers in the n-type material. All current directions
will refer to conventional (hole) flow and the arrows in all electronic symbols have a
direction defined by this convention.
Note that the applied biasing (voltage sources) are such as to establish current in the
direction indicated for each branch.
Fig 3.4 CB Configuration

To describe the behaviour of common-base amplifiers requires two set of
characteristics:
1. Input or driving point characteristics.
2. Output or collector characteristics
The output characteristic has 3 basic regions:
1. Active region –defined by the biasing arrangements
2. Cutoff region – region where the collector current is 0A
3. Saturation region- region of the characteristics to the left of VCB = 0V
Fig 3.5 CB Input-Output Characteristics

The curves (output characteristics) clearly indicate that a first approximation to the
relationship between IE and IC in the active region is given by IC ≈IE. Once a transistor is in
the ‗on‘ state, the base-emitter voltage will be assumed to be VBE = 0.7V
In the dc mode the level of IC and IE due to the majority carriers are related by a
quantity called alpha α= αdc
IC = IE + ICBO
It can then be summarize to IC = IE (ignore ICBO due to small value)
For ac situations where the point of operation moves on the characteristics curve, an
ac alpha defined by αac Alpha a common base current gain factor that shows the efficiency by
calculating the current percent from current flow from emitter to collector. The value of α is
typical from 0.9 ~ 0.998.
Biasing: Proper biasing CB configuration in active region by approximation IC IE (IB 0 uA)
Fig 3.6 CE Configurations

Common-Emitter Configuration
It is called common-emitter configuration since: emitter is common or reference to
both input and output terminals. Emitter is usually the terminal closest to or at ground
potential. Almost amplifier design is using connection of CE due to the high gain for current
and voltage. Two set of characteristics are necessary to describe the behaviour for CE; input

68
(base terminal) and output (collector terminal) parameters. Proper Biasing common-emitter
configuration in active region
Fig 3.8 CE Configuration
IB will flow when VBE > 0.7V for silicon and 0.3V for germanium
Before this value IB is very small and no IB.
Base-emitter junction is forward bias Increasing VCE will reduce IB for different values.
Fig 3.9a Input characteristics for common- Fig 3.9b Output characteristics for
emitter npn transistor common-emitter npn transistor
For small VCE (VCE < VCESAT, IC increase linearly with increasing of VCE
VCE > VCESAT IC not totally depends on VCE → constant IC
IB(uA) is very small compare to IC(mA). Small increase in IB cause big
increase in IC
IB=0 A → ICEO occur.
Noticing the value when IC=0A. There is still some value of current flows.
Beta ( ) or amplification factor
The ratio of dc collector current (IC) to the dc base current (IB) is dc beta (dc) which is
dc current gain where IC and IB are determined at a particular operating point, Q-point
(quiescent point). It‘s defined by the following equation:
30 < dc < 300 → 2N3904
On data sheet, dc=hfe with h is derived from ac hybrid equivalent circuit. FE is
derived from forward current amplification and common-emitter configuration respectively.

69
3.7 COMMON – COLLECTOR CONFIGURATION

It is also called emitter-follower (EF). It is called common-emitter configuration since
both the signal source and the load share the collector terminal as a common connection
point. The output voltage is obtained at emitter terminal. The input characteristic of common-
collector configuration is similar with common-emitter configuration. Common-collector
circuit configuration is provided with the load resistor connected from emitter to ground. It is
used primarily for impedance matching purpose since it has high input impedance and low
output impedance.
Fig 3.10 CC Configuration

For the common-collector configuration, the output characteristics are a plot of IE vs
VCE for a range of values of IB.

Fig 3.11 Output Characteristics of CC Configuration for npn Transistor

Common Base Configuration
This configuration is also called grounded base configuration. In this configuration the
input signal is applied between emitter and base while the output is taken from collector and
base. As base is common to input and output circuits, hence the name common base
configuration. Fig.3.12 (a) shows the common base NPN transistor circuit.
Fig.3.12 (a)
Current Amplification factor ()
When no signal is applied, the ratio of the collector current to the emitter current is
called d.c alpha (dc) of a transistor.
IC
 α 
dc
IE
If we write αdc simply by α , then
IC
α (1)
IE
When signal is applied, the ratio of change in collector current to the change in emitter
current at constant collector-base voltage is defined as current amplification factor αac .
 αdc ΔIC VCB constant

ΔIE
For all physical purposes, αdc  αac  α and practical values in commercial transistors
range from 0.95 to 0.995.

7155
Leakage Current in CB Configuration I CBO 
Fig.3.12 (b)
When emitter is open circuited, IE  0 in CB configuration. In such condition the
collector-base junction act as a reverse biased diode and hence a small leakage current flow
between the collector and base as shown in fig.3.12(b) The leakage current is known as
collector to base leakage current with emitter open and is abbreviated as ICBO .
Expression for Collector Current (IC)
The total collector current in a common base transistor has the following two
components:
1. The part of emitter current which reaches the collector. Its value is αIE and is due to
majority carriers.
2. The leakage current ICBO, produced by the movement of minority carriers across the
collector-base junction when reverse biased.
 Total collector current, IC  αIE  Ileakage  αIE  ICBO
Common Emitter Configuration (CE)
Fig. 3.13(a)
This configuration is also called grounded emitter configuration. In this configuration,
the input signal is applied between base and emitter and the output is taken from collector and
emitter. As emitter is common to both input and output circuits, hence the name common
emitter configuration. Fig.3.13 (a) shows the common-emitter NPN transistor circuit.
Current Amplification factor β
When no signal is applied, the ratio of collector current to the base current is called d.c
beta βdc  of transistor. I
β 
 dc
C
IB
If we write βdc simply byβ , then
IC
β (5)
IB

72
56
When signal is applied, the ratio of change in collector current to the change in base
current at constant collector-emitter voltage is defined as base current amplification factor βac .
β  ΔI (6)
 ac
C
VCE constant
ΔIB
For all physical purposes, βdc  βac  β
Almost in all transistors, the base current is less than 2% of the emitter current. Due to
this fact, β is generally greater than 20. Usually, β ranges from 20 to 500. Hence, this
configuration is frequently used when appreciable current gain as well as voltage gain is
required.
Relation between  and 
We know that emitter current (IE) of a transistor is the sum of its base current (IB) and
collector current (IC) i.e.
IE = IB+ IC
Dividing the above equation on both sides by IC,
IE IE
 1
IC IC
IC IC
Since α  and β 
IE IB
1 1
  1
α β
1 1β

α β
β
 α 
1β
The above expression may be written as
(1+) = 
α  αβ  β
β1 α α
α
 β 
 1α

Leakage Current in CE Configuration (CE)
When base is open circuited, IB  0 in CE configuration. In such condition a small
leakage current flow between the collector and emitter as shown in figure 3.13(b). The
leakage current is known as collector to emitter leakage current with base open and is
abbreviated as ICEO .
Fig. 3.13(b)

73
Expression for Collector Current (IC)

We have seen that in CB configuration IE is the input current and IC is the output
current. These currents are related through equations (1) and (2).
IE  I B  I C (1)
IC  αIE  ICBO (2)
To obtain the relation between output current I C  and input current I B  , we simply
substitute the equation (1) into equation (2), we get,
IC  αIB  IC  ICBO
IC  αIB  αIC  ICBO
IC 1 α αIB  ICBO
α 1
 IC  I  I (3)
1α
B
1α CBO
In this equation, IC is given in terms of IB . The equation can be simplified by defining.

α 1
β and 1  β 
1 α 1  α
I C  βI B  1  βI CBO
Thus in CE configuration the leakage current (ICEO ) is 1 β times the leakage current
in CB configuration I CBO  .
 IC  βIB  ICEO
This is the required expression for collector current in CE configuration.
Field Effect Transistor (FET)

Introduction
The field effect transistor (FET) is a three terminal semiconductor device in which the
current is controlled by an applied electric field. It is also called a uni-polar transistor because
the conduction or operation of FET depends only the majority carriers (i.e. either electrons or
holes). Types of FET’s
The FETs are broadly classified into two types as follows:
FET : Field Effect Transistor

JFET : Junction Field Effect Transistor
MOSFET or IGFET : Metal Oxide Semiconductor Field Effect Transistor (or)
Insulated Gate Field Effect Transistor

74
Construction and Principle of Operation of JFET

A FET consists of N-type or P-type silicon bar containing two PN-junctions at the sides
as shown in fig.3.14 (a) & (b). If the bar is N-type then it is named as N-channel FET and if
the bar is P-type, then it is named as P-channel FET. The structure of N-channel FET and P-
channel FETs are shown in fig.3.14. The circuit symbols employed for N-channel and P-
channel FETs are also shown in fig.3.14.
Fig. 3.14(a) Fig.3.14 (b)

Construction of N-channel FET
For the fabrication of N-channel FET, a narrow bar of N-type semiconductor material is
taken. On the opposite sides of its middle part, two heavily doped P-type regions are diffused.
The two PN-junctions are formed in the bar. These junctions form two PN-diodes and the
area between two P-regions is known as channel. The two P-regions are connected to a
common lead which is called gate terminal. Ohmic contacts are made at the two ends of N-
type semiconductor bar. One lead is called as source terminal S and the other lead is called as
drain terminal D. The source and drain may be interchanged. Hence FET is a three terminal
device whose terminals are source, drain and gate.
The FET has the following notations:
1. Source(S): The source S is a terminal through which the majority carriers enter the bar
(like emitter in BJT).
2. Drain (D): The drain D is a terminal through which the majority carriers leave the bar
(like collector in BJT).
3. Gate (G): It is the terminal which connects the both P-regions in case of N-channel
FET and the both N-regions in case of P-channel FET, which controls the carrier flow.
It is similar to base in BJT.
4. Channel: It is the space between the two gates through which the majority carriers
flows from source to drain.
Operation
The connections of N-channel FET to the external batteries is shown in fig.3.14(c) &
(d).
Case I: When VDS is applied and VGS =0
When no voltage is applied to gate i.e., VGS = 0 and VDS is applied between source and
drain. The majority carriers i.e. electrons flow through the N-channel from source to drain.
Therefore, the conventional drain current ID flows through the channel from drain to source.
The channel resistance is represented as rd and rs as shown in fig. 3.14(c) and its magnitude
depends on VDS and VGS.

75 59
The drain current ID produce a voltage drop along the channel. This voltage drop
reverse biases the PN-junctions and causes the depletion regions to penetrate into the channel,
which is not symmetrical.
It penetrates deeper on to channel near drain and less near source because Vrd>> Vrs.
(i.e., the reverse bias is higher near drain than compared to source).
Case II: When VGS is applied VDS = 0
Consider an N-channel JFET is shown in the fig.3.14 (d). Here the P-type gate and N-
type channel constitute PN-junction. In this case the PN-junctions are reverse biased and
hence the thickness of the depletion regions increases. As VGS is increased, the reverse bias
across the junction increases. Hence the thickness of the depletion regions in the channel will
increase till the two depletion regions make contact with each other. In this condition the
channel is said to be cut-off. The value of VGS which cut-off the channel is called the cut-off
voltage VGS (off).
Fig. 3.14(c) Fig.3.14 (d)

Case III: When VDS and VGS are applied
When voltage is applied between the drain and source with a battery VDS, the electrons
flow from source to drain through the narrow channel existing between the depletion regions.
This constitutes the drain current (ID), its conventional direction is indicated from drain to
source (fig.3.14(c)).
The value of drain current is maximum, when no external voltage is applied between
the gate and source (i.e., VGS=0) and is designated by symbol IDSS.
When a reverse voltage VGS is applied between the gate and source terminal, the width
of the depletion layer is increased, which in turn reduces the width of the conducting channel
there by increasing the resistance of the bar. Hence the current from source to drain
decreases.
If the reverse voltage on the gate is decreased the width of the depletion layer decreases
which in turn increases the width of conducting channel. Thus the current from source to
drain is controlled by the potential or electric field applied on the gate. Hence the device is
termed as field effect transistor (FET).
JFET Characteristics
Drain Characteristics of JFET
The curves shows the relationship between the drain current ID and drain to source
voltage VDS for different values of VGS are called drain characteristic of JFET.
Fig.3.15 (a) shows the experimental setup required to plot these characteristics. First
adjust the gate source voltage to some suitable value. Then increase the drain to source
voltage in small suitable value at each step and record the corresponding values of drain
current.

60
Plot a graph with drain to source voltage (VDS) along the horizontal axis and the current
(ID) along vertical axis, we shall obtain a curve as shown in fig.3.15 (b).
Fig.3.15(a)
ID
D
Ohmic region Pinch-off region Break down region
IDSS VGS = 0
B C V
A
VDS
0
Fig.3.15(b)
It can be sub divided into following four regions:
1. Ohmic region OA
2. Curve AB
3. Pinch-off region
4. Break down region
1. Ohmic region OA:In this region, the drain current ID increases linearly with VDS
following ohms law. It means that FET behaves like an ordinary resistor till point A
called knee point is reached.
2. Curve AB: In this region, ID increases at inverse square law rate up to point B which is
called pinch-off point. The drain to source voltage VDS corresponding to point B is
called pinch-off voltage (VP).
3. Pinch-off region: This region is shown by the curve BC in fig.3.15(b). It is also called
saturation region or constant current region. In this region, drain current remains
constant at its maximum value.
*Note:
a) The drain current in the pinch-off region depends upon the gate to source voltage
and is given by the relation,
 V 2
I I 1  GS 
DSS  


D
 VP 
b) This relation is known as Shockley‘s equation.

61
c) The pinch-off region is the normal operating region of JFET, when used as an
amplifier.
4. Break down region: This region is shown by the curve CD in fig. 4.2(b). In this
region, the drain current increase rapidly as the drain to source voltage is increased. It is
because of the breakdown of gate to source junction due to avalanche effect. The drain
to source voltage corresponding to point C is called breakdown voltage.
Transfer Characteristics of JFET
1. These curves shows the relationship between drain current (ID) and gate to source
voltage (VGS) for different values of drain to source (VDS) voltage.
ID
VDS = Constant
VGS
0
Fig.3.15(c)
2. These transfer characteristics curves are obtained by using the circuit shown in
fig.3.15(c). First adjust the drain to source voltage to some suitable value. Then
increase the gate to source voltage in small suitable value at each step and record the
corresponding values of drain current at each step.
3. Plot a graph with gate to source voltage (VGS) along the horizontal axis and the current
(ID) along the vertical axis, we shall obtain a curve as shown in the fig.3.15(c).
4. The transfer characteristic follow the equation,
 2
I  I 1 V GS 
D DSS  
Vp 

5. From the above equation, it is clear that when VGS= 0, ID=IDSS and when VGS= VP,
ID = 0.
JFET Parameters
A FET has certain parameters which determine its performance in a circuit. These
parameters can be obtained from its two characteristics. The main parameters of a JFET when
connected in common source mode are:
a) A.C. drain resistance (rd)
b) Trans-conductance (gm)
c) Amplification factor ( μ )
A.C. Drain Resistance (rd)
It is the a.c. resistance between drain and source terminals when JFET operates in the
pinch–off region. Therefore, it is defined as the ratio of the change in drain to source voltage
(VDS) to the change in drain current (ID) at constant gate to source voltage (VGS).

78
 rd  Change in VDS
Change in I D VGS Constant
 Δ V 
  DS  …(1)
or rd
 Δ ID VGSConstant
It is also called dynamic drain resistance. It is measured in ohms. Typically r d is about
400 KΩ.
Trans-conductance (gm)
The control that the gate voltage has over the drain current is measured by trans-
conductance. It is defined as the ratio of change in drain current (ID) to the change in gate to
source voltage at constant drain to source voltage (VDS).
 g m  Change in ID
Change in VDS VDS Constant
Or g m   ID … (2)
 VGS VDS  Constant
Its unit is Siemens (S) which was earlier called mho or A/V. it is unit also called
forward trans-conductance. Typically gm ranges from 150 μS to 250 μS.
Amplification factor (μ)
It is defined as the ratio of change in drain to source voltage (VDS) to the change in gate
to source voltage (VGS) at constant drain current (ID).

Change in VDS
μm  
Change in VGS I Constant
 ΔVDS 
D
or μm    …(3)
 Δ V 
 GS I  Constant
D
Since μ is the ratio of two voltages, it has no unit. The amplification factor of a FET
can be as high as 100.
Relation among FET Parameters
From eq. (1), (2) and (3) it can be seen that,
Δ VDS  Δ VGS Δ ID
μ
Δ VGS Δ VGS Δ ID
ΔVDS Δ VGS  ΔID
μ   ΔV
Δ VGS Δ ID GS
μ  rd gm
Advantages and Disadvantages of FET over BJT
Its advantages over BJT are as follows:
1. It has very high input impedance.
2. It produces low noise than BJT.
3. It has negative temperature coefficient of resistance. This avoids the risk of thermal run
away.
4. It has no offset voltage at zero drain current and hence it acts as an excellent signal
chopper.
5. Small size, longer life and high efficiency.
6. It has better thermal stability.
Disadvantages of FET
The following are the disadvantages of FET:

63
1. Less gain for a given bandwidth, i.e. small gain band width product.
2. Smaller power ratings.
3. Switching speed is lower.
Differences between JFET and BJT
S.No. Field Effect Transistor (FET) Bipolar Junction Transistor (BJT)

1. The current flowing is due to only The current flowing is due to both
majority carriers. majority and minority carriers
2. It is a uni-polar device. It is a bipolar device.
3. Its input impedance is high. Its input impedance is low.
4. It is a voltage controlled device. It is a current controlled device.
5. It has better thermal stability. It has poor thermal stability.
6. It has low voltage gain. It has high voltage gain.
7. No thermal runaway. There is thermal runaway.
8. It is less noisy than a BJT and vacuum Noisier than a FET.
tube.
9. Cost is high. Cost is low.
10. Its power gain is more at audio Its power gain is less at audio frequencies.
frequencies.
11. It is much simpler to fabricate and It is comparatively difficult to fabricate

occupies a less space on IC chip. and occupies more space on IC chip.
12. Source and Drain terminals are Emitter and collector terminals are not
interchangeable. interchangeable.
Applications of FETs
1. The main advantages of the unipolar transistor, or FET, are the very high input
impedance, no offset voltage, and low noise. For these reasons a FET is most useful in
a low level high input impedance circuit, such as a signal chopper or the first stage of a
unipolar-bipolar cascade combination.
2. FET is also used as a voltage variable resistor (VVR) or voltage dependent resistor
(VDR).
3. On account of being square law device, FETs are frequently used in the tuners of radio
and TV receivers.
4. In a FET, since the gate draws no current, it has very high input impedance and hence it
is suitable for being used in electronic voltmeters, which are popularly called FETs
meter.
5. Because of the high input impedance and low output impedance, a FET acts as an
excellent buffer amplifier.
Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
The input impedance of a JFET is not high because gate to source junction is reverse
biased and very small reverse current flows. Also, JFET can be operated in depletion mode

80 64
only. Thus, the signal handling capacity of an amplifier using JFET is limited and gain per
stage is less. To overcome the above limitations, fabrication of FET is modified.
Fig.3.16 (a) shows the constructional details of N-channel MOSFET. It is similar to
JFET except with the following modifications:
1. There is only a single P-region. This region is called substrate.
2. A thin layer of metal oxide (usually silicon dioxide) is deposited over the left side of
the channel. A metallic gate is deposited over the oxide layer.
As silicon dioxide (SiO2) is an insulator, therefore the gate current becomes very small,
resulting in very high input impedance lying in the range 1010 to 1015 . The gate can also
be forward biased. Thus MOSFETs may be operated in either enhancement mode or
depletion mode. Signal handling capacity improves greatly.
A parallel plate capacitor is formed with the metal area of the gate and the
semiconductor channel acting as the electrodes and the oxide layer as the dielectric in
between the electrodes. Thus the gate has been insulted by means of SiO2 layer. For this
reason, MOSFET is sometimes called insulated gate FET (IGFET).
Drain (D)
Gate (G) P Substrate
N
Oxide
Source(S)
Fig.3.16
The MOSFETs are broadly classified into two types as follows:
MOSFETs
Depletion type Enhancement type
N-Channel P-Channel N-Channel P-Channel

MOSFET: Metal Oxide Semiconductor Field Effect Transistor
Depletion type MOSFET
Construction of N-channel Depletion type MOSFET

81
The fig.3.17 (a) shows the basic construction of N-channel depletion type MOSFET.
Two highly doped N+ regions are diffused into a lightly doped P-type substrate. These two
highly doped N+ regions acts as source and drain. In some cases substrate is internally
connected to the source terminal.
*Note: As there is no direct electrical connection between the gate terminal and the channel
of a MOSFET, increasing the input impedance of the device
The source and drain terminals are connected through metallic contacts to N+ doped
regions linked by an N-channel as shown in fig.3.17(a). A thin layer of metal aluminium is
deposited over the layer of SiO2. This layer covers the entire channel region between source
and drain and it constitutes the gate.
S G D
Metal
SiO2
N+ N+
Diffused
N- channel
Fig.3.17 (a)
Working of N-channel Depletion type MOSFET
Case I: When VGS = 0 V and VDS = +Ve
Let us consider that VGS = 0 V and the drain D at a positive potential with respect to the
source S, the majority carriers i.e. electrons flow through the N-channel from source(S) to
drain(D). The behavior is similar to that of the JFET and the saturation current under these
conditions is called IDSS (drain current with source short circuited to gate).
Case II: When VGS = - Ve and VDS = + Ve {Depletion mode}
When a negative voltage is applied to the gate, the conduction electrons are repelled
from the channel and holes are attracted from P-type substrate. This initiates recombination
of repelled electrons and attracted holes.
The level of recombination between electrons and holes depends on the magnitude of
the negative voltage applied to the gate. This recombination reduces the number of free
electrons in the N-channel for the conduction, reducing the drain current. Thus the level of
drain current will reduce with increasing negative bias for VGS as shown in the transfer
characteristics of depletion type MOSFET (fig.3.17(c)).
*Note: In fact, too much negative gate voltage can cut off the channel. Hence with negative
gate voltage, a DEMOSFET behaves like a FET.
Case III: When VGS = +Ve and VDS = +Ve {Enhancement mode}
For positive values of VGS the positive gate will draw additional electrons from the P-
type substrate. These electrons are added to those already existing in the channel. This
increased number of electrons increases or enhances the conductivity of the channel.
*Note:
1. The device operates in depletion mode, when the gate voltage is negative.

66
2. The device operates in enhancement mode, when the gate voltage is positive.
Characteristics of N-channel Depletion type MOSFET
Drain Characteristics
The fig.3.17(b) shows the drain characteristics for the N-channel depletion type
MOSFET.
These curves are plotted for both negative and positive values of gate to source voltage
(VGS). The curves shown above the VGS = 0 have a positive value where as those below it
have a negative value of VGS.
When VGS is zero and negative, the MOSFET operates in the depletion mode. On the
other hand, if VGS is zero and positive, the MOSFET operates in the enhancement mode. The
only difference between the JFET and the depletion MOSFET is that JFET does not operate
for positive values of gate to source voltage (VGS).
ID
VGS = +1V
VGS = 0V
VGS = - 1V
VGS = - 2V
VGS = -
VGS = -
VGS = -
VGS = -
0 6V
Fig.3.17 (b)
Transfer Characteristics
The transfer characteristics for a N-channel MOSFET is shown in fig 3.17(c) The
transfer characteristics give the variation of the drain current ID with the gate to source
voltage VGS for a fixed value of VDS. On the left hand side of curve is the depletion mode,
where VGS is negative. On the right hand side of curve is the enhancement mode, where VGS
is positive.
*Note:It may be noted that even if VGS = 0, the device has a drain current equal to IDSS. Due
to this fact it is called normally ON MOSFET.
ID
10.9
Enhancement
Depletion mode
8 IDSS
mode
VDS= Constant 4
2
VGS
Fig. 3.17(c)
Enhancement type MOSFET
Construction
The fig.3.18 (a) shows the basic construction of N-channel enhancement type
MOSFET. Two highly doped N+ regions are diffused into a lightly doped P-type substrate.
These two highly doped N+ regions acts as the source and drain. A thin layer of SiO2 is
grown over the surface of the structure. Holes are cut into this SiO2 layer for making contact

83
with source and drain region. A thin layer of metal aluminium is formed over the layer of
SiO2, and it constitutes the gate
S G D
Metal
+++++
-------
+++++
-------
Induced channel
Fig. 3.18(a)
*Note:
1. It differs in construction from the depletion type MOSFET in that it has no physical
channel.
2. This type of MOSFET operates only in the enhancement mode and has no depletion
mode.
Working
Case I: VGS = 0 and VDS = +Ve
If the gate is grounded (VGS=0) and some voltage is applied to the drain VDS  Ve ,
the supply tries to draw free electrons (if any) towards the drain. However, the P-substrate
has very few thermally generated free electrons. As a result, this type of MOSFET is OFF
when VGS  0. this behaviour is different from that of the depletion type where IDSS flows.
Case II: VGS = +Ve and VDS = +Ve

When a positive potential is applied to the gate, electrons from the substrate are
attracted to the region near the SiO2 layer. When the gate potential is sufficiently positive,
sufficient number of electrons is drawn into that region and converts it into an N-type region
(i.e., the P-type material is inverted to form an N-type channel). Thus an N-type channel is
induced between the drain and the source.
At a particular value of VGS there is a measurable current flow between drain and
source. This value of VGS is called threshold voltage denoted by VT.
Thus we can say that in an enhancement type N-channel MOSFET, the conductivity of
the channel is enhanced by increasing the gate to source voltage and thus pulling more
electrons in to the channel.
*Note:
1. For any voltage below the threshold value, there is no channel.
2. Typical values of VT are in the range of 1-3 V.
3. The construction of the P-channel is exactly the reverse of the N-channel.
Drain Characteristics
Fig.3.18 (b) shows the drain characteristics of an N-channel enhancement type
MOSFET. Looking at fig.3.18 (b) we can say that as VGS increases beyond the threshold
level, the density of free carriers (electrons) in the induced channel increases, increasing the
drain current. However, at some point of VDS, for constant VGS, the drain current reaches a

84 68
saturation level. The levelling off of ID is due to a pinch-off process, is as described earlier
for the JFET.
VGS =
VGS =
VGS = +6V
VGS= +5V
V GS = +
VGS = + VDS
0
Fig. 3.18(b)
Transfer Characteristics
Fig.3.18(c)
Fig.3.18(c) shows the transfer characteristic for N-channel enhancement type
MOSFET. This characteristic is quite different from characteristic that we obtained for JFET
and depletion type MOSFET. For N-channel enhancement type MOSFET, VGS is in the
positive region. The drain current does not start rising until VGS = VT.
Circuit Symbols of MOSFETs
D-MOSFET Circuit Symbols
Fig.3.19 (a) shows graphic symbols for an N and P-channel depletion-type MOSFETs.
In the symbol insulation between gate and channel is represented by a space between the gate
and other terminals of the symbol. The vertical line represents that the channel is connected
between the drain and source and is supported by the substrate (in some cases it is internally
shorted to source terminal).
D D
G G
S S
Fig.3.19 (a)
E-MOSFET Circuit Symbols
D D
G G
S S
Fig. 3.19 (b)

85 69
Fig. 3.19(b) shows circuit symbols for an N and P-channel enhancement type
MOSFETs. The dashed line between drain and source represents the fact that a channel does
not exists between source and drain under no-bias conditions. It is the only difference
between the symbols for the depletion type and enhancement type.
Differences between JFET & MOSFET
Sl.No. JFET MOSFET
1. Input impedance is of the order Input impedance is of the order of 1010 to

of 108. 1015.
2. It is operated only in depletion The depletion MOSFET can be operated in

mode. both depletion mode and enhancement mode.
3. There are two P-regions in N- There is only one P-region in N-channel

channel JFET (or) two N-regions MOSFET (or) one N-region in P-channel
in P-channel JFET. MOSFET.
4. The channel and gate forms a The channel and gate forms a parallel a parallel
PN-junction. plate capacitor.
5. Gate is not insulated from Gate is insulated from channel by a layer of

channel. SiO2.
6. Gate current is high. Gate current is low.
7. Channel exists permanently. Channel exists permanently in depletion type

MOSFET, but not in enhancement type
MOSFET
8. Much easier to fabricate. Compared to JFETs, MOSFETs are much

easier to fabricate.
9. Conductivity is controlled by the Conductivity is controlled by the electric field

reverse voltage to the gate. induced across an insulating layer deposited on
the semiconducting material.
10. JFETs are widely used in analog MOSFETs are widely used in digital circuits.
circuits.
11. These are two types of JFETs These are two types of MOSFETs; they are: a)
they are: a) N-channel JFET Depletion type MOSFET
b) P-channel JFET b
) Enhancement type MOSFET
Applications of MOSFETs
The MOSFETs may be used in any of the circuits covered for JFET, with substrate connected
to the source. Because of their high input resistances, the enhancement type MOS devices
have been used as micro-resistors in integrated microcircuits.
It is easier to fabricate MOSFET. On account of the advantage of MOSFET, it is widely
used than JFET. The enhancement type MOSFET finds wide applications in digital circuitry.

70
UNIT-III
Solved Problems:
1. If a transistor has α of 0.97, find the value of β. If β=200, find the value of α? (June-2017)
Solution:
α = 0.97, β=?
Where β = α/1- α = 0.97/(1-0.97) = 32.33
β = 200, α =?
Where α = β /1+ β = 200/(1+200) = 0.99
2. A transistor has CE current gain of 100, If the collector current is 40mA, What is the value of
emitter current? (June-2018)
Solution:
Given data:- β = 100, IC = 40mA, IE = ?
Where β = IC/IB
IB = IC/ β = 40mA/100 = 0.4mA
IE = IB+IC = 0.4mA+40mA = 40.4mA
3. In a certain transistor, the emitter current is 1.02 times as large as the collector current. If the
emitter current is 12 mA, find the base current. 5M
Solution:
Given data:- Emitter current IE=12mA, Collector current is 1.02 times of emitter current so
IC=1.02X12mA=12.24mA, IB = ? we know that IB=IE-IC
= 12mA-12.24mA
IB= -0.24mA
4. A transistor with α = 0.97 has a reverse saturation current of 1µA in CB configuration. Calculate
the value of leakage current in CE configuration. Also find the collector current and the emitter
current if the value of base current is 20µA. 5M
Solution:
Given data:-
In CB configuration α = 0.97, ICO or ICBO = 1µA, Where β = α/1- α = 0.97/(1-0.97) = 32.33
In CE configuration IB =20µA IE =?, IC = ? and ICEO=?
The relation between CB and CE configuration. we know that
ICEO = (1+β) ICBO
= (1+32.33) 1µA
ICEO = 33.33 µA
In CE configuration IC = βIB+(1+ β) ICEO
=32.33X20µA+(1+32.33) 332286.42.33µA
IC = 2.286mA
In CE configuration IE=IB+IC
= 20 µA+2.286mA
IE = 2.306mA
1 87
UNIT- III PART-A (2 MARKS QUESTIONS WITH ANSWERS)
1. Why must the base be narrow for the transistor (BJT) action?
Beta (β) is the ratio of IC to IB .IB becomes less if the base width is narrow.
Higher value of β can be obtained with lower value of base current.
2. Why transistor (BJT) is called current controlled device?
The output voltage, current or power is controlled by the input current in a
transistor. So, it is called the current controlled device.
3. What are “emitter injection efficiency” and “base transport factor” of a transistor?
The ratio of current of injected carriers at emitter junction to the total emitter
current is called the emitter injection efficiency.
4. Why silicon type transistors are more often used than Germanium type?
Because silicon has smaller cut-off current ICBO , small variations in ICBO due to
variations in temperature and high operating temperature as compared to those in case of
Germanium.
5. Why collector is made larger than emitter and base?
Collector is made physically larger than emitter and base because collector is to
dissipate much power.
6. Why emitter is always forward biased with respect to base?
To supply majority charge carrier to the base.
7. Why collector is always reverse biased with respect to base?
To remove the charge carriers away from the collector-base junction.
8. Why CE configuration is most popular in amplifier circuits?
Because it’s current, voltage and power gains are quite high and the ratio of output
impedance and input impedance are quite moderate.
9. Define transistor action.
A transistor consists of 2 coupled PN junctions. The base is a common region to
both junctions and makes a coupling between them. Since the base regions are smaller, a
significant interaction between junctions will be available. This is called transistor
actions.
10. What are the advantages of MOSFET compared to JFET?
The input impedance of MOSFET is higher than that of JFET
11. What are the advantages of FET?
• Input impedance is very high. This allows high degree of Isolation between the
input & output Circuit.
• Current carriers are not crossing the junctions hence noise is highly reduced.
• It has a negative temperature Co-efficient of resistance. This avoids thermal
runaway.
12. Comparison of transistor connection.
S.NO Characteristics Common Base Common Emitter Common collector
1 Voltage gain About 150 About 500 <1
High Low
Input Low
2 (About 750 (about 750 k
resistance (about 75 ohms)
ohms) ohms)
Very High High
Output Low
3 (about 450 k (about 45 k
Resistance (about 45 ohms)
ohms) ohms)
For high For audio
For impedance
4 Applications frequency frequency
matching
applications applications
288
13. What are the biasing conditions to operate transistor in active region?
Emitter-base junction has to be forward biased and collector-base junction to be reverse
biased.
14. What is thermal runaway?
The power loss in transistor is primarily at the collector junction because the voltage there
is high compared to the low voltage at the forward biased emitter junction. If the collector
current increases, the power developed tends to raise the junction temperature. This causes an
increase in β and α further increase in collector current in temperature may occur resulting in
“thermal run away.”
15. In a transistor operating in the active region although the collector junction is reverse
biased, the collector current is quite large. Explain.
Forward biasing the input side and reverse biasing the output side are the requirements of
a transistor in the active region. The collector current is experimentally equal to the emitter
current. Therefore the collector current will be large as emitter current is large on the other hand,
in CE operation IB is multiplied by β, hence we get large collector current.
16. Write the range of parameter values for BJT.
Parameter Symbol Range of value
Input Resistance ri A few K ohms
Current gain in CB mode α 0.9-0.999
Current gain in CB mode þ 20-600
Input Resistance ro Tens of Kohms
Leakage current ICBO Na-µA
17. Define channel.
It is a bar like structure which determines the type of FET. Different types of N
channel are FET and P channel FET.
18. Explain the biasing of JFET.
Input is always reverse biased and output is forward biased. (Note: In transistor input
is forward biased and output is reverse biased)
19. Write the advantages of JFET.
• Input impedance of JFET is very high. This allows high degree of Isolation between
the Input and Output circuit.
• Current carriers are not crossing the junction hence noise is reduced drastically
20. List the JFET parameters?
• A.C drain resistance (rd)
• Tran conductance (gm)
• Amplification factor (μ)
21. Define pinch off voltage.
As the reverse bias is further increased, the effective width of the channel decreases, the
depletion region or the space charge region widens, reaching further into the channel and
restricting the passage of electrons from the source to drain. Finally at a certain gate to source
voltage VGS = VP.
22. Explain the depletion node of operation in MOSFET.
When the gate is at negative bias, the thickness of the depletion layer further increases
owing to the further increase of the induced positive charge. Thus the drain current decreases, as
the gate is made more negative. This is called depletion mode of operation.
23. Explain the term Drain in FET.
The drain is the terminal through which the current leaves the bar. Convention current
entering the bar is designated as ID.
24. Explain the terms source in FET.
The source is the terminal through which the current enters the bar.
Conventional current entering the bar is designated as IS.
25. Define the term Gate in FET.
The gate consists of either P+ or N+ impurity regions, heavily doped and diffused to the
3 89
bar. This region is always reverse biased and in fact, controls the drain current ID.
26. Write the relative disadvantages of an FET over that of a BJT.
The gain bandwidth product in case of a FET is low as compared with a BJT. The
category, called MOSFET, is extremely sensitive to handling therefore additional precautions
have to be considered while handling.
27. When does a transistor act as a switch?
A transistor should be operated in saturation and cut off regions to use it as a switch.
While operating in saturation region, transistor carry heavy current hence considered as ON state.
In cut-off, it carries no current and it is equivalent to open switch
28. Draw the EBER-MOLL model of BJT?
• This model was developed by Ebers and Moll in 1954.
• It is also called the “coupled diode model”.
29. Differentiate FET and BJT (any two)?

FET BJT
Unipolar Device Bipolar Device
High input impedance due to reverse bias low input impedance due to forward bias
Gain is characterized by trans conductance Gain is characterized by voltage gain
Low noise level High noise level
30. Define transistor factor β?
It is the ratio of injected carrier current reaching at collector base junction to injected carrier current at
emitter base junction.
31. Why do the output characteristics of a CB transistor have a slight upward slope?
The emitter and collector are forward biased under the saturation region. Hence a small
change in collector voltage causes a significant change in collector current. Therefore the slight
upward slope is found in output characteristics.
32. Compare JFET & MOSFET
S.
JFET MOSFET
No.
Gate is not insulated from Gate is insulated from channel by a
1
Channel thin layer of SiO2
Four types - P-channel
There are two types – N-channel enhancement, P-channel depletion,
2 and P-channel N-channel enhancement, N-
channel depletion
Cannot be operated in depletion Can be operated in depletion and
3 and enhancement modes enhancement modes
There is a continuous channel only
There is a continuous channel in depletion type, but not in
4
enhancement type
4 90
UNIT-III PART-B Questions (10 Marks):
1. Draw and explain characteristics of Common Collector configurations. 10M (Nov/Dec-2016)

2. Draw and explain characteristics of Common Emitter configurations. 10M (Nov/Dec-2016)
3. Illustrate the input and output characteristics of all three configurations of a BJT transistor. Also give
the important equations related to those configurations. 10M (Nov/Dec-2017)
4. (a) Explain the construction and operation of n-channel JFET. 5M
(b) Draw and explain the drain and transfer characteristics of n-channel JFET. 5M (Nov/Dec-2017)
5. (a) Explain in detail about the Ebers Moll model. Describe base spread resistance. 5M
(b) Explain the operation of JFET. Write some applications for JFET. 5M (June-2017)
6. (a) Explain the operation of BJT. Give the relationship between α, β and ϒ of a transistor. 6M
(b) Compare MOSFET with JFET. 4M (June-2017)
7. (a) Compare CB and CC amplifiers. 4M
(b) Analyze CS-FET amplifier. 6M (Nov/Dec-2018)
8. (a) Explain the operation of CC configuration of BJT and its input and output characteristics briefly. 5M
(b) Explain about Punch through and Base width modulation. 5M (Nov/Dec-2018)
9. With neat diagrams, explain the construction and operating characteristics of EMOSFE. 10M (June-2018)
10. With a neat circuit diagram, explain the CE configuration of BJT. Also draw and explain its input
and output characteristics. 10M (June-2018)
11. with the help of a neat diagram show different current components in a transistor. 10M (Dec-2014)
12. Draw and explain the drain characteristics of N-channel Enhancement type MOSFET. 10M (Dec-2014)
13. With reference to a BJT, explain the following terms in detail. 10M
(i) Emitter efficiency. (ii) Base transportation factor. (iii) Large signal current gain. (Dec-2015)
14. Detail the construction of an n-channel MOSFET of depletion type. Draw and explain its
characteristics. 10M (Dec-2015)
15. Explain with the help of neat diagram the structure of an N-channel FET. In what ways it is different
from a bipolar transistor. 10M (June-2015)
16. (a) Sketch and explain a family of CB output characteristics for a transistor. 5M
(b) Indicate the active, cut-off and saturation regions. Explain the shapes of the curves qualitatively.
5M (June-2015)
17. (a) Explain how transistor will act as an amplifier. 5M
(b) In a certain transistor, the emitter current is 1.02 times as large as the collector current. If the
emitter current is 12 mA, find the base current. 5M
18. (a) Discuss in detail about Early Effect 5M
(b) Discuss in detail about Punch Through or Reach Through 5M
18. (a) Explain input & output characteristics of transistor in CB configuration. 5M
(b) A transistor with α = 0.97 has a reverse saturation current of 1µA in CB configuration. Calculate
the value of leakage current in CE configuration. Also find the collector current and the emitter
current if the value of base current is 20µA. 5M
19. (a)With neat structure explain the principle of operation of n-channel JFET with characteristics. 5M
(b) For an n-channel silicon FET with a =3x10-4cm and ND =1015electrons/cm3 find i) the pinch- off
voltage and ii) the channel half-width when VGS =VP/2 at ID =0. 5M
20. (a) With neat sketch explain the operation & drain characteristics of Enhancement MOSFET. 5M
(b) With neat sketch explain the operation & drain characteristics of Depletion MOSFET. 5M
21. (a) Explain how FET acts as VVR. 5M
(b) State advantages and disadvantages of FET’s over BJT’s (or)
22. (a)Explain the mechanism of current flow in a PNP and NPN transistors. 6M
(b)Define α and β and derive the relation between them. 4M
5 91
UNIT- IV
Transistor Biasing and Thermal Stabilization
BJT BIASING
Need for Biasing in Amplifier Circuits

In order to operate transistor in the desired region, we have to apply external d.c
voltages of correct polarity and magnitude to the two junctions of the transistor. This is
nothing but the biasing of the transistor.
The basic purpose of transistor biasing is to keep the emitter-base junction properly
forward biased and collector-base junction properly reverse biased during the application of
signal. This can be achieved with a battery or associating a circuit with transistor. The latter
method is more efficient and is frequently employed. The circuit which provides transistor
biasing is known as biasing circuit. It may be noted that transistor biasing is very essential
for the proper operation of transistor in any region.
When we bias a transistor we establish certain current and voltage conditions for the
transistor. There conditions are known as operating conditions. By proper biasing of a
transistor, a desired quiescent or operating point is obtained. The operating point must be
stable for proper operation of the transistor. However, the operating point shifts with changes
in transistor parameters such as β, I C0 and VBE . As transistor parameters are temperature
dependent, the operating point also varies with change in temperature. Let us see the
different methods to establish and stabilize the operating point.
D.C Load Line
It is the line on the output characteristics of a transistor circuit which gives the values of
I C and VCE corresponding to zero signal or d.c conditions.
Consider a basic CE amplifier circuit shown in fig. 4.1(a).
Applying KVL to the collector circuit shown in fig. 4.1(a), we get,
 VCC  I C R C  VCE  0
 VCE  VCC  I C R C (1)
We can arrange the terms in equation (1) as
I C R C  VCC  VCE
Fig. 4.1(a)
YUVARAJ K, ASST.PROF, Department of ECE, SVEW Tirupathi Page 75

92
 1  V
or IC    VCE  CC (2)
 R C  RC
Equation (2) resembles the equation of a straight line equation y  mx  c . If equation

(2) is plotted on the transistor output characteristic (i.e. graph between VCE and I C ) we get a
straight line and is known as d.c load line as shown in fig. 4.1(b).
1
The slope of the line is given by, m and the intercept on I C axis (y-axis) is,
RC
VCC
c
RC
The d.c load line given us the following information:
1. The load line intersects the horizontal axis at a point marked VCC which is called
transistor cut-off point. At this point the values of I B and I C are zero. But actually
there is a small value of reverse saturation current I CB0  at cut-off point. As a result of
this the collector to emitter voltage VCE  is slightly less than the VCC .
2. The load line intersects the vertical axis at a point marked as I C . It is called transistor
saturation point. At this point the I C is maximum and the VCE is very small  0V  .
RC
Fig. 4.1(b)
Plotting of D.C Load line
To draw d.c load line, we need two end points of the straight line. These two points can
be located as follows:
We know that , VCE  VCC  I C R C …(1)
Case I: Cut-off point
When collector current I C  0 , then collector-emitter voltage is maximum and is equal
to VCC .
or
If I C  0, then VCEmax  VCC  0
 VCEmax  VCC …(2)
Thus we get point A known as cut- off point. The co-ordinates of A are:
VCE  VCC and I C  0 VCC ,0 

95
93
Case II: Saturation point

When collector emitter voltage VCE  0, the collector current is maximum and is equal
V
to CC . or
RC
 If VCE  0, then, 0  VCC  ICmax R C
V
 IC max  CC …(3)
RC
Thus we get point B known as saturation point. The co-ordinates of B are:
VCC  VCC 
VCE  0 and I C   0,  .
RC  RC 
These two points can be located on output characteristics, by joining points A and B we
get d.c load line as shown in fig. 4.1(b).
Operating Point or Q-Point
The zero signal values of I C and VCE is known as operating point or Q-point.
or
The point where the output characteristic and load line intersect is known as Q-point.
Suppose in the absence of signal, the base current is 8 μA . Then IC and VCE conditions
in the circuit may be represented by some point on I B  8 μA characteristic and d.c load line.
Referring to fig. 4.2(a) for I B  8 μA , the zero signal values are: VCEQ and I CQ . These values
fix up the operating point of the transistor and hence amplifier.
Fig.4.2(a)
Thus the operating point co-ordinates are VCEQ , I CQ  . Generally Q-point is located at
VCC
the midpoint of the d.c load line, so that VCEQ  .
2
*Note:
1. It is called operating point or working point because the variations of I C and VCE take
place about this point when signal is applied.
2. It is also called quiescent (silent) point because it is the point on output characteristics
when the transistor is silent i.e. in the absence of the signal.
Selection of operating point
The operating point can be selected at three different positions on the d.c load line: near
saturation region, near cut-off region or at the center, i.e. in the active region. Refer to fig.
YUVARAJ K, ASST.PROF, Department of ECE, SVEW Tirupathi Page

94
77
4.2 the selection of operating point will depend on its application. When transistor is used as
an amplifier, the Q point should be selected at the center of the d.c load line to prevent any
possible distortion in the amplified output signal. This is well-understood by going through
following cases.
Case - I
Biasing circuit is designed to fix a Q-point at a point P as shown in fig. 4.2(b). Point P
is very near to the saturation region. As shown in fig.4.2(b) the collector current is clipped at
the positive half cycle. So, even though base current varies sinusoidal, collector current is not
a useful sinusoidal waveform i.e. distortion is present at the output therefore, point P is not a
suitable operating point.
Fig.4.2(b)
Case - II
Biasing circuit is designed to fix a Q-point at point R as shown in fig. 4.2(c). Point R
is very near to the cut off region. As shown in fig.4.2(c) the collector current is clipped at the
negative half cycle. So, point R is also not a suitable operating point.
Case - III
Biasing circuit is designed to fix a Q-point at point Q as shown in fig.4.2(d). The
output signal is sinusoidal waveform without any distortion. Thus point Q is the best
operating point.
*Note:
1. For class A operation the Q-point is approximately at the midpoint of the load line.
2. For class B operation the Q-point is shifted on X-axis i.e. transistor is biased to cut-off.
3. For class C operation the Q-point is to be shifted below X-axis.
YUVARAJ K, ASST.PROF, Department of ECE, SVEW Tirupathi Page95

78
Fig.4.2(c)
Fig. 4.2(d)
A.C Load Line

This is the line on the output characteristics of a transistor circuit which gives the
values of i c and vce when signal is applied
To add a.c load line to the output characteristics, we again require two end points:

96
1. Maximum collector-emitter voltage point or cutoff point is,

 VCEmax  VCEQ  I CQ R ac
This locates the point C of the a.c load line on VCE axis.
2. Maximum collector current point or saturation point is,
VCEQ
 I Cmax  I CQ 
R ac
This locates the point D of a.c load line on I C axis. By joining points C and D the a.c
load line CD is constructed as shown in fig.4.3.
D.C load line (represented by AQB) is also drawn simultaneously in fig.4.3. It may be
seen that d.c and a.c load lines intersect the Q-point. The effective a.c load resistance ( R ac )
is the combination of R C parallel to R L i.e. R ac  R C R C . So the slope of the a.c load line
 1 
CQD will be    .
 R ac 
Fig.4.3
*Note: As R ac  R C a.c load is steeper than d.c load line.
Stabilization or Stability
The maintenance of the operating point stable is known as stabilization.
(or)
The process of making operating point independent of temperature changes or
variations in transistor parameters is known as stabilization.
There are two factors which are responsible for shifting the Q-point. Firstly, many of
the transistor parameters are temperature sensitive and secondly when a transistor is replaced
by another of the same type, there is a wide spread in the values of transistor parameters.
Need for Stabilization
The stabilization of the operating point is necessary due to the following reasons:
a) Temperature dependence of I C
b) Individual variations
c) Thermal runaway
a) Temperature dependence of IC:
The collector current I C  expression for CE circuit is given by,

I C  βI B  I CE0  βI B  1  β I CB0
Thus the collector current in a transistor changes due to the following reasons.
1. The collector leakage current I CB0 is greatly influenced by temperature changes. The
IC0 doubles for every 10 0 C rise in temperature.
2. Increase of β with increase of temperature.
3. Variation of VBE with temperature.
b) Individual Variations
When a transistor is replaced by another transistor of the same type the value of
β and VBE are not exactly the same. Hence the Q-point is changed. So it is necessary to
stabilize the Q-point irrespective of individual variations in transistor parameters.
c) Thermal runaway
Depending upon the construction of a transistor, the collector-base junction can
withstand a maximum temperature. The range of temperature lies between 60 0 C to 100 0 C
for Ge transistor and 150 0 C to 2250 C for Si transistor. If the temperature increases beyond
this range, then the transistor burns out.
The collector-base junction temperature may rise because of two reasons:
1. Due to rise in ambient temperature.
2. Due to self heating
The self heating can be explained as follows:
The increase in the collector current increases the power dissipation at the collector
junction. This in turn increases the temperature of the junction. If no stabilization is done,
the leakage current ICB0 increases.
Since I CE0  1  β I CB0 and I C  βI B  (1  β)ICB0 . The increase in I CB0 will cause I CE0 to
increase, which in turn increase the collector current I C . This further raise the temperature of
collector-base junction and whole cycle repeats again. Such a cumulative increase in I C will
ultimately burn out the transistor.
The self destruction of an un-stabilized transistor is known as thermal runaway.
Sequence of results shown in fig. 4.4.
Fig. 4.4
However, if the circuit is designed such that the base current ( I B ) is made to decrease
automatically with rise in temperature, then the decrease in βI B will compensate for the
increase in 1  β  I CB0 , keeping I C almost constant.
Stability Factor
The stability factor S is defined as the rate of change of collector current I C with
respect to collector leakage current ICB0 , keeping β and VBE constant.

dI C
 S
dICB0 β,VBE constant
Ideally stability factor should be zero. Practically the stability factor should be as low as
possible. Thus a high value of S indicates poor stability and low value of S indicates good
stability
General expression for Stability factor
For a CE configuration, the collector current expression is given as,
I C  βI B  I CE0
Or I C  βI B  1  β I CB0
Differentiating the above expression w.r.t I C , we get,
 1  β  CB0
dI B dI
1 β
dI C dI C
1  β B  1  β 
dI 1
dI C S
1 β
 S …(1)
 dI 
1  β B 
 dI C 
*Note:
1. The above equation can be considered as a standard equation for derivation of stability
factor of other biasing circuits.
2. The general procedure to obtain stability factor for various biasing circuits is as
follows:
Step1: Obtain the expression for I B .
dI B
Step2: Obtain and use it in equation (1) to get S.
dI C
Types of Biasing Circuits
The various methods of biasing a transistor are:
1. Fixed bias (also called base bias)
2. Collector to base bias (also called base bias with collector feedback)
3. Emitter bias (also called base bias with emitter feedback)
4. Voltage divider bias or universal bias or (also called self bias)
Fixed Bias or Base Resistor Method
Fig. 4.5(a) shows an NPN transistor connected in CE configuration with fixed bias. In
this method, a high resistance R B is connected between positive terminal of supply VCC and
base of the transistor. Here the required zero signal base current is provided by + VCC and it
flows through R B .
*Note:
1. In fig. 4.5(a) the base-emitter junction is forward biased because the base is positive
w.r.t emitter. By a proper selection of R B the required zero signal base current (and
hence I C  βI B ) can made to flow.
2. It should be remembered that if the transistor is PNP, then R B is connected between
negative terminal of supply VCC and base of the transistor.

99 82
Fig. 4.5(a) Fig. 4.5(b)
IC
RC
C
B VC VC
E
Fig. 4.5(c)
Circuit Analysis
Case I: Base Circuit
Let us consider the base circuit as shown in fig. 4.5(b).
Applying KVL to the base circuit, we get,
 VCC  I B R B  VBE  0
I B R B  VCC  VBE
V  VBE
 I B  CC …(1)
RB
The supply voltage VCC is of fixed value. Once the resistance R B is selected, I B is
also fixed hence this circuit is called fixed bias circuit.
Case II: Collector Circuit
Let us consider the collector circuit as shown in fig. 4.5(c). Applying KVL to the
collector circuit, we get,
VCC  I C R C  VCE  0
 VCE  VCC  IC R C … (2)
 I C R C  VCC  VCE
VCC  VCE
 IC  ... (3)
RC
Stability factor
1 β
The stability factor S is given by, S … (4)
 dI 
1  β B 
 dIC 

100 83
VCC  VBE
From equation (1), we have, IB 
RB
Differentiating the above equation w.r.t IC, we get,
dI B
0
dI C
Substituting this value in equation (4), we get,
S 1 β
Thus the stability factor in a fixed bias is 1 β  . If β  100 , then S=101. This shows
that I C changes 101 times as much as any change in I C0 . Due to the large value of S in a
fixed bias, it has poor thermal stability.
Advantages
1. The biasing circuit is very simple as only one resistance R B is required.
2. It is easy to fix the Q-point anywhere in active region by simply changing the value of
RB .
Disadvantages
1. This method provides poor stabilization. It is because there is no means to stop a self-
increase in collector current due to temperature rise and individual variations. For
example if β increases due to transistor replacement, then I C also increases by the
same factor as I B is constant.
2. The stability factor is very high. Therefore, there are strong chances of thermal
runaway.
*Note: Due to these disadvantages, this method of biasing is rarely employed.
Collector to Base Bias or Base Bias with Collector Feedback
The fig.4.6 shows collector to base bias circuit. This circuit is same as fixed bias circuit
except that the base resistor R B is connected between the collector and the base of
transistor. Thus I B flows through R B and I B  IC  flows through R C . Here the required zero
signal base current is determined not by VCC but by the collector base voltage VCB .
Fig. 4.6
Circuit Analysis
Let us consider the base circuit of fig. 4.6. Applying KVL to the base circuit, we get,
VCC  I B  I C R C  I B R B  VBE  0
VCC  I B R C  I C R C  I B R B  VBE  0 …(1)

101
I B R B  R C   VCC  I C R C  VBE

V  I R   VBE
I B  CC C C … (2)
RB  RC
Applying KVL to the collector circuit, we get,
 VCC  I B  IC R C  VCE  0 …(3)
VCC  I C R C  VCE  0 ( I C  I B )
VCE  VCC  I C R C …(4)
V  VCE
 IC  CC …(5)
RC
Special case:
Substituting the value of VCE from equation (4) in equation (2), we get,
VCE  VBE
 IB  …(6)
RB  RC
We know that, I C  βI B
βVCE  VBE 
 IC  …(7)
RB  RC
*Note:
1. The co-ordinates of the Q-point are determined by equations (4) and (5).
2. As R B is connected to collector i.e., output, the I B depends on collector voltage.
Therefore this circuit is also known as voltage feedback circuit.
Stability factor
1 β
The stability factor S is given by, S  …(8)
 dI 
1  β B 
 dI C 
VCC  I C R C  VBE
RB  RC
dI B  RC

dI C R B  R C
dI B
Substituting the value of in equation (8), we get,
dI C
1 β
S
 RC 
1  β 
 RB  RC 
This value is smaller than 1 β  , obtained for fixed bias circuit. Thus there is an
improvement in the stability. If R C is very small then S  1  β  . Hence the stability factor is
poor like fixed bias method hence R C must be quite large for good stabilization.
*Note: This method is not satisfactory for transformer coupled amplifier because R C is very
small.
Advantages
1. Simple circuit, as it requires R B only.
2. This circuit provides some stabilization of the Q-point.

102
Disadvantages
1. As R B is connected to collector terminal to provide d.c feedback it also provides a.c
feedback (negative feedback) which reduces the voltage gain (During the positive half
cycle of the signal, the collector current increases. The increased collector current
would result in greater voltage drop across R C . This will reduce the base current and
hence collector current).
2. The circuit is not very commonly used.
Emitter Bias or Base Bias with Emitter Feedback
The fig.4.7. Shows emitter bias circuit. It is an improvement over the fixed-bias
configuration. It is obtained by simply adding a resistor to the emitter terminal.
Circuit Analysis
 VCC  I BR B  VBE  I E R E  0
VCC  I BR B  VBE  I B  IC R E  0
I B R B  R E   VCC  IC R E  VBE
V  I R   VBE
 I B  CC C E …(1)
RB  RE
Fig. 4.7
 VCC  IC R C  VCE  I E R E  0
VCC  IC R C  VCE  I B  IC  R E  0
VCC  IC R C  VCE  IC R E  0 (I E  I C )
 VCE  VCC  (R C  R E ) IC …(2)
 IC ( R C  R E )  VCC  VCE
VCC  VCE
 IC  …(3)
RC  RE
*Note:
1. The co-ordinates of Q-point are determined by equations (2) and (3).
2. The RE is common to both input and output circuits and feedback is through this
resistor. The voltage feedback is proportional to IE. For this reason this circuit gets the
name current feedback circuit.
Stability factor
1 β
The stability factor S is given by, S …(4)
 dI 
1  β B 
 dI C 

103
VCC  VBE  I C R E
RE  RB
dI B 00RE RE
 
dI C RE  RB RE  RB
dI B
dI C
1 β
 S 
 RE 
1 β   
 RE  RB 
1 β

 RE 
1 β  
 RE  RB 
Advantages
1. It is simple bias circuit as it needs RB and RE only.
2. If the temperature is increased RE prevents the rising of collector current IC.
3. If a transistor is replaced by higher  transistor the IB and hence IC will fall. Therefore
this scheme has more stability (than fixed bias).
Disadvantages
1. It requires either a very high value of RE or very low value of RB. But a high value of
RE will necessary a high d.c source VCC . Also low values of RB will necessary a
separate low supply in the base circuit.
2. As RE is common to both input and output, there will be an a.c feedback also. This
reduces the voltage gain.
Potential divider bias or Self bias
A very commonly used biasing arrangement is voltage divider bias. The circuit
arrangement is shown in fig. 4.8(a). This is also known as universal bias stabilization circuit.
The name voltage-divider is derived from the fact that the resistors R1 and R2 form voltage
divider across VCC. The emitter resistance RE provides stabilization. The voltage developed
across R2 forward biases the base-emitter junction. This causes the base current and hence
collector current flows in the zero signal conditions.
Circuit Analysis
Method I: Approximate Analysis
Let current I1 flows through R1. As the base current IB is very small the current flowing
through R2 can also be taken as I1. The calculation of collector current IC is as follows:
The current I1 flowing through R1 and R2 is given by,
VCC
I1 =
R1  R 2
The voltage V2 developed across R2 can be determined by applying voltage divider
rule.
R2
 V2  VCC
R1  R 2
 VBE  VE  V2  0
VE  V2  VBE …(1)

87
 I E R E  V2  VBE
V  VBE
 IC  2 (  IE  IC ) …(2)
RE
Here IC is almost independent of transistor parameters and hence good stabilization is
achieved
Fig. 4.8(a)
 VCC ICRC  VCE IE RE  0
 VCE  VCC  I C R C  I E R E
VCE  VCC  IC R C  R E   I E  IC  …(3)
It may be noted that in equations (2) and (3) the  does not appear at all. Therefore the
variation of  will have no effect on Q-point. Hence Q-point is independent of beta ().
*Note: The equation (2) and (3) determines the co-ordinates of Q-point.
Method II: Exact Analysis
Applying Thevenins theorem to the input circuit of fig. 4.8(a).
Step 1: To find the Thevenins equivalent voltage considers the fig. 4.8(b).
Fig. 4.8(b) Fig. 4.8(c) Fig. 4.8(d)
The voltage across R2 is the Thevenins equivalent voltage Vth  .

 R2
Vth  VCC
R1  R 2

105
Step 2: To find Thevenins equivalent resistance (Rth) consider the fig. 4.8(d). Here Rth is the
parallel combination of R1 and R2.
R 1R 2
 R th  R 1 R 2 
R1  R 2
Step 3: Thevenins equivalent circuit of fig. 4.8(a) is shown in fig. 4.8(e).
Applying KVL to the base emitter circuit, we get,
 Vth  IB R th  VBE  IE RE  0
Vth  I B R th  VBE  ( I B  I C ) R E  0
I B (R th  R E )   Vth  I C R E   VBE
 IB 
 Vth  IC R E   VBE …(1)
R th  R E
Fig. 4.8(e)
Applying KVL to the emitter collector circuit, we get,
 VCC IC RC VCE  IE RE  0
 VCE  VCC  IC (R C  R E ) …(2)
VCC  VCE
 IC  …(3)
RC  RE
Stability factor
1 β
The stability factor S is given by, S …(4)
dI 
1 - β  B 
 dI C 
IB 
Vth  ICRE  VBE
From equation (1), we have,
Rth  RE
dI B  RE

dI C R th  R E
dI B
dI C
1 β
S
 RE 
1  β  
 R th  R E 
This expression shows that smaller is the value of Rth, better is the stability.

106
Advantages
1. Excellent stabilization.
2. IC and VBE are independent of  .
3. Increase in temperature will not affect the Q-point.
Disadvantages
1. Circuit is little complicated and need Thevenins theorem to do the calculations.
Comparison of Transistor Configurations
Sl.No Parameters Common Base Common Common
Emitter Collector
1. Input resistance Very Low Low High

2. Output resistance Very high High Low
3. Current gain Nearly unity High High
4. Voltage gain High High Nearly unity
5. Power gain High Very high Low
6. Phase reversal No Yes No
7. Input current IE IB IB
8. Output current IC IC IE
9. Input voltage applied Emitter & Base Base & Emitter Base &
between Collector
10. Output voltage taken Collector & Base Collector & Emitter &
between Emitter Collector
11. Current IC IC IE
= β= =
amplification factor IE IB IB
12. Applications As a input stage multi- For audio signal For impedance
stage amplifier amplification matching
FET BIASING
FIXED-BIAS CONFIGURATION
The simplest of biasing arrangements for the n-channel JFET appears in below
Figure. Referred to as the fixed-bias configuration, it is one of the few FET configurations
that can be solved just as directly using either a mathematical or graphical approach. Both
methods are included in this section to demonstrate the difference between the two
philosophies and also to establish the fact that the same solution can be obtained using either
method.

For D.C analysis

≅0
= = (0 ) = 0
The zero-volt drop across RG permits replacing RG by a short-circuit equivalent, as
appearing in the network of Figure specifically redrawn for the dc analysis.
The fact that the negative terminal of the battery is connected directly to the defined
positive potential of VGS clearly reveals that the polarity of VGS is directly opposite to that of
VGG. Applying Kirchhoff’s voltage law in the clockwise direction of the indicated loop of
Figure will result in
− − =0
=−
Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the notation
“fixed-bias configuration.”
The resulting level of drain current ID is now controlled by Shockley’s equation:
= (1 − )
Since VGS is a fixed quantity for this configuration, its magnitude and sign can simply be
substituted into Shockley’s equation and the resulting level of ID calculated. This is one of the
few instances in which a mathematical solution to a FET configuration is quite direct.
The drain-to-source voltage of the output section can be determined by applying Kirchhoff’s
voltage law as follows:
+ − =0
= −
Since VS=0
VDS=VD-VS
VD=VDS+VS
VD=VDS
In addition,
VGS=VG-VS
VG=VGS+VS
VG=VGS

SELF-BIAS CONFIGURATION
The self-bias configuration eliminates the need for two dc supplies. The controlling
gate-to-source voltage is now determined by the voltage across a resistor RS introduced in the
source leg of the configuration
For the dc analysis, the capacitors can again be replaced by “open circuits” and the
resistor RG replaced by a short-circuit equivalent since IG=0 A. The result is the network of
Figure for the important dc analysis.
The current through RS is the source current IS, but IS =ID and
=
− − =0
=−
=− (1)
Note in this case that VGS is a function of the output current ID and not fixed in magnitude as
occurred for the fixed-bias configuration. The above Equation is defined by the network
configuration, and Shockley’s equation relates the input and output quantities of the device.
Both equations relate the same two variables, permitting either a mathematical or graphical
solution.
A mathematical solution could be obtained simply by substituting Eq. 1 into
Shockley’s equation as shown below:
= (1 − )
−
= (1 − )
= (1 + )
By performing the squaring process indicated and rearranging terms, an equation of
the following form can be obtained:
+ + =0
The quadratic equation can then be solved for the appropriate solution for ID.

92
Let us now identify two points on the graph that are on the line and simply draw a
straight line between the two points. The most obvious condition to apply is ID=0 A since it
results in VGS=-IDRS =(0 A)RS=0 V.
One point on straight line is defined by ID=0A and VGS=0
The second point for Eq. (1) requires that a level of VGS or ID be chosen and the
corresponding level of the other quantity is determined using Eq.1. The resulting levels of ID
and VGS will then define another point on the straight line and permit an actual drawing of the
straight line.
Suppose, for example, that we choose a level of ID equal to one-half the saturation
level. That is,
=
2
−
=− =
2
The level of VDS can be determined by applying KVL to output circuit
+ + − =0
= − − = − −
But ID=IS
= − ( + )
In addition,
VS=IDRS
VG=0V
VD=VDS+VS=VDD-VRD
VOLTAGE-DIVIDER BIASING
The basic construction is exactly the same, but the dc analysis of each is quite
different. IG=0 A for FET amplifiers, but the magnitude of IB for common-emitter BJT
amplifiers can affect the dc levels of current and voltage in both the input and output circuits.
Recall that IB provided the link between input and output circuits for the BJT voltage-divider
configuration while VGS will do the same for the FET configuration.
Since IG =0 A, Kirchhoff’s current law requires that IR1 =IR2 and the series equivalent
circuit appearing to the left of the figure can be used to find the level of VG. The voltage VG,
equal to the voltage across R2, can be found using the voltage divider rule as follows:
=
+
Applying Kirchhoff’s voltage law in the clockwise direction to the indicated loop
− − =0
= −
And substituting = = , we have

= −

11093
The result is an equation that continues to include the same two variables appearing in
Shockley’s equation: VGS and ID. The quantities VG and RS are fixed by the network
construction.
Since any straight line requires two points to be defined, let us first use the fact that
anywhere on the horizontal axis of Figure the current ID =0 mA. If we therefore select ID to
be 0 mA, we are in essence stating that we are somewhere on the horizontal axis. The exact
location can be determined simply by substituting ID =0 mA into the above and finding the
resulting value of VGS as follows:
= −
= − (0)
=
For the other point, let us now employ the fact that at any point on the vertical axis VGS=0 V
and solve for the resulting value of ID:
= −
0= −
=
Increasing values of RS result in lower quiescent values of ID and more negative values of
VGS.
Once the quiescent values of IDQ and VGSQ are determined, the remaining network analysis
can be performed in the usual manner. That is,
= − ( + )
= − ( )
= ( )
= =
+
DEPLETION-TYPE MOSFETs
The similarities in appearance between the transfer curves of JFETs and depletion
type MOSFETs permit a similar analysis of each in the dc domain. The primary difference
between the two is the fact that depletion-type MOSFETs permit operating points with
positive values of VGS and levels of ID that exceeds IDSS. In fact, for all the configurations
discussed thus far, the analysis is the same if the JFET is replaced by a depletion-type

94
MOSFET. The only undefined part of the analysis is how to plot Shockley’s equation for
positive values of VGS. How far into the region of positive values of VGS and values of ID
greater than IDSS does the transfer curve have to extend? For most situations, this required
range will be fairly well defined by the MOSFET parameters and the resulting bias line of the
network. A few examples will reveal the impact of the change in device on the resulting
analysis.
ENHANCEMENT-TYPE MOSFETs
The transfer characteristics of the enhancement-type MOSFET are quite different
from those encountered for the JFET and depletion-type MOSFETs, resulting in a graphical
solution quite different from the preceding sections. First and foremost, recall that for the n-
channel enhancement-type MOSFET, the drain current is zero for levels of gate-to-source
voltage less than the threshold level VGS(Th), as shown in Figure. For levels of VGS greater than
VGS(Th), the drain current is defined by
= ( − ( ))
( ) = ( ( )− ( ))
( )
=
( ( )− ( ))
Feedback Biasing Arrangement
A popular biasing arrangement for enhancement-type MOSFETs is provided in Fig.
The resistor RG brings a suitably large voltage to the gate to drive the MOSFET “on.” Since
IG =0 mA and VRG =0 V, the dc equivalent network appears as shown in Fig. A direct
connection now exists between drain and gate, resulting in
VD=VG
VDS=VGS
For the output circuit
VGS=VDS=VDD-IDRD
VGS=VDD/(ID=0 mA)
ID=VDD/RD when VGS=0

112
Voltage-Divider Biasing Arrangement

A second popular biasing arrangement for the enhancement-type MOSFET appears in Figure.
The fact that IG =0 mA results in the following equation for VGG as derived from an
application of the voltage-divider rule:
=
+
Applying KVL
− − =0
= −
= −
For the output section
+ + − =0
= − − = − −
But ID=IS
= − ( + )

113
UNIT-IV
Solved Problems:
1. Determine the value of collector current and collector to emitter voltage for the voltage divider bias
circuit shown below. VCC = 10 V; R1 = 10 kΩ; R2 = 5 kΩ; RC = 1 kΩ; Re= 500 Ω. Assume VBE = 0.7V and
β = 100. 10M(June-2018)
=
=48.88
2. In the circuit show in figure transistor has β = 100 and VBE (active) = 0.6 V. Calculate the values of
R1 & R3 Such that collector current of 2 mA and VCE = 3 V.10M (Dec-2014)
1 114
= 2+0.02mA=2.02mA
(b)
=10-4888
=10-4.888-2.468
=2.64V
3. Find the stability factor of the circuit given below
2 115
4. For the circuit shown,calculate VE,IE,IC and VC.Assume VBE =0.7V
Since is not given, assume
5. Design a self-bias circuit for the following specifications
= 0.05mA+4 =4.05mA
Let
3 116
=12-2-3.167
=6.833V
UNIT- IV PART-A (2 MARKs QUESTIONS WITH ANSWERS)
1. What is meant by biasing a transistor?

Process of maintaining proper flow of zero signal collector current and collector emitter
voltage during the passage of signal. Biasing keeps emitter base junction forward biased and
collector base junction reverse biased during the passage of signal.
2. List the 3 sources of instability of collector current?
• Individual variations
• Temperature dependence of collector current
• Thermal runaway
3. What is the basic difference between bias compensation and stabilization?
Stabilization is the process of making operating point independent of temperature
variations or changes in transistor parameters using dc biasing circuits. In the case of
compensation technique, in order to stabilize the Q point, we use temperature sensitive devices
like diodes, thermistors, transistors instead of DC biasing circuits.
4. What are the various methods used for transistor biasing? Which one is popular?
• Base resistor method
• Biasing with feedback resistor
• Voltage divider bias
Voltage divider bias is wide popular because it offers excellent stabilization to the circuit.
5. Define Stability Factor?
The extent to which stabilize of the collector current is measured by the stability factors.
The stability factor is defined as the rate of change of collector current with respect to the
leakage current, holding both þ and VBE constant
6. List out the advantages and disadvantages of fixed bias method?
Advantages: the Stability of operating point is greatly improved when compared with
other circuits, low cost and simple circuits
Disadvantages: the stability is poor, when temperature changes, beta changes, and there
by collector current increases which leads to thermal run away.
7. What are the effects on the output signal if the operating point is not properly chosen?
If the operating point is not properly chosen then the transistor may driven into saturation
or cut-off during input voltage swing. As a result the output of the amplifier is clipped. In this
case the output is distorted.
8. What is the effect of change in temperature on the stability of operating point?
The reverse saturation current doubles for every 100 C rise in temperature. As a result
ICO increases which further increase collector current. That if the temperature is increased then
the collector current also increases shifting the operating point upwards. Now the operating point
is close to saturation than before. If we apply the input signal, the transistor may drive into
saturation during positive half cycle of the input signal which causes clipping in the output.
4 117
UNIT-IV PART-B Questions (10 Marks):
1. Why self bias technique is so popular? And derive its three stability factors. 10M (Nov/Dec-2016)
2. What is the difference between bias stabilization & bias compensation? And also explain any
two methods of bias compensation. 10M (Nov/Dec-2016)
3. (a) Design a common emitter BJT circuit with self bias and then explain its operation. 5M
(b) Derive the expression for stability factor S of self bias circuit. 5M (Nov/Dec-2017)
4. List out different FET biasing methods and then explain the same. 10M (Nov/Dec-2017)
5. (a) What is DC load line and AC load line? Explain the criteria for fixing operating point. 5M
(b) Discuss about self bias circuit and derive expression for stability factor. 5M (June-2017)
6. (a) Discuss about collector to base bias circuit and derive expression for stability factor. 5M
(b) Briefly explain about FET biasing. 5M (June-2017)
7. (a) Obtain stability factor. 4M
(b) Distinguish thermal runaway and thermal stability. 6M (Nov/Dec-2018)
8. (a) What is meant by thermal run-away? Briefly explain. 5M
(b) Draw the circuit diagram of a collector to base bias circuit of CE amplifier and derive an
expression for S. 5M (Nov/Dec-2018)
9. What is a biasing circuit? Explain the fixed bias and collector to base bias circuits in detail. 10M (June-2017)
10. Determine the value of collector current and collector to emitter voltage for the voltage divider bias
circuit shown below. VCC = 10 V; R1 = 10 kΩ; R2 = 5 kΩ; RC = 1 kΩ; Re= 500 Ω. Assume VBE =
0.7V and β = 100. 10M (June-2018)
11. In the circuit show in figure transistor has β = 100 and VBE (active) = 0.6 V. Calculate the values of
R1 & R3 Such that collector current of 1 mA and VCE = 2.5 V. 10M (Dec-2014)
12. For the improvement of stability of the operating point what suggestions you would like to give
for self-bias. Discuss with the help of stability factors. 10M (Dec-2014)
13. (a) Explain how biasing is provided to a transistor through potential divider bias. 5M
(b). An NPN transistor with is used in Common Emitter configuration with VCC = 10 V and RC =
2.2 kΩ. Biasing is done through a 100 kΩ resistance from collector-to-base. Assuming VBE to be
zero volts. Find: (i) The quiescent point. (ii) The stability factor S. 5M (Dec-2015)
5 118
14. Describe the significance of operating point, DC and AC load lines to ensure active region
operation of a BJT in CE configuration. 10M (Dec-2015)
15. (a) Derive the expression for IC versus IB for a CE transistor configuration in the active region. 5M
(b)for IB = 0, what is IC. 5M (June-2015)
16. In the voltage divider bias circuit, if VCC = 10 V, VCE = 5 V, IC = 1.2 mA, R2 = 10 kΩ, β = 100
and RE = 270Ω calculate R1 and R3. Assume VBE (active) = 0.6V. 5M (June-2015)
17. (a) Explain the criteria for fixing the operating point. 5M
(b) What are the drawbacks of transistor fixed bias circuits? 5M
18. (a) Derive an expression for stability factor ‘S’ in self bias circuit. 8M
(b) Define stability factor. 2M
19. (a) How self bias circuit will eliminate drawbacks in fixed bias circuit? 5M
(b) Explain collector to base bias circuit. 5M
20. (a) Explain diode compensation circuit for variations in VBE for self bias circuit. 5M
(b)Explain diode compensation circuit for variations in IC for self bias circuit. 5M
21. (a) In an NPN transistor if β=50 is used in common emitter circuit with VCC=10V and
RC=2KΩ. The bias is obtained by connecting 100KΩ resistor from collector to base. Find
the operating point. 5M
(b) Derive an expression for stability factor ‘S’ in fixed bias circuit. 5M
23. (a) Derive an expression for stability factor ‘S’ in Collector to Base bias circuit. 8M
(b) Define Q-point? 2M
24. (a) Explain about DC load line & AC load line. 5M
(b).the circuit show in figure transistor has β = 100 and VBE (active) = 0.6 V. Calculate the values of
R1 & R3 Such that collector current of 1 mA and VCE = 2.5 V. 5M
6 119
UNIT-V
BJT: Small Signal Low Frequency Transistor Amplifier Models
Introduction
In “Electronics”, small signal amplifiers are commonly used devices as they have the
ability to amplify a relatively small input signal, for example from a Sensor such as a photo-
device, into a much larger output signal to drive a relay, lamp or loudspeaker for example.
There are many forms of electronic circuits classed as amplifiers, from Operational
Amplifiers and Small Signal Amplifiers up to Large Signal and Power Amplifiers. The
classification of an amplifier depends upon the size of the signal, large or small, its physical
configuration and how it processes the input signal that is the relationship between input
signal and current flowing in the load.
In several situations, a signal picked up from a source may be too feeble to use it as it
is. It has to be magnified before it is put in use. For example, a microphone converts audio
signal into electrical signal. The output of microphone is in the order of mV or μV . If it
directly fed to the loud speaker no sound will be heard, because the weak signal is not able to
drive the loud speaker. So that it has to be magnified or amplified before it is fed to loud
speaker. The loud speaker converts electrical signal into audio signal. The function of
magnifying or amplifying the amplitude of a weak is known as amplification.
or
The process of strengthening of a weak signal is known as amplification.
A system which has the capability to amplify a given signal is known as an amplifier. A
system that amplifies voltage or current also amplifies power. This is an important
characteristic of an amplifier. One may think a transformer as an amplifier but, it can amplify
either voltage or current only but not both. That is a transformer cannot amplify the power.
This is the major difference between a transformer and an amplifier. The amplifiers can be
designed to amplify signals of any amplitude and frequency.
Note: The process of strengthening of a weak signal without any change in it general shape is
known as faithful amplification.
Classification of Amplifiers
Amplifiers are classified in different ways depending on their mode of operation.
Several factors are taken into account in making a classification. Some of the classifications
are as follows:
I. Based on Magnitude of Input
1. Small signal amplifiers
2. Large signal amplifiers

120
II. Based on Primary function

1. Voltage amplifier
2. Current amplifier
3. Power amplifier
III. Based on Frequency
1. Audio frequency (AF) amplifiers
2. Video frequency (VF) amplifiers
3. Intermediate frequency (IF) amplifiers
4. Radio frequency (RF) amplifiers
IV. Based on Conduction Angle
1. Class A amplifier
2. Class B amplifier
3. Class C amplifier
4. Class AB amplifier
V. Based on Coupling
1. RC coupled amplifiers
2. LC coupled amplifiers
3. Transformer coupled amplifiers
4. Direct coupled amplifiers
VI. Based on Number of Stages
1. Single stage amplifiers
2. Multistage amplifiers
VII. Based on Ground connection
1. CE amplifier
2. CB amplifier
3. CC amplifier
VIII.AC Small-signal analysis
 DC Analysis serves to establish the Q-point of the network
 The signal fed into an amplifier is AC
 Transistor network amplifies AC signal accordingly
 Actually, signal has AC and DC components, but we treat signal as AC only
 Small signal analysis: considers only small fluctuations / oscillations
Bipolar Junction Transistor Models
 Re model
 Hybrid model
HYBRID PARAMETER BJT MODEL
The circuit of the basic two port network is shown on the right. Depending on the application,
it may be used in a number of different ways to develop different models. We will use it to
develop the h-parameter model. Other models may be covered in EE III. The h-parameter
model is typically suited to transistor circuit modelling. It is important because:
1. its values are used on specification sheets
2. it is one model that may be used to analyze circuit behaviour

99
3. it may be used to form the basis of a more accurate transistor model
Short Circuit Input Impedance

h11 = ZIN with output shorted <Ω>
h11 = vi/ii
1. Short terminals 2 2’
2. Apply test source Vi to terminal 1 1’
3. Measure Ii
4. Calculate h11
Open Circuit Reverse Transfer Ratio

h12 <dimensionless>
h12 = vi/v0
1. Open terminals 1 1’
2. Apply test source V2 to terminal 2 2’
3. Measure Vi
4. Measure Vo
5. Calculate h12
Short Circuit Forward Transfer Ratio
h21 = <dimensionless>
h21 = I0/Ii
1. Short terminals 2 2’
2. Apply test source Vi to terminal 1 1’
3. Measure Ii
4. Measure Io
5. Calculate h21
Open Circuit Output Admittance

h22 <Siemans>
h22 = I0/V0
1. Open terminals 1 1’
2. Apply test source V2 to terminal 2 2’
3. Measure Io
4. Measure Vo
5. Calculate h22
The h parameter model has values that are complex numbers that vary as a function
of: 1. Frequency 2. Ambient temperature 3.Q-Point The revised two port network for the h
parameter model is shown on the right. At low and mid-band frequencies, the h parameter

122
values are real values. Other models exist because this model is not suited for circuit analysis
at high frequencies. The h-parameter model is defined by
V1 = h11I1 + h12V2 (KVL)

I2 = h21I1 + h22V2 (KCL)
The h-parameter model for the common emitter circuit is on the right. On spec sheet:
h11 = hix
h12 = hrx
h21 = hfx
h22 = hox
hrx and hfx are dimensionless ratios
hix is an impedance <Ω>
hox is an admittance <S> where x = lead based on circuit configuration e = emitter for
common emitter c = collector for common collector b = base for common base
Determination of h-parameters
Performance of a Linear Circuit in h Parameters
(i) Input impedance. Zin=v1/i1
Now v1 = h11 i1 + h12 v2 in terms of h parameters. Substituting the value of v1 in the
above expression, we get,
Zin= h11I1 +h12V2 /I1
=h11+h12V2 /I1
Now, i2 = h21 i1 + h22 v2 in terms of h parameters.

Further from Figure, it is clear that i2 =– v2/rL. The minus sign is used here because
the actual load current is opposite to the direction of i2.
– v2/rL= h21 i1 + h22 v2
–h21 i1= h22 v2+ v2/rL
–ℎ
2/ 1 =
1
ℎ +
This is the expression for input impedance of a linear circuit in terms of h parameters
and load connected to the output terminals. If either h12 or rL is very small, the second term in
exp. (iii) can be neglected and input impedance becomes:
Zin = h11

123
(ii) Current Gain

The current gain Ai of the circuit is given by
=
=ℎ +ℎ
=−
=ℎ −ℎ
(1 + ℎ )=ℎ
ℎ
=
1+ℎ
(iii) Voltage gain
=
=
While developing expression for input impedance, we found that:
−ℎ
=
1
ℎ +
Substituting the value of in the above expression, we get
−ℎ
=
1
(ℎ + )
(iv) Output impedance
With v1=0 and applying KVL to the input circuit, we have,
0= ℎ +ℎ
ℎ
=−
ℎ
Now
= ℎ +ℎ
Zout=v2/i2
putting the value of = − in this equation, we get,
ℎ
= ℎ (− )+ℎ
ℎ
Dividing throughout by v2, we have,
ℎ ℎ
=− +ℎ
ℎ
1
=
ℎ ℎ
ℎ −
ℎ

124
The h Parameters of a Transistor

It has been seen in the previous sections that every linear circuit is associated with h
parameters. When this linear circuit is terminated by load rL, we can find input impedance,
current gain, voltage gain, etc. in terms of h parameters. Fortunately, for small a.c. signals,
the transistor behaves as a linear device because the output a.c. signal is directly proportional
to the input a.c. signal. Under such circumstances, the a.c. operation of the transistor can be
described in terms of h parameters. The expressions derived for input impedance, voltage
gain etc. in the previous section shall hold good for transistor amplifier except that here rL is
the a.c. load seen by the transistor.
V1 = h11I1 + h12V2 (KVL)

I2 = h21I1 + h22V2 (KCL)
The following points are worth noting while considering the behaviour of transistor in
terms of h parameters:
i. For small a.c. signals, a transistor behaves as a linear circuit. Therefore, its a.c. operation
can be described in terms of h parameters.
ii. The value of h parameters of a transistor will depend upon the transistor connection (i.e.
CB, CE or CC) used. For instance, a transistor used in CB arrangement may have h11 =
20 Ω. If we use the same transistor in CE arrangement, h11 will have a different value.
Same is the case with other h parameters.
iii. The expressions for input impedance, voltage gain etc. derived are also applicable to
transistor amplifier except that rL is the a.c. load seen by the transistor i.e.
rL = RC || RL
iv. The values of h parameters depend upon the operating point. If the operating point is
changed, parameter values are also changed.
v. The notations v1, i1, v2 and i2 are used for general circuit analysis. In a transistor
amplifier, we use the notation depending upon the configuration in which transistor is
used. Thus for CE arrangement,
v1 = Vbe ; i1 = Ib ; v2 = Vce ; i2 = Ic
Here Vbe, Ib, Vce and Ic are the R.M.S. values.
Nomenclature for Transistor h Parameters
Transistor Circuit Performance in h Parameters

(i) Input impedance
The general expression foe the input impedance is
ℎ ℎ
=ℎ −
ℎ +1

125
Using standard h parameter nomenclature for transistor, its value for CE arrangement will be:
ℎ ℎ
=ℎ −
ℎ +1
Similarly, expressions for input impedance in CB and CC arrangements can be
written. It may be noted that rL is the a.c. load seen by the transistor.
(ii) Current gain
ℎ
= =
1+ℎ
Using standard transistor h parameter nomenclature, its value for CE arrangement is
ℎ
= =
1+ℎ
In the same way, expressions for voltage gain in CB and CC arrangement can be written
(iii) Voltage gain
−ℎ
=
1
(ℎ + )
−ℎ
=
1
(ℎ + )
In the same way, expressions for voltage gain in CB and CC arrangement can be
written
The general expression for output impedance is
1
=
ℎ ℎ
ℎ −
ℎ
1
=
ℎ ℎ
ℎ −
ℎ
In the same way, expression for output impedance in CB and CC arrangements can be
written. The above expression for Zout is for the transistor. If the transistor is connected in a
circuit to form a single stage amplifier, then output impedance of the stage = Zout || rL
Where rL = RC || RL.
Approximate Hybrid Formulas for Transistor Amplifier
The h-parameter formulas (CE configuration) covered can be approximated to a form
that is easier to handle. While these approximate formulas will not give results that are as
accurate as the original formulas, they can be used for many applications.
(i) Input impedance
ℎ ℎ
=ℎ −
ℎ +1
In actual practice, the second term in this expression is very small as compared to the
first term.
Zin = hie ... approximate formula
(ii) Current gain
ℎ
= =
1+ℎ

126
In actual practice, hoe rL is very small as compared to 1.

Ai = hfe ... approximate formula
(iii) Voltage gain
−ℎ
=
1
(ℎ + )
Now approximate formula for Zin is hie. Also hoe rL is very small as compared to 1.
−ℎ
=
ℎ
1
=
ℎ ℎ
ℎ −
ℎ
The second term in the denominator is very small as compared to hoe.
1
=
ℎ
The output impedance of transistor amplifier = Zout || rL
Where *rL = RC || RL
* If the amplifier is unloaded (i.e. RL = infinity∞), rL = RC.
CE Configuration as a Two Port Network (or) Equivalent Circuit for CE Configuration
Figure 5.1 shows the transistor connected in common emitter (CE) configuration. In
CE configuration, the input is applied between base and emitter and output is taken across
collector and emitter. Therefore V1 and I1 become Vbe and I b respectively, and at the
output port V2 and I 2 become Vce and Ic respectively.
Fig 5.1
The input voltage Vbe  and the output current Ic  are given by the following
equations:
Vbe  h ie I b  h re Vce … (1)
I c  h fe I b  h oe Vce … (2)
Note: The quantities ΔVBE Vbe , ΔVCE Vce  , ΔI B I b and ΔI C I c  represent the small change in
base and collector voltages and currents.
In equation (1) each term has the unit of voltage. Hence using KVL we get the
equivalent circuit shown in fig.5.1.
In equation (2) each term has the unit of current. Hence using KCL we get the
equivalent circuit shown in fig.5.2.
If the two circuits shown in fig.5.1 and 5.2 are combined, we get the complete h-
parameter equivalent circuit for CE configuration as shown in fig.5.3.

127
Ib hie Ic
Vbe hreVce hfeIb hoe Vce
Fig 5.1 Fig 5.2

Ib hie Ic
Vbe hreVce hfeIb hoe Vce
Fig 5.3
Limitations of h Parameters
The h parameter approach provides accurate information regarding the current gain,
voltage gain, input impedance and output impedance of a transistor amplifier. However, there
are two major limitations on the use of these parameters.
i. It is very difficult to get the exact values of h parameters for a particular transistor. It is
because these parameters are subject to considerable variation—unit to unit variation,
variation due to change in temperature and variation due to change in operating point. In
predicting an amplifier performance, care must be taken to use h parameter values that
are correct for the operating point being considered.
ii. The h parameter approach gives correct answers for small a.c. signals only. It is because
a transistor behaves as a linear device for small signals only.
Complete hybrid equivalent model-
Consider the general configuration of Figure with the two-port parameters of
particular interest. The complete hybrid equivalent model is then substituted in Figure using
parameters that do not specify the type of configuration. In other words, the solutions will be
in terms of hi, hr, hf, and ho

128
Current gain, =
Applying KVL to the output circuit yields
=ℎ + = ℎ +ℎ
Substituting = − gives
=ℎ −ℎ
Re writing the equation above, we have
+ℎ =ℎ
(1 + ℎ )=ℎ
So that = =
Note that the current gain will reduce to the familiar result of Ai =hf if the factor hoRL
is sufficiently small compared to 1.
Voltage gain
=
Applying KVL to the input circuit yields
=ℎ +ℎ
Substituting = (ℎ + 1) /ℎ and I0= -Vo/RL from above result
= −ℎ ((ℎ + 1) /ℎ ) + ℎ
Solving for the ratio V0/Vi yields
−ℎ
= =
ℎ + (ℎ ℎ − ℎ ℎ )
In this case, the familiar form of = returns if the factor (ℎ ℎ − ℎ ℎ ) is
small compared to hi
Input impedance, Zi=Vi/Ii
=ℎ +ℎ
=−
=ℎ −ℎ
=
Io=AiI
So that the equation above becomes
=ℎ −ℎ
Solving for the ratio Vi/Ii, we obtain
Vi/Ii = ℎ − ℎ
And substituting
ℎ
= =
1+ℎ
Yields = = ℎ −
The familiar form Zi=hi is obtained if the second factor in the denominator h0RL is
smaller than one.
Output impedance =
The output impedance of an amplifier is defined to be the ratio of the output voltage
to the output current with the signal Vs set to zero. For the input circuit with Vs=0,
ℎ
=−
+ℎ

129
Substituting this relationship into the following equation obtained from the output
circuit yields
=ℎ +ℎ
ℎ ℎ
=− +ℎ
+ℎ
And = =
In this case, the output impedance will reduce to the familiar form Zo=1/ho for the transistor
when the second factor in the denominator is sufficiently smaller than the first.
APPROXIMATE HYBRID EQUIVALENT CIRCUIT
Fixed-Bias Configuration
ℎ
=
+ℎ
1
( )
ℎ
=
1
+
ℎ
1
ℎ ( )
ℎ
1
+
ℎ
=−
ℎ
= =ℎ

130
Voltage-Divider Configuration
With =
= ‖ ′
=‖ ‖ℎ
=
−ℎ ( ‖1/ℎ )
=
ℎ
−ℎ ′
=
ℎ + ′
Un bypassed Emitter-Bias Configuration
≅ℎ
= ‖
=
−ℎ
=
−ℎ ( )
=
+
Emitter-Follower Configuration
≅ℎ
= ‖

ℎ
= ‖
1+ℎ
Because 1 + ℎ ≅ ℎ
ℎ
= ‖
ℎ
For the voltage gain, the voltage divider rule can be applied
( )
=
+ ℎ /(1 + ℎ )
But, since 1 + ℎ ≅ ℎ
=
+ ℎ /ℎ
ℎ
=
+
=−
Common Base configuration
=ℎ ‖
Z0=RC
=− = −(ℎ )
With = and = −ℎ

132
ℎ
=−
ℎ
=ℎ ≅1
FET Small-Signal Analysis
Field-effect transistor amplifiers provide an excellent voltage gain with the added
feature of high input impedance. They are also considered low-power consumption
configurations with good frequency range and minimal size and weight. Both JFET and
depletion MOSFET devices can be used to design amplifiers having similar voltage gains.
The depletion MOSFET circuit, however, has a much higher input impedancethan a similar
JFET configuration.
While a BJT device controls a large output (collector) current by means of a relatively
small input (base) current, the FET device controls an output (drain) current by means of a
small input (gate-voltage) voltage. In general, therefore, the BJT is a current-controlled
device and the FET is a voltage-controlled device. In both cases, however, note that the
output current is the controlled variable. Because of the high input characteristic of FETs, the
ac equivalent model is somewhat simpler than that employed for BJTs.
The ac analysis of an FET configuration requires that a small-signal ac model for the FET be
developed. A major component of the ac model will reflect the fact that an ac voltage applied
to the input gate-to-source terminals will control the level of current from drain to source.
FET AC Equivalent Circuit
The control of Id by Vgs is included as a current source gmVgs connected from drain to
source as shown in Fig.
The current source has its arrow pointing from drain to source to establish a 180°
phase shift between output and input voltages as will occur in actual operation.
The input impedance is represented by the open circuit at the input terminals and the
output impedance by the resistor rd from drain to source. Note that the gate to source voltage
is now represented by Vgs(lower-case subscripts) to distinguish it from dc levels. In addition,
take note of the fact that the source is common to both input and output circuits while the gate
and drain terminals are only in “touch” through the controlled current source gmVgs.
In situations where rd is ignored (assumed sufficiently large to other elements of the
network to be approximated by an open circuit), the equivalent circuit is simply a current
source whose magnitude is controlled by the signal Vgs and parameter gm—clearly a voltage-
controlled device.
JFET FIXED-BIAS CONFIGURATION
Zi=RG because of the open-circuit equivalence at the input terminals of the JFET.
Z0Setting Vi =0 V as required by the definition of Zo will establish Vgs as 0 V also. The result
is gmVgs=0 mA, and the current source can be replaced by an open-circuit equivalent as
shown in Figure
= ‖

133
If the resistance rdis sufficiently large (at least 10:1) compared to RD, the
approximation ‖ ≅ can often be applied and
≅
Solving for Vo, we find = − ( ‖ )
=
=− ( ‖ )≅−
JFET SELF-BIAS CONFIGURATION
Bypassed RS
The fixed-bias configuration has the distinct disadvantage of requiring two dc voltage
sources. The self-bias configuration of Figure requires only one dc supply to establish the
desired operating point.
The above circuit redrawn as
= ‖
If the resistance rd is sufficiently large (at least 10:1) compared to RD, the
approximation ‖ ≅ can often be applied and
≅
Solving for Vo, we find = − ( ‖ )
=
=− ( ‖ )≅−
JFET VOLTAGE-DIVIDER CONFIGURATION

134
Substituting the ac equivalent circuit of FET as shown in the figure below
= ‖
Setting Vi=0 sets Vgs and Vgsgm to zero, and
= ‖
≅
=− ( ‖ )
=− ( ‖ )/
=
=− ( ‖ )≅−
JFET SOURCE-FOLLOWER (COMMON-DRAIN) CONFIGURATION

135
DEPLETION-TYPE MOSFETs
The fact that Shockley’s equation is also applicable to depletion-type MOSFETs
results in the same equation for gm. In fact, the ac equivalent model for D-MOSFETs is
exactly the same as that employed for JFETs The only difference offered by D-MOSFETs is
that VGSQ can be positive for n-channel devices and negative for p-channel units. The result
is that gmcan be greater than gm0 as demonstrated by the example to follow. The range of
rdis very similar to that encountered for JFETs.
Enhancement MOSFETS
The enhancement-type MOSFET can be either an n-channel (nMOS) or p-channel
(pMOS) device, as shown in Fig.The ac small-signal equivalent circuit of either device is
shown in Figure, revealing an open-circuit between gate and drain source channel and a
current source from drain to source having a magnitude dependent on the gate-to-source
voltage.
E-MOSFET VOLTAGE-DIVIDER CONFIGURATION
= ‖
Setting Vi=0 sets Vgs and Vgsgm to zero, and
= ‖ ≅
=− ( ‖ )
=− ( ‖ )/
=
=− ( ‖ )≅−

136
UNIT-V
Solved Problems:
1. A CB amplifier is driven by a voltage source of internal resistance RS = 1 kΩ. The load

impedance is RL=1KΩ. The transistor parameters are hib = 22 Ω, hfb = -0.98, hrb = 2.9 x 10-4,
hob = 0.5μA/v. Compute current gain, voltage gain, input and output Impedance of the amplifier.
(5M)
Solution:
Given data:- RS = 1 kΩ, RL=1KΩ, hib = 22 Ω, hfb = -0.98, hrb = 2.9 x 10-4, hob = 0.5μA/v, AI = ?,
AV = ?, RI = ? and RO=?
AI = = = 0.653
RI = hib + hrbAIRL = 22+2.9X10-4X0.65X1KΩ = 22.188Ω
AV = AIRL/RI = 30
= 0.5x10-6- =0.5x10
-6
+ = 0.5X10
-6
+ 0.290
Yo = =7.78X10-7 mhos
RO = 1/YO = 1/=7.78X10-7 = 1.2M Ω
2. A transistor used in a common base configuration has the following h-parameters: 10M
calculate the values of input
resistance, output resistance, current gain and voltage gain, if the load resistance is 1.2 kΩ.
Assume source resistance as zero. (June-2018)
Solution:
Given data:- RS = 0Ω, RL=1.2KΩ, hib = 28 Ω, hfb = -0.98, hrb = 5 x 10-4, hob = 0.3μJ, AI = ?, AV =
?, RI = ? and RO=?
AI = = = 0.49
RI = hib + hrbAIRL = 28+5X10-4X0.49X1.2KΩ = 28.3Ω
AV = AIRL/RI = 0.49X1.2KΩ/28.3Ω =20.78

= 0.3x10-6- =0.3x10
-6
+ = 0.3X10
-6
+ 3.99X10-7
Yo = =6.99X10-7 mhos
RO = 1/YO = 1/=6.99X10-7 = 1.4M Ω
1137
3. For the transistor amplifier shown in below figure, compute AI = I0/Ii, AV, AVS and Ri. assume
hie=1100Ω, hfe=50, hre=2.5x10-4, hoe=24µA/V.(given in notes)
Solution:
Given Data:- hie=1100Ω, hfe=50, hre=2.5x10-4, hoe=24µA/V

Assume RL=1KΩ
AI = = = 49.01
RI = hie + hreAIRL = 1100+2.5X10-4X49.01X1KΩ = 1.1KΩ
AV = AIRL/RI = 49X1K/1.1K = 44.54

AVS = = = 40.49
UNIT- V PART-A (2 MARKS QUESTIONS WITH ANSWERS)

1. What is an amplifier?
• Amplifier raises the level of a weak signal.
• No change in the wave shape.
• No change in the frequency of the input signal
2. Why we need Amplification?
• The signal is generally the o/p of a transducer like microphone, thermo couple.
• It is very weak.
• It must be amplified before feeding to the loud speaker etc.
3. Which configuration is best suited as an amplifier?
C.E. Configuration
4. Why C.E. Configuration is commonly used?
• Its input and output impedances are suitable in many applications.
• It offers current gain, voltage gain, power gain.
5. Which parameters determine the operating conditions of a transistor?
The operating conditions of a transistor are determined by
• VCE collector to emitter voltage
• IC collector current
• The value of IC for a given VCE can be known from output characteristics of a
transistor and From D.C. Load Line
6. What is a D.C. Load Line?
It is a graph drawn between collector current IC and collector to emitter voltage
VCE for a given VCC and RC.
7. What is operating point?
It is a point on the DC load line which specifies collector current IC and collector
emitter voltage VCE that exist when no signal is applied.
8. Which parameter determines the output impedance of most FET configurations?
The output impedance for most FET configurations determined primarily by
RD. for the source follower it is determined by Rs and gm.
9. Define Tranconductance gm?
Tranconductance parameter is determined by the ratio of change in drain current
2 138
associated with a particular change in gate to source voltage in the region of interest.
10. How to obtain ac equivalent of a network?
• Setting all dc sources to zero and replacing them by a short-circuit equivalent
• Replacing all capacitors by a short-circuit equivalent
• Removing all elements bypassed by the short-circuit equivalents introduced by steps
1 and 2
• Redrawing the network in a more convenient and logical form
11. Which configurations having very low input impedance?
The common base configuration has very low input impedance, but it can have a
significant voltage gain. The current gain is just less than one, and the output impedance
is simply RC.
12. List out the advantages of h-parameters.
• H-parameters are real numbers at audio frequencies.
• These are easy to measure.
• H-parameter can also be obtained from the transistor static characteristic curves.
• H-parameters are convenient to use in circuit analysis and design.
• A set of h-parameters is specified for many transistors by the manufacturers
13. Draw the h-parameter circuit and its equivalent circuit in CE configuration.
14. What is the different analysis available to analyze a transistor?

Hybrid parameter model and re model
15. How are amplifiers classified according to the input?
Small signal amplifiers and large signal amplifiers
16. What is miller’s theorem?
The miller’s theorem refers to the process of creating equivalent circuits. It asserts
that a floating impedance element, supplied by two voltage sources connected in series,
may be split into two grounded elements with corresponding impedances.
17. Define small signal amplifier?
When the input signal of an amplifier is relatively weak and generates amplified
output signal, the amplifier is called small signal amplifier or voltage amplifier.
18. What are the limitations of h-parameters?
As temperature changes, h parameters may also vary.
UNIT-V PART-B Questions (10 Marks):

1. Discuss generalized analysis of transistor amplifier model using h-parameters. 10M (Nov/Dec-2016)
2. Discuss generalized analysis of FET amplifier model using small signal model. 10M (Nov/Dec-2016)
3. By performing generalized analysis of transistor amplifier, derive the expression for different gains and
impedances. 10M (Nov/Dec-2017)
4. (a) Design and analyze common source JFET amplifier for its gains and impedances. 6M
(b) Compare CE, CB and CC amplifiers. 4M (Nov/Dec-2017)
5. (a) Describe the determination of h-parameters of a transistor. 5M
(b) Draw the basic CE amplifier circuit and its equivalents h-parameter model. Derive an expression for
3
139
its Ri and Ro. 5M (June-2017)

6. (a) Draw the CS amplifier with self-bias and bypass resistor Rs. Derive the expressions for Ri, Av, Ro,
using its equivalent circuit. 5M
(b) Explain about relation between h-parameters of CE, CB and CC configurations. 5M (June-2017)
7. (a) A CB amplifier is driven by a voltage source of internal resistance RS = 1 kΩ. The load impedance is
RL=1KΩ. The transistor parameters are hib = 22 Ω, hfb = -0.98, hrb = 2.9 x 10-4, hob = 0.5μA/v.
Compute current gain, voltage gain, input and output Impedance of the amplifier. 5M
(b) Explain the method of evaluating h-parameter for a transistor in CC configuration. 5M (Nov/Dec-
2018)
8. Compare FET amplifiers in detail. 10M (Nov/Dec-2018)
9. A transistor used in a common base configuration has the following h-parameters: 10M
Calculate the values of input resistance,
output resistance, current gain and voltage gain, if the load resistance is 1.2 kΩ. Assume source resistance
as zero. (June-2018)
10. (a) Find the values of hfb and hfc if the values of hfe of a transistor is 50. 5M
(b) Write the conversion formulae for common base configuration from the common emitter h-
parameter values. 5M (June-2018)
11. Given IE = 2.5 mA, hfe = 140, hoe = 20 μs and hob = 0.5 μs determine: 10M
(a) The common- emitter hybrid equivalent circuit. (b) The common base re model.(Dec-2014)
12. (a) List out the typical values of h-parameters in the three BJT configurations (CE, CB and CC). 5M
(b) Describe how hie and hfe can be determined from characteristics. 5M (Dec-2015)
13. Draw the basic circuit and small-signal model of Common drain FET amplifier. Derive the expressions
for voltage gain and output resistance. 10M (Dec-2015)
14. (a) Derive the expression for AV in terms of AI. 5M
(b) In terms of the h parameters and the source resistance, derive the equation for the output admittance.
5M (June-2015)
15. Find hre in terms of the CB h parameters. 10M (June-2015)
4 140
www.Uandistar.blogspot.com Page No. 1
ELECTRONIC DEVICES AND CIRCUITS

BRIEF NOTES
SEE WWW.UANDISTAR.BLOGSPOT.COM FOR MORE JNTU
MATERIALS UNIT – I :: ELECTRON DYNAMICS: CRO
¾ e = 1.602 ×10−19 C , m = 9.1×10−31 kg , ‘F’ force on electron in uniform electric field ‘E’
eE
¾ F=eE; acceleration a =
m
¾ If electron with velocity ' v ' moves in field ' E ' making an angle 'θ ' can be
resolved to v sin θ , v cos θ .
¾ Effect of Magnetic Field ‘B’ on Electron.
mv 2π m
¾ When B & Q are perpendicular path is circular r = ; Period ' t ' =
Be Be
¾ When slant with 'θ ' path is # Helical.
¾ EQUATIONS OF CRT
lL
¾ ELECTROSTATIC DEFLECTION SENSITIVITY Se =
2dVa
e
¾ MAGNETIC DEFLECTION SENSITIVITY S m = lL
2mVa
2eV
¾ Velocity due to voltage V, v =
m
¾ When E and B are perpendicular and initial velocity of electron is zero, the path is
u
Cycloidal in plane perpendicular to B & E. Diameter of Cycloid=2Q, where Q= ,
ω
E Be
u= , ω= .
B m
UNIT – II :: SEMICONDUCTOR JUNCTION
¾ Si , Ge have 4 electrons in covalent bands. Valency of 4. Doping with trivalent

elements makes ' p ' , Pentavalent elements makes ' n ' semiconductor.
¾ Conductivity σ = e ( n μn + p μ p ) where n, p are concentrations of Dopants.

μn & μ p are mobility’s of electron and hole respectively.
Diode equation
⎛ Vd ⎞
I d = I s ⎜ e nVT − 1⎟
⎝ ⎠
kT
VT = ; K= Boltzman Constant
-1- q
ΔVd VT kT ⎛ N A N P ⎞
¾ rd = = ; Vo = ln ⎜ ⎟
ΔI d I q ⎝ ni 2 ⎠
¾ T = 00 C + 273; q = 1.602 × 10−19 C
0 0
¾ Diode drop changes @ 2.2mv / C , Leakage current I s doubles on 10 C
dq
¾ Diffusion capacitance is cd = of forward biased diode it is ∝ I
dv
−n
¾ Transition capacitance CT is capacitance of reverse biased diode ∝ V n = 1 to 1
2 3
¾ RECTIFIERS
¾ COMPARISION
HW FW CT FW BR
VDC Vm 2Vm 2Vm

π π π
Vm Vm Vm
Vrms
2 2 2
γ
1.21 0.482 0.482
Ripple factor
-2-
η
40.6% 81% 81%
Rectification efficiency
PIV Vm 2 Vm Vm
Peak Inverse Voltage
UNIT – III :: FILTERS
2Vm 4 ⎧1 1 ⎫
¾ Harmonic Components in FW Output, v0 = − ⎨ cos 2wt + cos 4 wt + .....⎬
π π ⎩3 15 ⎭
1
Capacitance Input Filter, γ=
4 3 f CRL
RL
Inductor Input Filter, γ=
3 2 ωL
Critical inductance
LC is that value at which
diode conducts continuously, in + ve or −ve
half cycle.
LC FILTER,
2 1.2
γ= or , for 50 Hz , L in H , C in μ F .
12ω LC
2
LC
2 X c1 X c2 Xc
LC LADDER, γ= . . ..... n
3 X L1 X L2 X Ln
2 X C1 X C2
π FILTER, γ= . .
3 RL X L
X C1 X C2
RC FILTER, γ = 2. .
RL R
¾ ZENER DIODE FWD Bias Normal

si Diode 0.7 V Drop
Reverse Bias
Zener drop = Vz forV > Vz
-3-
¾ ZENER REGULATOR
Vi − Vz
¾ Is = ;Vi >> Vz
Rs
ΔVz
¾ rz =
ΔI z
¾ TUNNEL DIODE
¾ Conducts in
f , r , Quantum mechanical tunneling in region a-0-b-c.
b b
¾ -ve resistance b-c, normal diode c-d.
I p = peak current, I v = valley current; v p =peak voltage ≈ 65 mV, vv =valley voltage
0.35 V. Heavy Doping, Narrow Junction , Used for switching & HF oscillators.
¾ VARACTOR DIODE
Used in reverse bias & as tuning variable capacitance.
K Co
¾ CT = ; n=0.3 for diffusion, n=0.5 for alloy junction, CT =
(VT + VR )
n n
⎛1 + VR ⎞
⎜ VT ⎟⎠
⎝
CB 1
¾ is figure of merit, Self resonance f o =
C25 2π LS CT
¾ PHOTO DIODES
-4-
¾ Diode used in reverse bias for light detection.
¾ Different materials have individual peak response to a range of wave lengths.
UNIT - IV
¾ BJT, Bipolar Junction Transistor has 2 Junctions: BE, BC

I nE I
¾ Components of current are I nE , I pE at EB junction where γ = = nE
I nE + I pE I E
I nc
¾ γ = Emitter efficiency, β * = transportation factor.
I nE
¾ BE = f / b; BC = r / b
Ie = Ib + Ic
Ic I
α= ;β = c
Ie Ib
Doping Emitter Highest
Base Lowest
Ie > I c > Ib
¾ Leakage currents : I CBO , I CEO , I EBO

¾ I CEO = (1 + β ) I CBO
-5-
¾ 3 Configurations are used on BJT, CE, CB & CC
¾
¾ Common Emitter, VI characteristics
IC
β = VCE
IB
ΔVBE ΔV
¾ Ri = hie = = β re ; rce = r0 = ce
ΔI B ΔI c
Input Characteristics Circuit Output Characteristics
AC Equivalent Circuit
¾ COMMON BASE VI CHARACTERISTICS
IC β
¾ α= ;α =
IE 1+ β
-6-
AC Equivalent Circuit
ΔVEB I ΔVcb
¾ hib = = re ; h fb = C ; rcb =
ΔI E Ie VCB
ΔI c
AMPLIFIER COMPARISON
COMPARISON
CB CE CF
BE BC
Ri LOW MED HIGH
SATURATION f/b f/b

AI AI β β +1
ACTIVE f/b r/b
AV High High <1
CUT OFF r/b r/b

Ro High High low
UNIT - V
¾ h- parameters originate from equations of amplifier
vi = hi ii + hr v2 , i2 = h f ii + h0v2
vi & ii are input voltage and current
v2 & i2 are output voltage and current
¾ hi → input impedance hie , hib , hic ⎡⎣ β re , re , ( β + 1) re ⎤⎦
¾ h f → current gain h fe , h fb , h fc ⎡⎣ β , α , (1 + β ) ⎤⎦
¾ hr → reverse voltage transfer hre , hrb , hrc
¾ ho → output admittance hoe , hob , hoc
¾ FIELD EFFECT TRANSISTOR, FET is Unipolar Device
Construction n-Channel p-Channel
¾ S=Source, G=Gate, D=Drain

¾ GS Junction in Reverse Bias Always
¾ Vgs Controls Gate Width
-7-
¾ VI CHARACTERSTICS
Transfer Characteristics Circuit Forward Characteristics
¾ Shockley Equation
2
⎛ Vgs ⎞ ⎛ V ⎞
¾ I d = I dss ⎜ 1 − ⎟⎟ , g m = g m 0 ⎜1 − gs ⎟⎟
⎜ V ⎜ V
⎝ p ⎠ ⎝ p ⎠
¾ MOSFET: Metal Oxide Semiconductor FET, IGFET
Depletion Type Mosfet Symbols Enhancement Mosfet
¾ Depletion Type MOSFET can work width Vgs > 0 and Vgs < 0
MOSFET JPET
High Ri = 10 −108
10
R0 = 50 k Ω ≥ 1mΩ
Depletion Depletion
Enhancement Mode Mode
Transfer Forward
Delicate Rugged
Characteristics Characteristics
¾ Enhancement MOSFET operates with, Vgs > Vt , Vt = Threshold Voltage
-8-
Forward Characteristics Transfer Characteristics
VDS ( sat ) = VGS − VT , I ds (ON ) = K (VGS − VT )

2
JFET I D Table COMPARISIONS
Vgs ID BJT FET
0 I DSS Current controlled Voltage controlled
0.3 VP I DSS High gain Med gain

2
Bipolar Unipolar
0.5 VP I DSS
4 Temp sensitive Little effect of T
VP 0 High GBWP Low GBWP
UNIT – VI :: BIASING in BJT & JFET
¾ Fixing Operating Point Q is biasing
Fixed Bias Emitter Stabilized Feedback Bias
VCC = I B RB + VBE Fixed Bias VCC = ( β + 1) RC I B + I B RB +VBE
VCC = I B RB + VBE + ( β + 1) Re
-9-
VCC R2
VB = ,
R1 + R2
VE
VE = VB − VBE ; I C ≈
RE
Vcc = ( β + 1)( Rc + Re ) Ib
+ Ib.Rb + Vbe
VOLTAGE DIVIDER BIAS EMITTER STABILIZED

FIXED BIAS
STABILITY EQUATIONS
¾ ΔI c = S1ΔI c 0 + S2 ΔVBE + S3 Δβ
¾ S1 =
ΔI C
; S2 =
ΔI C ΔI
; S3 = C , STABILITY FACTOR S =
( β + 1)
ΔI CO ΔVBE Δβ 1− β B
dI
dI C
¾ S must be as small as possible, Most ideal value =1
dI B
¾ How to do determine stability factor for bias arrangement? Derive and
dI C
substitute in S
Zl
¾ Amplifier formulae: AV = AI , Z i measured with output shorted
Zi
¾ Z0 measured with input shorted
¾ CE amplifier A I ≅ h fe or β ;
VT R
¾ Z i = β re; re = ; Av = − L ;
I re
R
¾ CB amplifier A1 = α ; Av = L ; Z i = re
re
CC amplifier A I = ( β + 1) ; AV = 1 − ; Ri = ( h fe + 1) RE + hie
hie
¾
Ri
¾ H Parameter Model CE
h fe ZL
¾ AI = ; AV = h fe
1 + hoe zl hie
RL
¾ CB amplifier Ri = hib ; AI = h fb ; AV = h fb .
hib
¾ FET
¾ CS amplifier AV = − g m ( Rd || rd ) ; Z 0 = Rd
Rs
¾ Common Gate Amplifier AV = g m Rd , Z i =
1 + g m Rs
- 10 -
g m Rs 1
¾ Common Drain AV = ; Zo =
1 + g m Rs gm
¾ RC Coupled Amplifiers
φ = tan −1 ⎛⎜ f1 f ⎞⎟ ; A =
1 1
¾ If cut off frequency f1 = ,
2π RC ⎝ ⎠ 1+ j ⎛⎜ 1
f ⎞
⎝ f ⎟⎠
¾ Slope = 6dB / octave, 20dB / decade , Octave= f
or 2 f
2
¾ f β is beta cut off frequency where h fe → falls by 0.707
¾ fα is α cut off frequency where α = 0.707
¾ ft is h fe = 1 gain bandwidth product.
UNIT – VII :: FEED BACK AMPLIFIERS
¾ Amplifier gain stands for any of Voltage amplifier, Current amplifier, Trans resistance
Trans admittance amplifier
A X X
Af = ; A= 0 ; β = f
1 + Aβ Xi X0
Xi = Xs − X f
¾ + Ve feed back amplifier depends on |1 + Aβ | > 1 − ve f b , < 1 + ve f b

−
¾ Feed back reduces noise distortion, gain variation due to parameters, increases BW.
(1 + Aβ ) is called de-sensitivity factor.
¾ Feed back amplifiers

Voltage series, voltage shunt; Current series, current shunt
for voltage, current series

zi f = zi (1 + Aβ )
A
Af = , for all
1 + Aβ
zi
zi f = , for voltage or current shunt
1 + Aβ
zo f = zo (1 + Aβ ) , for current series, shunt
z0
zo f = , for voltage series and shunt.
1 + Aβ
UNIT – VIII :: OSCILLATORS
¾ Barkausen Criterion for oscillation loop gain =1, θ =00, 3600.
- 11 -
¾ HARTLEY OSCILLATOR
1 L2
f = , LT = L1 + L2 ± M , ; β = ,
2π LT C L1
COLLPITS OSILLATOR,
L1 , L2 replaced by C1 ,C2 ,
1
C replaced by L; f =
2π LCT
¾ CRYSTAL OSCILLATORS
¾ Tuned ckt replaced with Crystal
1
ωs = ,
LC
1
ωp =
LCT
¾ Phase shift oscillator
FET MODEL
1
f = , A = 29 ,
2π 6 RC
Minimum RC sections 3
BJT MODEL
1
f = , A = 29 ,
⎛ 4R ⎞
2π RC 6 + ⎜ C ⎟
⎝ R ⎠
Minimum RC sections 3
¾ Wein Bridge Oscillator
1
f = ,
2π R1 R2C1C2
1 1
if R1=R2=R, C1=C2=C , f = ; A= =3
2π RC β
- 12 -

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ELECTRONIC DEVICES AND CIRCUITS (15A04301)

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

UNIT- III:- Transistor Characteristics: BJT: Junction transistor, transistor current

UNIT- I: - JUNCTION DIODE CHARACTERISTICS

Conductors: A conductor is a material which supports a generous flow of charge

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 1

1.0.1 Semiconductor Types

A pure form of semiconductors is called as intrinsic semiconductor. Conduction in

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 2

The absence of electrons in covalent bond is represented by a small circle usually

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 3

1.0.2 EXTRINSIC SEMICONDUCTOR

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 4

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 5

• The conductivity of N type sc is greater than that of P type sc as the mobility of

1.0.3 CONDUCTIVITY OF SEMICONDUCTOR

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 6

Where n=no. of electrons / unit volume i.e., concentration of free electrons

Therefore, J= ni (μn + μp) q E

1.0.4 CHARGE DENSITIES IN P TYPE AND N TYPE SEMICONDUCTOR:

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 7

Hence eq1.2 becomes ND ≈ nn

1.1 QUANTITATIVE THEORY OF PN JUNCTION DIODE

Fig 1.6: Symbol of PN Junction Diode

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 8

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 9

1.1.2 FORWARD BIASED JUNCTION DIODE

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 10

1.1.2 PN JUNCTION UNDER REVERSE BIAS CONDITION:

Reverse Characteristics Curve for a Junction Diode

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 11

Sometimes this avalanche effect has practical applications in voltage stabilizing

1.2 VI CHARACTERISTICS AND THEIR TEMPERATURE DEPENDENCE

Temperature Effects on Diode

Fig 1.11 Variation in Diode Characteristics with temperature change

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 12

1.3 IDEAL VERSUS PRACTICAL RESISTANCE LEVELS

Fig 1.12 Determining the dc resistance of a diode at a particular operating point.

Fig 1.13: Determining the ac resistance of a diode at a particular operating point.

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 13

1.4 DIODE EQUIVALENT CIRCUITS

Fig: 1.14aDiode piecewise-linear model characteristics

Fig: 1.14b Diode piecewise-linear model equivalent circuit

Fig 1.15 Ideal Diode and its characteristics

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 14

where CT - transition capacitance

where CD - diffusion capacitance

The diffusion capacitance at high frequencies is inversely proportional to the

1.6 BREAK DOWN MECHANISMS

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 15

Fig 1.18: Diode characteristics with breakdown

Either of the two (Zener breakdown or avalanche breakdown) may occur

1.7 ZENER DIODES

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 16

Fig 1.19 Zener diode characteristics

SPECIAL PURPOSE ELECTRONIC DEVICES

C.Padma,Asst.Professor Department of ECE, SVEW Tirupathi Page 17

Fig 1.19: Tunnel diode schematic symbol