Lab Program 14-9-22
Lab Program 14-9-22
Lab Program 14-9-22
test Bench
module mux2x1test;
reg [1:0] d;
reg sel;
wire y;
mux2x1 mux(d, sel,y);
initial
begin
d=2'b00; sel=0;
#50 d=2'b01; sel=0;
#50 d=2'b10; sel=0;
#50 d=2'b11; sel=0;
#100 $stop;
end
endmodule
Mux 8x1
test Bench
m
module mux8x1test;
reg [7:0] d;
reg [2:0]sel;
wire y;
mux8x1 mux8x1(d, sel,y);
initial
begin
#30 d=7'b00000001; sel=3'b000;
#30 d=7'b00000010; sel=3'b001;
#30 d=7'b00000100; sel=3'b010;
#30 d=7'b00001000; sel=3'b011;
#30 d=7'b00010000; sel=3'b100;
#30 d=7'b00100001; sel=3'b101;
#30 d=7'b01000000; sel=3'b110;
#30 d=7'b10000000; sel=3'b111;
#100 $stop;
end
endmodule
Mux 16x1
module mux16x1using2x1(d,sel,y);
input [15:0]d;
input [3:0]sel;
output y;
wire [7:0]m17;
wire[3:0]m23;
wire [1:0]m31;
mux2x1 m1(d[1:0],sel[0],m17[0]);
mux2x1 m2(d[3:2],sel[0],m17[1]);
mux2x1 m3(d[5:4],sel[0],m17[2]);
mux2x1 m4(d[7:6],sel[0],m17[3]);
mux2x1 m5(d[9:8],sel[0],m17[4]);
mux2x1 m6(d[11:10],sel[0],m17[5]);
mux2x1 m7(d[13:12],sel[0],m17[6]);
mux2x1 m8(d[15:14],sel[0],m17[7]);
mux2x1 m9(m17[1:0],sel[1],m23[0]);
mux2x1 m10(m17[3:2],sel[1],m23[1]);
mux2x1 m11(m17[5:4],sel[1],m23[2]);
mux2x1 m12(m17[7:6],sel[1],m23[3]);
mux2x1 m13(m23[1:0],sel[2],m31[0]);
mux2x1 m14(m23[3:2],sel[2],m31[1]);
mux2x1 m15(m31[1:0],sel[3],y);
endmodule
Test bench
module mux16x1using2x1test;
reg [0:15] d;
reg [0:3] sel;
wire y;
mux16x1using2x1 m16x1(d,sel,y);
initial
begin