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    Verilog

    Uploaded by

    KennethCharlesYamson
    The document contains source code for three Verilog modules that implement basic logic gates and test their functionality. Module exercise1_1 contains four-input NAND gates that are tested by a testbench module that simulates different input combinations. Module circuit1_1 contains a circuit with NOT, XOR, AND and NOR gates whose output is tested for all input combinations by another testbench module. The last module exercise1_3 uses XOR gates and is similarly tested for all input cases by a testbench module.

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    Verilog

    Uploaded by

    KennethCharlesYamson
    84 views3 pages
    The document contains source code for three Verilog modules that implement basic logic gates and test their functionality. Module exercise1_1 contains four-input NAND gates that are tested by a testbench module that simulates different input combinations. Module circuit1_1 contains a circuit with NOT, XOR, AND and NOR gates whose output is tested for all input combinations by another testbench module. The last module exercise1_3 uses XOR gates and is similarly tested for all input cases by a testbench module.

    Original Description:

    Experiment 1

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    The document contains source code for three Verilog modules that implement basic logic gates and test their functionality. Module exercise1_1 contains four-input NAND gates that are tested by a testbench module that simulates different input combinations. Module circuit1_1 contains a circuit with NOT, XOR, AND and NOR gates whose output is tested for all input combinations by another testbench module. The last module exercise1_3 uses XOR gates and is similarly tested for all input cases by a testbench module.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    84 views3 pages

    Verilog

    Uploaded by

    KennethCharlesYamson
    The document contains source code for three Verilog modules that implement basic logic gates and test their functionality. Module exercise1_1 contains four-input NAND gates that are tested by a testbench module that simulates different input combinations. Module circuit1_1 contains a circuit with NOT, XOR, AND and NOR gates whose output is tested for all input combinations by another testbench module. The last module exercise1_3 uses XOR gates and is similarly tested for all input cases by a testbench module.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    Source Code

    Exercise 1_1
    module exercise1_1(W,X,Y,Z);
    output [0:3] W;
    input X,Y;
    input Z;
    wire X1,Y1,Z1;
    not g1(X1,X), g2(Y1,Y), g3(Z1,Z);
    nand g4(W[0],X1,Y1,Z1), g5(W[1],X1,Y,Z1), g6(W[2],X,Y1,Z1), g7(W[3],X,Y,Z1);
    endmodule
    module testex1();
    reg X,Y,Z;
    wire [0:3] W;
    exercise1_1 tb(W,X,Y,Z);
    initial begin
    #4 X=1'b0; Y=1'b0; Z=1'b0;
    $monitor("X=%b Y=%b Z=%b W=%b",X,Y,Z,W);
    #4 X=1'b0; Y=1'b0; Z=1'b1;
    #4 X=1'b0; Y=1'b1; Z=1'b0;
    #4 X=1'b0; Y=1'b1; Z=1'b1;
    #4 X=1'b1; Y=1'b0; Z=1'b0;
    #4 X=1'b1; Y=1'b0; Z=1'b1;
    #4 X=1'b1; Y=1'b1; Z=1'b0;
    #4 X=1'b1; Y=1'b1; Z=1'b1;
    #2 $finish;
    end
    endmodule

    Exercise 1_2
    module circuit1_1(A,B,C,X);
    input A,B,C;
    output X;
    wire wire1, wire2, wire3;
    not NOT(wire2,A);
    xor EOR2(wire1,B,C);
    and AND2(wire3,wire1,A);
    nor NOR2(X,wire3,wire2);
    endmodule
    module testbench1_1();
    reg A,B,C;
    wire Z;
    circuit1_1 tb1(A,B,C,Z);
    initial
    begin
    A=1'b0; B=1'b0; C=1'b0;
    $strobe($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
    #20 A=1'b0; B=1'b0; C=1'b1;
    $strobe($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
    #10 A=1'b0; B=1'b1; C=1'b0;
    $strobe($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
    #10 A=1'b0; B=1'b1; C=1'b1;
    $strobe($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
    #10 A=1'b1; B=1'b0; C=1'b0;
    $strobe($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
    #10 A=1'b1; B=1'b0; C=1'b1;
    $strobe($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
    #10 A=1'b1; B=1'b1; C=1'b0;
    $strobe($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);

    #10 A=1'b1; B=1'b1; C=1'b1;


    $strobe($time,,,"A=%b B=%b C=%b Z=%b",A,B,C,Z);
    $finish;
    end
    endmodule
    Exercise 1_3
    module exercise1_3(var1,x_4,x_1,x_2,x_3);
    output var1,x_4;
    input x_1,x_2,x_3;
    xor EOR1(x_4,x_1,x_2,x_3);
    xor EOR2(var1,x_1,x_2,x_3,x_4);
    endmodule
    module testex3();
    reg x_1,x_2,x_3;
    wire var1,x_4;
    exercise1_3 tb(var1,x_4,x_1,x_2,x_3);
    initial begin
    #4 x_1=1'b0; x_2=1'b0; x_3=1'b0;
    $monitor("x_1=%b x_2=%b x_3=%b var1=%b x_4=%b",x_1,x_2,x_3,var1,x_4);
    #4 x_1=1'b0; x_2=1'b0; x_3=1'b1;
    #4 x_1=1'b0; x_2=1'b1; x_3=1'b0;
    #4 x_1=1'b0; x_2=1'b1; x_3=1'b1;
    #4 x_1=1'b1; x_2=1'b0; x_3=1'b0;
    #4 x_1=1'b1; x_2=1'b0; x_3=1'b1;
    #4 x_1=1'b1; x_2=1'b1; x_3=1'b0;
    #4 x_1=1'b1; x_2=1'b1; x_3=1'b1;
    #2 $finish;
    end
    endmodule

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