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    Lecture-7 (8086 System Connections and Timing)

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    AYSHA AKMAL 183-15-11959
    This document discusses the bus timing of the 8086 microprocessor. It explains that the 8086 requires multiple clock cycles, called T-states, to complete a single bus operation like reading from or writing to memory. Each bus cycle consists of 4 T-states where specific actions occur - in T1 the address is output, in T2 the bus cycle type is specified, in T3 data is supplied, and in T4 control signals are removed in preparation for the next cycle. Read operations sample data from the bus in T3 while write operations transfer data to memory or I/O in T4. Understanding the T-states is important because it allows the 8086 to multiplex the address and data lines during each bus

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    Lecture-7 (8086 System Connections and Timing)

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    AYSHA AKMAL 183-15-11959
    26 views18 pages
    This document discusses the bus timing of the 8086 microprocessor. It explains that the 8086 requires multiple clock cycles, called T-states, to complete a single bus operation like reading from or writing to memory. Each bus cycle consists of 4 T-states where specific actions occur - in T1 the address is output, in T2 the bus cycle type is specified, in T3 data is supplied, and in T4 control signals are removed in preparation for the next cycle. Read operations sample data from the bus in T3 while write operations transfer data to memory or I/O in T4. Understanding the T-states is important because it allows the 8086 to multiplex the address and data lines during each bus

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    This document discusses the bus timing of the 8086 microprocessor. It explains that the 8086 requires multiple clock cycles, called T-states, to complete a single bus operation like reading from or writing to memory. Each bus cycle consists of 4 T-states where specific actions occur - in T1 the address is output, in T2 the bus cycle type is specified, in T3 data is supplied, and in T4 control signals are removed in preparation for the next cycle. Read operations sample data from the bus in T3 while write operations transfer data to memory or I/O in T4. Understanding the T-states is important because it allows the 8086 to multiplex the address and data lines during each bus

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    26 views18 pages

    Lecture-7 (8086 System Connections and Timing)

    Uploaded by

    AYSHA AKMAL 183-15-11959
    This document discusses the bus timing of the 8086 microprocessor. It explains that the 8086 requires multiple clock cycles, called T-states, to complete a single bus operation like reading from or writing to memory. Each bus cycle consists of 4 T-states where specific actions occur - in T1 the address is output, in T2 the bus cycle type is specified, in T3 data is supplied, and in T4 control signals are removed in preparation for the next cycle. Read operations sample data from the bus in T3 while write operations transfer data to memory or I/O in T4. Understanding the T-states is important because it allows the 8086 to multiplex the address and data lines during each bus

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 18

    8086 System Connections and BUS Timing

    Course Teacher:
    Md. Obaidur Rahman, Ph.D.
    Assistant Professor,
    Department of Computer Science and Engineering (CSE),
    Dhaka University of Engineering & Technology (DUET), Gazipur.

    Course ID: CSE - 4503


    Course Title: Microprocessors and Assembly Language
    Department of Computer Science and Engineering (CSE),
    Islamic University of Technology (IUT), Gazipur.
    Lecture References:
     Book:
     Microprocessors and Interfacing: Programming and Hardware,
    Chapter # 7, Author: Douglas V. Hall.

     Lecture Materials:
     M. A. Sattar, Microprocessor and Microcontroller, BUET.
     Md. Omar Faruque, BRAC University.

    2 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    Remember !! 8086 Pin Specifications

    3 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    Microprocessor Operation

    Fetch Decode

    Execute

    4 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    Microprocessor Operation
     The time a µP requires to complete fetch-decode-
    execute operation of a single instruction is known as
    Instruction Cycle
     An Instruction Cycle consists of one or more Machine
    Cycles
     A basic µP operation such as reading or writing a byte
    from or to memory or I/O port is called a Machine
    Cycle or Bus cycle
     A Machine (bus) cycle consists of at least four clock
    cycles, called T states.
     One cycle of a clock is called a State

    5 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    Clock Generation
     Clock generator circuit is 8254A and connected to pin
    19 (CLK) of 8086.

    6 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    System Clock Concept

    7 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    System Clock Concept
     8086 is found to operate in between 5 to 10 Mhz.
     Each bus cycle consists of 4 clock cycles.
     An 8086 running at 5MHz, it’s clock pulses will be of
    200ns and it would take 800ns for a complete bus cycle.
     Again, an 8086 running at 10MHz, it’s clock pulses will be
    of 100ns and it would take 400ns for a complete bus
    cycle.
     Each read or write operation take 1 bus cycles.

    8 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    Clock States
     Why are there T states?
     In the 8086, the address and data lines are
    multiplexed.
     The microprocessor needs time to change the
    signals during each bus cycle.
     Memory devices need time to interpret the address
    value and then read/write the data (access time)

    9 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    Clock States
     A specific, defined action occurs during each T states
    (labeled T1 – T4)

     T1: Address is output


     Address of memory or I/O is sent out by 8086 via address
    bus
     Used Control signals: ALE, DT/R’, M/IO’ shows some output

     T2: Bus cycle type (MEMORY/IO, READ/WRITE)


     8086 issues either RD’ or WR’ and DEN’
     In case of WRITE (WR) operation, data to be written
    appear on data bus

    10 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    Clock States
     T3: Data is supplied
     READY is sampled at the end of T2
     If READY is low, T3 becomes a wait state (TW), means no
    operation (NOP).
     In READ bus cycle data bus is sampled at end of T3

     T4: Data latched by µP, control signals removed


     All bus signals deactivated in preparation for next bus cycle
     µP sampled data bus for data that read from M or I/O
     At trailing edge of WR’, transfer data to M or I/O

    11 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    READ BUS Timing (Complete BUS Cycle)

    12 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    READ BUS Timing (During T1 State)

    During T1 :
    • The address is placed on the
    Address/Data bus.
    • Control signals
    • M/ IO’ specify memory or I/O,
    • ALE latch the address onto the
    address bus and
    • DT/R’ set the direction of data
    transfer on data bus.

    13 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    READ BUS Timing (During T2 State)

    During T2 :
    • 8086 issues the RD’ or WR’
    signal.
    • DEN’ enables the 8086 to
    receive the data for READ
    operation (or the memory or I/O
    device to receive the data for
    WRITE operation).

    14 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    READ BUS Timing (During T3 State)
    During T3 :
    • This cycle is provided to
    allow memory to access
    data.

    • READY is sampled at
    the end of T2 .
    • If low, T3 becomes a
    wait state.
    • Otherwise, the data
    bus is sampled at the
    end of T3 .

    15 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    READ BUS Timing (During T4 State)

    During T4 :
    • All bus signals are deactivated, in preparation for next bus cycle.
    • Data is sampled for READ (or WRITE occurs for write) data.
    16 CSE-4503: Microprocessors and Assembly Language
    Islamic University of Technology (IUT)
    WRITE BUS Timing

     What are the functions of each pin in different T states


    during WRITE operation ??

    17 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)
    Thank You !!

    18 CSE-4503: Microprocessors and Assembly Language


    Islamic University of Technology (IUT)

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