MEENAKSHI SUNDARARAJAN

ENGINEERING COLLEGE
DEPARTMENT OF INFORMATION
TECHNOLOGY
QUESTION BANK
SUBJECT : DIGITAL PRINCIPLES AND SYSTEM
DESIGN SEM / YEAR : III SEMESTER/ SECOND YEAR

UNIT I - BOOLEAN ALGEBRA AND LOGIC GATES

Number Systems - Arithmetic Operations - Binary Codes- Boolean Algebra and Logic Gates -
Theorems and Properties of Boolean Algebra - Boolean Functions - Canonical and Standard
Forms - Simplification of Boolean Functions using Karnaugh Map method - NAND and NOR
Implementations.
PART-A
Q.no Question BTL Competence
1 Find the octal equivalent of hexadecimal numbers of AB.CD (OR) DC.BA BTL5 Evaluating
2 State and prove the Consensus theorem. BTL2 Understanding
3 State the principle of Duality. BTL2 Understanding
4 Implement AND gate using only NOR gates. (OR) Realize XOR gate BTL6 Creating
using only NAND gates.
5 Convert (0.6875)10 to binary (OR) Convert (126)10 to Octal & Binary BTL3 Applying
6 Prove the following using DeMorgan’s Theorem. BTL5 Evaluating
[(X + Y)'+(X + Y) '] '=X + Y.
7 Write short notes on weighted binary codes. BTL2 Understanding
8 Illustrate NOR Operation with a truth table BTL2 Understanding
9 What is Excess-3 Code? BTL1 Remembering
10 Simplify Z = (AB +C) (B'D + C'E')+(AB+C)' BTL4 Analyzing
11 Realize G = AB'C +DE+F' BTL4 Analyzing
12 Convert (1001010. 1101001)2 to base 16 &(231.07)8 to base 10 BTL3 Applying
13 Convert the binary number to (1011111011)2 into gray code. (OR) Convert BTL3 Applying
(A3B)H into decimal number.
14 Find the complement of the function F= X'YZ' + X'Y'Z. BTL1 Remembering
15 Express the Boolean Function F= A+B’C as sum of minterms.(SOP). BTL1 Remembering
16 What are Universal Gates? Why are they named so? BTL1 Remembering
17 How many NOR gates are required if NAND gate is implemented using BTL2 Understanding
NOR.
18 Express the following Boolean expression in to minimum number of BTL5 Evaluating
literals. XYZ+X'Y+XYZ'.
19 What are the limitations of K-map? BTL1 Remembering
 20 Analyse the following Boolean functions using three variable maps. BTL4 Analyzing
F(X,Y,Z) = ∑(0,2,3,6,7).
PART-B
Q.no Question Mark BTL Competence
1 Simplify the following switching function using Quine Mc 13 BTL3 Applying
Cluskey method and realize expression using gates
F(A,B,C,D)
= ∑(0,5,7,8,9,10,11,14,15)
2 Simplify the following switching function using karnaugh map 13 BTL2 Understanding
method and realize expression using gates F(A,B,C,D) =
∑(0,3,5,7,8,9,10,12,15)
3 Simplify the function F(w,x,y,z)=∑m(2,3,12,13,14,15) using 13 BTL4 Analyzing
Tabulation method. Implement the simplified function using
gates.
4(a) Simplify the Boolean function in Sum of Products(SOP) and 08 BTL4 Analyzing
Product of Sum(POS) F(w,x,y,z)=∑m(0,1,2,5,8,9,10).
4(b) Design the Boolean function in Karnaugh map and simplify 05 BTL6 Creating
it F(w,x,y,z)=∑m(0,1,2,4,5,6,8,9,12,13,14).
5 Simplify the following Boolean expression in (a) Sum of Product 06+07 BTL4 Analyzing
(b) Product of Sum using Karnaugh
map AC' + B'D + A'CD + ABCD.
6(a) Express the following function in sum of min-terms and product 08 BTL2 Understanding
of max-terms : F(x,y,z)=x+yz.
6(b) Convert the following logic system in to NAND gates only. 05 BTL3 Applying

7(a) Add, subtract and multiply the following numbers (110010)2 and 03 BTL1 Remembering
(11101)2.
7(b) State and prove De Morgan’s theorems for 2-variables 04 BTL1 Remembering
7(c) Find complement of the following Boolean expression xyz’ 06 BTL1 Remembering
+x’yz+z(xy+w)
8 Minimize the following function using Karnaugh map 13 BTL4 Analyzing
F(A,B,C,D) = ∑m(0,1,2,3,4,5,6,11,12,13) and implement
with
logic gates.
9 Minimize the expression using K-map and Quine 13 BTL2 Understanding
Mccluskey method Y= A’BC’D +
A’BC’D+ABC’D’+ABC’D’+AB’C’D+A’B’CD’
10(a) Implement the following Boolean function with NAND-NAND 07 BTL6 Creating
logic F(A,B,C)= ∑(0,1,3,5)
10(b) Define prime implicate and essential prime implicate. 04 BTL1 Remembering
10(c) Convert (78.5) 10 into binary 02 BTL3 Applying
11(a) Short notes on 1’s and 2’s complement 05 BTL1 Remembering
11(b) Explain the rules for Binary Addition and Subtraction using 1's & 08 BTL5 Evaluating
2’s complement. Give examples.
12 Explain about common postulates used to formulate various 13 BTL1 Remembering
 algebraic structures.
13(a) Explain the procedure for obtaining NAND- NAND circuit for 08 BTL5 Evaluating
any AND-OR network with a suitable example.
13(b) Implement Y= (A'B+AB') (C+D') using NOR gates. 05 BTL3 Applying
14(a) Explain the procedure for obtaining NOR- NOR circuit for any 08 BTL5 Evaluating
AND-OR network with a suitable example.
14(b) Simplify the given Boolean function in POS form using k-map 05 BTL4 Analyzing
F(A,B,C,D) =ΠM(0,1,4,7,8,10,12,15)+d(2,6,11,14)
PART-C
Q.no Question Mark BTL Competenc
e
1 Minimize the expression using Quine Mc Cluskey 15 BTL5 Evaluating
method F=∑m(0,1,9,15,24,29,30) + ∑d(8,11,31) (OR)
Reduce the
expression using tabulation method F(X1,X2,X3,X4,X5) =
∑m(0,2,4,5,6,7,8,10,14,17,18,21,29,31) + ∑d(11,20,22)
2 Express the following function in a simplified manner using K 15 BTL6 Creating
map
technique (i) G=πM(0,1,3,7,9,11).
(ii) f(W,X,Y,Z)=∑m(0,7,8,9,10,12) + ∑d(2,5,13).
3 Simplify the following function using five variable K- map 15 BTL5 Evaluating
F(A,B,C,D,E)=A’B’CE’+B’C’D’E’+A’B’D’+B’C’D’+A’CD+A’
BD
4 Simplify the following expression using Quine Mc 15 BTL5 Evaluating
Cluskey method & K map technique
Y= m1+m3+m4+m7+m8+m9+m10+m11+m12+m14
UNIT II - COMBINATIONAL LOGIC
Combinational Circuits – Analysis and Design Procedures - Binary Adder-Sub tractor - Decimal
Adder - Binary Multiplier - Magnitude Comparator - Decoders – Encoders – Multiplexers.
PART-A
Q.no Question BTL Competence
1 Implement (solve) the function G=∑m (0, 3) using a 2x4 decoder. BTL6 Creating
2 Draw (design) the circuit diagram for 2 to 1 line multiplexer. BTL3 Applying
3 Implement (solve) the following Boolean function using 8:1 multiplexer BTL5 Evaluating
F(A,B,C)=∑(1,3,5,6).
4 What is priority encoder? BTL1 Remembering
5 Implement (solve) a full adder with 4x1 multiplexer. BTL2 Understanding
6 Write the Data flow description of a 4 bit comparator. BTL2 Understanding
7 What is half adder?. Draw the truth table of half adder BTL1 Remembering
8 Write short notes on propagation delay BTL2 Understanding
9 Define combinational circuits BTL1 Remembering
10 Differentiate between Multiplexer and Demultiplexer. BTL4 Analyzing
11 State the difference between decoder and demultiplexer. BTL4 Analyzing
12 Obtain the truth table for BCD to Excess-3 code converter BTL1 Remembering
13 Draw the truth table and circuit diagram of 4 to 2 encoder. BTL3 Applying
 14 How many 3-to-8 line decoders with an enable input are needed to construct BTL6 Creating
a 6-to-64 line decoder without using any other logic gates?
15 Realize the combinational circuit of half subtractor. BTL2 Understanding
16 Differentiate between encoder and decoder. BTL4 Analyzing
17 List out the application of multiplexer. BTL1 Remembering
18 How many number of 2X1 multiplexers are required to implement 4x1 BTL5 Evaluating
multiplexer.
19 Draw the full adder circuit as a collection of two half adders. BTL3 Applying
20 List the truth table of full subtractor. BTL1 Remembering
PART-B
Q.no Question Mark BTL Competence
1 Describe the process involved in converting 8421 code to Excess 13 BTL2 Understanding
3 code with neat sketch. (OR) Design a code converter
that converts a 8421 to BCD Code
2(a) Examine the following Boolean function using 8 to 1 06 BTL4 Analyzing
Multiplexer. F(A,B,C,D)=A’BD’ + ACD + B'CD + A'C'D.
2(b) Discover the above function using 16 to 1 Multiplexer. 07 BTL4 Analyzing
3 Describe the procedure of converting 8421 to Gray code 13 BTL2 Understanding
converter also realize the converter using only NAND gates.
4 Design Full subtractor and derive expression for difference and 13 BTL6 Creating
borrow. Realize using two half subtractor.
5(a) Examine the following Boolean functions with a multiplexer. 06 BTL4 Analyzing
F(W,X,Y,Z) = ∑ (2,3,5,6,11,14,15)
5(b) Construct a 5 to 32 line decoder using 3 to 8 line decoders and 2 07 BTL3 Applying
to 4 line decoder.
6(a) Explain the Analysis procedure. Analyze the following 05 BTL5 Evaluating
logic diagram.
6(b) With neat diagram explain the 4 bit adder with Carry look 08 BTL5 Evaluating
ahead.

7 Design Full subtractor and derive expression for difference 13 BTL6 Creating
and
borrow. Realize using gates.

8 Design the full adder with inputs x,y,z and two outputs S 13 BTL6 Creating
and C.
The circuits perform x+y+z is the input carry, C is the
output carry and S is the Sum & realize it’s using only NOR
gates

9 Design a logic circuit that accepts a 4-bit gray code and 13 BTL6 Creating
converts
it to 4-bit binary code

10(a) Design a 2 bit binary multiplier to multiply two binary 06 BTL1 Remembering
numbers
and produce a 4-bit result.
10(b) Construct a 4-bit odd parity generator circuit using gates 07 BTL3 Applying

11 Recall the design procedure for binary multiplier 13 BTL1 Remembering

12 Define priority encoder and design 8 to 3 priority encoder 13 BTL1 Remembering

13(a) Explain the design procedure for combinational circuits 07 BTL5 Evaluating
with
suitable examples

13(b) Construct 16X1 multiplexer with two 8X1 and 2X1 06 BTL3 Applying
multiplexer.
Use Block diagrams
 14(a) Implement the following function using 74LS138 and gates. 07 BTL2 Understanding
F1(A,B,C)= Π(0,1,3,7) and F2(A,B,C)= Π(2,3,7)

14(b) Find the design procedure for a 4 –bit parallel binary adder / 06 BTL1 Remembering
subtractor.

PART-C
Q.no Question Mark BTL Competence
1 How to design a 4 bit magnitude comparator with 3 outputs 15 BTL2 Understanding
A>B,A=B,A<B
2a Implement the following function using 8 to 1 multiplexer 07 BTL5 Evaluating
f(a,b,c,d)= ∑m(0,1,3,5,9,12,14,15)
2b Implement the following function using multiplexer f(a,b,c,d)= 08 BTL5 Evaluating
∑m(0,1,3,4,8,9,15)
3 Design a binary to gray code converter circuit & a BCD to 7- 15 BTL6 Creating
Segment code converter circuit
4 Find the design procedure for a combinational circuit to perform 15 BTL6 Creating
BCD addition.

UNIT III - SYNCHRONOUS SEQUENTIAL LOGIC

Storage Elements- Latches - Flip-Flops- Registers - Analysis and Design Procedure of Sequential
Circuits - State Reduction and Assignment - Shift register - Sequence generator/detector-
Counters. HDL models of sequential circuits.