ECEg3202 Computer Architecture

and Organization

The slides here were originally prepared by

Betiglu- a great friend and colleague. RIP
REGISTER TRANSFER LANGUAGE AND
MICROOPERATIONS

Topics
 Introduction
 Microoperations
 Register Transfer Language
 Register Transfer
 Bus and Memory Transfer
 Design of Microoperations
 Arithmetic Logic Shift Unit

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A computer system is composed of various
digital elements. (Combinational, Sequential)
 Registers,
 Decoders,
 Multiplexers,
 Arithmetic Units, and
 Control Logics

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Elementary operations in a CPU that are
implemented in hardware.

Example:
 Shift operations in a shift register.
 Complement operations
 Increment operation.

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The most common microoperations can be
categorized to :
 Register Transfer Operations,
 Arithmetic Operations,
 Logic Operations, and
 Memory Operations.

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The symbolic notation used to describe a
sequence of microoperations that comprise an
instruction.

Hardware design is required to control reading

from source register and writing in to
destination register.

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Block Diagram Representation of Registers
R1
Register R1
15 0

Numbering of bits

7 6 5 4 3 2 1 0
Individual bits of register R
15 87 0
PC(H) PC(L)
Two parts of 16 bit register

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Notions in RTL

Symbol Description
Capital letter (followed by Computer register
numerals)
Arrow,
Replacement operator, Transfer
from register to register
Parenthesis ( ) Part of a register
Comma , Separates two microoperations

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Example:
 R1 represents one of the processor register.
 MAR Memory Address Register
 PC represents Program Counter register.
 PC(H) PC(15-8) higher bits of the PC
 R2
R1 transfer the content of R1 to register R2.
 R2
R1, R3
R2 + R3
 P: R2
R1 - if (P = 1) then (R2
R1)

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Memory transfer operations:
 Read: data transfer from memory to the CPU.
 Write: data transfer from the CPU to memory.

Notation for memory transfer
 The memory is denoted by the letter M,
 Data read from memory is stored to data register
DR
 Another register, address register - AR, holds the
memory address from which the data is to be read.

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RTL for memory transfer
 Read operation:

DR
M[AR]
 Write operation:

M[AR]
DR

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A register stores a binary string.

A flip flop / latch is required to store a bit.

So a register is implemented as an array of flip-
flops with some combinational logic for
control.
Din

load
shift
reset
clk

Dout
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Rather than connecting wires between all
registers, a common bus is used.
 A bus structure consists of a set of common lines,
one for each bit of a register.
 Multiplexers are used to selectively connect one of
the register outputs to the shared bus.
 The load control of the destination register is
activated to copy the data on the bus.

All register outputs can also be connected to the bus

via tri-state buffers.

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Example

Selected
S0 S1
Register
0 0 A
0 1 B
1 0 C
1 1 D

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Design a 4-to-1 Multiplexer
a
b output
c
d

Select

Design a 3-to-8 decoder
D7
D6
in2 D5
output
in1
in0 D0

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Addition

Subtraction

Increment

Decrement

Arithmetic Shift

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Add:
 R3 R1 + R2

Subtract:
 R3 R1 R2

Subtraction with 2s complement
 R3 R1 + R2 + 1

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Summary of Arithmetic Microoperations

Symbol Description
R3 R1 + R2 Contents R1 plus R2 put in R3
R3 R1 R2 Contents R1 minus R2 put in R3
R2 R2 1s complement whats in R2
R2 R2 + 1 2s complement whats in R2
R3 R1 + R2 + 1 R1 plus 2s complement of R2
R1 R1 + 1 Increment R1 by 1
R1 R1 1 Decrement R1 by 1

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Full adders are the basic building blocks
of the arithmetic unit.

Adder

Subtract

Increment

Decrement

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4-bit binary adder

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Both addition and subtraction can be
performed by using the same Full adder
network.

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4-bit binary adder/subtractor

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Binary Incrementer can be implemented using
half adder network.

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All basic arithmetic microoperations can be
implemented in one circuit
 A parallel adder constitutes the major component.
 By altering the inputs supplied to the adder, the
various operations can be selected.

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The full adders take in two inputs
 X = x3x2x1x0
 Y = y3y2y1y0

The adders produce a 4-bit input
 Z = z3z2z1z0
X Y

4 FA

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The first input is directly connected to one of
the operands.
 A  X

The other one however is connected to a
multiplexer.
 The multiplexer provides one of the four inputs

B, B, 1, 0
b0 b0 1 0

Y
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The four selections lead to different operations
Select In Output
S1 S0 Cin Y D = A + Y + Cin Microoperation
0 0 0 B D=A+B Add A and B
0 0 1 B D=A+B+1 Add A and B w/carry
0 1 0 B D = A + B Subtract w/borrow
0 1 1 B D = A + B + 1 Subtract B from A
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A1 Decrement A
1 1 1 1 D=A Transfer A

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4-bit Arithmetic
Circuit

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Logic operation b/n two binary strings
produce a binary string of the same width.
 AND, OR, COMPLEMENT, XOR, .

A multiplexer can be used to perform selected
operation on a pair of binary strings.

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With two inputs there can be sixteen possible
logic functions
Inputs
A B F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15

0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Clear (0)

(AB)
(A+B)

A + B
A + B

Set (1)
(AB)
AB
A+B
AB

AB
AB

A
B
A

Function
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Hardware Implementation
 Logic gates inserted for each bit or pair of bits in the registers to
perform needed logic function
 Most computers use only four microoperations and derive the
rest
 AND, OR, XOR, complement

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Left Shift
 Rightmost flip-flop gets binary data from serial input

Right Shift
 Leftmost flip-flop gets binary data from serial input

Serial input source determined by type of shift
 Logical Shift - 0
 Circular Shift - Other end
 Arithmetic Shift
 0 fill on right, and
 sign bit on left for arithmetic

Overflow when sign bit changes
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Example:
 Logical Shift

Original value: 11010011

Value after shift right: 01101001

Value after shift left: 10100110

 Circular Shift

Original value: 11010011

Value after shift right: 11101001

Value after shift left: 10100111

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Arithmetic Shift
 Original value: 11010011
 Value after shift right: 11101001
 Or, value after shift left: 10100110

 Second original value: 10011010

 Value after shift right: 11001101
 Or, value after shift left: 00110100 (overflow)

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Summary of Shift Microoperations

Symbolic Designation Description

R shl R Shift-left R
R shr R Shift-right R
R cil R Circular shift-left R
R cir R Circular shift-right R
R ashl R Arithmetic shift-left R
R ashr R Arithmetic shift-right R

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Hardware Implementation
 Register content is placed on bus
 Bus connected to combination circuit shifter
 Shifted value loaded back into same register
 All done in one clock pulse

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 Serial
Input, IR

Serial
Input IL

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All operations (Arithmetic, Logic and Shift) can
be combined into one unit called ALU.
 One or more source registers provide input
 ALU performs operation
 Result transferred into destination register
 All done in one clock pulse

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One bit ALU
S3
S2
S1
S0

Bi
Ai
Ai-1
Ai+1
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Arithmetic Logic Shift Unit function table
Operation Selectors
S3 S2 S1 S0 Cin Operation Function
0 0 0 0 0 FA Transfer A
0 0 0 0 1 FA+1 Increment A
0 0 0 1 0 FA+B Add A and B
0 0 0 1 1 FA+B+1 Add A and B with carry
0 0 1 0 0 F A + B' Subtract B from A with borrow
0 0 1 0 1 F A + B' + 1 Subtract B from A
0 0 1 1 0 FA-1 Decrement A
0 0 1 1 1 FA Transfer A
0 1 0 0 x FA AND A and b
0 1 0 1 x FAB OR A and B
0 1 1 0 x FAB XOR A and B
0 1 1 1 x FA Complement A
1 0 x x x F shr A Shift right A into F
1 1 x x x F shl A Shift left A into F

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